Phase B prereq item 4 per supervisor 06:27:29Z dispatch + theologian
06:28:41Z DRAFT + 06:29:45Z (B)-confirm.  Closes the catch-class gap
that exposed Phase A 5830b49 inert-scaffolding via librarian
00:04:37Z grep at frame_asm_c.c:527-532 (gate_passes_full_inline
computed then (void)-cast).  Pythia python#412/python#415/python#417 named the same
class repeatedly: "scaffolding-tier code can fail correctness while
passing every behavioural test."

F-1 attaches two pydebug/env-gated falsifiers to the existing gate
computation, both production-zero-overhead:

F-1.a oracle agreement (pydebug-only):
  assert(gate_passes_full_inline
         == frame_asm_c_full_inline_gate_oracle(hir_func));
The oracle in the new file Python/jit/codegen/frame_asm_c_oracle.c
re-derives the 4-condition predicate from theologian's design intent
(lightweight + non-generator + numCellvars==0 + numFreevars==0)
without re-reading the production gate.  Structural independence:

  - separate translation unit
  - reverse condition ordering (cellvars/freevars first; frame mode
    middle; generator last)
  - jit_get_config()->frame_mode lookup against JIT_FRAME_LIGHTWEIGHT
    enum vs. production's jit_hir_func_get_frame_mode +
    FRAME_MODE_LIGHTWEIGHT local #define
  - co_flags & {ASYNC_GENERATOR|COROUTINE|GENERATOR|ITERABLE_COROUTINE}
    bitmask spelled out in-line vs. production's jit_hir_func_is_gen
  - sequence of early-exit returns vs. &&-chained boolean compose

Production builds compile out the assert; the oracle then has no
caller and the linker may strip it.

F-1.b population coverage (env-gated PYTHONJITGATESTATS=1, both
build modes):
  per-JIT-compile fprintf to stderr with verdict + running true/false
  totals + each input field + qualname.  A single Phoenix smoke run
  produces a distribution that verifies >0 functions take each
  branch and shows which input decided each false case.

F-1.c sample test cases for theologian review post-build:
  - simple identity (lambda x: x): gate MUST be true
  - closure factory (def outer(): x=1; def inner(): return x; return
    inner): outer gate MUST be false (cellvars), inner gate MUST be
    false (freevars)
  - simple generator (def g(): yield 1): gate MUST be false (non-gen
    requirement fails)

F-1.d cross-arch: same input → same boolean on x86 and ARM64; per-
codepath counter distribution must match cross-arch within ±1.

Q1 oracle scope clarified pre-implementation per
[feedback_query_before_pivot]: gate is the 4 codegen-time
conditions only (theologian 06:29:45Z (B)-confirm); hasRtfsFunction
stays a runtime branch in Phase B (F0 measures its true-rate).

Auth chain: supervisor 06:27:29Z F-1 dispatch; theologian 06:28:41Z
F-1 design DRAFT + 06:29:45Z scope clarification; F-1 PASS gates F0
runtime branch-rate per supervisor 06:27:29Z.

Removal of F-1 instrumentation per I-F1.4 is a separate post-Phase-B
commit; this commit lands the instrumentation only.