From 7457c0c7f455a7e11c31bd5bb9388dc3b80866c4 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Tue, 11 May 2021 20:13:45 -0500 Subject: [PATCH 01/36] add config files --- .../asf4_conf/saml21/hpl_adc_config.h | 311 ++ .../asf4_conf/saml21/hpl_dac_config.h | 169 + .../asf4_conf/saml21/hpl_dmac_config.h | 3154 +++++++++++++++++ .../asf4_conf/saml21/hpl_gclk_config.h | 616 ++++ .../asf4_conf/saml21/hpl_mclk_config.h | 98 + .../asf4_conf/saml21/hpl_nvmctrl_config.h | 38 + .../asf4_conf/saml21/hpl_osc32kctrl_config.h | 208 ++ .../asf4_conf/saml21/hpl_oscctrl_config.h | 462 +++ .../asf4_conf/saml21/hpl_port_config.h | 284 ++ .../asf4_conf/saml21/hpl_rtc_config.h | 127 + .../asf4_conf/saml21/hpl_sercom_config.h | 712 ++++ .../asf4_conf/saml21/hpl_systick_config.h | 18 + .../asf4_conf/saml21/hpl_tc_config.h | 206 ++ .../asf4_conf/saml21/hpl_usb_config.h | 355 ++ .../asf4_conf/saml21/peripheral_clk_config.h | 418 +++ .../atmel-samd/asf4_conf/saml21/usbd_config.h | 850 +++++ 16 files changed, 8026 insertions(+) create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_adc_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_dac_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_dmac_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_mclk_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_nvmctrl_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_osc32kctrl_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_systick_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/hpl_usb_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h create mode 100644 ports/atmel-samd/asf4_conf/saml21/usbd_config.h diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_adc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_adc_config.h new file mode 100644 index 00000000000..82d367a66bb --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_adc_config.h @@ -0,0 +1,311 @@ +/* Auto-generated config file hpl_adc_config.h */ +#ifndef HPL_ADC_CONFIG_H +#define HPL_ADC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_ADC_0_ENABLE +#define CONF_ADC_0_ENABLE 1 +#endif + +// Basic Configuration + +// Conversion Result Resolution +// <0x0=>12-bit +// <0x1=>16-bit (averaging must be enabled) +// <0x2=>10-bit +// <0x3=>8-bit +// Defines the bit resolution for the ADC sample values (RESSEL) +// adc_resolution +#ifndef CONF_ADC_0_RESSEL +#define CONF_ADC_0_RESSEL 0x0 +#endif + +// Reference Selection +// <0x0=>Internal bandgap reference +// <0x1=>1/1.6 VDDANA +// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V) +// <0x3=>External reference A +// <0x4=>External reference B +// <0x5=>VDDANA +// Select the reference for the ADC (REFSEL) +// adc_reference +#ifndef CONF_ADC_0_REFSEL +#define CONF_ADC_0_REFSEL 0x0 +#endif + +// Prescaler configuration +// <0x0=>Peripheral clock divided by 2 +// <0x1=>Peripheral clock divided by 4 +// <0x2=>Peripheral clock divided by 8 +// <0x3=>Peripheral clock divided by 16 +// <0x4=>Peripheral clock divided by 32 +// <0x5=>Peripheral clock divided by 64 +// <0x6=>Peripheral clock divided by 128 +// <0x7=>Peripheral clock divided by 256 +// These bits define the ADC clock relative to the peripheral clock (PRESCALER) +// adc_prescaler +#ifndef CONF_ADC_0_PRESCALER +#define CONF_ADC_0_PRESCALER 0x1 +#endif + +// Free Running Mode +// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN) +// adc_freerunning_mode +#ifndef CONF_ADC_0_FREERUN +#define CONF_ADC_0_FREERUN 0 +#endif + +// Differential Mode +// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE) +// adc_differential_mode +#ifndef CONF_ADC_0_DIFFMODE +#define CONF_ADC_0_DIFFMODE 0 +#endif + +// Positive Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x08=>ADC AIN8 pin +// <0x09=>ADC AIN9 pin +// <0x0A=>ADC AIN10 pin +// <0x0B=>ADC AIN11 pin +// <0x0C=>ADC AIN12 pin +// <0x0D=>ADC AIN13 pin +// <0x0E=>ADC AIN14 pin +// <0x0F=>ADC AIN15 pin +// <0x10=>ADC AIN16 pin +// <0x11=>ADC AIN17 pin +// <0x12=>ADC AIN18 pin +// <0x13=>ADC AIN19 pin +// <0x14=>ADC AIN20 pin +// <0x15=>ADC AIN21 pin +// <0x16=>ADC AIN22 pin +// <0x17=>ADC AIN23 pin +// <0x18=>Temperature reference +// <0x19=>Bandgap voltage +// <0x1A=>1/4 scaled core supply +// <0x1B=>1/4 scaled I/O supply +// <0x1C=>DAC output +// <0x1D=>1/4 Scaled VBAT Supply +// <0x1E=>OPAMP0 or OPAMP1 Output +// <0x1F=>OPAMP2 Output +// These bits define the Mux selection for the positive ADC input. (MUXPOS) +// adc_pinmux_positive +#ifndef CONF_ADC_0_MUXPOS +#define CONF_ADC_0_MUXPOS 0x0 +#endif + +// Negative Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x18=>Internal ground +// These bits define the Mux selection for the negative ADC input. (MUXNEG) +// adc_pinmux_negative +#ifndef CONF_ADC_0_MUXNEG +#define CONF_ADC_0_MUXNEG 0x0 +#endif + +// + +// Advanced Configuration +// adc_advanced_settings +#ifndef CONF_ADC_0_ADVANCED +#define CONF_ADC_0_ADVANCED 0 +#endif + +// Run in standby +// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY) +// adc_arch_runstdby +#ifndef CONF_ADC_0_RUNSTDBY +#define CONF_ADC_0_RUNSTDBY 0 +#endif + +// Debug Run +// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN) +// adc_arch_dbgrun +#ifndef CONF_ADC_0_DBGRUN +#define CONF_ADC_0_DBGRUN 0 +#endif + +// On Demand Control +// Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND) +// adc_arch_ondemand +#ifndef CONF_ADC_0_ONDEMAND +#define CONF_ADC_0_ONDEMAND 0 +#endif + +// Left-Adjusted Result +// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ) +// adc_arch_leftadj +#ifndef CONF_ADC_0_LEFTADJ +#define CONF_ADC_0_LEFTADJ 0 +#endif + +// Reference Buffer Offset Compensation Enable +// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP) +// adc_arch_refcomp +#ifndef CONF_ADC_0_REFCOMP +#define CONF_ADC_0_REFCOMP 0 +#endif + +// Comparator Offset Compensation Enable +// This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP) +// adc_arch_offcomp +#ifndef CONF_ADC_0_OFFCOMP +#define CONF_ADC_0_OFFCOMP 0 +#endif + +// Digital Correction Logic Enabled +// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN) +// adc_arch_corren +#ifndef CONF_ADC_0_CORREN +#define CONF_ADC_0_CORREN 0 +#endif + +// Offset Correction Value <0-4095> +// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR) +// adc_arch_offsetcorr +#ifndef CONF_ADC_0_OFFSETCORR +#define CONF_ADC_0_OFFSETCORR 0 +#endif + +// Gain Correction Value <0-4095> +// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR) +// adc_arch_gaincorr +#ifndef CONF_ADC_0_GAINCORR +#define CONF_ADC_0_GAINCORR 0 +#endif + +// Adjusting Result / Division Coefficient <0-7> +// These bits define the division coefficient in 2n steps. (ADJRES) +// adc_arch_adjres +#ifndef CONF_ADC_0_ADJRES +#define CONF_ADC_0_ADJRES 0x0 +#endif + +// Number of Samples to be Collected +// <0x0=>1 sample +// <0x1=>2 samples +// <0x2=>4 samples +// <0x3=>8 samples +// <0x4=>16 samples +// <0x5=>32 samples +// <0x6=>64 samples +// <0x7=>128 samples +// <0x8=>256 samples +// <0x9=>512 samples +// <0xA=>1024 samples +// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM) +// adc_arch_samplenum +#ifndef CONF_ADC_0_SAMPLENUM +#define CONF_ADC_0_SAMPLENUM 0x0 +#endif + +// Sampling Time Length <0-63> +// These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) +// adc_arch_samplen +#ifndef CONF_ADC_0_SAMPLEN +#define CONF_ADC_0_SAMPLEN 0 +#endif + +// Window Monitor Mode +// <0x0=>No window mode +// <0x1=>Mode 1: RESULT above lower threshold +// <0x2=>Mode 2: RESULT beneath upper threshold +// <0x3=>Mode 3: RESULT inside lower and upper threshold +// <0x4=>Mode 4: RESULT outside lower and upper threshold +// These bits enable and define the window monitor mode. (WINMODE) +// adc_arch_winmode +#ifndef CONF_ADC_0_WINMODE +#define CONF_ADC_0_WINMODE 0x0 +#endif + +// Window Monitor Lower Threshold <0-65535> +// If the window monitor is enabled, these bits define the lower threshold value. (WINLT) +// adc_arch_winlt +#ifndef CONF_ADC_0_WINLT +#define CONF_ADC_0_WINLT 0 +#endif + +// Window Monitor Upper Threshold <0-65535> +// If the window monitor is enabled, these bits define the lower threshold value. (WINUT) +// adc_arch_winut +#ifndef CONF_ADC_0_WINUT +#define CONF_ADC_0_WINUT 0 +#endif + +// Bitmask for positive input sequence <0-4294967295> +// Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device). +// adc_arch_seqen +#ifndef CONF_ADC_0_SEQEN +#define CONF_ADC_0_SEQEN 0x0 +#endif + +// + +// Event Control +// adc_arch_event_settings +#ifndef CONF_ADC_0_EVENT_CONTROL +#define CONF_ADC_0_EVENT_CONTROL 0 +#endif + +// Window Monitor Event Out +// Enables event output on window event (WINMONEO) +// adc_arch_winmoneo +#ifndef CONF_ADC_0_WINMONEO +#define CONF_ADC_0_WINMONEO 0 +#endif + +// Result Ready Event Out +// Enables event output on result ready event (RESRDEO) +// adc_arch_resrdyeo +#ifndef CONF_ADC_0_RESRDYEO +#define CONF_ADC_0_RESRDYEO 0 +#endif + +// Invert flush Event Signal +// Invert the flush event input signal (FLUSHINV) +// adc_arch_flushinv +#ifndef CONF_ADC_0_FLUSHINV +#define CONF_ADC_0_FLUSHINV 0 +#endif + +// Trigger Flush On Event +// Trigger an ADC pipeline flush on event (FLUSHEI) +// adc_arch_flushei +#ifndef CONF_ADC_0_FLUSHEI +#define CONF_ADC_0_FLUSHEI 0 +#endif + +// Invert Start Conversion Event Signal +// Invert the start conversion event input signal (STARTINV) +// adc_arch_startinv +#ifndef CONF_ADC_0_STARTINV +#define CONF_ADC_0_STARTINV 0 +#endif + +// Trigger Conversion On Event +// Trigger a conversion on event. (STARTEI) +// adc_arch_startei +#ifndef CONF_ADC_0_STARTEI +#define CONF_ADC_0_STARTEI 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_ADC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_dac_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_dac_config.h new file mode 100644 index 00000000000..24a8a116cc4 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_dac_config.h @@ -0,0 +1,169 @@ +/* Auto-generated config file hpl_dac_config.h */ +#ifndef HPL_DAC_CONFIG_H +#define HPL_DAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic configuration +// Reference Selection +// <0x00=> Unbuffered external voltage reference +// <0x01=> Voltage supply +// <0x02=> Buffered external voltage reference +// <0x03=> Internal bandgap reference +// dac_arch_refsel +#ifndef CONF_DAC_REFSEL +#define CONF_DAC_REFSEL 0 +#endif + +// Differential mode +// Indicates whether the differential mode is enabled or not +// dac_arch_diff +#ifndef CONF_DAC_DIFF +#define CONF_DAC_DIFF 0 +#endif +// + +// Advanced Configuration +// dac_advanced_settings +#ifndef CONF_DAC_ADVANCED_CONFIG +#define CONF_DAC_ADVANCED_CONFIG 0 +#endif + +// Debug Run +// Indicate whether running when CPU is halted +// adc_arch_dbgrun +#ifndef CONF_DAC_DBGRUN +#define CONF_DAC_DBGRUN 1 +#endif + +// Channel 0 configuration +// Left Adjusted Data +// Indicate how the data is adjusted in the Data and Data Buffer register +// dac0_arch_leftadj +#ifndef CONF_DAC0_LEFTADJ +#define CONF_DAC0_LEFTADJ 0 +#endif + +// Current control +// <0=> GCLK_DAC <= 1.2MHz (100kSPS) +// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) +// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) +// This defines the current in output buffer according to conversion rate +// dac0_arch_cctrl +#ifndef CONF_DAC0_CCTRL +#define CONF_DAC0_CCTRL 0 +#endif + +// Run in standby +// Indicates whether the DAC channel will continue running in standby sleep mode or not +// dac0_arch_runstdby +#ifndef CONF_DAC0_RUNSTDBY +#define CONF_DAC0_RUNSTDBY 0 +#endif + +// Dithering Mode +// Indicate whether dithering mode is enabled +// dac0_arch_ditrher +#ifndef CONF_DAC0_DITHER +#define CONF_DAC0_DITHER 0 +#endif + +// Refresh period <0x00-0xFF> +// This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us +// dac0_arch_refresh +#ifndef CONF_DAC0_REFRESH +#define CONF_DAC0_REFRESH 0 +#endif +// +// Channel 1 configuration +// Left Adjusted Data +// Indicate how the data is adjusted in the Data and Data Buffer register +// dac1_arch_leftadj +#ifndef CONF_DAC1_LEFTADJ +#define CONF_DAC1_LEFTADJ 0 +#endif + +// Current control +// <0=> GCLK_DAC <= 1.2MHz (100kSPS) +// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) +// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) +// This defines the current in output buffer according to conversion rate +// dac1_arch_cctrl +#ifndef CONF_DAC1_CCTRL +#define CONF_DAC1_CCTRL 0 +#endif + +// Run in standby +// Indicates whether the DAC channel will continue running in standby sleep mode or not +// dac1_arch_runstdby +#ifndef CONF_DAC1_RUNSTDBY +#define CONF_DAC1_RUNSTDBY 0 +#endif + +// Dithering Mode +// Indicate whether dithering mode is enabled +// dac1_arch_ditrher +#ifndef CONF_DAC1_DITHER +#define CONF_DAC1_DITHER 0 +#endif + +// Refresh period <0x00-0xFF> +// This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us +// dac1_arch_refresh +#ifndef CONF_DAC1_REFRESH +#define CONF_DAC1_REFRESH 0 +#endif +// + +// Event configuration +// Inversion of DAC 0 event +// <0=> Detection on rising edge pf the input event +// <1=> Detection on falling edge pf the input event +// This defines the edge detection of the input event +// dac_arch_invei0 +#ifndef CONF_DAC_INVEI0 +#define CONF_DAC_INVEI0 0 +#endif + +// Data Buffer of DAC 0 Empty Event Output +// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// dac_arch_emptyeo_0 +#ifndef CONF_DAC_EMPTYEO0 +#define CONF_DAC_EMPTYEO0 0 +#endif + +// Start Conversion Event Input DAC 0 +// Indicate whether Start input event is enabled +// dac_arch_startei_0 +#ifndef CONF_DAC_STARTEI0 +#define CONF_DAC_STARTEI0 0 +#endif +// Inversion of DAC 1 event +// <0=> Detection on rising edge pf the input event +// <1=> Detection on falling edge pf the input event +// This defines the edge detection of the input event +// dac_arch_invei1 +#ifndef CONF_DAC_INVEI1 +#define CONF_DAC_INVEI1 0 +#endif + +// Data Buffer of DAC 1 Empty Event Output +// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// dac_arch_emptyeo_1 +#ifndef CONF_DAC_EMPTYEO1 +#define CONF_DAC_EMPTYEO1 0 +#endif + +// Start Conversion Event Input DAC 1 +// Indicate whether Start input event is enabled +// dac_arch_startei_1 +#ifndef CONF_DAC_STARTEI1 +#define CONF_DAC_STARTEI1 0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_DAC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_dmac_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_dmac_config.h new file mode 100644 index 00000000000..78aed2d5ec2 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_dmac_config.h @@ -0,0 +1,3154 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 0 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 0 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// Data Transfer Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the data transfer operation +// dmac_dqos +#ifndef CONF_DMAC_DQOS +#define CONF_DMAC_DQOS 0 +#endif + +// Fetch Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the fetch operation +// dmac_fqos +#ifndef CONF_DMAC_FQOS +#define CONF_DMAC_FQOS 0 +#endif + +// Write-Back Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the write-back operation +// dmac_wrbqos +#ifndef CONF_DMAC_WRBQOS +#define CONF_DMAC_WRBQOS 0 +#endif + +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 0 is enabled or not +// dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 1 is enabled or not +// dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 2 is enabled or not +// dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 3 is enabled or not +// dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 4 is enabled or not +// dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 5 is enabled or not +// dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 6 is enabled or not +// dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 7 is enabled or not +// dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 8 is enabled or not +// dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 9 is enabled or not +// dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 10 is enabled or not +// dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 11 is enabled or not +// dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 12 is enabled or not +// dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 13 is enabled or not +// dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 14 is enabled or not +// dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 15 is enabled or not +// dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h new file mode 100644 index 00000000000..cd563697438 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h @@ -0,0 +1,616 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DFLL48M +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_mclk_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_mclk_config.h new file mode 100644 index 00000000000..94bf182dea6 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_mclk_config.h @@ -0,0 +1,98 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_nvmctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_nvmctrl_config.h new file mode 100644 index 00000000000..88d6bb93ff4 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_nvmctrl_config.h @@ -0,0 +1,38 @@ +/* Auto-generated config file hpl_nvmctrl_config.h */ +#ifndef HPL_NVMCTRL_CONFIG_H +#define HPL_NVMCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings + +// Read Mode Selection +// <0x00=> No Miss Penalty +// <0x01=> Low Power +// <0x02=> Deterministic +// nvm_arch_read_mode +#ifndef CONF_NVM_READ_MODE +#define CONF_NVM_READ_MODE 0 +#endif + +// Power Reduction Mode During Sleep +// <0x00=> Wake On Access +// <0x01=> Wake Up Instant +// <0x03=> Disabled +// nvm_arch_sleepprm +#ifndef CONF_NVM_SLEEPPRM +#define CONF_NVM_SLEEPPRM 0 +#endif + +// Cache Disable +// Indicate whether cache is disable or not +// nvm_arch_cache +#ifndef CONF_NVM_CACHE +#define CONF_NVM_CACHE 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_NVMCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_osc32kctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_osc32kctrl_config.h new file mode 100644 index 00000000000..897774b905c --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_osc32kctrl_config.h @@ -0,0 +1,208 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// +// +// 32kHz Internal Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 0 +#endif + +// 32kHz Internal Oscillator Control +// Enable +// Indicates whether 32kHz Internal Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc32k_arch_calib_enable +#ifndef CONF_OSC32K_CALIB_ENABLE +#define CONF_OSC32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x7F> +// osc32k_arch_calib +#ifndef CONF_OSC32K_CALIB +#define CONF_OSC32K_CALIB 0x0 +#endif + +// Start-Up Time +// <0x0=>92us +// <0x1=>122us +// <0x2=>183us +// <0x3=>305us +// <0x4=>549us +// <0x5=>1038us +// <0x6=>2014us +// <0x7=>3967us +// osc32k_arch_startup +#ifndef CONF_OSC32K_STARTUP +#define CONF_OSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc32k_arch_ondemand +#ifndef CONF_OSC32K_ONDEMAND +#define CONF_OSC32K_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc32k_arch_runstdby +#ifndef CONF_OSC32K_RUNSTDBY +#define CONF_OSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// osc32k_arch_en1k +#ifndef CONF_OSC32K_EN1K +#define CONF_OSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// osc32k_arch_en32k +#ifndef CONF_OSC32K_EN32K +#define CONF_OSC32K_EN32K 0 +#endif +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x1F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h new file mode 100644 index 00000000000..c81ee97fd7a --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h @@ -0,0 +1,462 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC is enabled or not +// enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// Frequency <400000-32000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP 0x0 +#endif + +// Automatic Amplitude Gain Control +// Indicates whether Automatic Amplitude Gain Control is enabled or not +// xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// External Multipurpose Crystal Oscillator Gain +// <0x0=>2MHz +// <0x1=>4MHz +// <0x2=>8MHz +// <0x3=>16MHz +// <0x4=>30MHz +// xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif +// +// + +// 16MHz Internal Oscillator Configuration +// Indicates whether configuration for OSC8M is enabled or not +// enable_osc16m +#ifndef CONF_OSC16M_CONFIG +#define CONF_OSC16M_CONFIG 1 +#endif + +// 16MHz Internal Oscillator Control +// Enable +// Indicates whether 16MHz Internal Oscillator is enabled or not +// osc16m_arch_enable +#ifndef CONF_OSC16M_ENABLE +#define CONF_OSC16M_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc16m_arch_ondemand +#ifndef CONF_OSC16M_ONDEMAND +#define CONF_OSC16M_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc16m_arch_runstdby +#ifndef CONF_OSC16M_RUNSTDBY +#define CONF_OSC16M_RUNSTDBY 0 +#endif + +// Oscillator Frequency Selection(Mhz) +// 4 +// 8 +// 12 +// 16 +// This defines the oscillator frequency (Mhz) +// osc16m_freq +#ifndef CONF_OSC16M_FSEL +#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc16m_arch_calib_enable +#ifndef CONF_OSC16M_CALIB_ENABLE +#define CONF_OSC16M_CALIB_ENABLE 0 +#endif + +// 4MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_4m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_4M_FCAL 0 +#endif + +// 4MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_4m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_4M_TCAL 0 +#endif + +// 8MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_8m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_8M_FCAL 0 +#endif + +// 8MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_8m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_8M_TCAL 0 +#endif + +// 12MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_12m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_12M_FCAL 0 +#endif + +// 12MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_12m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_12M_TCAL 0 +#endif + +// 16MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_16M_FCAL 0 +#endif + +// 16MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_16m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_16M_TCAL 0 +#endif +// +// + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll48m +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 1 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// dfll48m_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll48m_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 1 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 0 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll48m_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 1 +#endif + +// Fine Maximum Step <0x0-0x3FF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll48m_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0x3FF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x200) +#endif + +// + +// + +// + +// DPLL Configuration +// Indicates whether configuration for DPLL is enabled or not +// enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// fdpll96m_ref_clock +#ifndef CONF_DPLL_GCLK +#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K + +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0xF> +// fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0xFFF> +// fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x3FF> +// fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// Lock Time +// <0=>No time-out, automatic lock +// <4=>The Time-out if no lock within 8 ms +// <5=>The Time-out if no lock within 9 ms +// <6=>The Time-out if no lock within 10 ms +// <7=>The Time-out if no lock within 11 ms +// fdpll96m_arch_ltime +#ifndef CONF_DPLL_LTIME +#define CONF_DPLL_LTIME 0 +#endif + +// Reference Clock Selection +// <0=>XOSC32K clock reference +// <1=>XOSC clock reference +// <2=>GCLK clock reference +// fdpll96m_arch_refclk +#ifndef CONF_DPLL_REFCLK +#define CONF_DPLL_REFCLK 0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll96m_arch_wuf +#ifndef CONF_DPLL_WUF +#define CONF_DPLL_WUF 0 +#endif + +// Low-Power Enable +// Indicates whether Low-Power Enable is enabled or not +// fdpll96m_arch_lpen +#ifndef CONF_DPLL_LPEN +#define CONF_DPLL_LPEN 0 +#endif + +// Reference Clock Selection +// <0=>Default filter mode +// <1=>Low bandwidth filter +// <2=>High bandwidth filter +// <3=>High damping filter +// fdpll96m_arch_filter +#ifndef CONF_DPLL_FILTER +#define CONF_DPLL_FILTER 0 +#endif + +// Output Clock Prescaler +// 1 +// 2 +// 4 +// fdpll96m_presc +#ifndef CONF_DPLL_PRESC +#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h new file mode 100644 index 00000000000..1efce33e332 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h @@ -0,0 +1,284 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h new file mode 100644 index 00000000000..481b831b8c4 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h @@ -0,0 +1,127 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// Force reset RTC on initialization +// Force RTC to reset on initialization. +// Note that the previous power down data in RTC is lost if it's enabled. +// rtc_arch_init_reset +#ifndef CONF_RTC_INIT_RESET +#define CONF_RTC_INIT_RESET 1 +#endif + +// Prescaler configuration +// <0x0=>OFF(Peripheral clock divided by 1) +// <0x1=>Peripheral clock divided by 1 +// <0x2=>Peripheral clock divided by 2 +// <0x3=>Peripheral clock divided by 4 +// <0x4=>Peripheral clock divided by 8 +// <0x5=>Peripheral clock divided by 16 +// <0x6=>Peripheral clock divided by 32 +// <0x7=>Peripheral clock divided by 64 +// <0x8=>Peripheral clock divided by 128 +// <0x9=>Peripheral clock divided by 256 +// <0xA=>Peripheral clock divided by 512 +// <0xB=>Peripheral clock divided by 1024 +// These bits define the RTC clock relative to the peripheral clock +// rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER +#define CONF_RTC_PRESCALER 0x0 + +#endif + +// Compare Value <1-4294967295> +// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), +// by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms. +// rtc_arch_comp_val + +#ifndef CONF_RTC_COMP_VAL + +#define CONF_RTC_COMP_VAL 32 + +#endif + +// Event control +// rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// Periodic Interval 0 Event Output +// This bit indicates whether Periodic interval 0 event is enabled and will be generated +// rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// Periodic Interval 1 Event Output +// This bit indicates whether Periodic interval 1 event is enabled and will be generated +// rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// Periodic Interval 2 Event Output +// This bit indicates whether Periodic interval 2 event is enabled and will be generated +// rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// Periodic Interval 3 Event Output +// This bit indicates whether Periodic interval 3 event is enabled and will be generated +// rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// Periodic Interval 4 Event Output +// This bit indicates whether Periodic interval 4 event is enabled and will be generated +// rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// Periodic Interval 5 Event Output +// This bit indicates whether Periodic interval 5 event is enabled and will be generated +// rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// Periodic Interval 6 Event Output +// This bit indicates whether Periodic interval 6 event is enabled and will be generated +// rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// Periodic Interval 7 Event Output +// This bit indicates whether Periodic interval 7 event is enabled and will be generated +// rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// Compare 0 Event Output +// This bit indicates whether Compare O event is enabled and will be generated +// rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// Overflow Event Output +// This bit indicates whether Overflow event is enabled and will be generated +// rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h new file mode 100644 index 00000000000..8a7b4395fe3 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h @@ -0,0 +1,712 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_0_SPI_MODE +#define CONF_SERCOM_0_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_0_SPI_RXEN +#define CONF_SERCOM_0_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_0_SPI_CHSIZE +#define CONF_SERCOM_0_SPI_CHSIZE 0x0 +#endif +// Baud rate <1-12000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_0_SPI_BAUD +#define CONF_SERCOM_0_SPI_BAUD 50000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_0_SPI_ADVANCED +#define CONF_SERCOM_0_SPI_ADVANCED 0 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE +#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_0_SPI_DORD +#define CONF_SERCOM_0_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_0_SPI_CPOL +#define CONF_SERCOM_0_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_0_SPI_CPHA +#define CONF_SERCOM_0_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_0_SPI_IBON +#define CONF_SERCOM_0_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_0_SPI_RUNSTDBY +#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_0_SPI_DBGSTOP +#define CONF_SERCOM_0_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_0_SPI_AMODE_EN +#define CONF_SERCOM_0_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_AMODE +#define CONF_SERCOM_0_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDR +#define CONF_SERCOM_0_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDRMASK +#define CONF_SERCOM_0_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_SSDE +#define CONF_SERCOM_0_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_MSSEN +#define CONF_SERCOM_0_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_0_SPI_PLOADEN +#define CONF_SERCOM_0_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_0_SPI_RXPO +#define CONF_SERCOM_0_SPI_RXPO 2 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_0_SPI_TXPO +#define CONF_SERCOM_0_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_0_SPI_BAUD_RATE +#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1 +#endif + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_1_I2CM_BAUD +#define CONF_SERCOM_1_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN +#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN +#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_1_I2CM_LOWTOUT +#define CONF_SERCOM_1_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_1_I2CM_INACTOUT +#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_1_I2CM_SDAHOLD +#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY +#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_1_I2CM_SPEED +#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215U +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10U)) +#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE +#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_1_I2CM_BAUD_RATE \ + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include + +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_2_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA09 */ +#endif + +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA08 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 4 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_3_SPI_MODE +#define CONF_SERCOM_3_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_3_SPI_RXEN +#define CONF_SERCOM_3_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_3_SPI_CHSIZE +#define CONF_SERCOM_3_SPI_CHSIZE 0x0 +#endif +// Baud rate <1-12000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_3_SPI_BAUD +#define CONF_SERCOM_3_SPI_BAUD 50000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_3_SPI_ADVANCED +#define CONF_SERCOM_3_SPI_ADVANCED 0 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE +#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_3_SPI_DORD +#define CONF_SERCOM_3_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_3_SPI_CPOL +#define CONF_SERCOM_3_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_3_SPI_CPHA +#define CONF_SERCOM_3_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_3_SPI_IBON +#define CONF_SERCOM_3_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_3_SPI_RUNSTDBY +#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_3_SPI_DBGSTOP +#define CONF_SERCOM_3_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_3_SPI_AMODE_EN +#define CONF_SERCOM_3_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_AMODE +#define CONF_SERCOM_3_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_ADDR +#define CONF_SERCOM_3_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_ADDRMASK +#define CONF_SERCOM_3_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_SSDE +#define CONF_SERCOM_3_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_MSSEN +#define CONF_SERCOM_3_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_3_SPI_PLOADEN +#define CONF_SERCOM_3_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_3_SPI_RXPO +#define CONF_SERCOM_3_SPI_RXPO 2 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_3_SPI_TXPO +#define CONF_SERCOM_3_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_3_SPI_BAUD_RATE +#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1 +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_systick_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_systick_config.h new file mode 100644 index 00000000000..a7f2f36208f --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h new file mode 100644 index 00000000000..d3175098b48 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h @@ -0,0 +1,206 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +// Basic settings +// Prescaler +// <0=> No division +// <1=> Divide by 2 +// <2=> Divide by 4 +// <3=> Divide by 8 +// <4=> Divide by 16 +// <5=> Divide by 64 +// <6=> Divide by 256 +// <7=> Divide by 1024 +// This defines the prescaler value +// tc_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0 +#endif +// + +// PWM Waveform Output settings +// Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// The unit of this value is us. +// tc_arch_wave_per_val +#ifndef CONF_TC0_WAVE_PER_VAL +#define CONF_TC0_WAVE_PER_VAL 0x3e8 +#endif + +// Waveform Duty Value (0.1%) <0x00-0x03E8> +// The unit of this value is 1/1000. +// tc_arch_wave_duty_val +#ifndef CONF_TC0_WAVE_DUTY_VAL +#define CONF_TC0_WAVE_DUTY_VAL 0x1f4 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 \ + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 64000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 256000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1024000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) +#endif + +// + +// Advanced settings +// Mode +// Counter in 16-bit mode +// Counter in 32-bit mode +// These bits mode +// tc_mode +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT16_Val +#endif + +/* Unused in 16/32 bit PWM mode */ +#ifndef CONF_TC0_PER +#define CONF_TC0_PER 0x32 +#endif + +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the will continue running in standby sleep mode or not +// tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// On-Demand +// Indicates whether the TC0's on-demand mode is on or not +// tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// Auto Lock +// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event +// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event +// tc_arch_alock +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CAPTEN0 0 +//#define CONF_TC0_CAPTEN1 0 +//#define CONF_TC0_COPEN0 0 +//#define CONF_TC0_COPEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_DIR 0 +//#define CONF_TC0_ONESHOT 0 +//#define CONF_TC0_LUPD 0 + +// Debug Running Mode +// Indicates whether the Debug Running Mode is enabled or not +// tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// Event control +// timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 0 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_INVEN0 0 +//#define CONF_TC0_INVEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_PERBUF 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CCBUF0 0 +//#define CONF_TC0_CCBUF1 0 + +// + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_usb_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_usb_config.h new file mode 100644 index 00000000000..73a9fea4421 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_usb_config.h @@ -0,0 +1,355 @@ +/* Auto-generated config file hpl_usb_config.h */ +#ifndef HPL_USB_CONFIG_H +#define HPL_USB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_USB_N_0 0 +#define CONF_USB_N_1 1 +#define CONF_USB_N_2 2 +#define CONF_USB_N_3 3 +#define CONF_USB_N_4 4 +#define CONF_USB_N_5 5 +#define CONF_USB_N_6 6 +#define CONF_USB_N_7 7 +#define CONF_USB_N_8 8 +#define CONF_USB_N_9 9 +#define CONF_USB_N_10 10 +#define CONF_USB_N_11 11 +#define CONF_USB_N_12 12 +#define CONF_USB_N_13 13 +#define CONF_USB_N_14 14 +#define CONF_USB_N_15 15 + +#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) +#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) + +// USB Device HAL Configuration + +// Max number of endpoints supported +// Limits the number of endpoints (described by EP address) can be used in app. +// 1 (EP0 only) +// 2 (EP0 + 1 endpoint) +// 3 (EP0 + 2 endpoints) +// 4 (EP0 + 3 endpoints) +// 5 (EP0 + 4 endpoints) +// 6 (EP0 + 5 endpoints) +// 7 (EP0 + 6 endpoints) +// 8 (EP0 + 7 endpoints) +// Max possible (by "Max Endpoint Number" config) +// usbd_num_ep_sp +#ifndef CONF_USB_D_NUM_EP_SP +#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 +#endif + +// + +// Max Endpoint Number supported +// Limits the max endpoint number. +// USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. +// Reduce the value according to specific device design, to cut-off memory usage. +// 0 (only EP0) +// 1 (EP 0x81 or 0x01) +// 2 (EP 0x82 or 0x02) +// 3 (EP 0x83 or 0x03) +// 4 (EP 0x84 or 0x04) +// 5 (EP 0x85 or 0x05) +// 6 (EP 0x86 or 0x06) +// 7 (EP 0x87 or 0x07) +// Max possible (by HW) +// The number of physical endpoints - 1 +// usbd_arch_max_ep_n +#ifndef CONF_USB_D_MAX_EP_N +#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 +#endif + +// USB Speed Limit +// Limits the working speed of the device. +// Full speed +// Low Speed +// usbd_arch_speed +#ifndef CONF_USB_D_SPEED +#define CONF_USB_D_SPEED USB_SPEED_FS +#endif + +// Cache buffer size for EP0 +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// usb_arch_ep0_cache +#ifndef CONF_USB_EP0_CACHE +#define CONF_USB_EP0_CACHE 64 +#endif + +// Cache configuration EP1 +// Cache buffer size for EP1 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep1_cache +#ifndef CONF_USB_EP1_CACHE +#define CONF_USB_EP1_CACHE 64 +#endif + +// Cache buffer size for EP1 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep1_I_CACHE +#ifndef CONF_USB_EP1_I_CACHE +#define CONF_USB_EP1_I_CACHE 0 +#endif +// + +// Cache configuration EP2 +// Cache buffer size for EP2 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep2_cache +#ifndef CONF_USB_EP2_CACHE +#define CONF_USB_EP2_CACHE 64 +#endif + +// Cache buffer size for EP2 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep2_I_CACHE +#ifndef CONF_USB_EP2_I_CACHE +#define CONF_USB_EP2_I_CACHE 0 +#endif +// + +// Cache configuration EP3 +// Cache buffer size for EP3 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep3_cache +#ifndef CONF_USB_EP3_CACHE +#define CONF_USB_EP3_CACHE 64 +#endif + +// Cache buffer size for EP3 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep3_I_CACHE +#ifndef CONF_USB_EP3_I_CACHE +#define CONF_USB_EP3_I_CACHE 0 +#endif +// + +// Cache configuration EP4 +// Cache buffer size for EP4 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep4_cache +#ifndef CONF_USB_EP4_CACHE +#define CONF_USB_EP4_CACHE 64 +#endif + +// Cache buffer size for EP4 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep4_I_CACHE +#ifndef CONF_USB_EP4_I_CACHE +#define CONF_USB_EP4_I_CACHE 0 +#endif +// + +// Cache configuration EP5 +// Cache buffer size for EP5 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep5_cache +#ifndef CONF_USB_EP5_CACHE +#define CONF_USB_EP5_CACHE 64 +#endif + +// Cache buffer size for EP5 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep5_I_CACHE +#ifndef CONF_USB_EP5_I_CACHE +#define CONF_USB_EP5_I_CACHE 0 +#endif +// + +// Cache configuration EP6 +// Cache buffer size for EP6 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep6_cache +#ifndef CONF_USB_EP6_CACHE +#define CONF_USB_EP6_CACHE 64 +#endif + +// Cache buffer size for EP6 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep6_I_CACHE +#ifndef CONF_USB_EP6_I_CACHE +#define CONF_USB_EP6_I_CACHE 0 +#endif +// + +// Cache configuration EP7 +// Cache buffer size for EP7 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep7_cache +#ifndef CONF_USB_EP7_CACHE +#define CONF_USB_EP7_CACHE 64 +#endif + +// Cache buffer size for EP7 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep7_I_CACHE +#ifndef CONF_USB_EP7_I_CACHE +#define CONF_USB_EP7_I_CACHE 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_USB_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h new file mode 100644 index 00000000000..5bc487b5a75 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h @@ -0,0 +1,418 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ADC Clock Source +// adc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for ADC. +#ifndef CONF_GCLK_ADC_SRC +#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_ADC_FREQUENCY + * \brief ADC's Clock frequency + */ +#ifndef CONF_GCLK_ADC_FREQUENCY +#define CONF_GCLK_ADC_FREQUENCY 48000000 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 48000000 +#endif + +// RTC Clock Source +// rtc_clk_selection +// RTC source +// Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 400000 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC0_SRC +#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC0_FREQUENCY + * \brief TC0's Clock frequency + */ +#ifndef CONF_GCLK_TC0_FREQUENCY +#define CONF_GCLK_TC0_FREQUENCY 48000000 +#endif + +// DAC Clock Source + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// dac_gclk_selection +// Select the clock source for DAC. +#ifndef CONF_GCLK_DAC_SRC +#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_DAC_FREQUENCY + * \brief DAC's Clock frequency + */ +#ifndef CONF_GCLK_DAC_FREQUENCY +#define CONF_GCLK_DAC_FREQUENCY 48000000 +#endif + +// USB Clock Source +// usb_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for USB. +#ifndef CONF_GCLK_USB_SRC +#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK0_Val + +#endif + +/** + * \def CONF_GCLK_USB_FREQUENCY + * \brief USB's Clock frequency + */ +#ifndef CONF_GCLK_USB_FREQUENCY +#define CONF_GCLK_USB_FREQUENCY 48000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/usbd_config.h b/ports/atmel-samd/asf4_conf/saml21/usbd_config.h new file mode 100644 index 00000000000..be1fa3c9e07 --- /dev/null +++ b/ports/atmel-samd/asf4_conf/saml21/usbd_config.h @@ -0,0 +1,850 @@ +/* Auto-generated config file usbd_config.h */ +#ifndef USBD_CONFIG_H +#define USBD_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ---- USB Device Stack Core Options ---- + +// High Speed Support +// Enable high speed specific descriptors support, e.g., DeviceQualifierDescriptor and OtherSpeedConfiguration Descriptor. +// High speed support require descriptors description array on start, for LS/FS and HS support in first and second place. +// usbd_hs_sp +#ifndef CONF_USBD_HS_SP +#define CONF_USBD_HS_SP 0 +#endif + +// ---- USB Device Stack Composite Options ---- + +// Enable String Descriptors +// usb_composite_str_en +#ifndef CONF_USB_COMPOSITE_STR_EN +#define CONF_USB_COMPOSITE_STR_EN 0 +#endif +// Language IDs +// Language IDs in c format, split by comma (E.g., 0x0409 ...) +// usb_composite_langid +#ifndef CONF_USB_COMPOSITE_LANGID +#define CONF_USB_COMPOSITE_LANGID "0x0409" +#endif + +#ifndef CONF_USB_COMPOSITE_LANGID_DESC +#define CONF_USB_COMPOSITE_LANGID_DESC +#endif +// + +// Composite Device Descriptor + +// bcdUSB +// <0x0200=> USB 2.0 version +// <0x0210=> USB 2.1 version +// usb_composite_bcdusb +#ifndef CONF_USB_COMPOSITE_BCDUSB +#define CONF_USB_COMPOSITE_BCDUSB 0x200 +#endif + +// bMaxPackeSize0 +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_bmaxpksz0 +#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 +#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 +#endif + +// idVender <0x0000-0xFFFF> +// usb_composite_idvender +#ifndef CONF_USB_COMPOSITE_IDVENDER +#define CONF_USB_COMPOSITE_IDVENDER 0x3eb +#endif + +// idProduct <0x0000-0xFFFF> +// usb_composite_idproduct +#ifndef CONF_USB_COMPOSITE_IDPRODUCT +#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421 +#endif + +// bcdDevice <0x0000-0xFFFF> +// usb_composite_bcddevice +#ifndef CONF_USB_COMPOSITE_BCDDEVICE +#define CONF_USB_COMPOSITE_BCDDEVICE 0x100 +#endif + +// Enable string descriptor of iManufact +// usb_composite_imanufact_en +#ifndef CONF_USB_COMPOSITE_IMANUFACT_EN +#define CONF_USB_COMPOSITE_IMANUFACT_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_IMANUFACT +#define CONF_USB_COMPOSITE_IMANUFACT (CONF_USB_COMPOSITE_IMANUFACT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN)) +#endif + +// Unicode string of iManufact +// usb_composite_imanufact_str +#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR +#define CONF_USB_COMPOSITE_IMANUFACT_STR "Atmel" +#endif + +#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR_DESC +#define CONF_USB_COMPOSITE_IMANUFACT_STR_DESC +#endif + +// + +// Enable string descriptor of iProduct +// usb_composite_iproduct_en +#ifndef CONF_USB_COMPOSITE_IPRODUCT_EN +#define CONF_USB_COMPOSITE_IPRODUCT_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_IPRODUCT +#define CONF_USB_COMPOSITE_IPRODUCT \ + (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) +#endif + +// Unicode string of iProduct +// usb_composite_iproduct_str +#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR +#define CONF_USB_COMPOSITE_IPRODUCT_STR "Composite Demo" +#endif + +#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR_DESC +#define CONF_USB_COMPOSITE_IPRODUCT_STR_DESC +#endif + +// + +// Enable string descriptor of iSerialNum +// usb_composite_iserialnum_en +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_EN +#define CONF_USB_COMPOSITE_ISERIALNUM_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_ISERIALNUM +#define CONF_USB_COMPOSITE_ISERIALNUM \ + (CONF_USB_COMPOSITE_ISERIALNUM_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) +#endif + +// Unicode string of iSerialNum +// usb_composite_iserialnum_str +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR +#define CONF_USB_COMPOSITE_ISERIALNUM_STR "123456789ABCDEF" +#endif + +#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC +#define CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC +#endif + +// + +// bNumConfigurations <0x01-0xFF> +// usb_composite_bnumconfig +#ifndef CONF_USB_COMPOSITE_BNUMCONFIG +#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1 +#endif + +// + +// Composite Configuration Descriptor +// bConfigurationValue <0x01-0xFF> +// usb_composite_bconfigval +#ifndef CONF_USB_COMPOSITE_BCONFIGVAL +#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1 +#endif +// Enable string descriptor of iConfig +// usb_composite_iconfig_en +#ifndef CONF_USB_COMPOSITE_ICONFIG_EN +#define CONF_USB_COMPOSITE_ICONFIG_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_ICONFIG +#define CONF_USB_COMPOSITE_ICONFIG \ + (CONF_USB_COMPOSITE_ICONFIG_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ + + CONF_USB_COMPOSITE_ICONFIG_EN)) +#endif + +// Unicode string of iConfig +// usb_composite_iconfig_str +#ifndef CONF_USB_COMPOSITE_ICONFIG_STR +#define CONF_USB_COMPOSITE_ICONFIG_STR "" +#endif + +#ifndef CONF_USB_COMPOSITE_ICONFIG_STR_DESC +#define CONF_USB_COMPOSITE_ICONFIG_STR_DESC +#endif + +// + +// bmAttributes +// <0x80=> Bus power supply, not support for remote wakeup +// <0xA0=> Bus power supply, support for remote wakeup +// <0xC0=> Self powered, not support for remote wakeup +// <0xE0=> Self powered, support for remote wakeup +// usb_composite_bmattri +#ifndef CONF_USB_COMPOSITE_BMATTRI +#define CONF_USB_COMPOSITE_BMATTRI 0x80 +#endif + +// bMaxPower <0x00-0xFF> +// usb_composite_bmaxpower +#ifndef CONF_USB_COMPOSITE_BMAXPOWER +#define CONF_USB_COMPOSITE_BMAXPOWER 0x32 +#endif +// + +// CDC ACM Support +// usb_composite_cdc_acm_support +#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN +#define CONF_USB_COMPOSITE_CDC_ACM_EN 0 +#endif + +// CDC ACM Comm Interrupt IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_cdc_acm_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 +#endif + +// CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_cdc_acm_comm_int_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_cdc_acm_data_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 +#endif + +// CDC ACM Data BULK IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_cdc_acm_data_builin_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK IN Endpoint wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// usb_composite_cdc_acm_data_builin_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS 0x200 +#endif + +// CDC ACM Data BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_cdc_acm_data_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 +#endif + +// CDC ACM Data BULK OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_cdc_acm_data_buckout_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK OUT Endpoint wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// usb_composite_cdc_acm_data_buckout_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS 0x200 +#endif + +// CDC ACM Echo Demo generation +// conf_usb_composite_cdc_echo_demo +// Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo. +// Buf is packet buffer for data receive and echo back. +// The buffer is 4 byte aligned to support DMA. +#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO +#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0 +#endif + +// + +// HID Mouse Support +// usb_composite_hid_mouse_support +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN +#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0 +#endif + +// HID Mouse INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_hid_mouse_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83 +#endif + +// HID Mouse INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_hid_mouse_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 +#endif + +// HID Mouse Move Demo generation +// conf_usb_composite_hid_mouse_demo +// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// Button1 and button3 are the pins used for mouse moving left and right. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO +#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0 +#endif + +// + +// HID Keyboard Support +// usb_composite_hid_keyboard_support +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN +#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0 +#endif + +// HID Keyboard INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_hid_keyboard_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84 +#endif + +// HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_hid_keyboard_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8 +#endif + +// HID Keyboard INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_hid_keyboard_intout_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2 +#endif + +// HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_hid_keyboard_intout_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 +#endif + +// HID Keyboard Caps Lock Demo generation +// conf_usb_composite_hid_keyboard_demo +// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. +// Buffon2 is the pin used for keyboard CAPS LOCK simulation. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO +#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0 +#endif + +// + +// HID Generic Support +// usb_composite_hid_generic_support +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN +#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 +#endif + +// HID Generic INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_hid_generic_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85 +#endif + +// HID Generic INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_hid_generic_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40 +#endif + +// HID Generic INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_hid_generic_intout_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3 +#endif + +// HID Generic INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_generic_intout_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40 +#endif + +// + +// MSC Support +// usb_composite_msc_support +#ifndef CONF_USB_COMPOSITE_MSC_EN +#define CONF_USB_COMPOSITE_MSC_EN 0 +#endif + +// MSC BULK Endpoints wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes + +// usb_composite_msc_bulk_maxpksz +#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ +#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x40 +#endif + +// MSC BULK Endpoints wMaxPacketSize for High Speed +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// <0x0080=> 128 bytes +// <0x0100=> 256 bytes +// <0x0200=> 512 bytes + +// usb_composite_msc_bulk_maxpksz_hs +#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS +#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS 0x200 +#endif + +// MSC BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// <0x88=> EndpointAddress = 0x88 +// <0x89=> EndpointAddress = 0x89 + +// usb_composite_msc_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86 +#endif + +// MSC BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// <0x08=> EndpointAddress = 0x08 +// <0x09=> EndpointAddress = 0x09 + +// usb_composite_msc_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x4 +#endif + +// Enable Demo code for Disk LUN handling +// usb_composite_msc_demo_en +#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO +#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1 +#endif + +// Disk access cache/buffer of sectors if non-RAM disk (e.g., SD/MMC) enabled <1-64> +// conf_usb_msc_lun_buf_sectors +#ifndef CONF_USB_MSC_LUN_BUF_SECTORS +#define CONF_USB_MSC_LUN_BUF_SECTORS 4 +#endif + +// Enable Demo for RAM Disk +// conf_usb_msc_lun0_enable +#ifndef CONF_USB_MSC_LUN0_ENABLE +#define CONF_USB_MSC_LUN0_ENABLE 1 +#endif + +#ifndef CONF_USB_MSC_LUN0_TYPE +#define CONF_USB_MSC_LUN0_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun0_rmb +#ifndef CONF_USB_MSC_LUN0_RMB +#define CONF_USB_MSC_LUN0_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN0_ISO +#define CONF_USB_MSC_LUN0_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ECMA +#define CONF_USB_MSC_LUN0_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_ANSI +#define CONF_USB_MSC_LUN0_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_REPO +#define CONF_USB_MSC_LUN0_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN0_FACTORY +#define CONF_USB_MSC_LUN0_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT +#define CONF_USB_MSC_LUN0_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN0_PRODUCT_VERSION +#define CONF_USB_MSC_LUN0_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// Windows will not show disk less than 20K, so 22K is used to reserve more RAM for APP +// conf_usb_msc_lun0_capacity + +#ifndef CONF_USB_MSC_LUN0_CAPACITY +#define CONF_USB_MSC_LUN0_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN0_BLOCK_SIZE +#define CONF_USB_MSC_LUN0_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for SD/MMC Disk +// SD/MMC stack must be added before enable SD/MMC demo +// SD/MMC insert/eject not supported by this simple demo +// conf_usb_msc_lun1_enable +#ifndef CONF_USB_MSC_LUN1_ENABLE +#define CONF_USB_MSC_LUN1_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN1_TYPE +#define CONF_USB_MSC_LUN1_TYPE 0x00 +#endif + +// The disk is removable +// SD/MMC stack must be added before enable SD/MMC demo +// SD/MMC insert/eject not supported by this simple demo +// conf_usb_msc_lun1_rmb +#ifndef CONF_USB_MSC_LUN1_RMB +#define CONF_USB_MSC_LUN1_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN1_ISO +#define CONF_USB_MSC_LUN1_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ECMA +#define CONF_USB_MSC_LUN1_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_ANSI +#define CONF_USB_MSC_LUN1_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_REPO +#define CONF_USB_MSC_LUN1_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN1_FACTORY +#define CONF_USB_MSC_LUN1_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT +#define CONF_USB_MSC_LUN1_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_PRODUCT_VERSION +#define CONF_USB_MSC_LUN1_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN1_CAPACITY +#define CONF_USB_MSC_LUN1_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN1_BLOCK_SIZE +#define CONF_USB_MSC_LUN1_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for LUN 2 +// conf_usb_msc_lun2_enable +#ifndef CONF_USB_MSC_LUN2_ENABLE +#define CONF_USB_MSC_LUN2_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN2_TYPE +#define CONF_USB_MSC_LUN2_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun2_rmb +#ifndef CONF_USB_MSC_LUN2_RMB +#define CONF_USB_MSC_LUN2_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN2_ISO +#define CONF_USB_MSC_LUN2_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_ECMA +#define CONF_USB_MSC_LUN2_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_ANSI +#define CONF_USB_MSC_LUN2_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_REPO +#define CONF_USB_MSC_LUN2_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN2_FACTORY +#define CONF_USB_MSC_LUN2_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_PRODUCT +#define CONF_USB_MSC_LUN2_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN2_PRODUCT_VERSION +#define CONF_USB_MSC_LUN2_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// conf_usb_msc_lun2_capacity + +#ifndef CONF_USB_MSC_LUN2_CAPACITY +#define CONF_USB_MSC_LUN2_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN2_BLOCK_SIZE +#define CONF_USB_MSC_LUN2_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for LUN 3 +// conf_usb_msc_lun3_enable +#ifndef CONF_USB_MSC_LUN3_ENABLE +#define CONF_USB_MSC_LUN3_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN3_TYPE +#define CONF_USB_MSC_LUN3_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun3_rmb +#ifndef CONF_USB_MSC_LUN3_RMB +#define CONF_USB_MSC_LUN3_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN3_ISO +#define CONF_USB_MSC_LUN3_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_ECMA +#define CONF_USB_MSC_LUN3_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_ANSI +#define CONF_USB_MSC_LUN3_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_REPO +#define CONF_USB_MSC_LUN3_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN3_FACTORY +#define CONF_USB_MSC_LUN3_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_PRODUCT +#define CONF_USB_MSC_LUN3_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN3_PRODUCT_VERSION +#define CONF_USB_MSC_LUN3_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// conf_usb_msc_lun3_capacity + +#ifndef CONF_USB_MSC_LUN3_CAPACITY +#define CONF_USB_MSC_LUN3_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN3_BLOCK_SIZE +#define CONF_USB_MSC_LUN3_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) +#endif + +// + +// +// + +// <<< end of configuration section >>> + +#endif // USBD_CONFIG_H From eb47681d38f7e1724c11cb1e5d8793542912042e Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Tue, 11 May 2021 20:18:46 -0500 Subject: [PATCH 02/36] add makefile saml21 --- ports/atmel-samd/Makefile | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile index 574d1152607..91df37bbdff 100644 --- a/ports/atmel-samd/Makefile +++ b/ports/atmel-samd/Makefile @@ -92,6 +92,13 @@ OPTIMIZATION_FLAGS ?= -Os CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD21 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=128 -DCFG_TUD_MSC_BUFSIZE=512 endif +ifeq ($(CHIP_FAMILY), saml21) +PERIPHERALS_CHIP_FAMILY=saml21 +OPTIMIZATION_FLAGS ?= -Os +# TinyUSB defines +#CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD21 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=128 -DCFG_TUD_MSC_BUFSIZE=512 +endif + ifeq ($(CHIP_FAMILY), samd51) PERIPHERALS_CHIP_FAMILY=sam_d5x_e5x OPTIMIZATION_FLAGS ?= -O2 -fno-inline-functions @@ -169,6 +176,15 @@ CFLAGS += \ -mfloat-abi=soft \ -DSAMD21 endif +ifeq ($(CHIP_FAMILY), saml21) +CFLAGS += \ + -mthumb \ + -mabi=aapcs-linux \ + -mcpu=cortex-m0plus \ + -msoft-float \ + -mfloat-abi=soft \ + -DSAML21 +endif ifeq ($(CHIP_FAMILY), samd51) CFLAGS += \ -mthumb \ @@ -211,6 +227,9 @@ endif ifeq ($(CHIP_FAMILY), samd21) LDFLAGS += -mthumb -mcpu=cortex-m0plus -Lasf/thirdparty/CMSIS/Lib/GCC/ BOOTLOADER_SIZE := 0x2000 +ifeq ($(CHIP_FAMILY), saml21) +LDFLAGS += -mthumb -mcpu=cortex-m0plus -Lasf/thirdparty/CMSIS/Lib/GCC/ +BOOTLOADER_SIZE := 0x2000 else ifeq ($(CHIP_FAMILY), samd51) LDFLAGS += -mthumb -mcpu=cortex-m4 BOOTLOADER_SIZE := 0x4000 @@ -253,6 +272,13 @@ SRC_ASF += \ hpl/core/hpl_core_m0plus_base.c \ hpl/sysctrl/hpl_sysctrl.c \ +ifeq ($(CHIP_FAMILY), saml21) +SRC_ASF += \ + hpl/core/hpl_core_m0plus_base.c \ + hpl/mclk/hpl_mclk.c \ + hpl/osc32kctrl/hpl_osc32kctrl.c \ + hpl/oscctrl/hpl_oscctrl.c \ + else ifeq ($(CHIP_FAMILY), samd51) SRC_ASF += \ hal/src/hal_rand_sync.c \ From 9a67c07f13c0e0808defbf99b80e998bd990e5b2 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Tue, 11 May 2021 20:20:20 -0500 Subject: [PATCH 03/36] add more saml21 --- ports/atmel-samd/supervisor/internal_flash.c | 3 +++ ports/atmel-samd/supervisor/port.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/ports/atmel-samd/supervisor/internal_flash.c b/ports/atmel-samd/supervisor/internal_flash.c index 98d7892c9f2..6f254d41102 100644 --- a/ports/atmel-samd/supervisor/internal_flash.c +++ b/ports/atmel-samd/supervisor/internal_flash.c @@ -39,6 +39,9 @@ #ifdef SAMD21 #include "hpl/pm/hpl_pm_base.h" #endif +#ifdef SAML21 +#include "hri/hri_mclk_l21.h" +#endif #ifdef SAME51 #include "hri/hri_mclk_e51.h" #endif diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 15112f5ba74..ef895144420 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -42,6 +42,8 @@ #if defined(SAMD21) #include "hri/hri_pm_d21.h" +#if defined(SAML21) +#include "hri/hri_rstc_l21.h" #elif defined(SAME54) #include "hri/hri_rstc_e54.h" #elif defined(SAME51) From d5fcc5b8e2e1557b8934ecd67ed09177d7913cbf Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Tue, 11 May 2021 22:49:56 -0500 Subject: [PATCH 04/36] fix if's makefile --- ports/atmel-samd/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile index 91df37bbdff..255101cb041 100644 --- a/ports/atmel-samd/Makefile +++ b/ports/atmel-samd/Makefile @@ -227,7 +227,7 @@ endif ifeq ($(CHIP_FAMILY), samd21) LDFLAGS += -mthumb -mcpu=cortex-m0plus -Lasf/thirdparty/CMSIS/Lib/GCC/ BOOTLOADER_SIZE := 0x2000 -ifeq ($(CHIP_FAMILY), saml21) +else ifeq ($(CHIP_FAMILY), saml21) LDFLAGS += -mthumb -mcpu=cortex-m0plus -Lasf/thirdparty/CMSIS/Lib/GCC/ BOOTLOADER_SIZE := 0x2000 else ifeq ($(CHIP_FAMILY), samd51) @@ -272,7 +272,7 @@ SRC_ASF += \ hpl/core/hpl_core_m0plus_base.c \ hpl/sysctrl/hpl_sysctrl.c \ -ifeq ($(CHIP_FAMILY), saml21) +else ifeq ($(CHIP_FAMILY), saml21) SRC_ASF += \ hpl/core/hpl_core_m0plus_base.c \ hpl/mclk/hpl_mclk.c \ From f773d2ee57c56d5198c8a5b8393441c224e5744f Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Tue, 11 May 2021 22:59:16 -0500 Subject: [PATCH 05/36] fix ifdef port --- ports/atmel-samd/supervisor/port.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index ef895144420..1f7819c6267 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -42,7 +42,7 @@ #if defined(SAMD21) #include "hri/hri_pm_d21.h" -#if defined(SAML21) +#elif defined(SAML21) #include "hri/hri_rstc_l21.h" #elif defined(SAME54) #include "hri/hri_rstc_e54.h" From 6d7b6084c6a7a114acf82185d5ec74681499a63a Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Wed, 12 May 2021 00:08:25 -0500 Subject: [PATCH 06/36] Add board SAML21 --- ports/atmel-samd/boards/bast_saml21/board.c | 37 +++++++++++++ .../boards/bast_saml21/mpconfigboard.h | 52 +++++++++++++++++++ .../boards/bast_saml21/mpconfigboard.mk | 11 ++++ ports/atmel-samd/boards/bast_saml21/pins.c | 35 +++++++++++++ 4 files changed, 135 insertions(+) create mode 100644 ports/atmel-samd/boards/bast_saml21/board.c create mode 100644 ports/atmel-samd/boards/bast_saml21/mpconfigboard.h create mode 100644 ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk create mode 100644 ports/atmel-samd/boards/bast_saml21/pins.c diff --git a/ports/atmel-samd/boards/bast_saml21/board.c b/ports/atmel-samd/boards/bast_saml21/board.c new file mode 100644 index 00000000000..84960e73cf2 --- /dev/null +++ b/ports/atmel-samd/boards/bast_saml21/board.c @@ -0,0 +1,37 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "supervisor/board.h" + +void board_init(void) { +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.h b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.h new file mode 100644 index 00000000000..40c7c43d1bb --- /dev/null +++ b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.h @@ -0,0 +1,52 @@ +#define MICROPY_HW_BOARD_NAME "Electronic Cats Bast SAML21" +#define MICROPY_HW_MCU_NAME "saml21e18" + +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) + +// No microcontroller.nvm +#define CIRCUITPY_INTERNAL_NVM_SIZE 0 + +#define DEFAULT_I2C_BUS_SCL (&pin_PA08) +#define DEFAULT_I2C_BUS_SDA (&pin_PA09) + +#define DEFAULT_SPI_BUS_SCK (&pin_PA17) +#define DEFAULT_SPI_BUS_MOSI (&pin_PA16) +#define DEFAULT_SPI_BUS_MISO (&pin_PA19) + +#define DEFAULT_UART_BUS_RX (&pin_PA01) +#define DEFAULT_UART_BUS_TX (&pin_PA00) + +#define IGNORE_PIN_PA03 1 +#define IGNORE_PIN_PA12 1 +#define IGNORE_PIN_PA13 1 +#define IGNORE_PIN_PA20 1 +#define IGNORE_PIN_PA21 1 +// USB is always used. +#define IGNORE_PIN_PA24 1 +#define IGNORE_PIN_PA25 1 +#define IGNORE_PIN_PA30 1 +#define IGNORE_PIN_PA31 1 +#define IGNORE_PIN_PB01 1 +#define IGNORE_PIN_PB02 1 +#define IGNORE_PIN_PB03 1 +#define IGNORE_PIN_PB04 1 +#define IGNORE_PIN_PB05 1 +#define IGNORE_PIN_PB06 1 +#define IGNORE_PIN_PB07 1 +#define IGNORE_PIN_PB08 1 +#define IGNORE_PIN_PB09 1 +#define IGNORE_PIN_PB10 1 +#define IGNORE_PIN_PB11 1 +#define IGNORE_PIN_PB12 1 +#define IGNORE_PIN_PB13 1 +#define IGNORE_PIN_PB14 1 +#define IGNORE_PIN_PB15 1 +#define IGNORE_PIN_PB16 1 +#define IGNORE_PIN_PB17 1 +#define IGNORE_PIN_PB22 1 +#define IGNORE_PIN_PB23 1 +#define IGNORE_PIN_PB30 1 +#define IGNORE_PIN_PB31 1 +#define IGNORE_PIN_PB00 1 diff --git a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk new file mode 100644 index 00000000000..6c5e54e0321 --- /dev/null +++ b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk @@ -0,0 +1,11 @@ +USB_VID = 0x1209 +USB_PID = 0xBAB3 +USB_PRODUCT = "Bast SAML21" +USB_MANUFACTURER = "Electronic Cats" + +CHIP_VARIANT = SAML21G18B +CHIP_FAMILY = saml21 + +INTERNAL_FLASH_FILESYSTEM = 1 +LONGINT_IMPL = NONE +CIRCUITPY_FULL_BUILD = 0 diff --git a/ports/atmel-samd/boards/bast_saml21/pins.c b/ports/atmel-samd/boards/bast_saml21/pins.c new file mode 100644 index 00000000000..425ace001d9 --- /dev/null +++ b/ports/atmel-samd/boards/bast_saml21/pins.c @@ -0,0 +1,35 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA23) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA27) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) }, + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA17) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); From 604e663e879236535ea09adbb6784fdf92784945 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Wed, 12 May 2021 00:09:23 -0500 Subject: [PATCH 07/36] add more ifdef for SAML21 --- ports/atmel-samd/supervisor/internal_flash.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ports/atmel-samd/supervisor/internal_flash.c b/ports/atmel-samd/supervisor/internal_flash.c index 6f254d41102..8717109628d 100644 --- a/ports/atmel-samd/supervisor/internal_flash.c +++ b/ports/atmel-samd/supervisor/internal_flash.c @@ -75,6 +75,9 @@ void supervisor_flash_init(void) { #ifdef SAMD21 _pm_enable_bus_clock(PM_BUS_APBB, NVMCTRL); #endif + #ifdef SAML21 + hri_mclk_set_AHBMASK_NVMCTRL_bit(MCLK); + #endif flash_init(&supervisor_flash_desc, NVMCTRL); } From c52f6c38244b702a626a101833c3275135ea3815 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Wed, 12 May 2021 00:27:07 -0500 Subject: [PATCH 08/36] add SAML21 to mpconfigport --- ports/atmel-samd/mpconfigport.h | 56 +++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/ports/atmel-samd/mpconfigport.h b/ports/atmel-samd/mpconfigport.h index c66ab99ab2a..650de07d080 100644 --- a/ports/atmel-samd/mpconfigport.h +++ b/ports/atmel-samd/mpconfigport.h @@ -61,6 +61,33 @@ #endif // SAMD21 +#ifdef SAML21 + +// HMCRAMC0_SIZE is defined in the ASF4 include files for each SAML21 chip. +#define RAM_SIZE HMCRAMC0_SIZE +#define BOOTLOADER_SIZE (8 * 1024) +#define CIRCUITPY_MCU_FAMILY saml21 +#define MICROPY_PY_SYS_PLATFORM "Atmel SAML21" +#define SPI_FLASH_MAX_BAUDRATE 8000000 +#define MICROPY_PY_BUILTINS_COMPLEX (0) +#define MICROPY_PY_BUILTINS_NOTIMPLEMENTED (0) +#define MICROPY_PY_FUNCTION_ATTRS (0) +#define MICROPY_PY_REVERSE_SPECIAL_METHODS (0) +#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (0) +#define MICROPY_PY_UERRNO_LIST \ + X(EPERM) \ + X(ENOENT) \ + X(EIO) \ + X(EAGAIN) \ + X(ENOMEM) \ + X(EACCES) \ + X(EEXIST) \ + X(ENODEV) \ + X(EISDIR) \ + X(EINVAL) \ + +#endif // SAML21 + //////////////////////////////////////////////////////////////////////////////////////////////////// #ifdef SAM_D5X_E5X @@ -122,6 +149,35 @@ #endif // SAMD21 +#ifdef SAML21 + +#if INTERNAL_FLASH_FILESYSTEM +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (64 * 1024) +#else +#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0) +#endif + +#ifndef CIRCUITPY_INTERNAL_NVM_SIZE +#define CIRCUITPY_INTERNAL_NVM_SIZE (256) +#endif + +#ifndef CIRCUITPY_DEFAULT_STACK_SIZE +#define CIRCUITPY_DEFAULT_STACK_SIZE 3584 +#endif + +#ifndef SAML21_BOD33_LEVEL +// Set brownout detection to ~2.7V. Default from factory is 1.7V, +// which is too low for proper operation of external SPI flash chips +// (they are 2.7-3.6V). +#define SAML21_BOD33_LEVEL (39) +// 2.77V with hysteresis off. Table 37.20 in datasheet. +#endif + +// Smallest unit of flash that can be erased. +#define FLASH_ERASE_SIZE NVMCTRL_ROW_SIZE + +#endif // SAML21 + //////////////////////////////////////////////////////////////////////////////////////////////////// #ifdef SAM_D5X_E5X From fe62ceaab0fc1a095fd3a16cc113ec2bf1d73a67 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Wed, 12 May 2021 02:12:28 -0500 Subject: [PATCH 09/36] added more directives for SAML21 in port and mphalport --- ports/atmel-samd/mphalport.c | 3 ++ ports/atmel-samd/supervisor/port.c | 51 ++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/ports/atmel-samd/mphalport.c b/ports/atmel-samd/mphalport.c index 5ebce1a8578..d71485ac352 100644 --- a/ports/atmel-samd/mphalport.c +++ b/ports/atmel-samd/mphalport.c @@ -58,6 +58,9 @@ extern uint32_t common_hal_mcu_processor_get_frequency(void); #ifdef SAMD21 #define DELAY_LOOP_ITERATIONS_PER_US ((10U * 48000000U) / common_hal_mcu_processor_get_frequency()) #endif +#ifdef SAML21 +#define DELAY_LOOP_ITERATIONS_PER_US ((10U * 48000000U) / common_hal_mcu_processor_get_frequency()) +#endif #ifdef SAM_D5X_E5X #define DELAY_LOOP_ITERATIONS_PER_US ((30U * 120000000U) / common_hal_mcu_processor_get_frequency()) #endif diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 1f7819c6267..ed968b4b64c 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -177,6 +177,17 @@ static void rtc_init(void) { RTC_MODE0_CTRL_MODE_COUNT32 | RTC_MODE0_CTRL_PRESCALER_DIV2; #endif + #ifdef SAML21 + hri_mclk_set_APBAMASK_RTC_bit(MCLK); + RTC->MODE0.CTRLA.bit.SWRST = true; + while (RTC->MODE0.SYNCBUSY.bit.SWRST != 0) { + } + + RTC->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_ENABLE | + RTC_MODE0_CTRLA_MODE_COUNT32 | + RTC_MODE0_CTRLA_PRESCALER_DIV2 | + RTC_MODE0_CTRLA_COUNTSYNC; + #endif #ifdef SAM_D5X_E5X hri_mclk_set_APBAMASK_RTC_bit(MCLK); RTC->MODE0.CTRLA.bit.SWRST = true; @@ -201,6 +212,10 @@ static void rtc_init(void) { NVIC_SetPriority(USB_IRQn, 1); #endif + #ifdef SAML21 + NVIC_SetPriority(USB_IRQn, 1); + #endif + #ifdef SAM_D5X_E5X NVIC_SetPriority(USB_0_IRQn, 1); NVIC_SetPriority(USB_1_IRQn, 1); @@ -235,6 +250,20 @@ safe_mode_t port_init(void) { #endif #endif + #if defined(SAML21) + // Set brownout detection. + // Disable while changing level. + SUPC->BOD33.bit.ENABLE = 0; + SUPC->BOD33.bit.LEVEL = SAMD21_BOD33_LEVEL; + SUPC->BOD33.bit.ENABLE = 1; + + #if 0 + // Designate QSPI memory mapped region as not cachable. + #endif + + samd_peripherals_enable_cache(); + #endif + #if defined(SAM_D5X_E5X) // Set brownout detection. // Disable while changing level. @@ -313,6 +342,11 @@ safe_mode_t port_init(void) { return BROWNOUT; } #endif + #ifdef SAML21 + if (RSTC->RCAUSE.bit.BOD33 == 1 || RSTC->RCAUSE.bit.BOD12 == 1) { + return BROWNOUT; + } + #endif #ifdef SAM_D5X_E5X if (RSTC->RCAUSE.bit.BODVDD == 1 || RSTC->RCAUSE.bit.BODCORE == 1) { return BROWNOUT; @@ -423,6 +457,9 @@ uint32_t *port_heap_get_top(void) { #ifdef SAMD21 uint32_t *safe_word = (uint32_t *)(HMCRAMC0_ADDR + HMCRAMC0_SIZE - 0x2000); #endif +#ifdef SAML21 +uint32_t *safe_word = (uint32_t *)(HSRAM_ADDR + HSRAM_SIZE - 0x2000); +#endif #ifdef SAM_D5X_E5X uint32_t *safe_word = (uint32_t *)(HSRAM_ADDR + HSRAM_SIZE - 0x2000); #endif @@ -447,6 +484,10 @@ static uint32_t _get_count(uint64_t *overflow_count) { while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) { } #endif + #ifdef SAML21 + while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) { + } + #endif #ifdef SAMD21 // Request a read so we don't stall the bus later. See section 14.3.1.5 Read Request RTC->MODE0.READREQ.reg = RTC_READREQ_RREQ | 0x0010; @@ -506,6 +547,9 @@ void RTC_Handler(void) { } } #endif + #ifdef SAML21 + RTC->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0; + #endif #ifdef SAM_D5X_E5X RTC->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0; #endif @@ -528,6 +572,10 @@ void port_enable_tick(void) { // PER2 will generate an interrupt every 32 ticks of the source 32.768 clock. RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; #endif + #ifdef SAML21 + // PER2 will generate an interrupt every 32 ticks of the source 32.768 clock. + RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + #endif #ifdef SAMD21 // TODO: Switch to using the PER *event* from the RTC to generate an interrupt via EVSYS. _ticks_enabled = true; @@ -540,6 +588,9 @@ void port_disable_tick(void) { #ifdef SAM_D5X_E5X RTC->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_PER2; #endif + #ifdef SAML21 + RTC->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_PER2; + #endif #ifdef SAMD21 _ticks_enabled = false; RTC->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0; From d835f868c992a936a8d9c6ba6790e548eb8c752b Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Wed, 12 May 2021 02:12:50 -0500 Subject: [PATCH 10/36] active tinyusb for SAML21 --- ports/atmel-samd/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile index 255101cb041..3de56cd07cb 100644 --- a/ports/atmel-samd/Makefile +++ b/ports/atmel-samd/Makefile @@ -96,7 +96,7 @@ ifeq ($(CHIP_FAMILY), saml21) PERIPHERALS_CHIP_FAMILY=saml21 OPTIMIZATION_FLAGS ?= -Os # TinyUSB defines -#CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD21 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=128 -DCFG_TUD_MSC_BUFSIZE=512 +CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_SAMD21 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_CDC_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 -DCFG_TUD_CDC_TX_BUFSIZE=128 -DCFG_TUD_MSC_BUFSIZE=512 endif ifeq ($(CHIP_FAMILY), samd51) From f0efd45bcf6225a88f76bf8c4be3fa4d8f36949f Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Fri, 14 May 2021 00:15:28 -0500 Subject: [PATCH 11/36] more add SAML21 --- .../asf4_conf/saml21/hpl_sercom_config.h | 17 ++++- .../atmel-samd/common-hal/analogio/AnalogIn.c | 10 ++- ports/atmel-samd/common-hal/busio/UART.c | 7 ++ .../common-hal/microcontroller/Pin.c | 13 ++++ .../common-hal/microcontroller/Processor.c | 76 +++++++++++++++++++ ports/atmel-samd/common-hal/os/__init__.c | 4 + ports/atmel-samd/common-hal/pwmio/PWMOut.c | 24 ++++++ ports/atmel-samd/supervisor/port.c | 2 +- 8 files changed, 150 insertions(+), 3 deletions(-) diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h index 8a7b4395fe3..ecc0914b788 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h @@ -1,4 +1,19 @@ -/* Auto-generated config file hpl_sercom_config.h */ +// For CircuitPython, use SERCOM settings as prototypes to set +// the default settings. This file defines these SERCOMs +// +// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous +// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous +// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous +// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA + +#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0 +#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY + +#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1 + +#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2 +#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY + #ifndef HPL_SERCOM_CONFIG_H #define HPL_SERCOM_CONFIG_H diff --git a/ports/atmel-samd/common-hal/analogio/AnalogIn.c b/ports/atmel-samd/common-hal/analogio/AnalogIn.c index 262e44350c5..4d0d37b6486 100644 --- a/ports/atmel-samd/common-hal/analogio/AnalogIn.c +++ b/ports/atmel-samd/common-hal/analogio/AnalogIn.c @@ -103,8 +103,16 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { #ifdef SAMD21 adc_sync_set_channel_gain(&adc, self->channel, ADC_INPUTCTRL_GAIN_DIV2_Val); #endif - + + #ifdef SAMD21 + adc_sync_set_resolution(&adc, ADC_CTRLB_RESSEL_12BIT_Val); + #endif + #ifdef SAML21 + adc_sync_set_resolution(&adc, ADC_CTRLC_RESSEL_12BIT_Val); + #endif + #ifdef SAM_D5X_E5X adc_sync_set_resolution(&adc, ADC_CTRLB_RESSEL_12BIT_Val); + #endif adc_sync_enable_channel(&adc, self->channel); diff --git a/ports/atmel-samd/common-hal/busio/UART.c b/ports/atmel-samd/common-hal/busio/UART.c index cd8263bc56c..0cb52cf2749 100644 --- a/ports/atmel-samd/common-hal/busio/UART.c +++ b/ports/atmel-samd/common-hal/busio/UART.c @@ -105,6 +105,13 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, continue; } #endif + #ifdef SAML21 + if (potential_sercom->USART.CTRLA.bit.ENABLE != 0 || + !(tx->sercom[i].pad == 0 || + tx->sercom[i].pad == 2)) { + continue; + } + #endif #ifdef SAM_D5X_E5X if (potential_sercom->USART.CTRLA.bit.ENABLE != 0 || !(tx->sercom[i].pad == 0)) { diff --git a/ports/atmel-samd/common-hal/microcontroller/Pin.c b/ports/atmel-samd/common-hal/microcontroller/Pin.c index 564d037e03f..68d65d2a753 100644 --- a/ports/atmel-samd/common-hal/microcontroller/Pin.c +++ b/ports/atmel-samd/common-hal/microcontroller/Pin.c @@ -53,6 +53,9 @@ bool speaker_enable_in_use; #ifdef SAMD21 #define SWD_MUX GPIO_PIN_FUNCTION_G #endif +#ifdef SAML21 +#define SWD_MUX GPIO_PIN_FUNCTION_G +#endif STATIC uint32_t never_reset_pins[PORT_COUNT]; @@ -89,6 +92,10 @@ void reset_all_pins(void) { gpio_set_pin_function(PIN_PA30, GPIO_PIN_FUNCTION_G); gpio_set_pin_function(PIN_PA31, GPIO_PIN_FUNCTION_G); #endif + #ifdef SAML21 + gpio_set_pin_function(PIN_PA30, GPIO_PIN_FUNCTION_G); + gpio_set_pin_function(PIN_PA31, GPIO_PIN_FUNCTION_G); + #endif #ifdef MICROPY_HW_NEOPIXEL neopixel_in_use = false; @@ -148,6 +155,9 @@ void reset_pin_number(uint8_t pin_number) { #ifdef SAMD21 || pin_number == PIN_PA31) { #endif + #ifdef SAML21 + || pin_number == PIN_PA31) { + #endif gpio_set_pin_function(pin_number, SWD_MUX); } else { gpio_set_pin_direction(pin_number, GPIO_DIRECTION_OFF); @@ -213,6 +223,9 @@ bool pin_number_is_free(uint8_t pin_number) { #endif #ifdef SAMD21 || pin_number == PIN_PA31) { + #endif + #ifdef SAML21 + || pin_number == PIN_PA31) { #endif) { return state->bit.PMUXEN == 1 && ((pmux->reg >> (4 * pin_index % 2)) & 0xf) == SWD_MUX; } diff --git a/ports/atmel-samd/common-hal/microcontroller/Processor.c b/ports/atmel-samd/common-hal/microcontroller/Processor.c index 2985cf5a67b..7ea86c38678 100644 --- a/ports/atmel-samd/common-hal/microcontroller/Processor.c +++ b/ports/atmel-samd/common-hal/microcontroller/Processor.c @@ -166,6 +166,27 @@ STATIC float calculate_temperature(uint16_t raw_value) { } #endif // SAMD21 +#ifdef SAML21 +STATIC float calculate_temperature(uint16_t TP, uint16_t TC) { + uint32_t TLI = (*(uint32_t *)FUSES_ROOM_TEMP_VAL_INT_ADDR & FUSES_ROOM_TEMP_VAL_INT_Msk) >> FUSES_ROOM_TEMP_VAL_INT_Pos; + uint32_t TLD = (*(uint32_t *)FUSES_ROOM_TEMP_VAL_DEC_ADDR & FUSES_ROOM_TEMP_VAL_DEC_Msk) >> FUSES_ROOM_TEMP_VAL_DEC_Pos; + float TL = TLI + convert_dec_to_frac(TLD); + + uint32_t THI = (*(uint32_t *)FUSES_HOT_TEMP_VAL_INT_ADDR & FUSES_HOT_TEMP_VAL_INT_Msk) >> FUSES_HOT_TEMP_VAL_INT_Pos; + uint32_t THD = (*(uint32_t *)FUSES_HOT_TEMP_VAL_DEC_ADDR & FUSES_HOT_TEMP_VAL_DEC_Msk) >> FUSES_HOT_TEMP_VAL_DEC_Pos; + float TH = THI + convert_dec_to_frac(THD); + + uint16_t VPL = (*(uint32_t *)FUSES_ROOM_ADC_VAL_ADDR & FUSES_ROOM_ADC_VAL_Msk) >> FUSES_ROOM_ADC_VAL_Pos; + uint16_t VPH = (*(uint32_t *)FUSES_HOT_ADC_VAL_ADDR & FUSES_HOT_ADC_VAL_Msk) >> FUSES_HOT_ADC_VAL_Pos; + + uint16_t VCL = (*(uint32_t *)FUSES_ROOM_ADC_VAL_ADDR & FUSES_ROOM_ADC_VAL_Msk) >> FUSES_ROOM_ADC_VAL_Pos; + uint16_t VCH = (*(uint32_t *)FUSES_HOT_ADC_VAL_ADDR & FUSES_HOT_ADC_VAL_Msk) >> FUSES_HOT_ADC_VAL_Pos; + + // From SAMD51 datasheet: section 45.6.3.1 (page 1327). + return (TL * VPH * TC - VPL * TH * TC - TL * VCH * TP + TH * VCL * TP) / (VCL * TP - VCH * TP - VPL * TC + VPH * TC); +} +#endif // SAML21 + #ifdef SAM_D5X_E5X STATIC float calculate_temperature(uint16_t TP, uint16_t TC) { uint32_t TLI = (*(uint32_t *)FUSES_ROOM_TEMP_VAL_INT_ADDR & FUSES_ROOM_TEMP_VAL_INT_Msk) >> FUSES_ROOM_TEMP_VAL_INT_Pos; @@ -234,6 +255,49 @@ float common_hal_mcu_processor_get_temperature(void) { return calculate_temperature(value); #endif // SAMD21 + #ifdef SAML21 + adc_sync_set_resolution(&adc, ADC_CTRLC_RESSEL_12BIT_Val); + // Using INTVCC0 as the reference voltage. + // INTVCC1 seems to read a little high. + // INTREF doesn't work: ADC hangs BUSY. It's supposed to work, but does not. + // The SAME54 example from Atmel START implicitly uses INTREF. + adc_sync_set_reference(&adc, ADC_REFCTRL_REFSEL_INTVCC0_Val); + + hri_supc_set_VREF_ONDEMAND_bit(SUPC); + // Enable temperature sensor. + hri_supc_set_VREF_TSEN_bit(SUPC); + hri_supc_set_VREF_VREFOE_bit(SUPC); + + // Channel arg is ignored. + adc_sync_enable_channel(&adc, IGNORED_CHANNEL); + adc_sync_set_inputs(&adc, + ADC_INPUTCTRL_MUXPOS_Pos, // pos_input + ADC_INPUTCTRL_MUXNEG_GND_Val, // neg_input + IGNORED_CHANNEL); // channel (ignored) + + // Read both temperature sensors. + volatile uint16_t ptat; + volatile uint16_t ctat; + + // Read twice for stability (necessary?). + adc_sync_read_channel(&adc, IGNORED_CHANNEL, ((uint8_t *)&ptat), 2); + adc_sync_read_channel(&adc, IGNORED_CHANNEL, ((uint8_t *)&ptat), 2); + + adc_sync_set_inputs(&adc, + ADC_INPUTCTRL_MUXPOS_Pos, // pos_input + ADC_INPUTCTRL_MUXNEG_GND_Val, // neg_input + IGNORED_CHANNEL); // channel (ignored) + + adc_sync_read_channel(&adc, IGNORED_CHANNEL, ((uint8_t *)&ctat), 2); + adc_sync_read_channel(&adc, IGNORED_CHANNEL, ((uint8_t *)&ctat), 2); + + // Turn off temp sensor. + hri_supc_clear_VREF_TSEN_bit(SUPC); + + adc_sync_deinit(&adc); + return calculate_temperature(ptat, ctat); + #endif // SAML51 + #ifdef SAM_D5X_E5X adc_sync_set_resolution(&adc, ADC_CTRLB_RESSEL_12BIT_Val); // Using INTVCC0 as the reference voltage. @@ -304,7 +368,15 @@ float common_hal_mcu_processor_get_voltage(void) { mp_hal_delay_ms(1); #endif + #ifdef SAMD21 adc_sync_set_resolution(&adc, ADC_CTRLB_RESSEL_12BIT_Val); + #endif + #ifdef SAML21 + adc_sync_set_resolution(&adc, ADC_CTRLC_RESSEL_12BIT_Val); + #endif + #ifdef SAM_D5X_E5X + adc_sync_set_resolution(&adc, ADC_CTRLB_RESSEL_12BIT_Val); + #endif // Channel arg is ignored. adc_sync_set_inputs(&adc, ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val, // IOVCC/4 (nominal 3.3V/4) @@ -339,6 +411,10 @@ void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { uint32_t *id_addresses[4] = {(uint32_t *)0x0080A00C, (uint32_t *)0x0080A040, (uint32_t *)0x0080A044, (uint32_t *)0x0080A048}; #endif + #ifdef SAML21 + uint32_t *id_addresses[4] = {(uint32_t *)0x0080A00C, (uint32_t *)0x0080A040, + (uint32_t *)0x0080A044, (uint32_t *)0x0080A048}; + #endif #ifdef SAM_D5X_E5X uint32_t *id_addresses[4] = {(uint32_t *)0x008061FC, (uint32_t *)0x00806010, (uint32_t *)0x00806014, (uint32_t *)0x00806018}; diff --git a/ports/atmel-samd/common-hal/os/__init__.c b/ports/atmel-samd/common-hal/os/__init__.c index 6c554bff300..a6b11fc9da4 100644 --- a/ports/atmel-samd/common-hal/os/__init__.c +++ b/ports/atmel-samd/common-hal/os/__init__.c @@ -42,6 +42,10 @@ STATIC const qstr os_uname_info_fields[] = { STATIC const MP_DEFINE_STR_OBJ(os_uname_info_sysname_obj, "samd21"); STATIC const MP_DEFINE_STR_OBJ(os_uname_info_nodename_obj, "samd21"); #endif +#ifdef SAML21 +STATIC const MP_DEFINE_STR_OBJ(os_uname_info_sysname_obj, "saml21"); +STATIC const MP_DEFINE_STR_OBJ(os_uname_info_nodename_obj, "saml21"); +#endif #ifdef SAM_D5X_E5X STATIC const MP_DEFINE_STR_OBJ(os_uname_info_sysname_obj, "samd51"); STATIC const MP_DEFINE_STR_OBJ(os_uname_info_nodename_obj, "samd51"); diff --git a/ports/atmel-samd/common-hal/pwmio/PWMOut.c b/ports/atmel-samd/common-hal/pwmio/PWMOut.c index 815f1a7fe05..3fe5bb6723a 100644 --- a/ports/atmel-samd/common-hal/pwmio/PWMOut.c +++ b/ports/atmel-samd/common-hal/pwmio/PWMOut.c @@ -56,6 +56,9 @@ uint8_t tcc_refcount[TCC_INST_NUM]; #ifdef SAMD21 uint8_t tcc_channels[3]; // Set by pwmout_reset() to {0xf0, 0xfc, 0xfc} initially. #endif +#ifdef SAML21 +uint8_t tcc_channels[3]; // Set by pwmout_reset() to {0xf0, 0xfc, 0xfc} initially. +#endif #ifdef SAM_D5X_E5X uint8_t tcc_channels[5]; // Set by pwmout_reset() to {0xc0, 0xf0, 0xf8, 0xfc, 0xfc} initially. #endif @@ -260,6 +263,12 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self, TC_CTRLA_WAVEGEN_MPWM; tc->COUNT16.CC[0].reg = top; #endif + #ifdef SAML21 + tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 | + TC_CTRLA_PRESCALER(divisor) | + TC_WAVE_WAVEGEN_MPWM; + tc->COUNT16.CC[0].reg = top; + #endif #ifdef SAM_D5X_E5X tc->COUNT16.CTRLA.bit.SWRST = 1; @@ -345,6 +354,9 @@ extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uin #ifdef SAMD21 tc_insts[t->index]->COUNT16.CC[t->wave_output].reg = adjusted_duty; #endif + #ifdef SAML21 + tc_insts[t->index]->COUNT16.CC[t->wave_output].reg = adjusted_duty; + #endif #ifdef SAM_D5X_E5X Tc *tc = tc_insts[t->index]; while (tc->COUNT16.SYNCBUSY.bit.CC1 != 0) { @@ -368,6 +380,9 @@ extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uin #ifdef SAMD21 tcc->CCB[channel].reg = adjusted_duty; #endif + #ifdef SAML21 + tcc->CCBUF[channel].reg = adjusted_duty; + #endif #ifdef SAM_D5X_E5X tcc->CCBUF[channel].reg = adjusted_duty; #endif @@ -399,6 +414,15 @@ uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) { cv = tcc->CC[channel].reg; } #endif + #ifdef SAML21 + // If CCBV (CCB valid) is set, the CCB value hasn't yet been copied + // to the CC value. + if ((tcc->STATUS.vec.CCBUFV & (1 << channel)) != 0) { + cv = tcc->CCBUF[channel].reg; + } else { + cv = tcc->CC[channel].reg; + } + #endif #ifdef SAM_D5X_E5X if ((tcc->STATUS.vec.CCBUFV & (1 << channel)) != 0) { cv = tcc->CCBUF[channel].reg; diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index ed968b4b64c..cfd0b6674de 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -254,7 +254,7 @@ safe_mode_t port_init(void) { // Set brownout detection. // Disable while changing level. SUPC->BOD33.bit.ENABLE = 0; - SUPC->BOD33.bit.LEVEL = SAMD21_BOD33_LEVEL; + SUPC->BOD33.bit.LEVEL = SAML21_BOD33_LEVEL; SUPC->BOD33.bit.ENABLE = 1; #if 0 From 1270a0cc096f1cafc0cd8a05a2b4efed9f7a1e58 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Sat, 15 May 2021 21:31:09 -0500 Subject: [PATCH 12/36] add saml_cpu and more directives SAML21 --- ports/atmel-samd/Makefile | 3 + ports/atmel-samd/bindings/samd/Clock.c | 116 +++++++++++++++++++++++ ports/atmel-samd/mpconfigport.h | 6 +- ports/atmel-samd/mpconfigport.mk | 58 ++++++++++++ ports/atmel-samd/supervisor/saml21_cpu.s | 35 +++++++ ports/atmel-samd/supervisor/usb.c | 6 +- 6 files changed, 218 insertions(+), 6 deletions(-) create mode 100755 ports/atmel-samd/supervisor/saml21_cpu.s diff --git a/ports/atmel-samd/Makefile b/ports/atmel-samd/Makefile index 3de56cd07cb..88adb312b01 100644 --- a/ports/atmel-samd/Makefile +++ b/ports/atmel-samd/Makefile @@ -137,6 +137,9 @@ ifeq ($(DEBUG), 1) ifeq ($(CHIP_FAMILY), samd21) CFLAGS += -DENABLE_MICRO_TRACE_BUFFER endif + ifeq ($(CHIP_FAMILY), saml21) + CFLAGS += -DENABLE_MICRO_TRACE_BUFFER + endif else CFLAGS += -DNDEBUG # -finline-limit can shrink the image size. diff --git a/ports/atmel-samd/bindings/samd/Clock.c b/ports/atmel-samd/bindings/samd/Clock.c index 01fb29f47a7..6b9a1cfd0c2 100644 --- a/ports/atmel-samd/bindings/samd/Clock.c +++ b/ports/atmel-samd/bindings/samd/Clock.c @@ -271,6 +271,122 @@ MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table); #endif // SAMD21 +#ifdef SAML21 + +#ifdef SAML21_EXPOSE_ALL_CLOCKS +CLOCK_SOURCE(XOSC); +CLOCK_SOURCE(GCLKIN); +CLOCK_SOURCE(GCLKGEN1); +CLOCK_SOURCE(OSCULP32K); +#endif +CLOCK_SOURCE(OSC32K); +CLOCK_SOURCE(XOSC32K); +#ifdef SAML21_EXPOSE_ALL_CLOCKS +CLOCK_SOURCE(OSC8M); +CLOCK_SOURCE(DFLL48M); +CLOCK_SOURCE(DPLL96M); + +CLOCK_GCLK_(SYSCTRL, DFLL48); +CLOCK_GCLK_(SYSCTRL, FDPLL); +CLOCK_GCLK_(SYSCTRL, FDPLL32K); +CLOCK_GCLK(WDT); +#endif +#ifdef SAML21_EXPOSE_ALL_CLOCKS +CLOCK_GCLK(EIC); +CLOCK_GCLK(USB); +CLOCK_GCLK_(EVSYS, 0); +CLOCK_GCLK_(EVSYS, 1); +CLOCK_GCLK_(EVSYS, 2); +CLOCK_GCLK_(EVSYS, 3); +CLOCK_GCLK_(EVSYS, 4); +CLOCK_GCLK_(EVSYS, 5); +CLOCK_GCLK_(EVSYS, 6); +CLOCK_GCLK_(EVSYS, 7); +CLOCK_GCLK_(EVSYS, 8); +CLOCK_GCLK_(EVSYS, 9); +CLOCK_GCLK_(EVSYS, 10); +CLOCK_GCLK_(EVSYS, 11); +CLOCK(SERCOMx_SLOW, 1, 19); +CLOCK_GCLK_(SERCOM0, CORE); +CLOCK_GCLK_(SERCOM1, CORE); +CLOCK_GCLK_(SERCOM2, CORE); +CLOCK_GCLK_(SERCOM3, CORE); +CLOCK_GCLK_(SERCOM4, CORE); +CLOCK_GCLK_(SERCOM5, CORE); +CLOCK(TCC0_TCC1, 1, 26); +CLOCK(TCC2_TCC3, 1, 27); +CLOCK(TC4_TC5, 1, 28); +CLOCK(TC6_TC7, 1, 29); +CLOCK_GCLK(ADC); +CLOCK_GCLK_(AC, DIG); +CLOCK_GCLK_(AC, ANA); +CLOCK_GCLK(DAC); +CLOCK_GCLK(PTC); +CLOCK_GCLK_(I2S, 0); +CLOCK_GCLK_(I2S, 1); + +CLOCK(SYSTICK, 2, 0); +#endif + +STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = { + #ifdef SAML21_EXPOSE_ALL_CLOCKS + CLOCK_ENTRY(XOSC), + CLOCK_ENTRY(GCLKIN), + CLOCK_ENTRY(GCLKGEN1), + CLOCK_ENTRY(OSCULP32K), + #endif + CLOCK_ENTRY(OSC32K), + CLOCK_ENTRY(XOSC32K), + #ifdef SAML21_EXPOSE_ALL_CLOCKS + CLOCK_ENTRY(OSC8M), + CLOCK_ENTRY(DFLL48M), + CLOCK_ENTRY(DPLL96M), + CLOCK_ENTRY_(SYSCTRL, DFLL48), + CLOCK_ENTRY_(SYSCTRL, FDPLL), + CLOCK_ENTRY_(SYSCTRL, FDPLL32K), + CLOCK_ENTRY(WDT), + #endif + #ifdef SAML21_EXPOSE_ALL_CLOCKS + CLOCK_ENTRY(EIC), + CLOCK_ENTRY(USB), + CLOCK_ENTRY_(EVSYS, 0), + CLOCK_ENTRY_(EVSYS, 1), + CLOCK_ENTRY_(EVSYS, 2), + CLOCK_ENTRY_(EVSYS, 3), + CLOCK_ENTRY_(EVSYS, 4), + CLOCK_ENTRY_(EVSYS, 5), + CLOCK_ENTRY_(EVSYS, 6), + CLOCK_ENTRY_(EVSYS, 7), + CLOCK_ENTRY_(EVSYS, 8), + CLOCK_ENTRY_(EVSYS, 9), + CLOCK_ENTRY_(EVSYS, 10), + CLOCK_ENTRY_(EVSYS, 11), + CLOCK_ENTRY(SERCOMx_SLOW), + CLOCK_ENTRY_(SERCOM0, CORE), + CLOCK_ENTRY_(SERCOM1, CORE), + CLOCK_ENTRY_(SERCOM2, CORE), + CLOCK_ENTRY_(SERCOM3, CORE), + CLOCK_ENTRY_(SERCOM4, CORE), + CLOCK_ENTRY_(SERCOM5, CORE), + CLOCK_ENTRY(TCC0_TCC1), + CLOCK_ENTRY(TCC2_TCC3), + CLOCK_ENTRY(TC4_TC5), + CLOCK_ENTRY(TC6_TC7), + CLOCK_ENTRY(ADC), + CLOCK_ENTRY_(AC, DIG), + CLOCK_ENTRY_(AC, ANA), + CLOCK_ENTRY(DAC), + CLOCK_ENTRY(PTC), + CLOCK_ENTRY_(I2S, 0), + CLOCK_ENTRY_(I2S, 1), + + CLOCK_ENTRY(SYSTICK), + #endif +}; +MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table); + +#endif // SAML21 + #ifdef SAM_D5X_E5X diff --git a/ports/atmel-samd/mpconfigport.h b/ports/atmel-samd/mpconfigport.h index 650de07d080..b98fffdfb32 100644 --- a/ports/atmel-samd/mpconfigport.h +++ b/ports/atmel-samd/mpconfigport.h @@ -63,8 +63,8 @@ #ifdef SAML21 -// HMCRAMC0_SIZE is defined in the ASF4 include files for each SAML21 chip. -#define RAM_SIZE HMCRAMC0_SIZE +// HSRAM_SIZE is defined in the ASF4 include files for each SAML21 chip. +#define RAM_SIZE HSRAM_SIZE #define BOOTLOADER_SIZE (8 * 1024) #define CIRCUITPY_MCU_FAMILY saml21 #define MICROPY_PY_SYS_PLATFORM "Atmel SAML21" @@ -147,7 +147,7 @@ // Smallest unit of flash that can be erased. #define FLASH_ERASE_SIZE NVMCTRL_ROW_SIZE -#endif // SAMD21 +#endif // SAML21 #ifdef SAML21 diff --git a/ports/atmel-samd/mpconfigport.mk b/ports/atmel-samd/mpconfigport.mk index 060b17daf59..30522dbc947 100644 --- a/ports/atmel-samd/mpconfigport.mk +++ b/ports/atmel-samd/mpconfigport.mk @@ -80,6 +80,64 @@ endif endif # samd21 ###################################################################### +###################################################################### +# Put saml21-only choices here. + +ifeq ($(CHIP_FAMILY),saml21) + +# The ?='s allow overriding in mpconfigboard.mk. + +# For Now No native touchio on SAML21. +CIRCUITPY_TOUCHIO_USE_NATIVE = 0 + +# Some of these are on by default with CIRCUITPY_FULL_BUILD, but don't +# fit in 256kB of flash + +CIRCUITPY_AUDIOMIXER ?= 0 +CIRCUITPY_BINASCII ?= 0 +CIRCUITPY_BITBANGIO ?= 0 +CIRCUITPY_BITMAPTOOLS ?= 0 +CIRCUITPY_BUSDEVICE ?= 0 +CIRCUITPY_AUDIOMP3 ?= 0 +CIRCUITPY_BLEIO_HCI = 0 +CIRCUITPY_BUILTINS_POW3 ?= 0 +CIRCUITPY_COMPUTED_GOTO_SAVE_SPACE ?= 1 +CIRCUITPY_COUNTIO ?= 0 +# Not enough RAM for framebuffers +CIRCUITPY_FRAMEBUFFERIO ?= 0 +CIRCUITPY_FREQUENCYIO ?= 0 +CIRCUITPY_I2CPERIPHERAL ?= 0 +CIRCUITPY_JSON ?= 0 +CIRCUITPY_MSGPACK ?= 0 +CIRCUITPY_RE ?= 0 +CIRCUITPY_SDCARDIO ?= 0 +CIRCUITPY_SYNTHIO ?= 0 +CIRCUITPY_TOUCHIO_USE_NATIVE = 0 +CIRCUITPY_ULAB = 0 +CIRCUITPY_VECTORIO = 0 + +MICROPY_PY_ASYNC_AWAIT = 0 + +ifeq ($(TRANSLATION), ja) +RELEASE_NEEDS_CLEAN_BUILD = 1 +CIRCUITPY_TERMINALIO = 0 +endif + +ifeq ($(TRANSLATION), ko) +RELEASE_NEEDS_CLEAN_BUILD = 1 +CIRCUITPY_TERMINALIO = 0 +endif + +SUPEROPT_GC = 0 +SUPEROPT_VM = 0 + +ifeq ($(CIRCUITPY_FULL_BUILD),0) +# On the smallest boards, this saves about 180 bytes. On other boards, it may -increase- space used. +CFLAGS_BOARD = -fweb -frename-registers +endif + +endif # saml21 +###################################################################### ###################################################################### # Put samd51-only choices here. diff --git a/ports/atmel-samd/supervisor/saml21_cpu.s b/ports/atmel-samd/supervisor/saml21_cpu.s new file mode 100755 index 00000000000..741bb21358a --- /dev/null +++ b/ports/atmel-samd/supervisor/saml21_cpu.s @@ -0,0 +1,35 @@ +.syntax unified +.cpu cortex-m0 +.thumb +.text +.align 2 + +@ uint cpu_get_regs_and_sp(r0=uint regs[10]) +.global cpu_get_regs_and_sp +.thumb +.thumb_func +.type cpu_get_regs_and_sp, %function +cpu_get_regs_and_sp: +@ store registers into given array +str r4, [r0, #0] +str r5, [r0, #4] +str r6, [r0, #8] +str r7, [r0, #12] +push {r1} +mov r1, r8 +str r1, [r0, #16] +mov r1, r9 +str r1, [r0, #20] +mov r1, r10 +str r1, [r0, #24] +mov r1, r11 +str r1, [r0, #28] +mov r1, r12 +str r1, [r0, #32] +mov r1, r13 +str r1, [r0, #36] +pop {r1} + +@ return the sp +mov r0, sp +bx lr diff --git a/ports/atmel-samd/supervisor/usb.c b/ports/atmel-samd/supervisor/usb.c index 2a4c2d4f78b..592d6195c19 100644 --- a/ports/atmel-samd/supervisor/usb.c +++ b/ports/atmel-samd/supervisor/usb.c @@ -39,7 +39,7 @@ void init_usb_hardware(void) { _gclk_enable_channel(USB_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val); #endif - #ifdef SAM_D5X_E5X + #if defined(SAM_D5X_E5X) || defined(SAML21) hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); hri_mclk_set_AHBMASK_USB_bit(MCLK); hri_mclk_set_APBBMASK_USB_bit(MCLK); @@ -51,7 +51,7 @@ void init_usb_hardware(void) { gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); gpio_set_pin_level(PIN_PA25, false); gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); - #ifdef SAMD21 + #if defined(SAMD21) || defined(SAML21) gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); #endif @@ -61,7 +61,7 @@ void init_usb_hardware(void) { #endif } -#ifdef SAMD21 +#if defined(SAMD21) || defined(SAML21) void USB_Handler(void) { usb_irq_handler(); } From cf495da7868d7194e6033191d1a995c874db46e9 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Sat, 15 May 2021 23:16:01 -0500 Subject: [PATCH 13/36] update asf4_config --- .../asf4_conf/saml21/hpl_rtc_config.h | 10 +- .../asf4_conf/saml21/hpl_sercom_config.h | 17 +- .../asf4_conf/saml21/hpl_tc_config.h | 171 ++++++++++++++++++ .../asf4_conf/saml21/peripheral_clk_config.h | 32 ++++ 4 files changed, 207 insertions(+), 23 deletions(-) diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h index 481b831b8c4..48e27f0a611 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h @@ -34,18 +34,14 @@ // These bits define the RTC clock relative to the peripheral clock // rtc_arch_prescaler #ifndef CONF_RTC_PRESCALER -#define CONF_RTC_PRESCALER 0x0 -#endif +#define CONF_RTC_PRESCALER 0x1 -// Compare Value <1-4294967295> -// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), -// by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms. -// rtc_arch_comp_val +#endif #ifndef CONF_RTC_COMP_VAL -#define CONF_RTC_COMP_VAL 32 +#define CONF_RTC_COMP_VAL 0 #endif diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h index ecc0914b788..8a7b4395fe3 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h @@ -1,19 +1,4 @@ -// For CircuitPython, use SERCOM settings as prototypes to set -// the default settings. This file defines these SERCOMs -// -// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous -// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous -// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous -// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA - -#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0 -#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY - -#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1 - -#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2 -#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY - +/* Auto-generated config file hpl_sercom_config.h */ #ifndef HPL_SERCOM_CONFIG_H #define HPL_SERCOM_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h index d3175098b48..a889793a886 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h @@ -201,6 +201,177 @@ // +#ifndef CONF_TC1_ENABLE +#define CONF_TC1_ENABLE 1 +#endif + +#include "peripheral_clk_config.h" + +// Basic configuration + +// Prescaler +// <0x0=> No division +// <0x1=> Divide by 2 +// <0x2=> Divide by 4 +// <0x3=> Divide by 8 +// <0x4=> Divide by 16 +// <0x5=> Divide by 64 +// <0x6=> Divide by 256 +// <0x7=> Divide by 1024 +// This defines the prescaler value +// timer_prescaler +#ifndef CONF_TC1_PRESCALER +#define CONF_TC1_PRESCALER 0x3 +#endif + +// Length of one timer tick in uS <0-4294967295> +// timer_tick +#ifndef CONF_TC1_TIMER_TICK +#define CONF_TC1_TIMER_TICK 1000 +#endif +// + +// Advanced configuration +// timer_advanced_configuration +#ifndef CONF_TC1__ADVANCED_CONFIGURATION_ENABLE +#define CONF_TC1__ADVANCED_CONFIGURATION_ENABLE 0 +#endif + +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC1_PRESCSYNC +#define CONF_TC1_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the module will continue to run in standby sleep mode +// tc_arch_runstdby +#ifndef CONF_TC1_RUNSTDBY +#define CONF_TC1_RUNSTDBY 0 +#endif + +// Run in debug mode +// Indicates whether the module will run in debug mode +// tc_arch_dbgrun +#ifndef CONF_TC1_DBGRUN +#define CONF_TC1_DBGRUN 0 +#endif + +// Run on demand +// Run if requested by some other peripheral in the device +// tc_arch_ondemand +#ifndef CONF_TC1_ONDEMAND +#define CONF_TC1_ONDEMAND 0 +#endif + +// + +// Event control +// timer_event_control +#ifndef CONF_TC1_EVENT_CONTROL_ENABLE +#define CONF_TC1_EVENT_CONTROL_ENABLE 0 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC1_MCEO0 +#define CONF_TC1_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC1_MCEO1 +#define CONF_TC1_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC1_OVFEO +#define CONF_TC1_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC1_TCEI +#define CONF_TC1_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC1_TCINV +#define CONF_TC1_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC1_EVACT +#define CONF_TC1_EVACT 0 +#endif +// + +// Default values which the driver needs in order to work correctly + +// Mode set to 32-bit +#ifndef CONF_TC1_MODE +#define CONF_TC1_MODE TC_CTRLA_MODE_COUNT32_Val +#endif + +// CC 1 register set to 0 +#ifndef CONF_TC1_CC1 +#define CONF_TC1_CC1 0 +#endif + +#ifndef CONF_TC1_ALOCK +#define CONF_TC1_ALOCK 0 +#endif + +// Not used in 32-bit mode +#define CONF_TC1_PER 0 + +// Calculating correct top value based on requested tick interval. +#define CONF_TC1_PRESCALE (1 << CONF_TC1_PRESCALER) + +// Prescaler set to 64 +#if CONF_TC1_PRESCALER > 0x4 +#undef CONF_TC1_PRESCALE +#define CONF_TC1_PRESCALE 64 +#endif + +// Prescaler set to 256 +#if CONF_TC1_PRESCALER > 0x5 +#undef CONF_TC1_PRESCALE +#define CONF_TC1_PRESCALE 256 +#endif + +// Prescaler set to 1024 +#if CONF_TC1_PRESCALER > 0x6 +#undef CONF_TC1_PRESCALE +#define CONF_TC1_PRESCALE 1024 +#endif + +#ifndef CONF_TC1_CC0 +#define CONF_TC1_CC0 \ + (uint32_t)(((float)CONF_TC1_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC1_FREQUENCY / CONF_TC1_PRESCALE))) +#endif + // <<< end of configuration section >>> #endif // HPL_TC_CONFIG_H diff --git a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h index 5bc487b5a75..6055efe321d 100644 --- a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h @@ -348,6 +348,38 @@ #define CONF_GCLK_TC0_FREQUENCY 48000000 #endif +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC1_SRC +#define CONF_GCLK_TC1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC1_FREQUENCY + * \brief TC1's Clock frequency + */ +#ifndef CONF_GCLK_TC1_FREQUENCY +#define CONF_GCLK_TC1_FREQUENCY 48000000 +#endif + // DAC Clock Source // Generic clock generator 0 From a1f22711e67e52a98b911d27b5d1d903ff2dc130 Mon Sep 17 00:00:00 2001 From: Eduardo Date: Mon, 7 Jun 2021 13:52:54 -0500 Subject: [PATCH 14/36] update boards --- .../boards/bast_saml21/mpconfigboard.h | 10 ------- ports/atmel-samd/boards/bast_saml21/pins.c | 26 +------------------ 2 files changed, 1 insertion(+), 35 deletions(-) diff --git a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.h b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.h index 40c7c43d1bb..94eb9fed148 100644 --- a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.h +++ b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.h @@ -8,16 +8,6 @@ // No microcontroller.nvm #define CIRCUITPY_INTERNAL_NVM_SIZE 0 -#define DEFAULT_I2C_BUS_SCL (&pin_PA08) -#define DEFAULT_I2C_BUS_SDA (&pin_PA09) - -#define DEFAULT_SPI_BUS_SCK (&pin_PA17) -#define DEFAULT_SPI_BUS_MOSI (&pin_PA16) -#define DEFAULT_SPI_BUS_MISO (&pin_PA19) - -#define DEFAULT_UART_BUS_RX (&pin_PA01) -#define DEFAULT_UART_BUS_TX (&pin_PA00) - #define IGNORE_PIN_PA03 1 #define IGNORE_PIN_PA12 1 #define IGNORE_PIN_PA13 1 diff --git a/ports/atmel-samd/boards/bast_saml21/pins.c b/ports/atmel-samd/boards/bast_saml21/pins.c index 425ace001d9..192f7dc185a 100644 --- a/ports/atmel-samd/boards/bast_saml21/pins.c +++ b/ports/atmel-samd/boards/bast_saml21/pins.c @@ -1,35 +1,11 @@ #include "shared-bindings/board/__init__.h" STATIC const mp_rom_map_elem_t board_global_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA09) }, { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA01) }, { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA00) }, { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA14) }, { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA23) }, { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA22) }, - { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA27) }, - { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, - { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, - { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) }, - { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) }, - { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA17) }, - { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PA16) }, - { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA19) }, - { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, - { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, - { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, + }; MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); From 22bb736bd7dcd8380e643ccedb23e85bfcc1e808 Mon Sep 17 00:00:00 2001 From: Eduardo Date: Mon, 7 Jun 2021 13:56:43 -0500 Subject: [PATCH 15/36] update clocks --- .../asf4_conf/saml21/hpl_gclk_config.h | 10 +-- .../asf4_conf/saml21/hpl_oscctrl_config.h | 14 ++-- .../asf4_conf/saml21/hpl_sercom_config.h | 16 ++++ .../boards/bast_saml21/mpconfigboard.mk | 75 ++++++++++++++++++- 4 files changed, 102 insertions(+), 13 deletions(-) diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h index cd563697438..a9376aa5534 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h @@ -25,7 +25,7 @@ // This defines the clock source for generic clock generator 0 // gclk_gen_0_oscillator #ifndef CONF_GCLK_GEN_0_SOURCE -#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DFLL48M +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M #endif // Run in Standby @@ -100,7 +100,7 @@ // This defines the clock source for generic clock generator 1 // gclk_gen_1_oscillator #ifndef CONF_GCLK_GEN_1_SOURCE -#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL48M #endif // Run in Standby @@ -235,7 +235,7 @@ // Indicates whether generic clock 3 configuration is enabled or not // enable_gclk_gen_3 #ifndef CONF_GCLK_GENERATOR_3_CONFIG -#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#define CONF_GCLK_GENERATOR_3_CONFIG 1 #endif // Generic Clock Generator Control @@ -252,7 +252,7 @@ // This defines the clock source for generic clock generator 3 // gclk_gen_3_oscillator #ifndef CONF_GCLK_GEN_3_SOURCE -#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K #endif // Run in Standby @@ -294,7 +294,7 @@ // Indicates whether Generic Clock Generator Enable is enabled or not // gclk_arch_gen_3_enable #ifndef CONF_GCLK_GEN_3_GENEN -#define CONF_GCLK_GEN_3_GENEN 0 +#define CONF_GCLK_GEN_3_GENEN 1 #endif // diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h index c81ee97fd7a..6e3aa289dc6 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h @@ -108,7 +108,7 @@ // Indicates whether On Demand Control is enabled or not // osc16m_arch_ondemand #ifndef CONF_OSC16M_ONDEMAND -#define CONF_OSC16M_ONDEMAND 1 +#define CONF_OSC16M_ONDEMAND 0 #endif // Run in Standby @@ -126,7 +126,7 @@ // This defines the oscillator frequency (Mhz) // osc16m_freq #ifndef CONF_OSC16M_FSEL -#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val +#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_16_Val #endif // Oscillator Calibration Control @@ -241,14 +241,14 @@ // Indicates whether Chill Cycle Disable is enabled or not // dfll_arch_ccdis #ifndef CONF_DFLL_CCDIS -#define CONF_DFLL_CCDIS 0 +#define CONF_DFLL_CCDIS 1 #endif // On Demand Control // Indicates whether On Demand Control is enabled or not // dfll_arch_ondemand #ifndef CONF_DFLL_ONDEMAND -#define CONF_DFLL_ONDEMAND 1 +#define CONF_DFLL_ONDEMAND 0 #endif // Run in Standby @@ -262,7 +262,7 @@ // Indicates whether USB Clock Recovery Mode is enabled or not // dfll_arch_usbcrm #ifndef CONF_DFLL_USBCRM -#define CONF_DFLL_USBCRM 0 +#define CONF_DFLL_USBCRM 1 #endif // Lose Lock After Wake @@ -284,7 +284,7 @@ // <1=>Closed Loop Mode // dfll48m_mode #ifndef CONF_DFLL_MODE -#define CONF_DFLL_MODE 0 +#define CONF_DFLL_MODE 1 #endif // Coarse Maximum Step <0x0-0x1F> @@ -302,7 +302,7 @@ // DFLL Multiply Factor <0x0-0xFFFF> // dfll48m_mul #ifndef CONF_DFLL_MUL -#define CONF_DFLL_MUL 0 +#define CONF_DFLL_MUL 48000 #endif // DFLL Calibration Overwrite diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h index 8a7b4395fe3..bccc62acf6e 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h @@ -1,3 +1,19 @@ +// For CircuitPython, use SERCOM settings as prototypes to set +// the default settings. This file defines these SERCOMs +// +// SERCOM0: SPI with hal_spi_m_sync.c driver: spi master synchronous +// SERCOM1: I2C with hal_i2c_m_sync.c driver: i2c master synchronous +// SERCOM2: USART with hal_usart_async.c driver: usart asynchronous +// SERCOM3: SPI with hal_spi_m_dma.c: spi master DMA + +#define PROTOTYPE_SERCOM_SPI_M_SYNC SERCOM0 +#define PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM0_CORE_FREQUENCY + +#define PROTOTYPE_SERCOM_I2CM_SYNC SERCOM1 + +#define PROTOTYPE_SERCOM_USART_ASYNC SERCOM2 +#define PROTOTYPE_SERCOM_USART_ASYNC_CLOCK_FREQUENCY CONF_GCLK_SERCOM2_CORE_FREQUENCY + /* Auto-generated config file hpl_sercom_config.h */ #ifndef HPL_SERCOM_CONFIG_H #define HPL_SERCOM_CONFIG_H diff --git a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk index 6c5e54e0321..7266c8cdcd3 100644 --- a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk +++ b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk @@ -3,9 +3,82 @@ USB_PID = 0xBAB3 USB_PRODUCT = "Bast SAML21" USB_MANUFACTURER = "Electronic Cats" -CHIP_VARIANT = SAML21G18B +CHIP_VARIANT = SAML21E18B CHIP_FAMILY = saml21 INTERNAL_FLASH_FILESYSTEM = 1 LONGINT_IMPL = NONE CIRCUITPY_FULL_BUILD = 0 + +CIRCUITPY_ANALOGIO = 0 +CIRCUITPY_ROTARYIO = 0 +CIRCUITPY_RTC = 0 +CIRCUITPY_PULSEIO = 0 +CIRCUITPY_PWMIO = 0 +CIRCUITPY_AUDIOCORE = 0 +CIRCUITPY_BUSIO = 0 +CIRCUITPY_PIXELBUF = 0 +CIRCUITPY_USB_MIDI = 0 +CIRCUITPY_TOUCHIO = 0 +CIRCUITPY_BITBANGIO = 0 +CIRCUITPY_BITMAPTOOLS = 0 +CIRCUITPY_BUSDEVICE = 0 +CIRCUITPY_AUDIOBUSIO = 0 +CIRCUITPY_AUDIOMP3 = 0 +CIRCUITPY_BLEIO_HCI = 0 +CIRCUITPY_DISPLAYIO = 0 +CIRCUITPY_FRAMEBUFFERIO = 0 +CIRCUITPY_MSGPACK = 0 +CIRCUITPY_PS2IO = 0 +CIRCUITPY_RGBMATRIX = 0 +CIRCUITPY_ALARM=0 +CIRCUITPY_AUDIOMIXER=0 +CIRCUITPY_AUDIOPWMIO=0 +CIRCUITPY_COUNTIO=0 +CIRCUITPY_CAMERA=0 +CIRCUITPY_CANIO=0 +CIRCUITPY_FRAMEBUFFERDISPLAY=0 +CIRCUITPY_GAMEPAD=0 +CIRCUITPY_GAMEPADSHIFT=0 +CIRCUITPY_GNSS=0 +CIRCUITPY_IPADDRESS=0 +CIRCUITPY_I2CPERIPHERAL=0 +CIRCUITPY_MATH=0 +CIRCUITPY_NETWORK=0 +CIRCUITPY_MSGPACK=0 +CIRCUITPY_NEOPIXEL_WRITE=0 +CIRCUITPY_RANDOM=0 +CIRCUITPY_RP2PIO=0 +CIRCUITPY_SDIOIO=0 +CIRCUITPY_SDCARDIO=0 +CIRCUITPY_SHARPDISPLAY=0 +CIRCUITPY_SOCKET=0 +CIRCUITPY_SOCKETPOO=0 +CIRCUITPY_SSL=0 +CIRCUITPY_STRUCT=0 +CIRCUITPY_TERMINALIO=0 +CIRCUITPY_ULAB=0 +CIRCUITPY_USB_HID=0 +CIRCUITPY_VECTORIO=0 +MICROPY_PY_ASYNC_AWAIT=0 +CIRCUITPY_AESIO=0 +CIRCUITPY_AUDIOBUSIO_I2SOUT=0 +CIRCUITPY_AUDIOBUSIO_PDMIN=0 +CIRCUITPY_AUDIOIO=0 +CIRCUITPY_BLEIO=0 +CIRCUITPY_BUILTINS_POW3=0 +CIRCUITPY_ESPIDF=0 +CIRCUITPY_FREQUENCYIO=0 +CIRCUITPY__EVE=0 +CIRCUITPY_DUALBANK=0 +CIRCUITPY_WIFI=0 +CIRCUITPY_STAGE=0 +CIRCUITPY_UHEAP=0 +CIRCUITPY_PEW=0 +CIRCUITPY_USTACK=0 +CIRCUITPY_BITBANG_APA102=0 +CIRCUITPY_REQUIRE_I2C_PULLUPS=0 +CIRCUITPY_SERIAL_BLE=0 +CIRCUITPY_BLE_FILE_SERVICE=0 +CIRCUITPY_SERIAL_UART=0 +SUPEROPT_GC=0 \ No newline at end of file From 296b04d884c51c9886be20688e699ae50aee25c5 Mon Sep 17 00:00:00 2001 From: Eduardo Date: Mon, 7 Jun 2021 13:56:51 -0500 Subject: [PATCH 16/36] add led flashing --- main.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/main.c b/main.c index 48373b68348..990006736c6 100755 --- a/main.c +++ b/main.c @@ -557,6 +557,12 @@ STATIC void __attribute__ ((noinline)) run_boot_py(safe_mode_t safe_mode) { #endif } +void delay(unsigned long milis){ + for(unsigned long i=0;i Date: Mon, 7 Jun 2021 13:57:23 -0500 Subject: [PATCH 17/36] update clocks on peripherals --- .../asf4_conf/saml21/peripheral_clk_config.h | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h index 6055efe321d..3e397005c81 100644 --- a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h @@ -33,7 +33,7 @@ * \brief ADC's Clock frequency */ #ifndef CONF_GCLK_ADC_FREQUENCY -#define CONF_GCLK_ADC_FREQUENCY 48000000 +#define CONF_GCLK_ADC_FREQUENCY 16000000 #endif /** @@ -41,7 +41,7 @@ * \brief CPU's Clock frequency */ #ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 48000000 +#define CONF_CPU_FREQUENCY 16000000 #endif // RTC Clock Source @@ -105,7 +105,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM0_SLOW_SRC -#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val #endif /** @@ -113,7 +113,7 @@ * \brief SERCOM0's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY -#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000 +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 16000000 #endif /** @@ -121,7 +121,7 @@ * \brief SERCOM0's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000 +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 16000000 #endif // Core Clock Source @@ -169,7 +169,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM1_SLOW_SRC -#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val #endif /** @@ -177,7 +177,7 @@ * \brief SERCOM1's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY -#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000 +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 16000000 #endif /** @@ -185,7 +185,7 @@ * \brief SERCOM1's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 400000 +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 16000000 #endif // Core Clock Source @@ -233,7 +233,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM2_SLOW_SRC -#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val #endif /** @@ -241,7 +241,7 @@ * \brief SERCOM2's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY -#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000 +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 16000000 #endif /** @@ -249,7 +249,7 @@ * \brief SERCOM2's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 400000 +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 16000000 #endif // Core Clock Source @@ -297,7 +297,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM3_SLOW_SRC -#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val #endif /** @@ -305,7 +305,7 @@ * \brief SERCOM3's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY -#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000 +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 16000000 #endif /** @@ -313,7 +313,7 @@ * \brief SERCOM3's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 400000 +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 16000000 #endif // TC Clock Source @@ -345,7 +345,7 @@ * \brief TC0's Clock frequency */ #ifndef CONF_GCLK_TC0_FREQUENCY -#define CONF_GCLK_TC0_FREQUENCY 48000000 +#define CONF_GCLK_TC0_FREQUENCY 16000000 #endif // TC Clock Source @@ -377,7 +377,7 @@ * \brief TC1's Clock frequency */ #ifndef CONF_GCLK_TC1_FREQUENCY -#define CONF_GCLK_TC1_FREQUENCY 48000000 +#define CONF_GCLK_TC1_FREQUENCY 16000000 #endif // DAC Clock Source @@ -409,7 +409,7 @@ * \brief DAC's Clock frequency */ #ifndef CONF_GCLK_DAC_FREQUENCY -#define CONF_GCLK_DAC_FREQUENCY 48000000 +#define CONF_GCLK_DAC_FREQUENCY 16000000 #endif // USB Clock Source @@ -433,7 +433,7 @@ // Select the clock source for USB. #ifndef CONF_GCLK_USB_SRC -#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val #endif From b63ceca8cc917532022022108dcda56c8a217584 Mon Sep 17 00:00:00 2001 From: Eduardo Date: Fri, 18 Jun 2021 14:17:13 -0500 Subject: [PATCH 18/36] add wero_init functiion --- main.c | 12 +- .../asf4_conf/saml21/hpl_oscctrl_config.h | 2 +- .../asf4_conf/saml21/peripheral_clk_config.h | 16 +-- ports/atmel-samd/supervisor/port.c | 118 +++++++++++++++++- supervisor/port.h | 2 + 5 files changed, 131 insertions(+), 19 deletions(-) diff --git a/main.c b/main.c index 990006736c6..9a704b94649 100755 --- a/main.c +++ b/main.c @@ -588,11 +588,11 @@ STATIC int run_repl(void) { int __attribute__((used)) main(void) { // initialise the cpu and peripherals - safe_mode_t safe_mode = port_init(); - + safe_mode_t safe_mode = 1;//port_init(); + wero_init(); // Turn on LEDs - init_status_leds(); - rgb_led_status_init(); + //init_status_leds(); + //rgb_led_status_init(); //port regs = 0x40002800 int *pt; @@ -604,7 +604,8 @@ int __attribute__((used)) main(void) { *pt =1<<23; pt = (int *)0x40002810; //pt =1<23; - for(int i=0;i<5;i++){ + //for(int i=0;i<5;i++){ + while(1){ *pt=1<<23; delay(500000); *pt=0x00000000; @@ -617,7 +618,6 @@ int __attribute__((used)) main(void) { } - stack_init(); // Create a new filesystem only if we're not in a safe mode. diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h index 6e3aa289dc6..6a6f918817e 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h @@ -284,7 +284,7 @@ // <1=>Closed Loop Mode // dfll48m_mode #ifndef CONF_DFLL_MODE -#define CONF_DFLL_MODE 1 +#define CONF_DFLL_MODE 0 #endif // Coarse Maximum Step <0x0-0x1F> diff --git a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h index 3e397005c81..c444341a720 100644 --- a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h @@ -105,7 +105,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM0_SLOW_SRC -#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val #endif /** @@ -121,7 +121,7 @@ * \brief SERCOM0's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 16000000 +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 #endif // Core Clock Source @@ -169,7 +169,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM1_SLOW_SRC -#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val #endif /** @@ -185,7 +185,7 @@ * \brief SERCOM1's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 16000000 +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 #endif // Core Clock Source @@ -233,7 +233,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM2_SLOW_SRC -#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val #endif /** @@ -249,7 +249,7 @@ * \brief SERCOM2's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 16000000 +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 #endif // Core Clock Source @@ -297,7 +297,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM3_SLOW_SRC -#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val #endif /** @@ -313,7 +313,7 @@ * \brief SERCOM3's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 16000000 +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 #endif // TC Clock Source diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index cfd0b6674de..53bb5e7c553 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -166,7 +166,9 @@ static void save_usb_clock_calibration(void) { } #endif + static void rtc_init(void) { + /* #ifdef SAMD21 _gclk_enable_channel(RTC_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK2_Val); RTC->MODE0.CTRL.bit.SWRST = true; @@ -227,7 +229,66 @@ static void rtc_init(void) { #if CIRCUITPY_RTC rtc_reset(); #endif +*/ +} + +/* Referenced GCLKs (out of 0~4), should be initialized firstly */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x0000001F +void wero_init(void) +{ + // Clock init ( follow hpl_init.c ) + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 0); + + _set_performance_level(2); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); +#endif + // Update SystemCoreClock since it is hard coded with asf4 and not correct + // Init 1ms tick timer (samd SystemCoreClock may not correct) + SystemCoreClock = CONF_CPU_FREQUENCY; + SysTick_Config(CONF_CPU_FREQUENCY / 1000); + + + /* USB Clock init + * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock + * for low speed and full speed operation. */ + hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); + hri_mclk_set_AHBMASK_USB_bit(MCLK); + hri_mclk_set_APBBMASK_USB_bit(MCLK); + + // USB Pin Init + gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA24, false); + gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); + gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA25, false); + gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); + + gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); + gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); + + // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed + hri_mclk_set_APBCMASK_TCC0_bit(MCLK); + TCC0->PER.bit.PER = 48000000 / 1000; + TCC0->CC[3].bit.CC = 48000000 / 2000; + TCC0->CTRLA.bit.ENABLE = true; + + gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3); + hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); } safe_mode_t port_init(void) { @@ -256,7 +317,7 @@ safe_mode_t port_init(void) { SUPC->BOD33.bit.ENABLE = 0; SUPC->BOD33.bit.LEVEL = SAML21_BOD33_LEVEL; SUPC->BOD33.bit.ENABLE = 1; - + #if 0 // Designate QSPI memory mapped region as not cachable. #endif @@ -317,6 +378,55 @@ safe_mode_t port_init(void) { _pm_init(); #endif + #ifdef SAML21 + + // Clock init ( follow hpl_init.c ) + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 0); + + _set_performance_level(2); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); + + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(0x0000001F); + + // Update SystemCoreClock since it is hard coded with asf4 and not correct + // Init 1ms tick timer (samd SystemCoreClock may not correct) + //SystemCoreClock = 16000000; + //SysTick_Config(16000000 / 1000); + + //USB Stuff + /* USB Clock init + * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock + * for low speed and full speed operation. */ + hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); + hri_mclk_set_AHBMASK_USB_bit(MCLK); + hri_mclk_set_APBBMASK_USB_bit(MCLK); + + // USB Pin Init + // gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); + // gpio_set_pin_level(PIN_PA24, false); + // gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); + // gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); + // gpio_set_pin_level(PIN_PA25, false); + // gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); + + // gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); + // gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); + + + // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed + hri_mclk_set_APBCMASK_TCC0_bit(MCLK); + TCC0->PER.bit.PER = 48000000 / 1000; + TCC0->CC[3].bit.CC = 48000000 / 2000; + TCC0->CTRLA.bit.ENABLE = true; + + gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3); + hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); + + #endif #if CALIBRATE_CRYSTALLESS uint32_t fine = DEFAULT_DFLL48M_FINE_CALIBRATION; // The fine calibration data is stored in an NVM page after the text and data storage but before @@ -324,10 +434,10 @@ safe_mode_t port_init(void) { if (strcmp((char *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) { fine = ((uint16_t *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8]; } - clock_init(BOARD_HAS_CRYSTAL, fine); + //clock_init(BOARD_HAS_CRYSTAL, fine); #else // Use a default fine value - clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION); + //clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION); #endif rtc_init(); @@ -392,7 +502,7 @@ void reset_port(void) { analogout_reset(); #endif - reset_gclks(); + //reset_gclks(); #if CIRCUITPY_GAMEPAD gamepad_reset(); diff --git a/supervisor/port.h b/supervisor/port.h index 0a8cdfd3424..1e080fbd100 100644 --- a/supervisor/port.h +++ b/supervisor/port.h @@ -41,6 +41,8 @@ extern uint32_t _estack; // Stored at the end of the bss section (which includes the heap). extern uint32_t _ebss; +void wero_init(void); + safe_mode_t port_init(void); // Reset the microcontroller completely. From 6ca62e19b065b8f1d333c7ea7a0bd5bc2b0242a5 Mon Sep 17 00:00:00 2001 From: Sabas Date: Mon, 21 Jun 2021 13:18:21 -0500 Subject: [PATCH 19/36] Update main.c --- main.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/main.c b/main.c index 9a704b94649..c200a10fe95 100755 --- a/main.c +++ b/main.c @@ -588,11 +588,11 @@ STATIC int run_repl(void) { int __attribute__((used)) main(void) { // initialise the cpu and peripherals - safe_mode_t safe_mode = 1;//port_init(); - wero_init(); + safe_mode_t safe_mode = port_init(); + // Turn on LEDs - //init_status_leds(); - //rgb_led_status_init(); + init_status_leds(); + rgb_led_status_init(); //port regs = 0x40002800 int *pt; @@ -604,8 +604,8 @@ int __attribute__((used)) main(void) { *pt =1<<23; pt = (int *)0x40002810; //pt =1<23; - //for(int i=0;i<5;i++){ - while(1){ + for(int i=0;i<5;i++){ + //while(1){ *pt=1<<23; delay(500000); *pt=0x00000000; From f326eb65b0ca0406b655a35171a2794f4f7ce6de Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Mon, 21 Jun 2021 14:09:46 -0500 Subject: [PATCH 20/36] Updated submodule lib/tinyusb --- .gitmodules | 4 ++-- lib/tinyusb | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index 24ba2e2f6f3..ad50dd01dac 100644 --- a/.gitmodules +++ b/.gitmodules @@ -35,7 +35,7 @@ url = https://github.com/k-bx/python-semver.git [submodule "atmel-samd/asf4"] path = ports/atmel-samd/asf4 - url = https://github.com/adafruit/asf4.git + url = https://github.com/UVA-DSI/asf4.git branch = circuitpython [submodule "tools/usb_descriptor"] path = tools/usb_descriptor @@ -66,7 +66,7 @@ url = https://github.com/adafruit/Adafruit_CircuitPython_DotStar.git [submodule "ports/atmel-samd/peripherals"] path = ports/atmel-samd/peripherals - url = https://github.com/adafruit/samd-peripherals.git + url = https://github.com/UVA-DSI/samd-peripherals [submodule "frozen/Adafruit_CircuitPython_Crickit"] path = frozen/Adafruit_CircuitPython_Crickit url = https://github.com/adafruit/Adafruit_CircuitPython_Crickit diff --git a/lib/tinyusb b/lib/tinyusb index ab4d30fd6bc..5a4fc1151a7 160000 --- a/lib/tinyusb +++ b/lib/tinyusb @@ -1 +1 @@ -Subproject commit ab4d30fd6bca02c73eb9b4ff82db0b2b0f403344 +Subproject commit 5a4fc1151a7e62a291a90836165942737a1a2d6f From e19543c6a36490be475371ccba32714bd035f60c Mon Sep 17 00:00:00 2001 From: Sabas Date: Mon, 21 Jun 2021 14:27:01 -0500 Subject: [PATCH 21/36] Update build.yml --- .github/workflows/build.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 65d58fbb9d5..5309f64352b 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -190,6 +190,7 @@ jobs: - "arduino_nano_33_iot" - "arduino_zero" - "bast_pro_mini_m0" + - "bast_saml21" - "bastble" - "bdmicro_vina_d21" - "bdmicro_vina_d51" From c17d4df789e3d0c2ce5ad11cc66831c383c1b6e5 Mon Sep 17 00:00:00 2001 From: Sabas Date: Mon, 21 Jun 2021 14:27:26 -0500 Subject: [PATCH 22/36] gitmodules update for CI --- .gitmodules | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/.gitmodules b/.gitmodules index ad50dd01dac..766a712b78c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -33,10 +33,6 @@ [submodule "tools/python-semver"] path = tools/python-semver url = https://github.com/k-bx/python-semver.git -[submodule "atmel-samd/asf4"] - path = ports/atmel-samd/asf4 - url = https://github.com/UVA-DSI/asf4.git - branch = circuitpython [submodule "tools/usb_descriptor"] path = tools/usb_descriptor url = https://github.com/adafruit/usb_descriptor.git @@ -64,9 +60,6 @@ [submodule "frozen/Adafruit_CircuitPython_DotStar"] path = frozen/Adafruit_CircuitPython_DotStar url = https://github.com/adafruit/Adafruit_CircuitPython_DotStar.git -[submodule "ports/atmel-samd/peripherals"] - path = ports/atmel-samd/peripherals - url = https://github.com/UVA-DSI/samd-peripherals [submodule "frozen/Adafruit_CircuitPython_Crickit"] path = frozen/Adafruit_CircuitPython_Crickit url = https://github.com/adafruit/Adafruit_CircuitPython_Crickit @@ -184,3 +177,5 @@ [submodule "frozen/Adafruit_CircuitPython_MIDI"] path = frozen/Adafruit_CircuitPython_MIDI url = https://github.com/adafruit/Adafruit_CircuitPython_MIDI +[submodule "ports/atmel-samd/peripherals"] + url = https://github.com/UVA-DSI/samd-peripherals From d0e526dd7293918d8898179e5bb71835b34e0d3a Mon Sep 17 00:00:00 2001 From: Sabas Date: Mon, 21 Jun 2021 14:28:24 -0500 Subject: [PATCH 23/36] Update port.c --- ports/atmel-samd/supervisor/port.c | 116 +++++++++-------------------- 1 file changed, 37 insertions(+), 79 deletions(-) diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 53bb5e7c553..7ad326c5964 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -168,7 +168,7 @@ static void save_usb_clock_calibration(void) { static void rtc_init(void) { - /* + #ifdef SAMD21 _gclk_enable_channel(RTC_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK2_Val); RTC->MODE0.CTRL.bit.SWRST = true; @@ -229,67 +229,13 @@ static void rtc_init(void) { #if CIRCUITPY_RTC rtc_reset(); #endif -*/ + } /* Referenced GCLKs (out of 0~4), should be initialized firstly */ #define _GCLK_INIT_1ST 0x00000000 /* Not referenced GCLKs, initialized last */ #define _GCLK_INIT_LAST 0x0000001F -void wero_init(void) -{ - // Clock init ( follow hpl_init.c ) - hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 0); - - _set_performance_level(2); - - _osc32kctrl_init_sources(); - _oscctrl_init_sources(); - _mclk_init(); -#if _GCLK_INIT_1ST - _gclk_init_generators_by_fref(_GCLK_INIT_1ST); -#endif - _oscctrl_init_referenced_generators(); - _gclk_init_generators_by_fref(_GCLK_INIT_LAST); - -#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) - hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); -#endif - - // Update SystemCoreClock since it is hard coded with asf4 and not correct - // Init 1ms tick timer (samd SystemCoreClock may not correct) - SystemCoreClock = CONF_CPU_FREQUENCY; - SysTick_Config(CONF_CPU_FREQUENCY / 1000); - - - /* USB Clock init - * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock - * for low speed and full speed operation. */ - hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); - hri_mclk_set_AHBMASK_USB_bit(MCLK); - hri_mclk_set_APBBMASK_USB_bit(MCLK); - - // USB Pin Init - gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA24, false); - gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); - gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA25, false); - gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); - - gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); - gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); - - // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed - hri_mclk_set_APBCMASK_TCC0_bit(MCLK); - TCC0->PER.bit.PER = 48000000 / 1000; - TCC0->CC[3].bit.CC = 48000000 / 2000; - TCC0->CTRLA.bit.ENABLE = true; - - gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3); - hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); -} safe_mode_t port_init(void) { #if defined(SAMD21) @@ -388,10 +334,18 @@ safe_mode_t port_init(void) { _osc32kctrl_init_sources(); _oscctrl_init_sources(); _mclk_init(); + #if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); + #endif _oscctrl_init_referenced_generators(); _gclk_init_generators_by_fref(0x0000001F); + #if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); + #endif + // Update SystemCoreClock since it is hard coded with asf4 and not correct // Init 1ms tick timer (samd SystemCoreClock may not correct) //SystemCoreClock = 16000000; @@ -406,27 +360,18 @@ safe_mode_t port_init(void) { hri_mclk_set_APBBMASK_USB_bit(MCLK); // USB Pin Init - // gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); - // gpio_set_pin_level(PIN_PA24, false); - // gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); - // gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); - // gpio_set_pin_level(PIN_PA25, false); - // gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); - - // gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); - // gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); - - - // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed - hri_mclk_set_APBCMASK_TCC0_bit(MCLK); - TCC0->PER.bit.PER = 48000000 / 1000; - TCC0->CC[3].bit.CC = 48000000 / 2000; - TCC0->CTRLA.bit.ENABLE = true; + gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA24, false); + gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); + gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA25, false); + gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); - gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3); - hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); + gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); + gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); #endif + #if CALIBRATE_CRYSTALLESS uint32_t fine = DEFAULT_DFLL48M_FINE_CALIBRATION; // The fine calibration data is stored in an NVM page after the text and data storage but before @@ -502,7 +447,7 @@ void reset_port(void) { analogout_reset(); #endif - //reset_gclks(); + reset_gclks(); #if CIRCUITPY_GAMEPAD gamepad_reset(); @@ -521,11 +466,24 @@ void reset_port(void) { // Output clocks for debugging. // not supported by SAMD51G; uncomment for SAMD51J or update for 51G // #ifdef SAM_D5X_E5X - // gpio_set_pin_function(PIN_PA10, GPIO_PIN_FUNCTION_M); // GCLK4, D3 - // gpio_set_pin_function(PIN_PA11, GPIO_PIN_FUNCTION_M); // GCLK5, A4 - // gpio_set_pin_function(PIN_PB14, GPIO_PIN_FUNCTION_M); // GCLK0, D5 - // gpio_set_pin_function(PIN_PB15, GPIO_PIN_FUNCTION_M); // GCLK1, D6 + //gpio_set_pin_function(PIN_PA10, GPIO_PIN_FUNCTION_M); // GCLK4, D3 + //gpio_set_pin_function(PIN_PA11, GPIO_PIN_FUNCTION_M); // GCLK5, A4 + //gpio_set_pin_function(PIN_PB14, GPIO_PIN_FUNCTION_M); // GCLK0, D5 + //gpio_set_pin_function(PIN_PB15, GPIO_PIN_FUNCTION_M); // GCLK1, D6 // #endif + + // Output clocks for debugging. + // not supported by SAMD21G; uncomment for SAML51J or update for 21G + #ifdef SAML21 + // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed + hri_mclk_set_APBCMASK_TCC0_bit(MCLK); + TCC0->PER.bit.PER = 48000000 / 1000; + TCC0->CC[3].bit.CC = 48000000 / 2000; + TCC0->CTRLA.bit.ENABLE = true; + + gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3); + hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); + #endif #if CALIBRATE_CRYSTALLESS if (tud_cdc_connected()) { From 32cacf3c592a4c7b0ab3c3be1cf05bd65c32b929 Mon Sep 17 00:00:00 2001 From: Sabas Date: Mon, 21 Jun 2021 14:32:39 -0500 Subject: [PATCH 24/36] Revert "gitmodules update for CI" This reverts commit c17d4df789e3d0c2ce5ad11cc66831c383c1b6e5. --- .gitmodules | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 766a712b78c..ad50dd01dac 100644 --- a/.gitmodules +++ b/.gitmodules @@ -33,6 +33,10 @@ [submodule "tools/python-semver"] path = tools/python-semver url = https://github.com/k-bx/python-semver.git +[submodule "atmel-samd/asf4"] + path = ports/atmel-samd/asf4 + url = https://github.com/UVA-DSI/asf4.git + branch = circuitpython [submodule "tools/usb_descriptor"] path = tools/usb_descriptor url = https://github.com/adafruit/usb_descriptor.git @@ -60,6 +64,9 @@ [submodule "frozen/Adafruit_CircuitPython_DotStar"] path = frozen/Adafruit_CircuitPython_DotStar url = https://github.com/adafruit/Adafruit_CircuitPython_DotStar.git +[submodule "ports/atmel-samd/peripherals"] + path = ports/atmel-samd/peripherals + url = https://github.com/UVA-DSI/samd-peripherals [submodule "frozen/Adafruit_CircuitPython_Crickit"] path = frozen/Adafruit_CircuitPython_Crickit url = https://github.com/adafruit/Adafruit_CircuitPython_Crickit @@ -177,5 +184,3 @@ [submodule "frozen/Adafruit_CircuitPython_MIDI"] path = frozen/Adafruit_CircuitPython_MIDI url = https://github.com/adafruit/Adafruit_CircuitPython_MIDI -[submodule "ports/atmel-samd/peripherals"] - url = https://github.com/UVA-DSI/samd-peripherals From fbeef92feee54de1b5a8c766d8910353bc0f1b0f Mon Sep 17 00:00:00 2001 From: Sabas Date: Mon, 21 Jun 2021 14:43:20 -0500 Subject: [PATCH 25/36] fix PID --- ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk index 7266c8cdcd3..3c9f2a0a3ad 100644 --- a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk +++ b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk @@ -1,5 +1,5 @@ USB_VID = 0x1209 -USB_PID = 0xBAB3 +USB_PID = 0xBAE3 USB_PRODUCT = "Bast SAML21" USB_MANUFACTURER = "Electronic Cats" From f305bec28c08e6df206ae957ee3c491e4d8e90a8 Mon Sep 17 00:00:00 2001 From: Sabas Date: Mon, 21 Jun 2021 14:58:10 -0500 Subject: [PATCH 26/36] pre-commit format --- main.c | 4 +- .../asf4_conf/saml21/hpl_gclk_config.h | 48 +++++++++--------- .../asf4_conf/saml21/hpl_oscctrl_config.h | 18 +++---- .../asf4_conf/saml21/hpl_port_config.h | 24 ++++----- .../asf4_conf/saml21/hpl_sercom_config.h | 28 +++++------ .../asf4_conf/saml21/hpl_tc_config.h | 34 ++++++------- .../atmel-samd/asf4_conf/saml21/usbd_config.h | 26 +++++----- .../boards/bast_saml21/mpconfigboard.mk | 4 +- .../atmel-samd/common-hal/analogio/AnalogIn.c | 2 +- ports/atmel-samd/supervisor/port.c | 50 +++++++++---------- 10 files changed, 119 insertions(+), 119 deletions(-) diff --git a/main.c b/main.c index c200a10fe95..05c072bdf95 100755 --- a/main.c +++ b/main.c @@ -589,7 +589,7 @@ STATIC int run_repl(void) { int __attribute__((used)) main(void) { // initialise the cpu and peripherals safe_mode_t safe_mode = port_init(); - + // Turn on LEDs init_status_leds(); rgb_led_status_init(); @@ -616,7 +616,7 @@ int __attribute__((used)) main(void) { if (safe_mode == NO_SAFE_MODE) { safe_mode = wait_for_safe_mode_reset(); } - + stack_init(); diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h index a9376aa5534..a960dfab71e 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h @@ -37,7 +37,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_0_div_sel +// gclk_gen_0_div_sel #ifndef CONF_GCLK_GEN_0_DIVSEL #define CONF_GCLK_GEN_0_DIVSEL 0 #endif @@ -71,8 +71,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 0 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> // gclk_gen_0_div #ifndef CONF_GCLK_GEN_0_DIV #define CONF_GCLK_GEN_0_DIV 1 @@ -112,7 +112,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_1_div_sel +// gclk_gen_1_div_sel #ifndef CONF_GCLK_GEN_1_DIVSEL #define CONF_GCLK_GEN_1_DIVSEL 0 #endif @@ -146,8 +146,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 1 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> // gclk_gen_1_div #ifndef CONF_GCLK_GEN_1_DIV #define CONF_GCLK_GEN_1_DIV 1 @@ -188,7 +188,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_2_div_sel +// gclk_gen_2_div_sel #ifndef CONF_GCLK_GEN_2_DIVSEL #define CONF_GCLK_GEN_2_DIVSEL 0 #endif @@ -222,8 +222,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 2 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> // gclk_gen_2_div #ifndef CONF_GCLK_GEN_2_DIV #define CONF_GCLK_GEN_2_DIV 1 @@ -264,7 +264,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_3_div_sel +// gclk_gen_3_div_sel #ifndef CONF_GCLK_GEN_3_DIVSEL #define CONF_GCLK_GEN_3_DIVSEL 0 #endif @@ -298,8 +298,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 3 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> // gclk_gen_3_div #ifndef CONF_GCLK_GEN_3_DIV #define CONF_GCLK_GEN_3_DIV 1 @@ -340,7 +340,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_4_div_sel +// gclk_gen_4_div_sel #ifndef CONF_GCLK_GEN_4_DIVSEL #define CONF_GCLK_GEN_4_DIVSEL 0 #endif @@ -374,8 +374,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 4 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> // gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV #define CONF_GCLK_GEN_4_DIV 1 @@ -416,7 +416,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_5_div_sel +// gclk_gen_5_div_sel #ifndef CONF_GCLK_GEN_5_DIVSEL #define CONF_GCLK_GEN_5_DIVSEL 0 #endif @@ -450,8 +450,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 5 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> // gclk_gen_5_div #ifndef CONF_GCLK_GEN_5_DIV #define CONF_GCLK_GEN_5_DIV 1 @@ -492,7 +492,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_6_div_sel +// gclk_gen_6_div_sel #ifndef CONF_GCLK_GEN_6_DIVSEL #define CONF_GCLK_GEN_6_DIVSEL 0 #endif @@ -526,8 +526,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 6 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> // gclk_gen_6_div #ifndef CONF_GCLK_GEN_6_DIV #define CONF_GCLK_GEN_6_DIV 1 @@ -568,7 +568,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_7_div_sel +// gclk_gen_7_div_sel #ifndef CONF_GCLK_GEN_7_DIVSEL #define CONF_GCLK_GEN_7_DIVSEL 0 #endif @@ -602,8 +602,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 7 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> // gclk_gen_7_div #ifndef CONF_GCLK_GEN_7_DIV #define CONF_GCLK_GEN_7_DIV 1 diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h index 6a6f918817e..b77477e5468 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h @@ -86,8 +86,8 @@ #ifndef CONF_XOSC_XTALEN #define CONF_XOSC_XTALEN 0 #endif -// -// +// +// // 16MHz Internal Oscillator Configuration // Indicates whether configuration for OSC8M is enabled or not @@ -183,8 +183,8 @@ #ifndef CONF_OSC16M_TCAL #define CONF_OSC16M_16M_TCAL 0 #endif -// -// +// +// // DFLL Configuration // Indicates whether configuration for DFLL is enabled or not @@ -324,11 +324,11 @@ #define CONF_DFLL_FINE (0x200) #endif -// +// -// +// -// +// // DPLL Configuration // Indicates whether configuration for DPLL is enabled or not @@ -454,8 +454,8 @@ #ifndef CONF_DPLL_PRESC #define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val #endif -// -// +// +// // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h index 1efce33e332..60b3de02c06 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h @@ -265,19 +265,19 @@ // #define CONF_PORTA_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ - | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ - | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) #define CONF_PORTB_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ - | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ - | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h index bccc62acf6e..34607d2838b 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h @@ -293,12 +293,12 @@ // BAUD: register value low [7:0] // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW #define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ - / 1000U)) \ - * 10U \ - + 5U) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10U)) + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10U)) #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) #warning Requested I2C baudrate too low, please check @@ -308,9 +308,9 @@ #define CONF_SERCOM_1_I2CM_BAUD_RATE 1 #else #define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) #endif #endif @@ -525,7 +525,7 @@ #if CONF_SERCOM_2_USART_SAMPR == 0 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -533,7 +533,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 1 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -541,7 +541,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 2 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -549,7 +549,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 3 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -557,7 +557,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 4 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h index a889793a886..05f55d0c803 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h @@ -45,7 +45,7 @@ /* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ #if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val #define CONF_TC0_CC0 \ - ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) #define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) #elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val @@ -111,15 +111,15 @@ #endif /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CAPTEN0 0 -//#define CONF_TC0_CAPTEN1 0 -//#define CONF_TC0_COPEN0 0 -//#define CONF_TC0_COPEN1 0 +// #define CONF_TC0_CAPTEN0 0 +// #define CONF_TC0_CAPTEN1 0 +// #define CONF_TC0_COPEN0 0 +// #define CONF_TC0_COPEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_DIR 0 -//#define CONF_TC0_ONESHOT 0 -//#define CONF_TC0_LUPD 0 +// #define CONF_TC0_DIR 0 +// #define CONF_TC0_ONESHOT 0 +// #define CONF_TC0_LUPD 0 // Debug Running Mode // Indicates whether the Debug Running Mode is enabled or not @@ -179,25 +179,25 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // Event which will be performed on an event -// tc_arch_evact +// tc_arch_evact #ifndef CONF_TC0_EVACT #define CONF_TC0_EVACT 0 #endif // /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val +// #define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_INVEN0 0 -//#define CONF_TC0_INVEN1 0 +// #define CONF_TC0_INVEN0 0 +// #define CONF_TC0_INVEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_PERBUF 0 +// #define CONF_TC0_PERBUF 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CCBUF0 0 -//#define CONF_TC0_CCBUF1 0 +// #define CONF_TC0_CCBUF0 0 +// #define CONF_TC0_CCBUF1 0 // @@ -321,7 +321,7 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // Event which will be performed on an event -// tc_arch_evact +// tc_arch_evact #ifndef CONF_TC1_EVACT #define CONF_TC1_EVACT 0 #endif @@ -369,7 +369,7 @@ #ifndef CONF_TC1_CC0 #define CONF_TC1_CC0 \ - (uint32_t)(((float)CONF_TC1_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC1_FREQUENCY / CONF_TC1_PRESCALE))) + (uint32_t)(((float)CONF_TC1_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC1_FREQUENCY / CONF_TC1_PRESCALE))) #endif // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/usbd_config.h b/ports/atmel-samd/asf4_conf/saml21/usbd_config.h index be1fa3c9e07..b2629e12397 100644 --- a/ports/atmel-samd/asf4_conf/saml21/usbd_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/usbd_config.h @@ -101,7 +101,7 @@ #ifndef CONF_USB_COMPOSITE_IPRODUCT #define CONF_USB_COMPOSITE_IPRODUCT \ - (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) + (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) #endif // Unicode string of iProduct @@ -124,8 +124,8 @@ #ifndef CONF_USB_COMPOSITE_ISERIALNUM #define CONF_USB_COMPOSITE_ISERIALNUM \ - (CONF_USB_COMPOSITE_ISERIALNUM_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) + (CONF_USB_COMPOSITE_ISERIALNUM_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) #endif // Unicode string of iSerialNum @@ -162,9 +162,9 @@ #ifndef CONF_USB_COMPOSITE_ICONFIG #define CONF_USB_COMPOSITE_ICONFIG \ - (CONF_USB_COMPOSITE_ICONFIG_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ - + CONF_USB_COMPOSITE_ICONFIG_EN)) + (CONF_USB_COMPOSITE_ICONFIG_EN \ + * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ + + CONF_USB_COMPOSITE_ICONFIG_EN)) #endif // Unicode string of iConfig @@ -453,9 +453,9 @@ #ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT #define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ - 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ - 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ - 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 #endif // HID Generic INTERRUPT IN Endpoint Address @@ -650,7 +650,7 @@ #ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) #endif // @@ -713,7 +713,7 @@ #ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) #endif // @@ -775,7 +775,7 @@ #ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) #endif // @@ -837,7 +837,7 @@ #ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) #endif // diff --git a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk index 3c9f2a0a3ad..a8a30dbcaee 100644 --- a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk +++ b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk @@ -41,7 +41,7 @@ CIRCUITPY_FRAMEBUFFERDISPLAY=0 CIRCUITPY_GAMEPAD=0 CIRCUITPY_GAMEPADSHIFT=0 CIRCUITPY_GNSS=0 -CIRCUITPY_IPADDRESS=0 +CIRCUITPY_IPADDRESS=0 CIRCUITPY_I2CPERIPHERAL=0 CIRCUITPY_MATH=0 CIRCUITPY_NETWORK=0 @@ -81,4 +81,4 @@ CIRCUITPY_REQUIRE_I2C_PULLUPS=0 CIRCUITPY_SERIAL_BLE=0 CIRCUITPY_BLE_FILE_SERVICE=0 CIRCUITPY_SERIAL_UART=0 -SUPEROPT_GC=0 \ No newline at end of file +SUPEROPT_GC=0 diff --git a/ports/atmel-samd/common-hal/analogio/AnalogIn.c b/ports/atmel-samd/common-hal/analogio/AnalogIn.c index 4d0d37b6486..e7822f1569a 100644 --- a/ports/atmel-samd/common-hal/analogio/AnalogIn.c +++ b/ports/atmel-samd/common-hal/analogio/AnalogIn.c @@ -103,7 +103,7 @@ uint16_t common_hal_analogio_analogin_get_value(analogio_analogin_obj_t *self) { #ifdef SAMD21 adc_sync_set_channel_gain(&adc, self->channel, ADC_INPUTCTRL_GAIN_DIV2_Val); #endif - + #ifdef SAMD21 adc_sync_set_resolution(&adc, ADC_CTRLB_RESSEL_12BIT_Val); #endif diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 7ad326c5964..dbd9ef59c85 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -168,7 +168,7 @@ static void save_usb_clock_calibration(void) { static void rtc_init(void) { - + #ifdef SAMD21 _gclk_enable_channel(RTC_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK2_Val); RTC->MODE0.CTRL.bit.SWRST = true; @@ -263,7 +263,7 @@ safe_mode_t port_init(void) { SUPC->BOD33.bit.ENABLE = 0; SUPC->BOD33.bit.LEVEL = SAML21_BOD33_LEVEL; SUPC->BOD33.bit.ENABLE = 1; - + #if 0 // Designate QSPI memory mapped region as not cachable. #endif @@ -325,7 +325,7 @@ safe_mode_t port_init(void) { #endif #ifdef SAML21 - + // Clock init ( follow hpl_init.c ) hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 0); @@ -335,11 +335,11 @@ safe_mode_t port_init(void) { _oscctrl_init_sources(); _mclk_init(); #if _GCLK_INIT_1ST - _gclk_init_generators_by_fref(_GCLK_INIT_1ST); + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); #endif _oscctrl_init_referenced_generators(); - _gclk_init_generators_by_fref(0x0000001F); + _gclk_init_generators_by_fref(0x0000001F); #if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); @@ -348,10 +348,10 @@ safe_mode_t port_init(void) { // Update SystemCoreClock since it is hard coded with asf4 and not correct // Init 1ms tick timer (samd SystemCoreClock may not correct) - //SystemCoreClock = 16000000; - //SysTick_Config(16000000 / 1000); + // SystemCoreClock = 16000000; + // SysTick_Config(16000000 / 1000); - //USB Stuff + // USB Stuff /* USB Clock init * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock * for low speed and full speed operation. */ @@ -360,15 +360,15 @@ safe_mode_t port_init(void) { hri_mclk_set_APBBMASK_USB_bit(MCLK); // USB Pin Init - gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA24, false); - gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); - gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA25, false); - gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); + gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA24, false); + gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); + gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA25, false); + gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); - gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); - gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); + gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); + gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); #endif @@ -379,10 +379,10 @@ safe_mode_t port_init(void) { if (strcmp((char *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) { fine = ((uint16_t *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8]; } - //clock_init(BOARD_HAS_CRYSTAL, fine); + // clock_init(BOARD_HAS_CRYSTAL, fine); #else // Use a default fine value - //clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION); + // clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION); #endif rtc_init(); @@ -466,12 +466,12 @@ void reset_port(void) { // Output clocks for debugging. // not supported by SAMD51G; uncomment for SAMD51J or update for 51G // #ifdef SAM_D5X_E5X - //gpio_set_pin_function(PIN_PA10, GPIO_PIN_FUNCTION_M); // GCLK4, D3 - //gpio_set_pin_function(PIN_PA11, GPIO_PIN_FUNCTION_M); // GCLK5, A4 - //gpio_set_pin_function(PIN_PB14, GPIO_PIN_FUNCTION_M); // GCLK0, D5 - //gpio_set_pin_function(PIN_PB15, GPIO_PIN_FUNCTION_M); // GCLK1, D6 + // gpio_set_pin_function(PIN_PA10, GPIO_PIN_FUNCTION_M); // GCLK4, D3 + // gpio_set_pin_function(PIN_PA11, GPIO_PIN_FUNCTION_M); // GCLK5, A4 + // gpio_set_pin_function(PIN_PB14, GPIO_PIN_FUNCTION_M); // GCLK0, D5 + // gpio_set_pin_function(PIN_PB15, GPIO_PIN_FUNCTION_M); // GCLK1, D6 // #endif - + // Output clocks for debugging. // not supported by SAMD21G; uncomment for SAML51J or update for 21G #ifdef SAML21 @@ -596,12 +596,12 @@ void RTC_Handler(void) { // Our RTC is 32 bits and we're clocking it at 16.384khz which is 16 (2 ** 4) subticks per // tick. overflowed_ticks += (1L << (32 - 4)); - #ifdef SAM_D5X_E5X + #ifdef SAM_D5X_E5X } else if (intflag & RTC_MODE0_INTFLAG_PER2) { RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; // Do things common to all ports when the tick occurs supervisor_tick(); - #endif + #endif } else if (intflag & RTC_MODE0_INTFLAG_CMP0) { // Clear the interrupt because we may have hit a sleep and _ticks_enabled RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; From 9623d105871b4a3e9e5ae1485c136594dd1bbb99 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Mon, 21 Jun 2021 23:06:58 -0500 Subject: [PATCH 27/36] fix ident port.c --- ports/atmel-samd/supervisor/port.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index dbd9ef59c85..888aad32949 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -596,12 +596,12 @@ void RTC_Handler(void) { // Our RTC is 32 bits and we're clocking it at 16.384khz which is 16 (2 ** 4) subticks per // tick. overflowed_ticks += (1L << (32 - 4)); - #ifdef SAM_D5X_E5X + #ifdef SAM_D5X_E5X } else if (intflag & RTC_MODE0_INTFLAG_PER2) { RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; // Do things common to all ports when the tick occurs supervisor_tick(); - #endif + #endif } else if (intflag & RTC_MODE0_INTFLAG_CMP0) { // Clear the interrupt because we may have hit a sleep and _ticks_enabled RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; From 0e7e19cb4a00c9a229bf0ab8c02cef63286d08c5 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Wed, 23 Jun 2021 17:20:44 -0500 Subject: [PATCH 28/36] restart clock init --- ports/atmel-samd/supervisor/port.c | 39 ++---------------------------- 1 file changed, 2 insertions(+), 37 deletions(-) diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 888aad32949..c4a8c546272 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -334,41 +334,6 @@ safe_mode_t port_init(void) { _osc32kctrl_init_sources(); _oscctrl_init_sources(); _mclk_init(); - #if _GCLK_INIT_1ST - _gclk_init_generators_by_fref(_GCLK_INIT_1ST); - #endif - - _oscctrl_init_referenced_generators(); - _gclk_init_generators_by_fref(0x0000001F); - - #if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) - hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); - #endif - - // Update SystemCoreClock since it is hard coded with asf4 and not correct - // Init 1ms tick timer (samd SystemCoreClock may not correct) - // SystemCoreClock = 16000000; - // SysTick_Config(16000000 / 1000); - - // USB Stuff - /* USB Clock init - * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock - * for low speed and full speed operation. */ - hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); - hri_mclk_set_AHBMASK_USB_bit(MCLK); - hri_mclk_set_APBBMASK_USB_bit(MCLK); - - // USB Pin Init - gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA24, false); - gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); - gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA25, false); - gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); - - gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); - gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); #endif @@ -379,10 +344,10 @@ safe_mode_t port_init(void) { if (strcmp((char *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) { fine = ((uint16_t *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8]; } - // clock_init(BOARD_HAS_CRYSTAL, fine); + clock_init(BOARD_HAS_CRYSTAL, fine); #else // Use a default fine value - // clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION); + clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION); #endif rtc_init(); From 5cebce8c306bf09db77732759277e25b4bc1e822 Mon Sep 17 00:00:00 2001 From: Eduardo Date: Mon, 28 Jun 2021 20:02:18 -0500 Subject: [PATCH 29/36] comment line with bug on flash --- supervisor/shared/filesystem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/supervisor/shared/filesystem.c b/supervisor/shared/filesystem.c index 33d6c70dd22..c02f42c3861 100644 --- a/supervisor/shared/filesystem.c +++ b/supervisor/shared/filesystem.c @@ -97,8 +97,8 @@ void filesystem_init(bool create_allowed, bool force_create) { if ((res == FR_NO_FILESYSTEM && create_allowed) || force_create) { // No filesystem so create a fresh one, or reformat has been requested. - uint8_t working_buf[FF_MAX_SS]; - res = f_mkfs(&vfs_fat->fatfs, FM_FAT, 0, working_buf, sizeof(working_buf)); + //uint8_t working_buf[FF_MAX_SS]; + //res = f_mkfs(&vfs_fat->fatfs, FM_FAT, 0, working_buf, sizeof(working_buf)); // Flush the new file system to make sure it's repaired immediately. supervisor_flash_flush(); if (res != FR_OK) { From 2258ce997d45d6730d9779ecda76338c07ab11b5 Mon Sep 17 00:00:00 2001 From: Eduardo Date: Tue, 6 Jul 2021 14:22:03 -0500 Subject: [PATCH 30/36] modify usb init --- main.c | 15 ++++++++------- ports/atmel-samd/supervisor/port.c | 14 ++++---------- ports/atmel-samd/supervisor/usb.c | 4 ++++ 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/main.c b/main.c index 05c072bdf95..297b5b8b004 100755 --- a/main.c +++ b/main.c @@ -591,8 +591,8 @@ int __attribute__((used)) main(void) { safe_mode_t safe_mode = port_init(); // Turn on LEDs - init_status_leds(); - rgb_led_status_init(); + //init_status_leds(); + //rgb_led_status_init(); //port regs = 0x40002800 int *pt; @@ -607,9 +607,9 @@ int __attribute__((used)) main(void) { for(int i=0;i<5;i++){ //while(1){ *pt=1<<23; - delay(500000); + delay(10); *pt=0x00000000; - delay(500000); + delay(10); } // Wait briefly to give a reset window where we'll enter safe mode after the reset. @@ -626,13 +626,15 @@ int __attribute__((used)) main(void) { filesystem_init(safe_mode == NO_SAFE_MODE, false); // displays init after filesystem, since they could share the flash SPI - board_init(); + //board_init(); // Start the debug serial - serial_early_init(); + //serial_early_init(); // Reset everything and prep MicroPython to run boot.py. + #if 1 reset_port(); + #endif // Port-independent devices, like CIRCUITPY_BLEIO_HCI. reset_devices(); reset_board(); @@ -649,7 +651,6 @@ int __attribute__((used)) main(void) { // writable over USB. Set it here so that boot.py can change it. filesystem_set_internal_concurrent_write_protection(true); filesystem_set_internal_writable_by_usb(true); - run_boot_py(safe_mode); // Start USB after giving boot.py a chance to tweak behavior. diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index c4a8c546272..7c8abf50543 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -258,6 +258,8 @@ safe_mode_t port_init(void) { #endif #if defined(SAML21) + //SystemCoreClock = CONF_CPU_FREQUENCY; + //SysTick_Config(CONF_CPU_FREQUENCY / 1000); // Set brownout detection. // Disable while changing level. SUPC->BOD33.bit.ENABLE = 0; @@ -325,16 +327,8 @@ safe_mode_t port_init(void) { #endif #ifdef SAML21 - - // Clock init ( follow hpl_init.c ) - hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 0); - + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2); _set_performance_level(2); - - _osc32kctrl_init_sources(); - _oscctrl_init_sources(); - _mclk_init(); - #endif #if CALIBRATE_CRYSTALLESS @@ -355,7 +349,7 @@ safe_mode_t port_init(void) { init_shared_dma(); // Reset everything into a known state before board_init. - reset_port(); + //reset_port(); #ifdef SAMD21 if (PM->RCAUSE.bit.BOD33 == 1 || PM->RCAUSE.bit.BOD12 == 1) { diff --git a/ports/atmel-samd/supervisor/usb.c b/ports/atmel-samd/supervisor/usb.c index 592d6195c19..1d4107b6f2b 100644 --- a/ports/atmel-samd/supervisor/usb.c +++ b/ports/atmel-samd/supervisor/usb.c @@ -45,6 +45,10 @@ void init_usb_hardware(void) { hri_mclk_set_APBBMASK_USB_bit(MCLK); #endif + hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); + hri_mclk_set_AHBMASK_USB_bit(MCLK); + hri_mclk_set_APBBMASK_USB_bit(MCLK); + gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); gpio_set_pin_level(PIN_PA24, false); gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); From b7e64ea055234acfa5168b55170eeffe10c5ac52 Mon Sep 17 00:00:00 2001 From: Eduardo Date: Tue, 6 Jul 2021 14:26:52 -0500 Subject: [PATCH 31/36] modify asf4_conf --- .../asf4_conf/saml21/hpl_adc_config.h | 2 +- .../asf4_conf/saml21/hpl_gclk_config.h | 63 +- .../asf4_conf/saml21/hpl_osc32kctrl_config.h | 7 +- .../asf4_conf/saml21/hpl_oscctrl_config.h | 41 +- .../asf4_conf/saml21/hpl_port_config.h | 143 +++- .../asf4_conf/saml21/hpl_rtc_config.h | 195 +++++ .../asf4_conf/saml21/hpl_sercom_config.h | 28 +- .../asf4_conf/saml21/hpl_tc_config.h | 34 +- .../asf4_conf/saml21/hpl_usb_config.h | 16 +- .../asf4_conf/saml21/peripheral_clk_config.h | 6 +- .../atmel-samd/asf4_conf/saml21/usbd_config.h | 789 ++++++++---------- .../boards/bast_saml21/mpconfigboard.mk | 3 - 12 files changed, 797 insertions(+), 530 deletions(-) diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_adc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_adc_config.h index 82d367a66bb..dc5b54b0b61 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_adc_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_adc_config.h @@ -46,7 +46,7 @@ // These bits define the ADC clock relative to the peripheral clock (PRESCALER) // adc_prescaler #ifndef CONF_ADC_0_PRESCALER -#define CONF_ADC_0_PRESCALER 0x1 +#define CONF_ADC_0_PRESCALER 0x0 #endif // Free Running Mode diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h index a960dfab71e..4d6304eeab5 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h @@ -17,7 +17,6 @@ // Generic clock generator input pad // Generic clock generator 1 // 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) // 32kHz External Crystal Oscillator (XOSC32K) // 16MHz Internal Oscillator (OSC16M) // Digital Frequency Locked Loop (DFLL48M) @@ -37,7 +36,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_0_div_sel +// gclk_gen_0_div_sel #ifndef CONF_GCLK_GEN_0_DIVSEL #define CONF_GCLK_GEN_0_DIVSEL 0 #endif @@ -71,8 +70,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 0 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> // gclk_gen_0_div #ifndef CONF_GCLK_GEN_0_DIV #define CONF_GCLK_GEN_0_DIV 1 @@ -92,7 +91,6 @@ // External Crystal Oscillator 0.4-32MHz (XOSC) // Generic clock generator input pad // 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) // 32kHz External Crystal Oscillator (XOSC32K) // 16MHz Internal Oscillator (OSC16M) // Digital Frequency Locked Loop (DFLL48M) @@ -112,7 +110,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_1_div_sel +// gclk_gen_1_div_sel #ifndef CONF_GCLK_GEN_1_DIVSEL #define CONF_GCLK_GEN_1_DIVSEL 0 #endif @@ -146,8 +144,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 1 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> // gclk_gen_1_div #ifndef CONF_GCLK_GEN_1_DIV #define CONF_GCLK_GEN_1_DIV 1 @@ -168,7 +166,6 @@ // Generic clock generator input pad // Generic clock generator 1 // 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) // 32kHz External Crystal Oscillator (XOSC32K) // 16MHz Internal Oscillator (OSC16M) // Digital Frequency Locked Loop (DFLL48M) @@ -176,7 +173,7 @@ // This defines the clock source for generic clock generator 2 // gclk_gen_2_oscillator #ifndef CONF_GCLK_GEN_2_SOURCE -#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSC16M #endif // Run in Standby @@ -188,9 +185,9 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_2_div_sel +// gclk_gen_2_div_sel #ifndef CONF_GCLK_GEN_2_DIVSEL -#define CONF_GCLK_GEN_2_DIVSEL 0 +#define CONF_GCLK_GEN_2_DIVSEL 1 #endif // Output Enable @@ -218,12 +215,12 @@ // Indicates whether Generic Clock Generator Enable is enabled or not // gclk_arch_gen_2_enable #ifndef CONF_GCLK_GEN_2_GENEN -#define CONF_GCLK_GEN_2_GENEN 0 +#define CONF_GCLK_GEN_2_GENEN 1 #endif // -// Generic Clock Generator Division -// Generic clock generator 2 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> // gclk_gen_2_div #ifndef CONF_GCLK_GEN_2_DIV #define CONF_GCLK_GEN_2_DIV 1 @@ -244,7 +241,6 @@ // Generic clock generator input pad // Generic clock generator 1 // 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) // 32kHz External Crystal Oscillator (XOSC32K) // 16MHz Internal Oscillator (OSC16M) // Digital Frequency Locked Loop (DFLL48M) @@ -264,7 +260,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_3_div_sel +// gclk_gen_3_div_sel #ifndef CONF_GCLK_GEN_3_DIVSEL #define CONF_GCLK_GEN_3_DIVSEL 0 #endif @@ -298,8 +294,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 3 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> // gclk_gen_3_div #ifndef CONF_GCLK_GEN_3_DIV #define CONF_GCLK_GEN_3_DIV 1 @@ -320,7 +316,6 @@ // Generic clock generator input pad // Generic clock generator 1 // 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) // 32kHz External Crystal Oscillator (XOSC32K) // 16MHz Internal Oscillator (OSC16M) // Digital Frequency Locked Loop (DFLL48M) @@ -328,7 +323,7 @@ // This defines the clock source for generic clock generator 4 // gclk_gen_4_oscillator #ifndef CONF_GCLK_GEN_4_SOURCE -#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_OSC16M #endif // Run in Standby @@ -340,7 +335,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_4_div_sel +// gclk_gen_4_div_sel #ifndef CONF_GCLK_GEN_4_DIVSEL #define CONF_GCLK_GEN_4_DIVSEL 0 #endif @@ -370,12 +365,12 @@ // Indicates whether Generic Clock Generator Enable is enabled or not // gclk_arch_gen_4_enable #ifndef CONF_GCLK_GEN_4_GENEN -#define CONF_GCLK_GEN_4_GENEN 0 +#define CONF_GCLK_GEN_4_GENEN 1 #endif // -// Generic Clock Generator Division -// Generic clock generator 4 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> // gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV #define CONF_GCLK_GEN_4_DIV 1 @@ -416,7 +411,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_5_div_sel +// gclk_gen_5_div_sel #ifndef CONF_GCLK_GEN_5_DIVSEL #define CONF_GCLK_GEN_5_DIVSEL 0 #endif @@ -450,8 +445,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 5 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> // gclk_gen_5_div #ifndef CONF_GCLK_GEN_5_DIV #define CONF_GCLK_GEN_5_DIV 1 @@ -492,7 +487,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_6_div_sel +// gclk_gen_6_div_sel #ifndef CONF_GCLK_GEN_6_DIVSEL #define CONF_GCLK_GEN_6_DIVSEL 0 #endif @@ -526,8 +521,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 6 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> // gclk_gen_6_div #ifndef CONF_GCLK_GEN_6_DIV #define CONF_GCLK_GEN_6_DIV 1 @@ -568,7 +563,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_7_div_sel +// gclk_gen_7_div_sel #ifndef CONF_GCLK_GEN_7_DIVSEL #define CONF_GCLK_GEN_7_DIVSEL 0 #endif @@ -602,8 +597,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 7 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> // gclk_gen_7_div #ifndef CONF_GCLK_GEN_7_DIV #define CONF_GCLK_GEN_7_DIV 1 diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_osc32kctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_osc32kctrl_config.h index 897774b905c..e8720a5e81a 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_osc32kctrl_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_osc32kctrl_config.h @@ -13,7 +13,6 @@ // RTC source control // RTC Clock Source Selection // 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) // 32kHz External Crystal Oscillator (XOSC32K) // This defines the clock source for RTC // rtc_source_oscillator @@ -25,7 +24,7 @@ // rtc_1khz_selection #ifndef CONF_RTCCTRL_1KHZ -#define CONF_RTCCTRL_1KHZ 0 +#define CONF_RTCCTRL_1KHZ 1 #endif @@ -73,7 +72,7 @@ // Indicates whether On Demand Control is enabled or not // xosc32k_arch_ondemand #ifndef CONF_XOSC32K_ONDEMAND -#define CONF_XOSC32K_ONDEMAND 1 +#define CONF_XOSC32K_ONDEMAND 0 #endif // Run in Standby @@ -182,7 +181,7 @@ // Indicates whether configuration for OSCULP32K is enabled or not // enable_osculp32k #ifndef CONF_OSCULP32K_CONFIG -#define CONF_OSCULP32K_CONFIG 1 +#define CONF_OSCULP32K_CONFIG 0 #endif // 32kHz Ultra Low Power Internal Oscillator Control diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h index b77477e5468..9756aa19072 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h @@ -70,7 +70,7 @@ // Indicates whether On Demand Control is enabled or not // xosc_arch_ondemand #ifndef CONF_XOSC_ONDEMAND -#define CONF_XOSC_ONDEMAND 1 +#define CONF_XOSC_ONDEMAND 0 #endif // Run in Standby @@ -80,14 +80,35 @@ #define CONF_XOSC_RUNSTDBY 0 #endif +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc_arch_swben +#ifndef CONF_XOSC_SWBEN +#define CONF_XOSC_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc_arch_cfden +#ifndef CONF_XOSC_CFDEN +#define CONF_XOSC_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc_arch_cfdeo +#ifndef CONF_XOSC_CFDEO +#define CONF_XOSC_CFDEO 0 +#endif + // Crystal connected to XIN/XOUT Enable // Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not // xosc_arch_xtalen #ifndef CONF_XOSC_XTALEN #define CONF_XOSC_XTALEN 0 #endif -// -// +// +// // 16MHz Internal Oscillator Configuration // Indicates whether configuration for OSC8M is enabled or not @@ -183,8 +204,8 @@ #ifndef CONF_OSC16M_TCAL #define CONF_OSC16M_16M_TCAL 0 #endif -// -// +// +// // DFLL Configuration // Indicates whether configuration for DFLL is enabled or not @@ -324,11 +345,11 @@ #define CONF_DFLL_FINE (0x200) #endif -// +// -// +// -// +// // DPLL Configuration // Indicates whether configuration for DPLL is enabled or not @@ -454,8 +475,8 @@ #ifndef CONF_DPLL_PRESC #define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val #endif -// -// +// +// // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h index 60b3de02c06..a7bd3797368 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h @@ -65,6 +65,34 @@ #define CONF_PORTB_EVCTRL_EVACT_0 0 #endif +// +// PORT Input Event 0 configuration on PORT C + +// PORTC Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled +// portc_input_event_enable_0 +#ifndef CONF_PORTC_EVCTRL_PORTEI_0 +#define CONF_PORTC_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTC Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_0 +#ifndef CONF_PORTC_EVCTRL_PID_0 +#define CONF_PORTC_EVCTRL_PID_0 0x0 +#endif + +// PORTC Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 0 +// portc_event_action_0 +#ifndef CONF_PORTC_EVCTRL_EVACT_0 +#define CONF_PORTC_EVCTRL_EVACT_0 0 +#endif + // // @@ -130,6 +158,34 @@ #define CONF_PORTB_EVCTRL_EVACT_1 0 #endif +// +// PORT Input Event 1 configuration on PORT C + +// PORTC Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled +// portc_input_event_enable_1 +#ifndef CONF_PORTC_EVCTRL_PORTEI_1 +#define CONF_PORTC_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTC Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_1 +#ifndef CONF_PORTC_EVCTRL_PID_1 +#define CONF_PORTC_EVCTRL_PID_1 0x0 +#endif + +// PORTC Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 1 +// portc_event_action_1 +#ifndef CONF_PORTC_EVCTRL_EVACT_1 +#define CONF_PORTC_EVCTRL_EVACT_1 0 +#endif + // // @@ -195,6 +251,34 @@ #define CONF_PORTB_EVCTRL_EVACT_2 0 #endif +// +// PORT Input Event 2 configuration on PORT C + +// PORTC Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled +// portc_input_event_enable_2 +#ifndef CONF_PORTC_EVCTRL_PORTEI_2 +#define CONF_PORTC_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTC Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_2 +#ifndef CONF_PORTC_EVCTRL_PID_2 +#define CONF_PORTC_EVCTRL_PID_2 0x0 +#endif + +// PORTC Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 2 +// portc_event_action_2 +#ifndef CONF_PORTC_EVCTRL_EVACT_2 +#define CONF_PORTC_EVCTRL_EVACT_2 0 +#endif + // // @@ -260,24 +344,59 @@ #define CONF_PORTB_EVCTRL_EVACT_3 0 #endif +// +// PORT Input Event 3 configuration on PORT C + +// PORTC Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled +// portc_input_event_enable_3 +#ifndef CONF_PORTC_EVCTRL_PORTEI_3 +#define CONF_PORTC_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTC Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_3 +#ifndef CONF_PORTC_EVCTRL_PID_3 +#define CONF_PORTC_EVCTRL_PID_3 0x0 +#endif + +// PORTC Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 3 +// portc_event_action_3 +#ifndef CONF_PORTC_EVCTRL_EVACT_3 +#define CONF_PORTC_EVCTRL_EVACT_3 0 +#endif + // // #define CONF_PORTA_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ - | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ - | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) #define CONF_PORTB_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ - | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ - | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) +#define CONF_PORTC_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ + | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ + | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h index 48e27f0a611..60acebafff7 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_rtc_config.h @@ -45,6 +45,201 @@ #endif +// RTC Tamper Input 0 settings +// tamper_input_0_settings +#ifndef CONF_TAMPER_INPUT_0_SETTINGS +#define CONF_TAMPER_INPUT_0_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 0 level +// tamper_level_0 +#ifndef CONF_RTC_TAMP_LVL_0 +#define CONF_RTC_TAMP_LVL_0 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_0 +#ifndef CONF_RTC_TAMPER_INACT_0 +#define CONF_RTC_TAMPER_INACT_0 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 0 +// tamper_debounce_enable_0 +#ifndef CONF_RTC_TAMP_DEBNC_0 +#define CONF_RTC_TAMP_DEBNC_0 0 +#endif + +// + +// RTC Tamper Input 1 settings +// tamper_input_1_settings +#ifndef CONF_TAMPER_INPUT_1_SETTINGS +#define CONF_TAMPER_INPUT_1_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 1 level +// tamper_level_1 +#ifndef CONF_RTC_TAMP_LVL_1 +#define CONF_RTC_TAMP_LVL_1 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_1 +#ifndef CONF_RTC_TAMPER_INACT_1 +#define CONF_RTC_TAMPER_INACT_1 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 1 +// tamper_debounce_enable_1 +#ifndef CONF_RTC_TAMP_DEBNC_1 +#define CONF_RTC_TAMP_DEBNC_1 0 +#endif + +// + +// RTC Tamper Input 2 settings +// tamper_input_2_settings +#ifndef CONF_TAMPER_INPUT_2_SETTINGS +#define CONF_TAMPER_INPUT_2_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 2 level +// tamper_level_2 +#ifndef CONF_RTC_TAMP_LVL_2 +#define CONF_RTC_TAMP_LVL_2 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_2 +#ifndef CONF_RTC_TAMPER_INACT_2 +#define CONF_RTC_TAMPER_INACT_2 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 2 +// tamper_debounce_enable_2 +#ifndef CONF_RTC_TAMP_DEBNC_2 +#define CONF_RTC_TAMP_DEBNC_2 0 +#endif + +// + +// RTC Tamper Input 3 settings +// tamper_input_3_settings +#ifndef CONF_TAMPER_INPUT_3_SETTINGS +#define CONF_TAMPER_INPUT_3_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 3 level +// tamper_level_3 +#ifndef CONF_RTC_TAMP_LVL_3 +#define CONF_RTC_TAMP_LVL_3 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_3 +#ifndef CONF_RTC_TAMPER_INACT_3 +#define CONF_RTC_TAMPER_INACT_3 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 3 +// tamper_debounce_enable_3 +#ifndef CONF_RTC_TAMP_DEBNC_3 +#define CONF_RTC_TAMP_DEBNC_3 0 +#endif + +// + +// RTC Tamper Input 4 settings +// tamper_input_4_settings +#ifndef CONF_TAMPER_INPUT_4_SETTINGS +#define CONF_TAMPER_INPUT_4_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 4 level +// tamper_level_4 +#ifndef CONF_RTC_TAMP_LVL_4 +#define CONF_RTC_TAMP_LVL_4 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_4 +#ifndef CONF_RTC_TAMPER_INACT_4 +#define CONF_RTC_TAMPER_INACT_4 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 4 +// tamper_debounce_enable_4 +#ifndef CONF_RTC_TAMP_DEBNC_4 +#define CONF_RTC_TAMP_DEBNC_4 0 +#endif + +// + +// RTC Tamper Active Layer Frequency Prescalar +// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2 +// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4 +// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8 +// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16 +// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32 +// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64 +// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128 +// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256 +// These bits define the RTC Tamper Active Layer Frequecny Prescalar +// rtc_tamper_active_layer_frequency_prescalar +#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES +#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0 +#endif + +// RTC Tamper Debounce Frequency Prescalar +// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2 +// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4 +// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8 +// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16 +// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32 +// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64 +// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128 +// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256 +// These bits define the RTC Debounce Frequency Prescalar +// rtc_tamper_debounce_frequency_prescalar +#ifndef CONF_RTC_TAMP_DEBF_PRES +#define CONF_RTC_TAMP_DEBF_PRES 0 +#endif + // Event control // rtc_event_control #ifndef CONF_RTC_EVENT_CONTROL_ENABLE diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h index 34607d2838b..bccc62acf6e 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h @@ -293,12 +293,12 @@ // BAUD: register value low [7:0] // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW #define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ - / 1000U)) \ - * 10U \ - + 5U) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10U)) + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10U)) #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) #warning Requested I2C baudrate too low, please check @@ -308,9 +308,9 @@ #define CONF_SERCOM_1_I2CM_BAUD_RATE 1 #else #define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) #endif #endif @@ -525,7 +525,7 @@ #if CONF_SERCOM_2_USART_SAMPR == 0 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -533,7 +533,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 1 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -541,7 +541,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 2 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -549,7 +549,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 3 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -557,7 +557,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 4 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h index 05f55d0c803..a889793a886 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h @@ -45,7 +45,7 @@ /* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ #if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val #define CONF_TC0_CC0 \ - ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) #define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) #elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val @@ -111,15 +111,15 @@ #endif /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -// #define CONF_TC0_CAPTEN0 0 -// #define CONF_TC0_CAPTEN1 0 -// #define CONF_TC0_COPEN0 0 -// #define CONF_TC0_COPEN1 0 +//#define CONF_TC0_CAPTEN0 0 +//#define CONF_TC0_CAPTEN1 0 +//#define CONF_TC0_COPEN0 0 +//#define CONF_TC0_COPEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -// #define CONF_TC0_DIR 0 -// #define CONF_TC0_ONESHOT 0 -// #define CONF_TC0_LUPD 0 +//#define CONF_TC0_DIR 0 +//#define CONF_TC0_ONESHOT 0 +//#define CONF_TC0_LUPD 0 // Debug Running Mode // Indicates whether the Debug Running Mode is enabled or not @@ -179,25 +179,25 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // Event which will be performed on an event -// tc_arch_evact +// tc_arch_evact #ifndef CONF_TC0_EVACT #define CONF_TC0_EVACT 0 #endif // /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -// #define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val +//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -// #define CONF_TC0_INVEN0 0 -// #define CONF_TC0_INVEN1 0 +//#define CONF_TC0_INVEN0 0 +//#define CONF_TC0_INVEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -// #define CONF_TC0_PERBUF 0 +//#define CONF_TC0_PERBUF 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -// #define CONF_TC0_CCBUF0 0 -// #define CONF_TC0_CCBUF1 0 +//#define CONF_TC0_CCBUF0 0 +//#define CONF_TC0_CCBUF1 0 // @@ -321,7 +321,7 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // Event which will be performed on an event -// tc_arch_evact +// tc_arch_evact #ifndef CONF_TC1_EVACT #define CONF_TC1_EVACT 0 #endif @@ -369,7 +369,7 @@ #ifndef CONF_TC1_CC0 #define CONF_TC1_CC0 \ - (uint32_t)(((float)CONF_TC1_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC1_FREQUENCY / CONF_TC1_PRESCALE))) + (uint32_t)(((float)CONF_TC1_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC1_FREQUENCY / CONF_TC1_PRESCALE))) #endif // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_usb_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_usb_config.h index 73a9fea4421..af2178acd38 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_usb_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_usb_config.h @@ -39,7 +39,7 @@ // Max possible (by "Max Endpoint Number" config) // usbd_num_ep_sp #ifndef CONF_USB_D_NUM_EP_SP -#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 +#define CONF_USB_D_NUM_EP_SP CONF_USB_D_N_EP_MAX #endif // @@ -60,7 +60,7 @@ // The number of physical endpoints - 1 // usbd_arch_max_ep_n #ifndef CONF_USB_D_MAX_EP_N -#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 +#define CONF_USB_D_MAX_EP_N CONF_USB_N_1 #endif // USB Speed Limit @@ -138,7 +138,7 @@ // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) // usb_arch_ep2_cache #ifndef CONF_USB_EP2_CACHE -#define CONF_USB_EP2_CACHE 64 +#define CONF_USB_EP2_CACHE 0 #endif // Cache buffer size for EP2 IN @@ -176,7 +176,7 @@ // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) // usb_arch_ep3_cache #ifndef CONF_USB_EP3_CACHE -#define CONF_USB_EP3_CACHE 64 +#define CONF_USB_EP3_CACHE 0 #endif // Cache buffer size for EP3 IN @@ -214,7 +214,7 @@ // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) // usb_arch_ep4_cache #ifndef CONF_USB_EP4_CACHE -#define CONF_USB_EP4_CACHE 64 +#define CONF_USB_EP4_CACHE 0 #endif // Cache buffer size for EP4 IN @@ -252,7 +252,7 @@ // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) // usb_arch_ep5_cache #ifndef CONF_USB_EP5_CACHE -#define CONF_USB_EP5_CACHE 64 +#define CONF_USB_EP5_CACHE 0 #endif // Cache buffer size for EP5 IN @@ -290,7 +290,7 @@ // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) // usb_arch_ep6_cache #ifndef CONF_USB_EP6_CACHE -#define CONF_USB_EP6_CACHE 64 +#define CONF_USB_EP6_CACHE 0 #endif // Cache buffer size for EP6 IN @@ -328,7 +328,7 @@ // <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) // usb_arch_ep7_cache #ifndef CONF_USB_EP7_CACHE -#define CONF_USB_EP7_CACHE 64 +#define CONF_USB_EP7_CACHE 0 #endif // Cache buffer size for EP7 IN diff --git a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h index c444341a720..e69a1609897 100644 --- a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h @@ -57,7 +57,7 @@ * \brief RTC's Clock frequency */ #ifndef CONF_GCLK_RTC_FREQUENCY -#define CONF_GCLK_RTC_FREQUENCY 32768 +#define CONF_GCLK_RTC_FREQUENCY 1024 #endif // Core Clock Source @@ -297,7 +297,7 @@ // Select the slow clock source. #ifndef CONF_GCLK_SERCOM3_SLOW_SRC -#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val #endif /** @@ -313,7 +313,7 @@ * \brief SERCOM3's Slow Clock frequency */ #ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 16000000 #endif // TC Clock Source diff --git a/ports/atmel-samd/asf4_conf/saml21/usbd_config.h b/ports/atmel-samd/asf4_conf/saml21/usbd_config.h index b2629e12397..6317a856948 100644 --- a/ports/atmel-samd/asf4_conf/saml21/usbd_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/usbd_config.h @@ -14,33 +14,33 @@ #define CONF_USBD_HS_SP 0 #endif -// ---- USB Device Stack Composite Options ---- +// ---- USB Device Stack Mass Storage Options ---- // Enable String Descriptors -// usb_composite_str_en -#ifndef CONF_USB_COMPOSITE_STR_EN -#define CONF_USB_COMPOSITE_STR_EN 0 +// usb_msc_str_en +#ifndef CONF_USB_MSC_STR_EN +#define CONF_USB_MSC_STR_EN 1 #endif // Language IDs // Language IDs in c format, split by comma (E.g., 0x0409 ...) -// usb_composite_langid -#ifndef CONF_USB_COMPOSITE_LANGID -#define CONF_USB_COMPOSITE_LANGID "0x0409" +// usb_msc_langid +#ifndef CONF_USB_MSC_LANGID +#define CONF_USB_MSC_LANGID "0x0409" #endif -#ifndef CONF_USB_COMPOSITE_LANGID_DESC -#define CONF_USB_COMPOSITE_LANGID_DESC +#ifndef CONF_USB_MSC_LANGID_DESC +#define CONF_USB_MSC_LANGID_DESC 4, 0x03, 0x09, 0x04, #endif // -// Composite Device Descriptor +// Mass Storage Class (MSC) Device Descriptor // bcdUSB // <0x0200=> USB 2.0 version // <0x0210=> USB 2.1 version -// usb_composite_bcdusb -#ifndef CONF_USB_COMPOSITE_BCDUSB -#define CONF_USB_COMPOSITE_BCDUSB 0x200 +// usb_msc_bcdusb +#ifndef CONF_USB_MSC_BCDUSB +#define CONF_USB_MSC_BCDUSB 0x200 #endif // bMaxPackeSize0 @@ -48,133 +48,122 @@ // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes -// usb_composite_bmaxpksz0 -#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 -#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 +// usb_msc_bmaxpksz0 +#ifndef CONF_USB_MSC_BMAXPKSZ0 +#define CONF_USB_MSC_BMAXPKSZ0 0x40 #endif // idVender <0x0000-0xFFFF> -// usb_composite_idvender -#ifndef CONF_USB_COMPOSITE_IDVENDER -#define CONF_USB_COMPOSITE_IDVENDER 0x3eb +// usb_msc_idvender +#ifndef CONF_USB_MSC_IDVENDER +#define CONF_USB_MSC_IDVENDER 0x3eb #endif // idProduct <0x0000-0xFFFF> -// usb_composite_idproduct -#ifndef CONF_USB_COMPOSITE_IDPRODUCT -#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421 +// usb_msc_idproduct +#ifndef CONF_USB_MSC_IDPRODUCT +#define CONF_USB_MSC_IDPRODUCT 0x2403 #endif // bcdDevice <0x0000-0xFFFF> -// usb_composite_bcddevice -#ifndef CONF_USB_COMPOSITE_BCDDEVICE -#define CONF_USB_COMPOSITE_BCDDEVICE 0x100 +// usb_msc_bcddevice +#ifndef CONF_USB_MSC_BCDDEVICE +#define CONF_USB_MSC_BCDDEVICE 0x100 #endif // Enable string descriptor of iManufact -// usb_composite_imanufact_en -#ifndef CONF_USB_COMPOSITE_IMANUFACT_EN -#define CONF_USB_COMPOSITE_IMANUFACT_EN 0 +// usb_msc_imanufact_en +#ifndef CONF_USB_MSC_IMANUFACT_EN +#define CONF_USB_MSC_IMANUFACT_EN 0 #endif -#ifndef CONF_USB_COMPOSITE_IMANUFACT -#define CONF_USB_COMPOSITE_IMANUFACT (CONF_USB_COMPOSITE_IMANUFACT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN)) +#ifndef CONF_USB_MSC_IMANUFACT +#define CONF_USB_MSC_IMANUFACT (CONF_USB_MSC_IMANUFACT_EN * (CONF_USB_MSC_IMANUFACT_EN)) #endif // Unicode string of iManufact -// usb_composite_imanufact_str -#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR -#define CONF_USB_COMPOSITE_IMANUFACT_STR "Atmel" +// usb_msc_imanufact_str +#ifndef CONF_USB_MSC_IMANUFACT_STR +#define CONF_USB_MSC_IMANUFACT_STR "Atmel" #endif -#ifndef CONF_USB_COMPOSITE_IMANUFACT_STR_DESC -#define CONF_USB_COMPOSITE_IMANUFACT_STR_DESC +#ifndef CONF_USB_MSC_IMANUFACT_STR_DESC +#define CONF_USB_MSC_IMANUFACT_STR_DESC #endif // // Enable string descriptor of iProduct -// usb_composite_iproduct_en -#ifndef CONF_USB_COMPOSITE_IPRODUCT_EN -#define CONF_USB_COMPOSITE_IPRODUCT_EN 0 +// usb_msc_iproduct_en +#ifndef CONF_USB_MSC_IPRODUCT_EN +#define CONF_USB_MSC_IPRODUCT_EN 0 #endif -#ifndef CONF_USB_COMPOSITE_IPRODUCT -#define CONF_USB_COMPOSITE_IPRODUCT \ - (CONF_USB_COMPOSITE_IPRODUCT_EN * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN)) +#ifndef CONF_USB_MSC_IPRODUCT +#define CONF_USB_MSC_IPRODUCT (CONF_USB_MSC_IPRODUCT_EN * (CONF_USB_MSC_IMANUFACT_EN + CONF_USB_MSC_IPRODUCT_EN)) #endif // Unicode string of iProduct -// usb_composite_iproduct_str -#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR -#define CONF_USB_COMPOSITE_IPRODUCT_STR "Composite Demo" +// usb_msc_iproduct_str +#ifndef CONF_USB_MSC_IPRODUCT_STR +#define CONF_USB_MSC_IPRODUCT_STR "Mass Storage Class (MSC) Demo" #endif -#ifndef CONF_USB_COMPOSITE_IPRODUCT_STR_DESC -#define CONF_USB_COMPOSITE_IPRODUCT_STR_DESC +#ifndef CONF_USB_MSC_IPRODUCT_STR_DESC +#define CONF_USB_MSC_IPRODUCT_STR_DESC #endif // // Enable string descriptor of iSerialNum -// usb_composite_iserialnum_en -#ifndef CONF_USB_COMPOSITE_ISERIALNUM_EN -#define CONF_USB_COMPOSITE_ISERIALNUM_EN 0 +// usb_msc_iserialnum_en +#ifndef CONF_USB_MSC_ISERIALNUM_EN +#define CONF_USB_MSC_ISERIALNUM_EN 1 #endif -#ifndef CONF_USB_COMPOSITE_ISERIALNUM -#define CONF_USB_COMPOSITE_ISERIALNUM \ - (CONF_USB_COMPOSITE_ISERIALNUM_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN)) +#ifndef CONF_USB_MSC_ISERIALNUM +#define CONF_USB_MSC_ISERIALNUM \ + (CONF_USB_MSC_ISERIALNUM_EN * (CONF_USB_MSC_IMANUFACT_EN + CONF_USB_MSC_IPRODUCT_EN + CONF_USB_MSC_ISERIALNUM_EN)) #endif // Unicode string of iSerialNum -// usb_composite_iserialnum_str -#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR -#define CONF_USB_COMPOSITE_ISERIALNUM_STR "123456789ABCDEF" +// usb_msc_iserialnum_str +#ifndef CONF_USB_MSC_ISERIALNUM_STR +#define CONF_USB_MSC_ISERIALNUM_STR "123456789ABCDEF" #endif -#ifndef CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC -#define CONF_USB_COMPOSITE_ISERIALNUM_STR_DESC +#ifndef CONF_USB_MSC_ISERIALNUM_STR_DESC +#define CONF_USB_MSC_ISERIALNUM_STR_DESC \ + 32, 0x03, '1', 0x00, '2', 0x00, '3', 0x00, '4', 0x00, '5', 0x00, '6', 0x00, '7', 0x00, '8', 0x00, '9', 0x00, 'A', \ + 0x00, 'B', 0x00, 'C', 0x00, 'D', 0x00, 'E', 0x00, 'F', 0x00, #endif // -// bNumConfigurations <0x01-0xFF> -// usb_composite_bnumconfig -#ifndef CONF_USB_COMPOSITE_BNUMCONFIG -#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1 -#endif - // -// Composite Configuration Descriptor -// bConfigurationValue <0x01-0xFF> -// usb_composite_bconfigval -#ifndef CONF_USB_COMPOSITE_BCONFIGVAL -#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1 -#endif +// MSC Configuration Descriptor + // Enable string descriptor of iConfig -// usb_composite_iconfig_en -#ifndef CONF_USB_COMPOSITE_ICONFIG_EN -#define CONF_USB_COMPOSITE_ICONFIG_EN 0 +// usb_msc_iconfig_en +#ifndef CONF_USB_MSC_ICONFIG_EN +#define CONF_USB_MSC_ICONFIG_EN 0 #endif -#ifndef CONF_USB_COMPOSITE_ICONFIG -#define CONF_USB_COMPOSITE_ICONFIG \ - (CONF_USB_COMPOSITE_ICONFIG_EN \ - * (CONF_USB_COMPOSITE_IMANUFACT_EN + CONF_USB_COMPOSITE_IPRODUCT_EN + CONF_USB_COMPOSITE_ISERIALNUM_EN \ - + CONF_USB_COMPOSITE_ICONFIG_EN)) +#ifndef CONF_USB_MSC_ICONFIG +#define CONF_USB_MSC_ICONFIG \ + (CONF_USB_MSC_ICONFIG_EN \ + * (CONF_USB_MSC_IMANUFACT_EN + CONF_USB_MSC_IPRODUCT_EN + CONF_USB_MSC_ISERIALNUM_EN + CONF_USB_MSC_ICONFIG_EN)) #endif // Unicode string of iConfig -// usb_composite_iconfig_str -#ifndef CONF_USB_COMPOSITE_ICONFIG_STR -#define CONF_USB_COMPOSITE_ICONFIG_STR "" +// usb_msc_iconfig_str +#ifndef CONF_USB_MSC_ICONFIG_STR +#define CONF_USB_MSC_ICONFIG_STR "" #endif -#ifndef CONF_USB_COMPOSITE_ICONFIG_STR_DESC -#define CONF_USB_COMPOSITE_ICONFIG_STR_DESC +#ifndef CONF_USB_MSC_ICONFIG_STR_DESC +#define CONF_USB_MSC_ICONFIG_STR_DESC #endif // @@ -184,52 +173,29 @@ // <0xA0=> Bus power supply, support for remote wakeup // <0xC0=> Self powered, not support for remote wakeup // <0xE0=> Self powered, support for remote wakeup -// usb_composite_bmattri -#ifndef CONF_USB_COMPOSITE_BMATTRI -#define CONF_USB_COMPOSITE_BMATTRI 0x80 +// usb_msc_bmattri +#ifndef CONF_USB_MSC_BMATTRI +#define CONF_USB_MSC_BMATTRI 0x80 #endif // bMaxPower <0x00-0xFF> -// usb_composite_bmaxpower -#ifndef CONF_USB_COMPOSITE_BMAXPOWER -#define CONF_USB_COMPOSITE_BMAXPOWER 0x32 +// usb_msc_bmaxpower +#ifndef CONF_USB_MSC_BMAXPOWER +#define CONF_USB_MSC_BMAXPOWER 0x32 #endif // -// CDC ACM Support -// usb_composite_cdc_acm_support -#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN -#define CONF_USB_COMPOSITE_CDC_ACM_EN 0 -#endif - -// CDC ACM Comm Interrupt IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 +// MSC Interface Descriptor -// usb_composite_cdc_acm_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 +#ifndef CONF_USB_MSC_BIFCNUM +#define CONF_USB_MSC_BIFCNUM 0x00 #endif -// CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_cdc_acm_comm_int_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 +#ifndef CONF_USB_MSC_IIFC +#define CONF_USB_MSC_IIFC 0x00 #endif -// CDC ACM Data BULK IN Endpoint Address +// BULK IN Endpoint Address // <0x81=> EndpointAddress = 0x81 // <0x82=> EndpointAddress = 0x82 // <0x83=> EndpointAddress = 0x83 @@ -237,67 +203,24 @@ // <0x85=> EndpointAddress = 0x85 // <0x86=> EndpointAddress = 0x86 // <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_cdc_acm_data_bulkin_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 -#endif - -// CDC ACM Data BULK IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_cdc_acm_data_builin_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 -#endif - -// CDC ACM Data BULK IN Endpoint wMaxPacketSize for High Speed -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes -// <0x0080=> 128 bytes -// <0x0100=> 256 bytes -// <0x0200=> 512 bytes - -// usb_composite_cdc_acm_data_builin_maxpksz_hs -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ_HS 0x200 -#endif - -// CDC ACM Data BULK OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_cdc_acm_data_bulkout_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 +// usb_msc_bulkin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_MSC_BULKIN_EPADDR +#define CONF_USB_MSC_BULKIN_EPADDR 0x81 #endif -// CDC ACM Data BULK OUT Endpoint wMaxPacketSize +// BULK IN Endpoint wMaxPacketSize // <0x0008=> 8 bytes // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes - -// usb_composite_cdc_acm_data_buckout_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 +// usb_msc_bulkin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_MSC_BULKIN_MAXPKSZ +#define CONF_USB_MSC_BULKIN_MAXPKSZ 0x40 #endif -// CDC ACM Data BULK OUT Endpoint wMaxPacketSize for High Speed +// BULK IN Endpoint wMaxPacketSize for High Speed // <0x0008=> 8 bytes // <0x0010=> 16 bytes // <0x0020=> 32 bytes @@ -305,189 +228,13 @@ // <0x0080=> 128 bytes // <0x0100=> 256 bytes // <0x0200=> 512 bytes - -// usb_composite_cdc_acm_data_buckout_maxpksz_hs -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ_HS 0x200 -#endif - -// CDC ACM Echo Demo generation -// conf_usb_composite_cdc_echo_demo -// Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo. -// Buf is packet buffer for data receive and echo back. -// The buffer is 4 byte aligned to support DMA. -#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO -#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0 -#endif - -// - -// HID Mouse Support -// usb_composite_hid_mouse_support -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN -#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0 -#endif - -// HID Mouse INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_mouse_intin_epaddr +// usb_msc_bulkin_maxpksz_hs // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83 +#ifndef CONF_USB_MSC_BULKIN_MAXPKSZ_HS +#define CONF_USB_MSC_BULKIN_MAXPKSZ_HS 0x200 #endif -// HID Mouse INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_mouse_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 -#endif - -// HID Mouse Move Demo generation -// conf_usb_composite_hid_mouse_demo -// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. -// Button1 and button3 are the pins used for mouse moving left and right. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO -#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0 -#endif - -// - -// HID Keyboard Support -// usb_composite_hid_keyboard_support -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN -#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0 -#endif - -// HID Keyboard INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_keyboard_intin_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84 -#endif - -// HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_keyboard_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8 -#endif - -// HID Keyboard INTERRUPT OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_hid_keyboard_intout_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2 -#endif - -// HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_keyboard_intout_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 -#endif - -// HID Keyboard Caps Lock Demo generation -// conf_usb_composite_hid_keyboard_demo -// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. -// Buffon2 is the pin used for keyboard CAPS LOCK simulation. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO -#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0 -#endif - -// - -// HID Generic Support -// usb_composite_hid_generic_support -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN -#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0 -#endif - -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN -#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53 -#endif - -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT -#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ - 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ - 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ - 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 -#endif - -// HID Generic INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_generic_intin_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85 -#endif - -// HID Generic INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_generic_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40 -#endif - -// HID Generic INTERRUPT OUT Endpoint Address +// BULK OUT Endpoint Address // <0x01=> EndpointAddress = 0x01 // <0x02=> EndpointAddress = 0x02 // <0x03=> EndpointAddress = 0x03 @@ -495,46 +242,24 @@ // <0x05=> EndpointAddress = 0x05 // <0x06=> EndpointAddress = 0x06 // <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_hid_generic_intout_epaddr +// usb_msc_bulkout_epaddr // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR -#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3 +#ifndef CONF_USB_MSC_BULKOUT_EPADDR +#define CONF_USB_MSC_BULKOUT_EPADDR 0x1 #endif -// HID Generic INTERRUPT OUT Endpoint wMaxPacketSize +// BULK OUT Endpoint wMaxPacketSize // <0x0008=> 8 bytes // <0x0010=> 16 bytes // <0x0020=> 32 bytes // <0x0040=> 64 bytes -// usb_composite_hid_generic_intout_maxpksz +// usb_msc_bulkout_maxpksz // Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40 +#ifndef CONF_USB_MSC_BULKOUT_MAXPKSZ +#define CONF_USB_MSC_BULKOUT_MAXPKSZ 0x40 #endif -// - -// MSC Support -// usb_composite_msc_support -#ifndef CONF_USB_COMPOSITE_MSC_EN -#define CONF_USB_COMPOSITE_MSC_EN 0 -#endif - -// MSC BULK Endpoints wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_msc_bulk_maxpksz -#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ -#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x40 -#endif - -// MSC BULK Endpoints wMaxPacketSize for High Speed +// BULK OUT Endpoint wMaxPacketSize for High Speed // <0x0008=> 8 bytes // <0x0010=> 16 bytes // <0x0020=> 32 bytes @@ -542,48 +267,17 @@ // <0x0080=> 128 bytes // <0x0100=> 256 bytes // <0x0200=> 512 bytes - -// usb_composite_msc_bulk_maxpksz_hs -#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS -#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ_HS 0x200 -#endif - -// MSC BULK IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_msc_bulkin_epaddr -#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR -#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86 -#endif - -// MSC BULK OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_msc_bulkout_epaddr -#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR -#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x4 +// usb_msc_bulkout_maxpksz_hs +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_MSC_BULKOUT_MAXPKSZ_HS +#define CONF_USB_MSC_BULKOUT_MAXPKSZ_HS 0x200 #endif +// // Enable Demo code for Disk LUN handling -// usb_composite_msc_demo_en -#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO -#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1 +// conf_usb_msc_demo_en +#ifndef CONF_USB_MSC_LUN_DEMO +#define CONF_USB_MSC_LUN_DEMO 1 #endif // Disk access cache/buffer of sectors if non-RAM disk (e.g., SD/MMC) enabled <1-64> @@ -650,7 +344,7 @@ #ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) #endif // @@ -713,7 +407,7 @@ #ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) #endif // @@ -775,7 +469,7 @@ #ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) #endif // @@ -837,12 +531,259 @@ #ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for LUN 4 +// conf_usb_msc_lun4_enable +#ifndef CONF_USB_MSC_LUN4_ENABLE +#define CONF_USB_MSC_LUN4_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN4_TYPE +#define CONF_USB_MSC_LUN4_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun4_rmb +#ifndef CONF_USB_MSC_LUN4_RMB +#define CONF_USB_MSC_LUN4_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN4_ISO +#define CONF_USB_MSC_LUN4_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN4_ECMA +#define CONF_USB_MSC_LUN4_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN4_ANSI +#define CONF_USB_MSC_LUN4_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN4_REPO +#define CONF_USB_MSC_LUN4_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN4_FACTORY +#define CONF_USB_MSC_LUN4_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN4_PRODUCT +#define CONF_USB_MSC_LUN4_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN4_PRODUCT_VERSION +#define CONF_USB_MSC_LUN4_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// conf_usb_msc_lun4_capacity + +#ifndef CONF_USB_MSC_LUN4_CAPACITY +#define CONF_USB_MSC_LUN4_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN4_BLOCK_SIZE +#define CONF_USB_MSC_LUN4_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN4_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN4_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN4_CAPACITY * 1024 / CONF_USB_MSC_LUN4_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for LUN 5 +// conf_usb_msc_lun5_enable +#ifndef CONF_USB_MSC_LUN5_ENABLE +#define CONF_USB_MSC_LUN5_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN5_TYPE +#define CONF_USB_MSC_LUN5_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun5_rmb +#ifndef CONF_USB_MSC_LUN5_RMB +#define CONF_USB_MSC_LUN5_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN5_ISO +#define CONF_USB_MSC_LUN5_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN5_ECMA +#define CONF_USB_MSC_LUN5_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN5_ANSI +#define CONF_USB_MSC_LUN5_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN5_REPO +#define CONF_USB_MSC_LUN5_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN5_FACTORY +#define CONF_USB_MSC_LUN5_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN5_PRODUCT +#define CONF_USB_MSC_LUN5_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN5_PRODUCT_VERSION +#define CONF_USB_MSC_LUN5_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// conf_usb_msc_lun5_capacity + +#ifndef CONF_USB_MSC_LUN5_CAPACITY +#define CONF_USB_MSC_LUN5_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN5_BLOCK_SIZE +#define CONF_USB_MSC_LUN5_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN5_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN5_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN5_CAPACITY * 1024 / CONF_USB_MSC_LUN5_BLOCK_SIZE - 1) +#endif + +// + +// Enable Demo for LUN 6 +// conf_usb_msc_lun6_enable +#ifndef CONF_USB_MSC_LUN6_ENABLE +#define CONF_USB_MSC_LUN6_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN6_TYPE +#define CONF_USB_MSC_LUN6_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun6_rmb +#ifndef CONF_USB_MSC_LUN6_RMB +#define CONF_USB_MSC_LUN6_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN6_ISO +#define CONF_USB_MSC_LUN6_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN6_ECMA +#define CONF_USB_MSC_LUN6_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN6_ANSI +#define CONF_USB_MSC_LUN6_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN6_REPO +#define CONF_USB_MSC_LUN6_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN6_FACTORY +#define CONF_USB_MSC_LUN6_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN6_PRODUCT +#define CONF_USB_MSC_LUN6_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN6_PRODUCT_VERSION +#define CONF_USB_MSC_LUN6_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// conf_usb_msc_lun6_capacity + +#ifndef CONF_USB_MSC_LUN6_CAPACITY +#define CONF_USB_MSC_LUN6_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN6_BLOCK_SIZE +#define CONF_USB_MSC_LUN6_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN6_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN6_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN6_CAPACITY * 1024 / CONF_USB_MSC_LUN6_BLOCK_SIZE - 1) #endif // +// Enable Demo for LUN 7 +// conf_usb_msc_lun7_enable +#ifndef CONF_USB_MSC_LUN7_ENABLE +#define CONF_USB_MSC_LUN7_ENABLE 0 +#endif + +#ifndef CONF_USB_MSC_LUN7_TYPE +#define CONF_USB_MSC_LUN7_TYPE 0x00 +#endif + +// The disk is removable +// conf_usb_msc_lun7_rmb +#ifndef CONF_USB_MSC_LUN7_RMB +#define CONF_USB_MSC_LUN7_RMB 0x1 +#endif + +#ifndef CONF_USB_MSC_LUN7_ISO +#define CONF_USB_MSC_LUN7_ISO 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN7_ECMA +#define CONF_USB_MSC_LUN7_ECMA 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN7_ANSI +#define CONF_USB_MSC_LUN7_ANSI 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN7_REPO +#define CONF_USB_MSC_LUN7_REPO 0x01 +#endif + +#ifndef CONF_USB_MSC_LUN7_FACTORY +#define CONF_USB_MSC_LUN7_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN7_PRODUCT +#define CONF_USB_MSC_LUN7_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#endif + +#ifndef CONF_USB_MSC_LUN7_PRODUCT_VERSION +#define CONF_USB_MSC_LUN7_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 +#endif + +// Disk Size (in KB) <0x1-0xFFFFFFFF> +// conf_usb_msc_lun7_capacity + +#ifndef CONF_USB_MSC_LUN7_CAPACITY +#define CONF_USB_MSC_LUN7_CAPACITY 22 +#endif + +#ifndef CONF_USB_MSC_LUN7_BLOCK_SIZE +#define CONF_USB_MSC_LUN7_BLOCK_SIZE 512 +#endif + +#ifndef CONF_USB_MSC_LUN7_LAST_BLOCK_ADDR +#define CONF_USB_MSC_LUN7_LAST_BLOCK_ADDR \ + ((uint32_t)CONF_USB_MSC_LUN7_CAPACITY * 1024 / CONF_USB_MSC_LUN7_BLOCK_SIZE - 1) +#endif + // + // // <<< end of configuration section >>> diff --git a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk index a8a30dbcaee..0043231fcf8 100644 --- a/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk +++ b/ports/atmel-samd/boards/bast_saml21/mpconfigboard.mk @@ -18,7 +18,6 @@ CIRCUITPY_PWMIO = 0 CIRCUITPY_AUDIOCORE = 0 CIRCUITPY_BUSIO = 0 CIRCUITPY_PIXELBUF = 0 -CIRCUITPY_USB_MIDI = 0 CIRCUITPY_TOUCHIO = 0 CIRCUITPY_BITBANGIO = 0 CIRCUITPY_BITMAPTOOLS = 0 @@ -58,7 +57,6 @@ CIRCUITPY_SSL=0 CIRCUITPY_STRUCT=0 CIRCUITPY_TERMINALIO=0 CIRCUITPY_ULAB=0 -CIRCUITPY_USB_HID=0 CIRCUITPY_VECTORIO=0 MICROPY_PY_ASYNC_AWAIT=0 CIRCUITPY_AESIO=0 @@ -80,5 +78,4 @@ CIRCUITPY_BITBANG_APA102=0 CIRCUITPY_REQUIRE_I2C_PULLUPS=0 CIRCUITPY_SERIAL_BLE=0 CIRCUITPY_BLE_FILE_SERVICE=0 -CIRCUITPY_SERIAL_UART=0 SUPEROPT_GC=0 From fefff3cd8ecec6867c91df15b9eb65905846a8d4 Mon Sep 17 00:00:00 2001 From: Sabas Date: Tue, 6 Jul 2021 18:20:39 -0500 Subject: [PATCH 32/36] check pre-commit --- .../asf4_conf/saml21/hpl_gclk_config.h | 48 +++++++++---------- .../asf4_conf/saml21/hpl_oscctrl_config.h | 18 +++---- .../asf4_conf/saml21/hpl_port_config.h | 36 +++++++------- .../asf4_conf/saml21/hpl_sercom_config.h | 28 +++++------ .../asf4_conf/saml21/hpl_tc_config.h | 34 ++++++------- .../asf4_conf/saml21/peripheral_clk_config.h | 32 +++++++++++++ .../atmel-samd/asf4_conf/saml21/usbd_config.h | 26 +++++----- ports/atmel-samd/supervisor/port.c | 10 ++-- supervisor/shared/filesystem.c | 4 +- 9 files changed, 134 insertions(+), 102 deletions(-) diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h index 4d6304eeab5..01ec013ed59 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_gclk_config.h @@ -36,7 +36,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_0_div_sel +// gclk_gen_0_div_sel #ifndef CONF_GCLK_GEN_0_DIVSEL #define CONF_GCLK_GEN_0_DIVSEL 0 #endif @@ -70,8 +70,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 0 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> // gclk_gen_0_div #ifndef CONF_GCLK_GEN_0_DIV #define CONF_GCLK_GEN_0_DIV 1 @@ -110,7 +110,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_1_div_sel +// gclk_gen_1_div_sel #ifndef CONF_GCLK_GEN_1_DIVSEL #define CONF_GCLK_GEN_1_DIVSEL 0 #endif @@ -144,8 +144,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 1 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> // gclk_gen_1_div #ifndef CONF_GCLK_GEN_1_DIV #define CONF_GCLK_GEN_1_DIV 1 @@ -185,7 +185,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_2_div_sel +// gclk_gen_2_div_sel #ifndef CONF_GCLK_GEN_2_DIVSEL #define CONF_GCLK_GEN_2_DIVSEL 1 #endif @@ -219,8 +219,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 2 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> // gclk_gen_2_div #ifndef CONF_GCLK_GEN_2_DIV #define CONF_GCLK_GEN_2_DIV 1 @@ -260,7 +260,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_3_div_sel +// gclk_gen_3_div_sel #ifndef CONF_GCLK_GEN_3_DIVSEL #define CONF_GCLK_GEN_3_DIVSEL 0 #endif @@ -294,8 +294,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 3 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> // gclk_gen_3_div #ifndef CONF_GCLK_GEN_3_DIV #define CONF_GCLK_GEN_3_DIV 1 @@ -335,7 +335,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_4_div_sel +// gclk_gen_4_div_sel #ifndef CONF_GCLK_GEN_4_DIVSEL #define CONF_GCLK_GEN_4_DIVSEL 0 #endif @@ -369,8 +369,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 4 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> // gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV #define CONF_GCLK_GEN_4_DIV 1 @@ -411,7 +411,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_5_div_sel +// gclk_gen_5_div_sel #ifndef CONF_GCLK_GEN_5_DIVSEL #define CONF_GCLK_GEN_5_DIVSEL 0 #endif @@ -445,8 +445,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 5 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> // gclk_gen_5_div #ifndef CONF_GCLK_GEN_5_DIV #define CONF_GCLK_GEN_5_DIV 1 @@ -487,7 +487,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_6_div_sel +// gclk_gen_6_div_sel #ifndef CONF_GCLK_GEN_6_DIVSEL #define CONF_GCLK_GEN_6_DIVSEL 0 #endif @@ -521,8 +521,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 6 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> // gclk_gen_6_div #ifndef CONF_GCLK_GEN_6_DIV #define CONF_GCLK_GEN_6_DIV 1 @@ -563,7 +563,7 @@ // Divide Selection // Indicates whether Divide Selection is enabled or not -// gclk_gen_7_div_sel +// gclk_gen_7_div_sel #ifndef CONF_GCLK_GEN_7_DIVSEL #define CONF_GCLK_GEN_7_DIVSEL 0 #endif @@ -597,8 +597,8 @@ #endif // -// Generic Clock Generator Division -// Generic clock generator 7 division <0x0000-0xFFFF> +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> // gclk_gen_7_div #ifndef CONF_GCLK_GEN_7_DIV #define CONF_GCLK_GEN_7_DIV 1 diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h index 9756aa19072..a4951dbf128 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_oscctrl_config.h @@ -107,8 +107,8 @@ #ifndef CONF_XOSC_XTALEN #define CONF_XOSC_XTALEN 0 #endif -// -// +// +// // 16MHz Internal Oscillator Configuration // Indicates whether configuration for OSC8M is enabled or not @@ -204,8 +204,8 @@ #ifndef CONF_OSC16M_TCAL #define CONF_OSC16M_16M_TCAL 0 #endif -// -// +// +// // DFLL Configuration // Indicates whether configuration for DFLL is enabled or not @@ -345,11 +345,11 @@ #define CONF_DFLL_FINE (0x200) #endif -// +// -// +// -// +// // DPLL Configuration // Indicates whether configuration for DPLL is enabled or not @@ -475,8 +475,8 @@ #ifndef CONF_DPLL_PRESC #define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val #endif -// -// +// +// // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h index a7bd3797368..e5e69ea3346 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_port_config.h @@ -377,26 +377,26 @@ // #define CONF_PORTA_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ - | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ - | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) #define CONF_PORTB_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ - | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ - | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) #define CONF_PORTC_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ - | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ - | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) + (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ + | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ + | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h index bccc62acf6e..34607d2838b 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_sercom_config.h @@ -293,12 +293,12 @@ // BAUD: register value low [7:0] // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW #define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ - / 1000U)) \ - * 10U \ - + 5U) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10U)) + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10U)) #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) #warning Requested I2C baudrate too low, please check @@ -308,9 +308,9 @@ #define CONF_SERCOM_1_I2CM_BAUD_RATE 1 #else #define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) #endif #endif @@ -525,7 +525,7 @@ #if CONF_SERCOM_2_USART_SAMPR == 0 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -533,7 +533,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 1 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -541,7 +541,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 2 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -549,7 +549,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 3 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 @@ -557,7 +557,7 @@ #elif CONF_SERCOM_2_USART_SAMPR == 4 #ifndef CONF_SERCOM_2_USART_BAUD_RATE #define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) #endif #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 diff --git a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h index a889793a886..05f55d0c803 100644 --- a/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/hpl_tc_config.h @@ -45,7 +45,7 @@ /* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ #if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val #define CONF_TC0_CC0 \ - ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) #define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) #elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val @@ -111,15 +111,15 @@ #endif /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CAPTEN0 0 -//#define CONF_TC0_CAPTEN1 0 -//#define CONF_TC0_COPEN0 0 -//#define CONF_TC0_COPEN1 0 +// #define CONF_TC0_CAPTEN0 0 +// #define CONF_TC0_CAPTEN1 0 +// #define CONF_TC0_COPEN0 0 +// #define CONF_TC0_COPEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_DIR 0 -//#define CONF_TC0_ONESHOT 0 -//#define CONF_TC0_LUPD 0 +// #define CONF_TC0_DIR 0 +// #define CONF_TC0_ONESHOT 0 +// #define CONF_TC0_LUPD 0 // Debug Running Mode // Indicates whether the Debug Running Mode is enabled or not @@ -179,25 +179,25 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // Event which will be performed on an event -// tc_arch_evact +// tc_arch_evact #ifndef CONF_TC0_EVACT #define CONF_TC0_EVACT 0 #endif // /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val +// #define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_INVEN0 0 -//#define CONF_TC0_INVEN1 0 +// #define CONF_TC0_INVEN0 0 +// #define CONF_TC0_INVEN1 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_PERBUF 0 +// #define CONF_TC0_PERBUF 0 /* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CCBUF0 0 -//#define CONF_TC0_CCBUF1 0 +// #define CONF_TC0_CCBUF0 0 +// #define CONF_TC0_CCBUF1 0 // @@ -321,7 +321,7 @@ // <6=> Period captured in CC1, pulse width in CC0 // <7=> Pulse width capture // Event which will be performed on an event -// tc_arch_evact +// tc_arch_evact #ifndef CONF_TC1_EVACT #define CONF_TC1_EVACT 0 #endif @@ -369,7 +369,7 @@ #ifndef CONF_TC1_CC0 #define CONF_TC1_CC0 \ - (uint32_t)(((float)CONF_TC1_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC1_FREQUENCY / CONF_TC1_PRESCALE))) + (uint32_t)(((float)CONF_TC1_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC1_FREQUENCY / CONF_TC1_PRESCALE))) #endif // <<< end of configuration section >>> diff --git a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h index e69a1609897..1977b2e61ce 100644 --- a/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/peripheral_clk_config.h @@ -380,6 +380,38 @@ #define CONF_GCLK_TC1_FREQUENCY 16000000 #endif +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC1_SRC +#define CONF_GCLK_TC1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC1_FREQUENCY + * \brief TC1's Clock frequency + */ +#ifndef CONF_GCLK_TC1_FREQUENCY +#define CONF_GCLK_TC1_FREQUENCY 48000000 +#endif + // DAC Clock Source // Generic clock generator 0 diff --git a/ports/atmel-samd/asf4_conf/saml21/usbd_config.h b/ports/atmel-samd/asf4_conf/saml21/usbd_config.h index 6317a856948..ea4c440f5f8 100644 --- a/ports/atmel-samd/asf4_conf/saml21/usbd_config.h +++ b/ports/atmel-samd/asf4_conf/saml21/usbd_config.h @@ -123,7 +123,7 @@ #ifndef CONF_USB_MSC_ISERIALNUM #define CONF_USB_MSC_ISERIALNUM \ - (CONF_USB_MSC_ISERIALNUM_EN * (CONF_USB_MSC_IMANUFACT_EN + CONF_USB_MSC_IPRODUCT_EN + CONF_USB_MSC_ISERIALNUM_EN)) + (CONF_USB_MSC_ISERIALNUM_EN * (CONF_USB_MSC_IMANUFACT_EN + CONF_USB_MSC_IPRODUCT_EN + CONF_USB_MSC_ISERIALNUM_EN)) #endif // Unicode string of iSerialNum @@ -134,8 +134,8 @@ #ifndef CONF_USB_MSC_ISERIALNUM_STR_DESC #define CONF_USB_MSC_ISERIALNUM_STR_DESC \ - 32, 0x03, '1', 0x00, '2', 0x00, '3', 0x00, '4', 0x00, '5', 0x00, '6', 0x00, '7', 0x00, '8', 0x00, '9', 0x00, 'A', \ - 0x00, 'B', 0x00, 'C', 0x00, 'D', 0x00, 'E', 0x00, 'F', 0x00, + 32, 0x03, '1', 0x00, '2', 0x00, '3', 0x00, '4', 0x00, '5', 0x00, '6', 0x00, '7', 0x00, '8', 0x00, '9', 0x00, 'A', \ + 0x00, 'B', 0x00, 'C', 0x00, 'D', 0x00, 'E', 0x00, 'F', 0x00, #endif // @@ -152,8 +152,8 @@ #ifndef CONF_USB_MSC_ICONFIG #define CONF_USB_MSC_ICONFIG \ - (CONF_USB_MSC_ICONFIG_EN \ - * (CONF_USB_MSC_IMANUFACT_EN + CONF_USB_MSC_IPRODUCT_EN + CONF_USB_MSC_ISERIALNUM_EN + CONF_USB_MSC_ICONFIG_EN)) + (CONF_USB_MSC_ICONFIG_EN \ + * (CONF_USB_MSC_IMANUFACT_EN + CONF_USB_MSC_IPRODUCT_EN + CONF_USB_MSC_ISERIALNUM_EN + CONF_USB_MSC_ICONFIG_EN)) #endif // Unicode string of iConfig @@ -344,7 +344,7 @@ #ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) #endif // @@ -407,7 +407,7 @@ #ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) #endif // @@ -469,7 +469,7 @@ #ifndef CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN2_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN2_CAPACITY * 1024 / CONF_USB_MSC_LUN2_BLOCK_SIZE - 1) #endif // @@ -531,7 +531,7 @@ #ifndef CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN3_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN3_CAPACITY * 1024 / CONF_USB_MSC_LUN3_BLOCK_SIZE - 1) #endif // @@ -593,7 +593,7 @@ #ifndef CONF_USB_MSC_LUN4_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN4_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN4_CAPACITY * 1024 / CONF_USB_MSC_LUN4_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN4_CAPACITY * 1024 / CONF_USB_MSC_LUN4_BLOCK_SIZE - 1) #endif // @@ -655,7 +655,7 @@ #ifndef CONF_USB_MSC_LUN5_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN5_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN5_CAPACITY * 1024 / CONF_USB_MSC_LUN5_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN5_CAPACITY * 1024 / CONF_USB_MSC_LUN5_BLOCK_SIZE - 1) #endif // @@ -717,7 +717,7 @@ #ifndef CONF_USB_MSC_LUN6_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN6_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN6_CAPACITY * 1024 / CONF_USB_MSC_LUN6_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN6_CAPACITY * 1024 / CONF_USB_MSC_LUN6_BLOCK_SIZE - 1) #endif // @@ -779,7 +779,7 @@ #ifndef CONF_USB_MSC_LUN7_LAST_BLOCK_ADDR #define CONF_USB_MSC_LUN7_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN7_CAPACITY * 1024 / CONF_USB_MSC_LUN7_BLOCK_SIZE - 1) + ((uint32_t)CONF_USB_MSC_LUN7_CAPACITY * 1024 / CONF_USB_MSC_LUN7_BLOCK_SIZE - 1) #endif // diff --git a/ports/atmel-samd/supervisor/port.c b/ports/atmel-samd/supervisor/port.c index 7c8abf50543..3b05c84c6bf 100644 --- a/ports/atmel-samd/supervisor/port.c +++ b/ports/atmel-samd/supervisor/port.c @@ -258,8 +258,8 @@ safe_mode_t port_init(void) { #endif #if defined(SAML21) - //SystemCoreClock = CONF_CPU_FREQUENCY; - //SysTick_Config(CONF_CPU_FREQUENCY / 1000); + // SystemCoreClock = CONF_CPU_FREQUENCY; + // SysTick_Config(CONF_CPU_FREQUENCY / 1000); // Set brownout detection. // Disable while changing level. SUPC->BOD33.bit.ENABLE = 0; @@ -338,10 +338,10 @@ safe_mode_t port_init(void) { if (strcmp((char *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) { fine = ((uint16_t *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8]; } - clock_init(BOARD_HAS_CRYSTAL, fine); + clock_init(BOARD_HAS_CRYSTAL, fine); #else // Use a default fine value - clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION); + clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION); #endif rtc_init(); @@ -349,7 +349,7 @@ safe_mode_t port_init(void) { init_shared_dma(); // Reset everything into a known state before board_init. - //reset_port(); + // reset_port(); #ifdef SAMD21 if (PM->RCAUSE.bit.BOD33 == 1 || PM->RCAUSE.bit.BOD12 == 1) { diff --git a/supervisor/shared/filesystem.c b/supervisor/shared/filesystem.c index c02f42c3861..77d720ea692 100644 --- a/supervisor/shared/filesystem.c +++ b/supervisor/shared/filesystem.c @@ -97,8 +97,8 @@ void filesystem_init(bool create_allowed, bool force_create) { if ((res == FR_NO_FILESYSTEM && create_allowed) || force_create) { // No filesystem so create a fresh one, or reformat has been requested. - //uint8_t working_buf[FF_MAX_SS]; - //res = f_mkfs(&vfs_fat->fatfs, FM_FAT, 0, working_buf, sizeof(working_buf)); + // uint8_t working_buf[FF_MAX_SS]; + // res = f_mkfs(&vfs_fat->fatfs, FM_FAT, 0, working_buf, sizeof(working_buf)); // Flush the new file system to make sure it's repaired immediately. supervisor_flash_flush(); if (res != FR_OK) { From d93b73ac26a9cfb9095b8a315be241e163e55b10 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Wed, 18 Aug 2021 21:34:43 -0500 Subject: [PATCH 33/36] update tinyusb --- lib/tinyusb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/tinyusb b/lib/tinyusb index 5a4fc1151a7..3a248951e27 160000 --- a/lib/tinyusb +++ b/lib/tinyusb @@ -1 +1 @@ -Subproject commit 5a4fc1151a7e62a291a90836165942737a1a2d6f +Subproject commit 3a248951e2744ba89f5fb96eda85a971001115f0 From 9a7061c75dda58b64d9bd6fabb4edf1f2a7425a6 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Fri, 20 Aug 2021 18:01:04 -0500 Subject: [PATCH 34/36] update module peripherals --- ports/atmel-samd/peripherals | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atmel-samd/peripherals b/ports/atmel-samd/peripherals index a7e39c4d01a..df80fecd1f4 160000 --- a/ports/atmel-samd/peripherals +++ b/ports/atmel-samd/peripherals @@ -1 +1 @@ -Subproject commit a7e39c4d01aa5916015beecb021777617e77b0ad +Subproject commit df80fecd1f4360ac7dad15864b6605d42b730b6a From d455bf0b2fcfb2e3760e858111cc07cd6546d2a9 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Fri, 20 Aug 2021 18:04:20 -0500 Subject: [PATCH 35/36] Update submodule asf4 --- ports/atmel-samd/asf4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/atmel-samd/asf4 b/ports/atmel-samd/asf4 index 84f56af1329..c9c2c1b7f4b 160000 --- a/ports/atmel-samd/asf4 +++ b/ports/atmel-samd/asf4 @@ -1 +1 @@ -Subproject commit 84f56af13292d8f32c40acbd949bde698ddd4507 +Subproject commit c9c2c1b7f4b5025f553c5030c51b75506d2f0791 From 47bd598becfc5ae4ca044f22db1286353a409cfd Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Sun, 29 Aug 2021 20:12:40 -0500 Subject: [PATCH 36/36] Add AudioOut for SAML21 --- .../atmel-samd/common-hal/audioio/AudioOut.c | 92 ++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/ports/atmel-samd/common-hal/audioio/AudioOut.c b/ports/atmel-samd/common-hal/audioio/AudioOut.c index 5c1a02634b0..28d79966431 100644 --- a/ports/atmel-samd/common-hal/audioio/AudioOut.c +++ b/ports/atmel-samd/common-hal/audioio/AudioOut.c @@ -74,6 +74,29 @@ static void ramp_value(uint16_t start, uint16_t end) { } #endif +#ifdef SAML21 +static void ramp_value(uint16_t start, uint16_t end) { + int32_t diff = (int32_t)end - start; + int32_t step = 49; + int32_t steps = diff / step; + if (diff < 0) { + steps = -steps; + step = -step; + } + + for (int32_t i = 0; i < steps; i++) { + uint16_t value = start + step * i; + DAC->DATA[0].reg = value; + DAC->DATABUF[0].reg = value; + DAC->DATA[1].reg = value; + DAC->DATABUF[1].reg = value; + + common_hal_mcu_delay_us(50); + RUN_BACKGROUND_TASKS; + } +} +#endif + #ifdef SAM_D5X_E5X static void ramp_value(uint16_t start, uint16_t end) { int32_t diff = (int32_t)end - start; @@ -98,13 +121,17 @@ static void ramp_value(uint16_t start, uint16_t end) { #endif void audioout_reset(void) { - #if defined(SAMD21) && !defined(PIN_PA02) + #if (defined(SAMD21) && !defined(PIN_PA02)) || (defined(SAML21) && !defined(PIN_PA02)) return; #endif #ifdef SAMD21 while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) { } #endif + #ifdef SAML21 + while (DAC->STATUS.reg & DAC_SYNCBUSY_SWRST) { + } + #endif #ifdef SAM_D5X_E5X while (DAC->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) { } @@ -127,6 +154,9 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self, #ifdef SAMD21 bool dac_clock_enabled = PM->APBCMASK.bit.DAC_; #endif + #ifdef SAML21 + bool dac_clock_enabled = hri_mclk_get_APBCMASK_DAC_bit(MCLK); + #endif // Only support exclusive use of the DAC. if (dac_clock_enabled && DAC->CTRLA.bit.ENABLE == 1) { mp_raise_RuntimeError(translate("DAC already in use")); @@ -140,6 +170,15 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self, } claim_pin(left_channel); #endif + #ifdef SAML21 + if (right_channel != NULL) { + mp_raise_ValueError(translate("Right channel unsupported")); + } + if (left_channel != &pin_PA02) { + mp_raise_ValueError(translate("Invalid pin")); + } + claim_pin(left_channel); + #endif #ifdef SAM_D5X_E5X self->right_channel = NULL; if (left_channel != &pin_PA02 && left_channel != &pin_PA05) { @@ -169,6 +208,10 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self, _pm_enable_bus_clock(PM_BUS_APBC, DAC); #endif + #ifdef SAML21 + hri_mclk_set_APBCMASK_DAC_bit(MCLK); + #endif + // SAMD51: This clock should be <= 12 MHz, per datasheet section 47.6.3. // SAMD21: This clock is 48mhz despite the datasheet saying it must only be <= 350kHz, per // datasheet table 37-6. It's incorrect because the max output rate is 350ksps and is only @@ -198,6 +241,13 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self, DAC_CTRLB_EOEN | DAC_CTRLB_VPD; #endif + #ifdef SAML21 + DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; + DAC->DACCTRL[0].reg = DAC_DACCTRL_CCTRL_CC12M | + DAC_DACCTRL_ENABLE | + DAC_DACCTRL_LEFTADJ; + DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU; + #endif #ifdef SAM_D5X_E5X DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; DAC->DACCTRL[0].reg = DAC_DACCTRL_CCTRL_CC12M | @@ -222,6 +272,10 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self, while (DAC->STATUS.bit.SYNCBUSY == 1) { } #endif + #ifdef SAML21 + while (DAC->SYNCBUSY.bit.ENABLE == 1) { + } + #endif #ifdef SAM_D5X_E5X while (DAC->SYNCBUSY.bit.ENABLE == 1) { } @@ -266,6 +320,9 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self, #ifdef SAMD21 t->COUNT16.CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_MFRQ_Val; #endif + #ifdef SAML21 + t->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MFRQ; + #endif t->COUNT16.EVCTRL.reg = TC_EVCTRL_OVFEO; tc_set_enable(t, true); t->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_STOP; @@ -275,6 +332,9 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self, #ifdef SAMD21 #define FIRST_TC_GEN_ID EVSYS_ID_GEN_TC3_OVF #endif + #ifdef SAML21 + #define FIRST_TC_GEN_ID EVSYS_ID_GEN_TC3_OVF + #endif #ifdef SAM_D5X_E5X #define FIRST_TC_GEN_ID EVSYS_ID_GEN_TC0_OVF #endif @@ -296,6 +356,13 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self, } #define EVSYS_ID_USER_DAC_START EVSYS_ID_USER_DAC_START_0 #endif + #ifdef SAML21 + connect_event_user_to_channel(EVSYS_ID_USER_DAC_START_1, channel); + if (right_channel != NULL) { + gpio_set_pin_function(self->left_channel->number, GPIO_PIN_FUNCTION_B); + } + #define EVSYS_ID_USER_DAC_START EVSYS_ID_USER_DAC_START_0 + #endif connect_event_user_to_channel(EVSYS_ID_USER_DAC_START, channel); gpio_set_pin_function(self->left_channel->number, GPIO_PIN_FUNCTION_B); init_async_event_channel(channel, tc_gen_id); @@ -330,6 +397,10 @@ void common_hal_audioio_audioout_deinit(audioio_audioout_obj_t *self) { while (DAC->STATUS.bit.SYNCBUSY == 1) { } #endif + #ifdef SAML21 + while (DAC->SYNCBUSY.bit.ENABLE == 1) { + } + #endif #ifdef SAM_D5X_E5X while (DAC->SYNCBUSY.bit.ENABLE == 1) { } @@ -378,6 +449,9 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t *self, #ifdef SAMD21 uint32_t max_sample_rate = 350000; #endif + #ifdef SAML21 + uint32_t max_sample_rate = 350000; + #endif #ifdef SAM_D5X_E5X uint32_t max_sample_rate = 1000000; #endif @@ -391,6 +465,19 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t *self, DAC_DMAC_ID_EMPTY); #endif + #ifdef SAML21 + uint32_t left_channel_reg = (uint32_t)&DAC->DATABUF[0].reg; + uint8_t tc_trig_id = TC0_DMAC_ID_OVF + 3 * self->tc_index; + uint8_t left_channel_trigger = tc_trig_id; + if (self->left_channel == &pin_PA02) { + left_channel_reg = (uint32_t)&DAC->DATABUF[0].reg; + } + result = audio_dma_setup_playback(&self->left_dma, sample, loop, true, 0, + false /* output unsigned */, + left_channel_reg, + left_channel_trigger); + #endif + #ifdef SAM_D5X_E5X uint32_t left_channel_reg = (uint32_t)&DAC->DATABUF[0].reg; uint8_t tc_trig_id = TC0_DMAC_ID_OVF + 3 * self->tc_index; @@ -454,6 +541,9 @@ void common_hal_audioio_audioout_resume(audioio_audioout_obj_t *self) { #ifdef SAMD21 DAC->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; #endif + #ifdef SAML21 + DAC->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; + #endif #ifdef SAM_D5X_E5X DAC->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_UNDERRUN1; #endif