diff --git a/.gitignore b/.gitignore old mode 100644 new mode 100755 index 57af07cf7..4b8b578bb --- a/.gitignore +++ b/.gitignore @@ -42,8 +42,8 @@ modules.builtin /vmlinux /vmlinuz /System.map -/Module.markers -/Module.symvers +Module.markers +Module.symvers # # Debian directory (make deb-pkg) @@ -56,6 +56,9 @@ modules.builtin !.gitignore !.mailmap +#ignore CVS control file +CVS + # # Generated include files # @@ -82,5 +85,6 @@ GSYMS GTAGS *.orig +*.rej *~ \#*# diff --git a/Documentation/ABI/testing/debugfs-aufs b/Documentation/ABI/testing/debugfs-aufs new file mode 100755 index 000000000..4110b94c1 --- /dev/null +++ b/Documentation/ABI/testing/debugfs-aufs @@ -0,0 +1,40 @@ +What: /debug/aufs/si_/ +Date: March 2009 +Contact: J. R. Okajima +Description: + Under /debug/aufs, a directory named si_ is created + per aufs mount, where is a unique id generated + internally. + +What: /debug/aufs/si_/xib +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the consumed blocks by xib (External Inode Number + Bitmap), its block size and file size. + When the aufs mount option 'noxino' is specified, it + will be empty. About XINO files, see + Documentation/filesystems/aufs/aufs.5 in detail. + +What: /debug/aufs/si_/xino0, xino1 ... xinoN +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the consumed blocks by xino (External Inode Number + Translation Table), its link count, block size and file + size. + When the aufs mount option 'noxino' is specified, it + will be empty. About XINO files, see + Documentation/filesystems/aufs/aufs.5 in detail. + +What: /debug/aufs/si_/xigen +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the consumed blocks by xigen (External Inode + Generation Table), its block size and file size. + If CONFIG_AUFS_EXPORT is disabled, this entry will not + be created. + When the aufs mount option 'noxino' is specified, it + will be empty. About XINO files, see + Documentation/filesystems/aufs/aufs.5 in detail. diff --git a/Documentation/ABI/testing/sysfs-aufs b/Documentation/ABI/testing/sysfs-aufs new file mode 100755 index 000000000..ca493306e --- /dev/null +++ b/Documentation/ABI/testing/sysfs-aufs @@ -0,0 +1,25 @@ +What: /sys/fs/aufs/si_/ +Date: March 2009 +Contact: J. R. Okajima +Description: + Under /sys/fs/aufs, a directory named si_ is created + per aufs mount, where is a unique id generated + internally. + +What: /sys/fs/aufs/si_/br0, br1 ... brN +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the abolute path of a member directory (which + is called branch) in aufs, and its permission. + +What: /sys/fs/aufs/si_/xi_path +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the abolute path of XINO (External Inode Number + Bitmap, Translation Table and Generation Table) file + even if it is the default path. + When the aufs mount option 'noxino' is specified, it + will be empty. About XINO files, see + Documentation/filesystems/aufs/aufs.5 in detail. diff --git a/Documentation/arm/kernel_mode_neon.txt b/Documentation/arm/kernel_mode_neon.txt new file mode 100755 index 000000000..525452726 --- /dev/null +++ b/Documentation/arm/kernel_mode_neon.txt @@ -0,0 +1,121 @@ +Kernel mode NEON +================ + +TL;DR summary +------------- +* Use only NEON instructions, or VFP instructions that don't rely on support + code +* Isolate your NEON code in a separate compilation unit, and compile it with + '-mfpu=neon -mfloat-abi=softfp' +* Put kernel_neon_begin() and kernel_neon_end() calls around the calls into your + NEON code +* Don't sleep in your NEON code, and be aware that it will be executed with + preemption disabled + + +Introduction +------------ +It is possible to use NEON instructions (and in some cases, VFP instructions) in +code that runs in kernel mode. However, for performance reasons, the NEON/VFP +register file is not preserved and restored at every context switch or taken +exception like the normal register file is, so some manual intervention is +required. Furthermore, special care is required for code that may sleep [i.e., +may call schedule()], as NEON or VFP instructions will be executed in a +non-preemptible section for reasons outlined below. + + +Lazy preserve and restore +------------------------- +The NEON/VFP register file is managed using lazy preserve (on UP systems) and +lazy restore (on both SMP and UP systems). This means that the register file is +kept 'live', and is only preserved and restored when multiple tasks are +contending for the NEON/VFP unit (or, in the SMP case, when a task migrates to +another core). Lazy restore is implemented by disabling the NEON/VFP unit after +every context switch, resulting in a trap when subsequently a NEON/VFP +instruction is issued, allowing the kernel to step in and perform the restore if +necessary. + +Any use of the NEON/VFP unit in kernel mode should not interfere with this, so +it is required to do an 'eager' preserve of the NEON/VFP register file, and +enable the NEON/VFP unit explicitly so no exceptions are generated on first +subsequent use. This is handled by the function kernel_neon_begin(), which +should be called before any kernel mode NEON or VFP instructions are issued. +Likewise, the NEON/VFP unit should be disabled again after use to make sure user +mode will hit the lazy restore trap upon next use. This is handled by the +function kernel_neon_end(). + + +Interruptions in kernel mode +---------------------------- +For reasons of performance and simplicity, it was decided that there shall be no +preserve/restore mechanism for the kernel mode NEON/VFP register contents. This +implies that interruptions of a kernel mode NEON section can only be allowed if +they are guaranteed not to touch the NEON/VFP registers. For this reason, the +following rules and restrictions apply in the kernel: +* NEON/VFP code is not allowed in interrupt context; +* NEON/VFP code is not allowed to sleep; +* NEON/VFP code is executed with preemption disabled. + +If latency is a concern, it is possible to put back to back calls to +kernel_neon_end() and kernel_neon_begin() in places in your code where none of +the NEON registers are live. (Additional calls to kernel_neon_begin() should be +reasonably cheap if no context switch occurred in the meantime) + + +VFP and support code +-------------------- +Earlier versions of VFP (prior to version 3) rely on software support for things +like IEEE-754 compliant underflow handling etc. When the VFP unit needs such +software assistance, it signals the kernel by raising an undefined instruction +exception. The kernel responds by inspecting the VFP control registers and the +current instruction and arguments, and emulates the instruction in software. + +Such software assistance is currently not implemented for VFP instructions +executed in kernel mode. If such a condition is encountered, the kernel will +fail and generate an OOPS. + + +Separating NEON code from ordinary code +--------------------------------------- +The compiler is not aware of the special significance of kernel_neon_begin() and +kernel_neon_end(), i.e., that it is only allowed to issue NEON/VFP instructions +between calls to these respective functions. Furthermore, GCC may generate NEON +instructions of its own at -O3 level if -mfpu=neon is selected, and even if the +kernel is currently compiled at -O2, future changes may result in NEON/VFP +instructions appearing in unexpected places if no special care is taken. + +Therefore, the recommended and only supported way of using NEON/VFP in the +kernel is by adhering to the following rules: +* isolate the NEON code in a separate compilation unit and compile it with + '-mfpu=neon -mfloat-abi=softfp'; +* issue the calls to kernel_neon_begin(), kernel_neon_end() as well as the calls + into the unit containing the NEON code from a compilation unit which is *not* + built with the GCC flag '-mfpu=neon' set. + +As the kernel is compiled with '-msoft-float', the above will guarantee that +both NEON and VFP instructions will only ever appear in designated compilation +units at any optimization level. + + +NEON assembler +-------------- +NEON assembler is supported with no additional caveats as long as the rules +above are followed. + + +NEON code generated by GCC +-------------------------- +The GCC option -ftree-vectorize (implied by -O3) tries to exploit implicit +parallelism, and generates NEON code from ordinary C source code. This is fully +supported as long as the rules above are followed. + + +NEON intrinsics +--------------- +NEON intrinsics are also supported. However, as code using NEON intrinsics +relies on the GCC header , (which #includes ), you should +observe the following in addition to the rules above: +* Compile the unit containing the NEON intrinsics with '-ffreestanding' so GCC + uses its builtin version of (this is a C99 header which the kernel + does not supply); +* Include last, or at least after diff --git a/Documentation/blackfin/bfin-gpio-notes.txt b/Documentation/blackfin/bfin-gpio-notes.txt old mode 100644 new mode 100755 index d36b01f77..f7715559e --- a/Documentation/blackfin/bfin-gpio-notes.txt +++ b/Documentation/blackfin/bfin-gpio-notes.txt @@ -3,7 +3,7 @@ * Based on: * Author: * - * Created: $Id: bfin-gpio-note.txt 2008-11-24 16:42 grafyang $ + * Created: $Id: bfin-gpio-notes.txt,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ * Description: This file contains the notes in developing/using bfin-gpio. * * diff --git a/Documentation/cdrom/cdrom-standard.tex b/Documentation/cdrom/cdrom-standard.tex old mode 100644 new mode 100755 index c06233fe5..59c42f55f --- a/Documentation/cdrom/cdrom-standard.tex +++ b/Documentation/cdrom/cdrom-standard.tex @@ -1,5 +1,5 @@ \documentclass{article} -\def\version{$Id: cdrom-standard.tex,v 1.9 1997/12/28 15:42:49 david Exp $} +\def\version{$Id: cdrom-standard.tex,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $} \newcommand{\newsection}[1]{\newpage\section{#1}} \evensidemargin=0pt diff --git a/Documentation/cris/README b/Documentation/cris/README old mode 100644 new mode 100755 index d9b086869..65c548f92 --- a/Documentation/cris/README +++ b/Documentation/cris/README @@ -1,6 +1,6 @@ Linux 2.4 on the CRIS architecture ================================== -$Id: README,v 1.7 2001/04/19 12:38:32 bjornw Exp $ +$Id: README,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ This is a port of Linux 2.4 to Axis Communications ETRAX 100LX embedded network CPU. For more information about CRIS and ETRAX please see further @@ -103,7 +103,7 @@ block: queued sectors max/low 9109kB/3036kB, 64 slots per queue ETRAX 100LX 10/100MBit ethernet v2.0 (c) 2000 Axis Communications AB eth0 initialized eth0: changed MAC to 00:40:8C:CD:00:00 -ETRAX 100LX serial-driver $Revision: 1.7 $, (c) 2000 Axis Communications AB +ETRAX 100LX serial-driver $Revision: 1.1.1.1 $, (c) 2000 Axis Communications AB ttyS0 at 0xb0000060 is a builtin UART with DMA ttyS1 at 0xb0000068 is a builtin UART with DMA ttyS2 at 0xb0000070 is a builtin UART with DMA @@ -133,7 +133,7 @@ Default gateway is 10.13.9.1 Hostname is bbox1 Telnetd starting, using port 23. using /bin/sash as shell. -sftpd[15]: sftpd $Revision: 1.7 $ starting up +sftpd[15]: sftpd $Revision: 1.1.1.1 $ starting up diff --git a/Documentation/crypto/descore-readme.txt b/Documentation/crypto/descore-readme.txt old mode 100644 new mode 100755 index 16e9e6350..30307ab95 --- a/Documentation/crypto/descore-readme.txt +++ b/Documentation/crypto/descore-readme.txt @@ -20,7 +20,7 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. Author's address: how@isl.stanford.edu -$Id: README,v 1.15 1992/05/20 00:25:32 how E $ +$Id: descore-readme.txt,v 1.1.1.1 2010/04/15 12:28:21 khchen Exp $ ==>> To compile after untarring/unsharring, just `make' <<== diff --git a/Documentation/devices.txt b/Documentation/devices.txt old mode 100644 new mode 100755 index eccffe715..39b2fa5fb --- a/Documentation/devices.txt +++ b/Documentation/devices.txt @@ -447,6 +447,9 @@ Your cooperation is appreciated. 234 = /dev/btrfs-control Btrfs control device 235 = /dev/autofs Autofs control device 236 = /dev/mapper/control Device-Mapper control device + 237 = /dev/loop-control Loopback control device + 238 = /dev/vhost-net Host kernel accelerator for virtio net + 240-254 Reserved for local use 255 Reserved for MISC_DYNAMIC_MINOR diff --git a/Documentation/fb/pvr2fb.txt b/Documentation/fb/pvr2fb.txt old mode 100644 new mode 100755 index 36bdeff58..b8aa0490e --- a/Documentation/fb/pvr2fb.txt +++ b/Documentation/fb/pvr2fb.txt @@ -1,4 +1,4 @@ -$Id: pvr2fb.txt,v 1.1 2001/05/24 05:09:16 mrbrown Exp $ +$Id: pvr2fb.txt,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ What is pvr2fb? =============== diff --git a/Documentation/fb/sstfb.txt b/Documentation/fb/sstfb.txt old mode 100644 new mode 100755 index 550ca775a..7e93e852b --- a/Documentation/fb/sstfb.txt +++ b/Documentation/fb/sstfb.txt @@ -170,5 +170,5 @@ ghoz. Ghozlane Toumi -$Date: 2002/05/09 20:11:45 $ +$Date: 2010/04/15 12:28:20 $ http://sstfb.sourceforge.net/README diff --git a/Documentation/fb/tgafb.txt b/Documentation/fb/tgafb.txt old mode 100644 new mode 100755 index 250083ada..e2fadfa61 --- a/Documentation/fb/tgafb.txt +++ b/Documentation/fb/tgafb.txt @@ -1,4 +1,4 @@ -$Id: tgafb.txt,v 1.1.2.2 2000/04/04 06:50:18 mato Exp $ +$Id: tgafb.txt,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ What is tgafb? =============== diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt old mode 100644 new mode 100755 index 47c4ec2fc..b66ca8a01 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -410,7 +410,7 @@ Who: FUJITA Tomonori What: iwlwifi disable_hw_scan module parameters When: 3.0 -Why: Hareware scan is the prefer method for iwlwifi devices for +Why: Hardware scan is the prefer method for iwlwifi devices for scanning operation. Remove software scan support for all the iwlwifi devices. diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking old mode 100644 new mode 100755 index d819ba16a..7ff055690 --- a/Documentation/filesystems/Locking +++ b/Documentation/filesystems/Locking @@ -37,15 +37,15 @@ d_manage: no no yes (ref-walk) maybe --------------------------- inode_operations --------------------------- prototypes: - int (*create) (struct inode *,struct dentry *,int, struct nameidata *); + int (*create) (struct inode *,struct dentry *,umode_t, struct nameidata *); struct dentry * (*lookup) (struct inode *,struct dentry *, struct nameid ata *); int (*link) (struct dentry *,struct inode *,struct dentry *); int (*unlink) (struct inode *,struct dentry *); int (*symlink) (struct inode *,struct dentry *,const char *); - int (*mkdir) (struct inode *,struct dentry *,int); + int (*mkdir) (struct inode *,struct dentry *,umode_t); int (*rmdir) (struct inode *,struct dentry *); - int (*mknod) (struct inode *,struct dentry *,int,dev_t); + int (*mknod) (struct inode *,struct dentry *,umode_t,dev_t); int (*rename) (struct inode *, struct dentry *, struct inode *, struct dentry *); int (*readlink) (struct dentry *, char __user *,int); @@ -62,6 +62,7 @@ ata *); int (*removexattr) (struct dentry *, const char *); void (*truncate_range)(struct inode *, loff_t, loff_t); int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 start, u64 len); + void (*update_time)(struct inode *, struct timespec *, int); locking rules: all may block @@ -89,6 +90,8 @@ listxattr: no removexattr: yes truncate_range: yes fiemap: no +update_time: no + Additionally, ->rmdir(), ->unlink() and ->rename() have ->i_mutex on victim. cross-directory ->rename() has (per-superblock) ->s_vfs_rename_sem. diff --git a/Documentation/filesystems/ext3.txt b/Documentation/filesystems/ext3.txt old mode 100644 new mode 100755 index b100adc38..22f3a0eda --- a/Documentation/filesystems/ext3.txt +++ b/Documentation/filesystems/ext3.txt @@ -73,6 +73,14 @@ nobarrier (*) This also requires an IO stack which can support also be used to enable or disable barriers, for consistency with other ext3 mount options. +orlov (*) This enables the new Orlov block allocator. It is + enabled by default. + +oldalloc This disables the Orlov block allocator and enables + the old block allocator. Orlov should have better + performance - we'd like to get some feedback if it's + the contrary for you. + user_xattr Enables Extended User Attributes. Additionally, you need to have extended attribute support enabled in the kernel configuration (CONFIG_EXT3_FS_XATTR). See the diff --git a/Documentation/filesystems/ext4.txt b/Documentation/filesystems/ext4.txt old mode 100644 new mode 100755 index 4917cf24a..7e8e78b9e --- a/Documentation/filesystems/ext4.txt +++ b/Documentation/filesystems/ext4.txt @@ -203,6 +203,14 @@ inode_readahead_blks=n This tuning parameter controls the maximum table readahead algorithm will pre-read into the buffer cache. The default value is 32 blocks. +orlov (*) This enables the new Orlov block allocator. It is + enabled by default. + +oldalloc This disables the Orlov block allocator and enables + the old block allocator. Orlov should have better + performance - we'd like to get some feedback if it's + the contrary for you. + nouser_xattr Disables Extended User Attributes. If you have extended attribute support enabled in the kernel configuration (CONFIG_EXT4_FS_XATTR), extended attribute support @@ -581,6 +589,13 @@ Table of Ext4 specific ioctls behaviour may change in the future as it is not necessary and has been done this way only for sake of simplicity. + + EXT4_IOC_RESIZE_FS Resize the filesystem to a new size. The number + of blocks of resized filesystem is passed in via + 64 bit integer argument. The kernel allocates + bitmaps and inode table, the userspace tool thus + just passes the new number of blocks. + .............................................................................. References diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt old mode 100644 new mode 100755 index 43cbd0821..9b2869d1b --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -341,14 +341,14 @@ This describes how the VFS can manipulate an inode in your filesystem. As of kernel 2.6.22, the following members are defined: struct inode_operations { - int (*create) (struct inode *,struct dentry *,int, struct nameidata *); + int (*create) (struct inode *,struct dentry *, umode_t, struct nameidata *); struct dentry * (*lookup) (struct inode *,struct dentry *, struct nameidata *); int (*link) (struct dentry *,struct inode *,struct dentry *); int (*unlink) (struct inode *,struct dentry *); int (*symlink) (struct inode *,struct dentry *,const char *); - int (*mkdir) (struct inode *,struct dentry *,int); + int (*mkdir) (struct inode *,struct dentry *,umode_t); int (*rmdir) (struct inode *,struct dentry *); - int (*mknod) (struct inode *,struct dentry *,int,dev_t); + int (*mknod) (struct inode *,struct dentry *,umode_t,dev_t); int (*rename) (struct inode *, struct dentry *, struct inode *, struct dentry *); int (*readlink) (struct dentry *, char __user *,int); @@ -364,6 +364,7 @@ struct inode_operations { ssize_t (*listxattr) (struct dentry *, char *, size_t); int (*removexattr) (struct dentry *, const char *); void (*truncate_range)(struct inode *, loff_t, loff_t); + void (*update_time)(struct inode *, struct timespec *, int); }; Again, all methods are called without any locks being held, unless @@ -475,6 +476,9 @@ otherwise noted. truncate_range: a method provided by the underlying filesystem to truncate a range of blocks , i.e. punch a hole somewhere in a file. + update_time: called by the VFS to update a specific time or the i_version of + an inode. If this is not defined the VFS will update the inode itself + and call mark_inode_dirty_sync. The Address Space Object ======================== diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801 old mode 100644 new mode 100755 index 99d4e442b..8bb57d7c1 --- a/Documentation/i2c/busses/i2c-i801 +++ b/Documentation/i2c/busses/i2c-i801 @@ -22,6 +22,7 @@ Supported adapters: * Intel Panther Point (PCH) * Intel Lynx Point (PCH) * Intel Lynx Point-LP (PCH) + * Intel Avoton (SOC) Datasheets: Publicly available at the Intel website On Intel Patsburg and later chipsets, both the normal host SMBus controller diff --git a/Documentation/isdn/INTERFACE b/Documentation/isdn/INTERFACE old mode 100644 new mode 100755 index 5df17e5b2..3c3e6324e --- a/Documentation/isdn/INTERFACE +++ b/Documentation/isdn/INTERFACE @@ -1,4 +1,4 @@ -$Id: INTERFACE,v 1.15.8.2 2001/03/13 16:17:07 kai Exp $ +$Id: INTERFACE,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ Description of the Interface between Linklevel and Hardwarelevel of isdn4linux: diff --git a/Documentation/isdn/INTERFACE.fax b/Documentation/isdn/INTERFACE.fax old mode 100644 new mode 100755 index 9c8c6d914..fc4ac2a7f --- a/Documentation/isdn/INTERFACE.fax +++ b/Documentation/isdn/INTERFACE.fax @@ -1,4 +1,4 @@ -$Id: INTERFACE.fax,v 1.2 2000/08/06 09:22:50 armin Exp $ +$Id: INTERFACE.fax,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ Description of the fax-subinterface between linklevel and hardwarelevel of diff --git a/Documentation/isdn/README.act2000 b/Documentation/isdn/README.act2000 old mode 100644 new mode 100755 index ce7115e7f..24d81f97d --- a/Documentation/isdn/README.act2000 +++ b/Documentation/isdn/README.act2000 @@ -1,4 +1,4 @@ -$Id: README.act2000,v 1.3 2000/08/06 09:22:51 armin Exp $ +$Id: README.act2000,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ This document describes the ACT2000 driver for the IBM Active 2000 ISDN card. diff --git a/Documentation/isdn/README.audio b/Documentation/isdn/README.audio old mode 100644 new mode 100755 index 8ebca1929..14bfe5389 --- a/Documentation/isdn/README.audio +++ b/Documentation/isdn/README.audio @@ -1,4 +1,4 @@ -$Id: README.audio,v 1.8 1999/07/11 17:17:29 armin Exp $ +$Id: README.audio,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ ISDN subsystem for Linux. Description of audio mode. diff --git a/Documentation/isdn/README.hysdn b/Documentation/isdn/README.hysdn old mode 100644 new mode 100755 index eeca11f00..9824f098b --- a/Documentation/isdn/README.hysdn +++ b/Documentation/isdn/README.hysdn @@ -1,4 +1,4 @@ -$Id: README.hysdn,v 1.3.6.1 2001/02/10 14:41:19 kai Exp $ +$Id: README.hysdn,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ The hysdn driver has been written by Werner Cornelius (werner@isdn4linux.de or werner@titro.de) for Hypercope GmbH Aachen Germany. Hypercope agreed to publish this driver diff --git a/Documentation/isdn/README.icn b/Documentation/isdn/README.icn old mode 100644 new mode 100755 index 13f833d4e..e6850d5ab --- a/Documentation/isdn/README.icn +++ b/Documentation/isdn/README.icn @@ -1,4 +1,4 @@ -$Id: README.icn,v 1.7 2000/08/06 09:22:51 armin Exp $ +$Id: README.icn,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ You can get the ICN-ISDN-card from: diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt old mode 100644 new mode 100755 index ddbf18eaa..65f39c796 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -110,6 +110,7 @@ parameter is applicable: USB USB support is enabled. USBHID USB Human Interface Device support is enabled. V4L Video For Linux support is enabled. + VMMIO Driver for memory mapped virtio devices is enabled. VGA The VGA console has been enabled. VT Virtual terminal support is enabled. WDT Watchdog support is enabled. @@ -2725,6 +2726,22 @@ bytes respectively. Such letter suffixes can also be entirely omitted. video= [FB] Frame buffer configuration See Documentation/fb/modedb.txt. + virtio_mmio.device= + [VMMIO] Memory mapped virtio (platform) device. + + @:[:] + where: + := size (can use standard suffixes + like K, M and G) + := physical base address + := interrupt number (as passed to + request_irq()) + := (optional) platform device id + example: + virtio_mmio.device=1K@0x100b0000:48:7 + + Can be used multiple times for multiple devices. + vga= [BOOT,X86-32] Select a particular video mode See Documentation/x86/boot.txt and Documentation/svga.txt. diff --git a/Documentation/power/freezing-of-tasks.txt b/Documentation/power/freezing-of-tasks.txt old mode 100644 new mode 100755 index 316c2ba18..697afafe8 --- a/Documentation/power/freezing-of-tasks.txt +++ b/Documentation/power/freezing-of-tasks.txt @@ -21,7 +21,7 @@ freeze_processes() (defined in kernel/power/process.c) is called. It executes try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and either wakes them up, if they are kernel threads, or sends fake signals to them, if they are user space processes. A task that has TIF_FREEZE set, should react -to it by calling the function called refrigerator() (defined in +to it by calling the function called __refrigerator() (defined in kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it. Then, we say that the task is 'frozen' and therefore the set of functions @@ -29,10 +29,10 @@ handling this mechanism is referred to as 'the freezer' (these functions are defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h). User space processes are generally frozen before kernel threads. -It is not recommended to call refrigerator() directly. Instead, it is -recommended to use the try_to_freeze() function (defined in -include/linux/freezer.h), that checks the task's TIF_FREEZE flag and makes the -task enter refrigerator() if the flag is set. +__refrigerator() must not be called directly. Instead, use the +try_to_freeze() function (defined in include/linux/freezer.h), that checks +the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the +flag is set. For user space processes try_to_freeze() is called automatically from the signal-handling code, but the freezable kernel threads need to call it @@ -61,7 +61,7 @@ wait_event_freezable() and wait_event_freezable_timeout() macros. After the system memory state has been restored from a hibernation image and devices have been reinitialized, the function thaw_processes() is called in order to clear the PF_FROZEN flag for each frozen task. Then, the tasks that -have been frozen leave refrigerator() and continue running. +have been frozen leave __refrigerator() and continue running. III. Which kernel threads are freezable? diff --git a/Documentation/scsi/aha152x.txt b/Documentation/scsi/aha152x.txt old mode 100644 new mode 100755 index 94848734a..09381e4eb --- a/Documentation/scsi/aha152x.txt +++ b/Documentation/scsi/aha152x.txt @@ -1,4 +1,4 @@ -$Id: README.aha152x,v 1.2 1999/12/25 15:32:30 fischer Exp fischer $ +$Id: aha152x.txt,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x) Copyright 1993-1999 Jürgen Fischer diff --git a/Documentation/scsi/aic7xxx_old.txt b/Documentation/scsi/aic7xxx_old.txt old mode 100644 new mode 100755 index ecfc474f3..8fe53a72c --- a/Documentation/scsi/aic7xxx_old.txt +++ b/Documentation/scsi/aic7xxx_old.txt @@ -505,7 +505,7 @@ linux-1.1.x and fairly stable since linux-1.2.x, and are also in FreeBSD Dean W. Gehnert deang@teleport.com -$Revision: 3.0 $ +$Revision: 1.1.1.1 $ Modified by Doug Ledford 1998-2000 diff --git a/Documentation/scsi/osst.txt b/Documentation/scsi/osst.txt old mode 100644 new mode 100755 index ad86c6d1e..0d27ecbd2 --- a/Documentation/scsi/osst.txt +++ b/Documentation/scsi/osst.txt @@ -188,7 +188,7 @@ Makedevs.sh #!/bin/sh # Script to create OnStream SC-x0 device nodes (major 206) # Usage: Makedevs.sh [nos [path to dev]] -# $Id: README.osst.kernel,v 1.4 2000/12/20 14:13:15 garloff Exp $ +# $Id: osst.txt,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ major=206 nrs=4 dir=/dev diff --git a/Documentation/scsi/tmscsim.txt b/Documentation/scsi/tmscsim.txt old mode 100644 new mode 100755 index 61c0531e0..7d7f93f3a --- a/Documentation/scsi/tmscsim.txt +++ b/Documentation/scsi/tmscsim.txt @@ -446,4 +446,4 @@ development and maintenance. Special thanks! ------------------------------------------------------------------------- Written by Kurt Garloff 1998/06/11 Last updated 2000/11/28, driver revision 2.0e7 -$Id: README.tmscsim,v 2.25.2.7 2000/12/20 01:07:12 garloff Exp $ +$Id: tmscsim.txt,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ diff --git a/Documentation/video4linux/README.cpia2 b/Documentation/video4linux/README.cpia2 old mode 100644 new mode 100755 index ce8213d28..64beadd8e --- a/Documentation/video4linux/README.cpia2 +++ b/Documentation/video4linux/README.cpia2 @@ -1,4 +1,4 @@ -$Id: README,v 1.7 2005/08/29 23:39:57 sbertin Exp $ +$Id: README.cpia2,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ 1. Introduction diff --git a/Documentation/video4linux/README.pvrusb2 b/Documentation/video4linux/README.pvrusb2 old mode 100644 new mode 100755 index 2137b5892..70b892bca --- a/Documentation/video4linux/README.pvrusb2 +++ b/Documentation/video4linux/README.pvrusb2 @@ -1,5 +1,5 @@ -$Id$ +$Id: README.pvrusb2,v 1.1.1.1 2010/04/15 12:28:20 khchen Exp $ Mike Isely pvrusb2 driver diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt old mode 100644 new mode 100755 index e2a4b5287..f80ed63de --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -1466,6 +1466,167 @@ is supported; 2 if the processor requires all virtual machines to have an RMA, or 1 if the processor can use an RMA but doesn't require it, because it supports the Virtual RMA (VRMA) facility. +4.64 KVM_NMI + +Capability: KVM_CAP_USER_NMI +Architectures: x86 +Type: vcpu ioctl +Parameters: none +Returns: 0 on success, -1 on error + +Queues an NMI on the thread's vcpu. Note this is well defined only +when KVM_CREATE_IRQCHIP has not been called, since this is an interface +between the virtual cpu core and virtual local APIC. After KVM_CREATE_IRQCHIP +has been called, this interface is completely emulated within the kernel. + +To use this to emulate the LINT1 input with KVM_CREATE_IRQCHIP, use the +following algorithm: + + - pause the vpcu + - read the local APIC's state (KVM_GET_LAPIC) + - check whether changing LINT1 will queue an NMI (see the LVT entry for LINT1) + - if so, issue KVM_NMI + - resume the vcpu + +Some guests configure the LINT1 NMI input to cause a panic, aiding in +debugging. + +4.65 KVM_S390_UCAS_MAP + +Capability: KVM_CAP_S390_UCONTROL +Architectures: s390 +Type: vcpu ioctl +Parameters: struct kvm_s390_ucas_mapping (in) +Returns: 0 in case of success + +The parameter is defined like this: + struct kvm_s390_ucas_mapping { + __u64 user_addr; + __u64 vcpu_addr; + __u64 length; + }; + +This ioctl maps the memory at "user_addr" with the length "length" to +the vcpu's address space starting at "vcpu_addr". All parameters need to +be alligned by 1 megabyte. + +4.66 KVM_S390_UCAS_UNMAP + +Capability: KVM_CAP_S390_UCONTROL +Architectures: s390 +Type: vcpu ioctl +Parameters: struct kvm_s390_ucas_mapping (in) +Returns: 0 in case of success + +The parameter is defined like this: + struct kvm_s390_ucas_mapping { + __u64 user_addr; + __u64 vcpu_addr; + __u64 length; + }; + +This ioctl unmaps the memory in the vcpu's address space starting at +"vcpu_addr" with the length "length". The field "user_addr" is ignored. +All parameters need to be alligned by 1 megabyte. + +4.67 KVM_S390_VCPU_FAULT + +Capability: KVM_CAP_S390_UCONTROL +Architectures: s390 +Type: vcpu ioctl +Parameters: vcpu absolute address (in) +Returns: 0 in case of success + +This call creates a page table entry on the virtual cpu's address space +(for user controlled virtual machines) or the virtual machine's address +space (for regular virtual machines). This only works for minor faults, +thus it's recommended to access subject memory page via the user page +table upfront. This is useful to handle validity intercepts for user +controlled virtual machines to fault in the virtual cpu's lowcore pages +prior to calling the KVM_RUN ioctl. + +4.68 KVM_SET_ONE_REG + +Capability: KVM_CAP_ONE_REG +Architectures: all +Type: vcpu ioctl +Parameters: struct kvm_one_reg (in) +Returns: 0 on success, negative value on failure + +struct kvm_one_reg { + __u64 id; + __u64 addr; +}; + +Using this ioctl, a single vcpu register can be set to a specific value +defined by user space with the passed in struct kvm_one_reg, where id +refers to the register identifier as described below and addr is a pointer +to a variable with the respective size. There can be architecture agnostic +and architecture specific registers. Each have their own range of operation +and their own constants and width. To keep track of the implemented +registers, find a list below: + + Arch | Register | Width (bits) + | | + PPC | KVM_REG_PPC_HIOR | 64 + +4.69 KVM_GET_ONE_REG + +Capability: KVM_CAP_ONE_REG +Architectures: all +Type: vcpu ioctl +Parameters: struct kvm_one_reg (in and out) +Returns: 0 on success, negative value on failure + +This ioctl allows to receive the value of a single register implemented +in a vcpu. The register to read is indicated by the "id" field of the +kvm_one_reg struct passed in. On success, the register value can be found +at the memory location pointed to by "addr". + +The list of registers accessible using this interface is identical to the +list in 4.64. + +4.70 KVM_KVMCLOCK_CTRL + +Capability: KVM_CAP_KVMCLOCK_CTRL +Architectures: Any that implement pvclocks (currently x86 only) +Type: vcpu ioctl +Parameters: None +Returns: 0 on success, -1 on error + +This signals to the host kernel that the specified guest is being paused by +userspace. The host will set a flag in the pvclock structure that is checked +from the soft lockup watchdog. The flag is part of the pvclock structure that +is shared between guest and host, specifically the second bit of the flags +field of the pvclock_vcpu_time_info structure. It will be set exclusively by +the host and read/cleared exclusively by the guest. The guest operation of +checking and clearing the flag must an atomic operation so +load-link/store-conditional, or equivalent must be used. There are two cases +where the guest will clear the flag: when the soft lockup watchdog timer resets +itself or when a soft lockup is detected. This ioctl can be called any time +after pausing the vcpu, but before it is resumed. + +4.71 KVM_SIGNAL_MSI + +Capability: KVM_CAP_SIGNAL_MSI +Architectures: x86 +Type: vm ioctl +Parameters: struct kvm_msi (in) +Returns: >0 on delivery, 0 if guest blocked the MSI, and -1 on error + +Directly inject a MSI message. Only valid with in-kernel irqchip that handles +MSI messages. + +struct kvm_msi { + __u32 address_lo; + __u32 address_hi; + __u32 data; + __u32 flags; + __u8 pad[16]; +}; + +No flags are defined so far. The corresponding field must be 0. + 5. The kvm_run structure Application code obtains a pointer to the kvm_run structure by diff --git a/MAINTAINERS b/MAINTAINERS index 83f156e28..5ae5f79a9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6765,6 +6765,12 @@ F: drivers/mtd/ubi/ F: include/linux/mtd/ubi.h F: include/mtd/ubi-user.h +UNSORTED BLOCK IMAGES (UBI) Fastmap +M: Richard Weinberger +L: linux-mtd@lists.infradead.org +S: Maintained +F: drivers/mtd/ubi/fastmap.c + USB ACM DRIVER M: Oliver Neukum L: linux-usb@vger.kernel.org diff --git a/Makefile b/Makefile index 47af1e967..eaf91f076 100644 --- a/Makefile +++ b/Makefile @@ -192,8 +192,11 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ # Default value for CROSS_COMPILE is not to prefix executables # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile export KBUILD_BUILDHOST := $(SUBARCH) -ARCH ?= $(SUBARCH) -CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%) +#ARCH ?= $(SUBARCH) +#CROSS_COMPILE ?= +ARCH ?= x86_64 +CROSS_COMPILE ?= ../x86_64-pc-linux-gnu/bin/x86_64-pc-linux-gnu- +#CROSS_COMPILE ?= /usr/local/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi- # Architecture as present in compile.h UTS_MACHINE := $(ARCH) @@ -360,7 +363,8 @@ CFLAGS_GCOV = -fprofile-arcs -ftest-coverage LINUXINCLUDE := -I$(srctree)/arch/$(hdr-arch)/include \ -Iarch/$(hdr-arch)/include/generated -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ - -include $(srctree)/include/linux/kconfig.h + -include $(srctree)/include/linux/kconfig.h \ + -include $(if $(KBUILD_SRC),$(srctree)/)include/linux/syno.h KBUILD_CPPFLAGS := -D__KERNEL__ @@ -536,8 +540,9 @@ else # but do not care if they are up-to-date. Use auto.conf to trigger the test PHONY += include/config/auto.conf + include/config/auto.conf: - $(Q)test -e include/generated/autoconf.h -a -e $@ || ( \ + @$(Q)test -e include/generated/autoconf.h -a -e $@ || ( \ echo; \ echo " ERROR: Kernel configuration is invalid."; \ echo " include/generated/autoconf.h or $@ are missing.";\ @@ -559,10 +564,22 @@ endif # $(dot-config) all: vmlinux ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE +ifdef CONFIG_SYNO_COMCERTO +KBUILD_CFLAGS += -Os -fno-caller-saves +else KBUILD_CFLAGS += -Os +endif +else +ifdef CONFIG_SYNO_COMCERTO +ifdef CONFIG_COMCERTO_CC_OPTIMIZE_O3 +KBUILD_CFLAGS += -O3 -fno-reorder-blocks -fno-tree-ch -fno-caller-saves +else +KBUILD_CFLAGS += -O2 -fno-reorder-blocks -fno-tree-ch -fno-caller-saves +endif else KBUILD_CFLAGS += -O2 endif +endif include $(srctree)/arch/$(SRCARCH)/Makefile @@ -620,6 +637,11 @@ endif NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include) CHECKFLAGS += $(NOSTDINC_FLAGS) +ifdef CONFIG_SYNO_COMCERTO +# improve gcc optimization +CFLAGS += $(call cc-option,-funit-at-a-time,) +endif + # warn about C99 declaration after statement KBUILD_CFLAGS += $(call cc-option,-Wdeclaration-after-statement,) diff --git a/README b/README index 0d5a7ddbe..c2c581afb 100644 --- a/README +++ b/README @@ -18,6 +18,8 @@ WHAT IS LINUX? It is distributed under the GNU General Public License - see the accompanying COPYING file for more details. + Test by Evan + ON WHAT HARDWARE DOES IT RUN? Although originally developed first for 32-bit x86-based PCs (386 or higher), diff --git a/arch/alpha/include/asm/dma.h b/arch/alpha/include/asm/dma.h old mode 100644 new mode 100755 index 87cfdbdf0..9e68e8f29 --- a/arch/alpha/include/asm/dma.h +++ b/arch/alpha/include/asm/dma.h @@ -8,7 +8,7 @@ * as this will also enable DMA across 64 KB boundaries. */ -/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $ +/* $Id: dma.h,v 1.1.1.1 2010/04/15 12:28:08 khchen Exp $ * linux/include/asm/dma.h: Defines for using and allocating dma channels. * Written by Hennus Bergman, 1992. * High DMA channel support & info by Hannu Savolainen diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig old mode 100644 new mode 100755 index 27bcd12b1..52da5d154 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -266,6 +266,16 @@ config ARCH_INTEGRATOR help Support for ARM's Integrator platform. +config ARCH_COMCERTO + bool "Mindspeed Comcerto" + select ARCH_SUPPORTS_MSI + select NEED_MACH_MEMORY_H + select ARCH_REQUIRE_GPIOLIB + help + This enables support for Mindspeed's Comcerto development boards. + If you would like to build your kernel to run on one of these boards + then you must say 'Y' here. Otherwise say 'N' + config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA @@ -540,6 +550,8 @@ config ARCH_DOVE config ARCH_KIRKWOOD bool "Marvell Kirkwood" + select ARCH_FEROCEON + select ARCH_FEROCEON_KW select CPU_FEROCEON select PCI select PCI_QUIRKS @@ -548,7 +560,7 @@ config ARCH_KIRKWOOD select PLAT_ORION help Support for the following Marvell Kirkwood series SoCs: - 88F6180, 88F6192 and 88F6281. + 88F6180, 88F6192, 88F6281 and 88F6282. config ARCH_LPC32XX bool "NXP LPC32XX" @@ -562,6 +574,40 @@ config ARCH_LPC32XX select GENERIC_CLOCKEVENTS help Support for the NXP LPC32XX family of processors + +config ARCH_ARMADA370 + bool "Marvell Armada-370" + select PCI + select ARCH_REQUIRE_GPIOLIB + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select PLAT_ARMADA + select HAVE_REGS_AND_STACK_ACCESS_API + select COMMON_CLKDEV + select NEED_MACH_MEMORY_H + help + Support for the Marvell Armada-370 SoC Family + +config ARCH_ARMADA_XP + bool "Marvell Armada XP" + select PCI + select ARCH_HAS_CPUFREQ + select ARCH_SUPPORTS_MSI + select ARCH_REQUIRE_GPIOLIB + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select PLAT_ARMADA +# select PLAT_ORION + select HAVE_REGS_AND_STACK_ACCESS_API + select COMMON_CLKDEV + select CLKSRC_MMIO + select CLKDEV_LOOKUP + select NEED_MACH_MEMORY_H + select DMABOUNCE + select ARCH_HAS_HOLES_MEMORYMODEL + config ARCH_MV78XX0 bool "Marvell MV78xx0" @@ -1020,6 +1066,7 @@ source "arch/arm/mach-ixp2000/Kconfig" source "arch/arm/mach-ixp23xx/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" +source "arch/arm/plat-orion/Kconfig" source "arch/arm/mach-ks8695/Kconfig" @@ -1055,6 +1102,10 @@ source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-sa1100/Kconfig" +source "arch/arm/mach-armada370/Kconfig" +source "arch/arm/mach-armadaxp/Kconfig" +source "arch/arm/plat-armada/Kconfig" + source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s5p/Kconfig" @@ -1100,7 +1151,15 @@ source "arch/arm/mach-vt8500/Kconfig" source "arch/arm/mach-w90x900/Kconfig" +source "arch/arm/mach-comcerto/Kconfig" + # Definitions to make life easier +config PLAT_ARMADA + bool + select CLKSRC_MMIO + select GENERIC_IRQ_CHIP + select HAVE_SCHED_CLOCK + config ARCH_ACORN bool @@ -1115,6 +1174,11 @@ config PLAT_ORION select GENERIC_IRQ_CHIP select HAVE_SCHED_CLOCK +config ARCH_FEROCEON_KW + bool + +config ARCH_FEROCEON + bool config PLAT_PXA bool @@ -1375,6 +1439,16 @@ config PL310_ERRATA_769419 on systems with an outer cache, the store buffer is drained explicitly. +config ARM_ERRATA_775420 + bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" + depends on CPU_V7 && SYNO_COMCERTO + help + This option enables the workaround for the 775420 Cortex-A9 (r2p2, + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance + operation aborts with MMU exception, it might cause the processor + to deadlock. This workaround puts DSB before executing ISB if + an abort may occur on cache maintenance. + endmenu source "arch/arm/common/Kconfig" @@ -1403,7 +1477,7 @@ config ISA_DMA_API bool config PCI - bool "PCI support" if MIGHT_HAVE_PCI + bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || MIGHT_HAVE_PCI help Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside @@ -1452,7 +1526,7 @@ config SMP depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ - ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q + ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q || ARCH_ARMADA_XP || ARCH_COMCERTO depends on MMU select USE_GENERIC_SMP_HELPERS select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP @@ -1516,6 +1590,11 @@ config HAVE_ARM_SCU help This option enables support for the ARM system coherency unit +config SCU_SPECULATIVE_LINE_FILLS + bool "SCU speculative line fills" + depends on HAVE_ARM_SCU && CACHE_PL310 + default n + config HAVE_ARM_TWD bool depends on SMP @@ -1563,7 +1642,7 @@ config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP default y - select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) + select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !ARCH_ARMADA_XP) help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system @@ -1710,6 +1789,7 @@ config FORCE_MAX_ZONEORDER int "Maximum zone order" if ARCH_SHMOBILE range 11 64 if ARCH_SHMOBILE default "9" if SA1111 + default "19" if ARCH_ARMADA370 default "11" help The kernel memory allocator divides physically contiguous memory @@ -1982,7 +2062,7 @@ endchoice config XIP_KERNEL bool "Kernel Execute-In-Place from ROM" - depends on !ZBOOT_ROM + depends on !ZBOOT_ROM && !ARM_LPAE help Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM @@ -2212,6 +2292,13 @@ config NEON Say Y to include support code for NEON, the ARMv7 Advanced SIMD Extension. +config KERNEL_MODE_NEON + bool "Support for NEON in kernel mode" + default n + depends on NEON + help + Say Y to include support for NEON in kernel mode. + endmenu menu "Userspace binary formats" diff --git a/arch/arm/Makefile b/arch/arm/Makefile old mode 100644 new mode 100755 index 362c7cad2..59eb2c298 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -13,6 +13,7 @@ LDFLAGS_vmlinux :=-p --no-undefined -X ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) LDFLAGS_vmlinux += --be8 +LDFLAGS_MODULE += --be8 endif OBJCOPYFLAGS :=-O binary -R .comment -S @@ -26,7 +27,11 @@ KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) # Do not use arch/arm/defconfig - it's always outdated. # Select a platform tht is kept up-to-date +ifeq ($(CONFIG_SYNO_COMCERTO),y) +KBUILD_DEFCONFIG := c2krtsm_defconfig +else KBUILD_DEFCONFIG := versatile_defconfig +endif # defines filename extension depending memory management type. ifeq ($(CONFIG_MMU),) @@ -64,7 +69,7 @@ arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6, ifeq ($(CONFIG_CPU_32v6),y) arch-$(CONFIG_CPU_32v6K) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k) endif -arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t) +arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t) arch-$(CONFIG_CPU_32v4T) :=-D__LINUX_ARM_ARCH__=4 -march=armv4t arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4 arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3 @@ -134,10 +139,15 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +machine-$(CONFIG_ARCH_ARMADA370) := armada370 machine-$(CONFIG_ARCH_AT91) := at91 machine-$(CONFIG_ARCH_BCMRING) := bcmring machine-$(CONFIG_ARCH_CLPS711X) := clps711x machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx +machine-$(CONFIG_ARCH_COMCERTO) := comcerto +ifeq ($(CONFIG_ARCH_COMCERTO),y) +textofs-$(CONFIG_ZONE_DMA) := 0x04008000 +endif machine-$(CONFIG_ARCH_DAVINCI) := davinci machine-$(CONFIG_ARCH_DOVE) := dove machine-$(CONFIG_ARCH_EBSA110) := ebsa110 @@ -186,6 +196,7 @@ machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_TCC8K) := tcc8k machine-$(CONFIG_ARCH_TEGRA) := tegra +machine-$(CONFIG_ARCH_ALPINE) += alpine machine-$(CONFIG_ARCH_U300) := u300 machine-$(CONFIG_ARCH_U8500) := ux500 machine-$(CONFIG_ARCH_VERSATILE) := versatile @@ -198,9 +209,13 @@ machine-$(CONFIG_MACH_SPEAR310) := spear3xx machine-$(CONFIG_MACH_SPEAR320) := spear3xx machine-$(CONFIG_MACH_SPEAR600) := spear6xx machine-$(CONFIG_ARCH_ZYNQ) := zynq +machine-$(CONFIG_ARCH_ARMADA_XP) := armadaxp + + # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +plat-$(CONFIG_PLAT_ARMADA) := armada plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_S3C64XX) := samsung @@ -232,6 +247,8 @@ else MACHINE := endif +export MACHINE + machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y)) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile old mode 100644 new mode 100755 index 21f56ff32..ea31cb97d --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -33,6 +33,11 @@ CFLAGS_string.o := -Os # # Architecture dependencies # + +ifeq ($(CONFIG_ARCH_COMCERTO),y) +OBJS += head-comcerto.o +endif + ifeq ($(CONFIG_ARCH_ACORN),y) OBJS += ll_char_wr.o font.o endif @@ -126,8 +131,11 @@ ccflags-y := -fpic -fno-builtin -I$(obj) asflags-y := -Wa,-march=all # Supply kernel BSS size to the decompressor via a linker symbol. -KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}') +KBSS_SZ = $(shell if $(CROSS_COMPILE)size $(obj)/../../../../vmlinux; then :; \ + else size $(obj)/../../../../vmlinux; fi | awk 'END{print $$3}') +ifneq ($(KBSS_SZ),) LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ) +endif # Supply ZRELADDR to the decompressor via a linker symbol. ifneq ($(CONFIG_AUTO_ZRELADDR),y) LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) diff --git a/arch/arm/boot/compressed/head-comcerto.S b/arch/arm/boot/compressed/head-comcerto.S new file mode 100755 index 000000000..e48f6e606 --- /dev/null +++ b/arch/arm/boot/compressed/head-comcerto.S @@ -0,0 +1,6 @@ +#include + + .section ".start", "ax" + ldr r7,mach_type + +mach_type: .word MACH_TYPE_COMCERTO diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S old mode 100644 new mode 100755 index d63632f35..c659ac371 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -9,6 +9,12 @@ * published by the Free Software Foundation. */ #include +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARCH_ARMADA_XP) +#include +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARCH_ARMADA370) +#include +#endif /* * Debugging stuff @@ -123,6 +129,11 @@ start: .rept 7 mov r0, r0 .endr +#ifdef CONFIG_SYNO_ARMADA_ARCH +#ifdef CONFIG_BE8_ON_LE + setend be +#endif +#endif ARM( mov r0, r0 ) ARM( b 1f ) THUMB( adr r12, BSYM(1f) ) @@ -132,7 +143,39 @@ start: .word start @ absolute load/run zImage address .word _edata @ zImage end address THUMB( .thumb ) +#if defined(CONFIG_SYNO_ARMADA_ARCH) +1: +#ifdef CONFIG_PLAT_ARMADA +/* Update Internal Regs offset in case UBoot is configured +** to use a different base address. +*/ + mrc p15, 0, r0, c5, c0, 0 @ Get the internal registers indication + tst r0, #(1 << 11) @ Check 0xF1000000 indication - bit 11 + beq 1f @ If bit 11 is not set (equal): + @ AXP - Need to check original Internal regs offset CP15 register + @ A370 - U-Boot was using 0xD0000000 + b 2f @ Else, bit 11 is set - U-Boot was using 0xF1000000 - Nothing to do +1: +#ifdef CONFIG_ARCH_ARMADA_XP + mrc p15, 4, r0, c15, c0, 0 @ Get the internal registers base address + lsl r0, r0, #13 @ the address is R-shifted, need to recover it +#else /* CONFIG_ARCH_ARMADA_370 */ + ldr r0, =0xD0000000 +#endif + ldr r5, =0x20080 + add r0, r0, r5 + ldr r6, =INTER_REGS_PHYS_BASE +#ifdef CONFIG_BE8_ON_LE + rev r6, r6 +#endif + str r6, [r0] +2: +#endif + + mov r7, r1 @ save architecture ID +#else 1: mov r7, r1 @ save architecture ID +#endif mov r8, r2 @ save atags pointer #ifndef __ARM_ARCH_2__ @@ -659,6 +702,9 @@ __armv7_mmu_cache_on: movne r1, #-1 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control +#endif +#ifdef CONFIG_SYNO_ARMADA_ARCH + mcr p15, 0, r0, c7, c5, 4 @ ISB #endif mcr p15, 0, r0, c1, c0, 0 @ load control register mrc p15, 0, r0, c1, c0, 0 @ and read it back @@ -694,6 +740,13 @@ __arm6_mmu_cache_on: __common_mmu_cache_on: #ifndef CONFIG_THUMB2_KERNEL +#ifdef CONFIG_SYNO_ARMADA_ARCH +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_4948 + mrc p15, 1, r1, c15, c1, 0 + orr r1, r1, #1 @ Disable L0 cache. + mcr p15, 1, r1, c15, c1, 0 +#endif +#endif #ifndef DEBUG orr r0, r0, #0x000d @ Write buffer, mmu #endif @@ -883,8 +936,21 @@ proc_types: W(b) __armv4_mmu_cache_off W(b) __armv5tej_mmu_cache_flush +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_CPU_SHEEVA_PJ4B_V6) + .word 0x000f0000 @ Marvell PJ4B ARMv6 + .word 0x000f0000 +#else .word 0x0007b000 @ ARMv6 .word 0x000ff000 +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) + W(b) __armv4_mmu_cache_on + W(b) __armv4_mmu_cache_off + W(b) __armv6_mmu_cache_flush + + .word 0x560f5810 @ Marvell PJ4 ARMv6 + .word 0xff0ffff0 +#endif W(b) __armv4_mmu_cache_on W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c old mode 100644 new mode 100755 index 410a54606..864688cb5 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -43,6 +43,10 @@ #include #include +#if defined(CONFIG_SYNO_COMCERTO) +#include +#endif + static DEFINE_RAW_SPINLOCK(irq_controller_lock); /* Address of GIC 0 CPU interface */ @@ -90,30 +94,70 @@ static inline unsigned int gic_irq(struct irq_data *d) static void gic_mask_irq(struct irq_data *d) { u32 mask = 1 << (gic_irq(d) % 32); +#if defined(CONFIG_SYNO_COMCERTO) + unsigned long flags; +#endif + +#if defined(CONFIG_SYNO_COMCERTO) + if ((gic_irq(d) == 87) || (gic_irq(d) == 66) || (gic_irq(d) == 33)) { + return; + } +#endif raw_spin_lock(&irq_controller_lock); +#if defined(CONFIG_SYNO_COMCERTO) + flags = msp_lock_frqsave(); +#endif writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); if (gic_arch_extn.irq_mask) gic_arch_extn.irq_mask(d); +#if defined(CONFIG_SYNO_COMCERTO) + msp_unlock_frqrestore(flags); +#endif raw_spin_unlock(&irq_controller_lock); } static void gic_unmask_irq(struct irq_data *d) { u32 mask = 1 << (gic_irq(d) % 32); +#if defined(CONFIG_SYNO_COMCERTO) + unsigned long flags; +#endif + +#if defined(CONFIG_SYNO_COMCERTO) + if ((gic_irq(d) == 87) || (gic_irq(d) == 66) || (gic_irq(d) == 33)) { + return; + } +#endif raw_spin_lock(&irq_controller_lock); +#if defined(CONFIG_SYNO_COMCERTO) + flags = msp_lock_frqsave(); +#endif if (gic_arch_extn.irq_unmask) gic_arch_extn.irq_unmask(d); writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); +#if defined(CONFIG_SYNO_COMCERTO) + msp_unlock_frqrestore(flags); +#endif raw_spin_unlock(&irq_controller_lock); } static void gic_eoi_irq(struct irq_data *d) { if (gic_arch_extn.irq_eoi) { +#if defined(CONFIG_SYNO_COMCERTO) + unsigned long flags; +#endif + raw_spin_lock(&irq_controller_lock); +#if defined(CONFIG_SYNO_COMCERTO) + flags = msp_lock_frqsave(); +#endif gic_arch_extn.irq_eoi(d); +#if defined(CONFIG_SYNO_COMCERTO) + msp_unlock_frqrestore(flags); +#endif raw_spin_unlock(&irq_controller_lock); } @@ -308,6 +352,14 @@ static void __init gic_dist_init(struct gic_chip_data *gic) for (i = 32; i < gic_irqs; i += 32) writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_MSP) + /* + * Set SPI interrupts are nonSecure + */ + for (i = 32; i < gic_irqs; i += 32) + writel_relaxed(0xffffffff, base + GIC_DIST_SECURITY_BIT + i * 4 / 32); +#endif /* CONFIG_SYNO_COMCERTO && CONFIG_COMCERTO_MSP */ + /* * Setup the Linux IRQ subsystem. */ @@ -325,7 +377,14 @@ static void __init gic_dist_init(struct gic_chip_data *gic) irq_set_chip_data(irq, gic); } +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_MSP) + /* + * Enable NonSecure interrupts in Distributor + */ + writel_relaxed(3, base + GIC_DIST_CTRL); +#else /* !CONFIG_SYNO_COMCERTO || !CONFIG_COMCERTO_MSP */ writel_relaxed(1, base + GIC_DIST_CTRL); +#endif /*CONFIG_SYNO_COMCERTO && CONFIG_COMCERTO_MSP */ } static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) @@ -348,9 +407,62 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); + +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_MSP) + /* + * Set PPI and SGI interrupts are nonSecure + */ + writel_relaxed(0xffffffff, dist_base + GIC_DIST_SECURITY_BIT); + + /* + * Enable NonSecure interrupts in CPU interface, + * Secure interrupts go to FIQ line, + * Secure read returns valid NonSecure interrupt ID + */ + writel_relaxed(0xf, base + GIC_CPU_CTRL); +#else /* !CONFIG_SYNO_COMCERTO || !CONFIG_COMCERTO_MSP */ writel_relaxed(1, base + GIC_CPU_CTRL); +#endif /* CONFIG_SYNO_COMCERTO && CONFIG_COMCERTO_MSP */ } +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_MSP) + +static void __cpuinit gic_cpu_init_irq_only(struct gic_chip_data *gic) +{ + void __iomem *dist_base = gic->dist_base; + void __iomem *base = gic->cpu_base; + int i; + + /* + * Deal with the banked PPI and SGI interrupts - disable all + * PPI interrupts, ensure all SGI interrupts are enabled. + */ + writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); + writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); + + /* + * Set priority on PPI and SGI interrupts + */ + for (i = 0; i < 32; i += 4) + writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); + + writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); + + /* + * Set PPI and SGI interrupts are nonSecure + */ + writel_relaxed(0xffffffff, dist_base + GIC_DIST_SECURITY_BIT); + + /* + * Enable NonSecure interrupts in CPU interface, + * Secure interrupts go to IRQ line, + * Secure read returns valid NonSecure interrupt ID + */ + writel_relaxed(0x7, base + GIC_CPU_CTRL); +} + +#endif /* CONFIG_SYNO_COMCERTO && CONFIG_COMCERTO_MSP */ + #ifdef CONFIG_CPU_PM /* * Saves the GIC distributor registers during suspend or idle. Must be called @@ -625,7 +737,12 @@ void __cpuinit gic_secondary_init(unsigned int gic_nr) { BUG_ON(gic_nr >= MAX_GIC_NR); +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_MSP) + /* run alternative secondary_boot gic init */ + gic_cpu_init_irq_only(&gic_data[gic_nr]); +#else /* !CONFIG_SYNO_COMCERTO || !CONFIG_COMCERTO_MSP */ gic_cpu_init(&gic_data[gic_nr]); +#endif /* CONFIG_SYNO_COMCERTO && CONFIG_COMCERTO_MSP */ } #ifdef CONFIG_SMP @@ -645,7 +762,16 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) dsb(); /* this always happens on GIC0 */ + +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_MSP) +#define GIC_SGI_SATT (1 << 15) + /* + * Send SGI from Secure write to NonSecure target + */ + writel_relaxed(map << 16 | GIC_SGI_SATT | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); +#else /* !CONFIG_SYNO_COMCERTO || !CONFIG_COMCERTO_MSP */ writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); +#endif /* CONFIG_SYNO_COMCERTO && CONFIG_COMCERTO_MSP */ } #endif diff --git a/arch/arm/configs/armada_370_v7up_defconfig b/arch/arm/configs/armada_370_v7up_defconfig new file mode 100755 index 000000000..7f50d9f65 --- /dev/null +++ b/arch/arm/configs/armada_370_v7up_defconfig @@ -0,0 +1,244 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA370=y +CONFIG_MV_ETH_PORTS_NUM=2 +CONFIG_MV_ETH_RXQ=8 +CONFIG_MV_ETH_TXQ=8 +CONFIG_NET_SKB_HEADROOM=96 +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_FEROCEON_PROC=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +CONFIG_MV_ETH_GROUP0_CPU=0x1 +CONFIG_MV_ETH_SWITCH=y +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +CONFIG_MV_CESA_TOOL=y +CONFIG_MV_CESA_CHAIN_MODE=y +CONFIG_MV_CESA_OCF=y +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_SHEEVA_DEEP_IDLE=y +CONFIG_ARMADA_SUPPORT_DEEP_IDLE_DRAM_SR=y +CONFIG_NO_HZ=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_MV_THOR=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_SKY2=y +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_PHYLIB=y +CONFIG_PHONE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_ARMADA370_SOC=y +CONFIG_SND_SOC_ALL_CODECS=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_USB_GADGET=m +CONFIG_USB_ETH=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_FRAME_WARN=0 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_370_v7up_nas_defconfig b/arch/arm/configs/armada_370_v7up_nas_defconfig new file mode 100755 index 000000000..20bf02699 --- /dev/null +++ b/arch/arm/configs/armada_370_v7up_nas_defconfig @@ -0,0 +1,243 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA370=y +CONFIG_MV_ETH_PORTS_NUM=2 +CONFIG_NET_SKB_HEADROOM=96 +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_FEROCEON_PROC=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +CONFIG_MV_ETH_GROUP0_CPU=0x1 +CONFIG_MV_ETH_SWITCH=y +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_SHEEVA_DEEP_IDLE=y +CONFIG_NO_HZ=y +CONFIG_VMSPLIT_2G=y +CONFIG_AEABI=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_MV_STAGGERED_SPINUP=y +CONFIG_SCSI_MV_THOR=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_SKY2=y +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_PHYLIB=y +# CONFIG_WLAN is not set +CONFIG_PHONE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_ARMADA370_SOC=y +CONFIG_SND_SOC_ALL_CODECS=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_USB_GADGET=m +CONFIG_USB_ETH=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_SPLICE_NET_DMA_SUPPORT=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_370_v7up_nat_defconfig b/arch/arm/configs/armada_370_v7up_nat_defconfig new file mode 100755 index 000000000..839d9c422 --- /dev/null +++ b/arch/arm/configs/armada_370_v7up_nat_defconfig @@ -0,0 +1,257 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA370=y +CONFIG_MV_ETH_PORTS_NUM=2 +CONFIG_MV_ETH_RXQ=8 +CONFIG_MV_ETH_TXQ=8 +CONFIG_NET_SKB_HEADROOM=96 +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_FEROCEON_PROC=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +CONFIG_MV_ETH_GROUP0_CPU=0x1 +CONFIG_MV_ETH_SWITCH=y +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_SHEEVA_DEEP_IDLE=y +CONFIG_NO_HZ=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_MV_THOR=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HP is not set +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_SKY2=y +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_PHYLIB=y +CONFIG_PPP=y +CONFIG_PHONE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_ARMADA370_SOC=y +CONFIG_SND_SOC_ALL_CODECS=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_USB_GADGET=m +CONFIG_USB_ETH=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_xp_fpga_b0_defconfig b/arch/arm/configs/armada_xp_fpga_b0_defconfig new file mode 100755 index 000000000..448dee34b --- /dev/null +++ b/arch/arm/configs/armada_xp_fpga_b0_defconfig @@ -0,0 +1,196 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA_XP=y +# CONFIG_MV_INCLUDE_SWITCH is not set +CONFIG_MV_ETH_PORTS_NUM=4 +CONFIG_MV_ETH_RXQ=8 +CONFIG_MV_ETH_TXQ=8 +CONFIG_NET_SKB_HEADROOM=96 +CONFIG_MV_ETH_NFP=y +CONFIG_ARMADA_XP_REV_A0=y +# CONFIG_MACH_ARMADA_XP_DB is not set +# CONFIG_MACH_ARMADA_XP_RDSRV is not set +# CONFIG_MACH_ARMADA_XP_RD_NAS is not set +CONFIG_MV_INCLUDE_PCI=y +# CONFIG_MV_INCLUDE_XOR is not set +# CONFIG_MV_INCLUDE_NFC is not set +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +# CONFIG_MV_INCLUDE_SFLASH_MTD is not set +CONFIG_MV_ETH_NETA=y +CONFIG_MV_ETH_BM_PORT_0_SHORT_BUF_NUM=4096 +CONFIG_MV_ETH_BM_PORT_1_SHORT_BUF_NUM=4096 +CONFIG_MV_ETH_BM_PORT_2_SHORT_BUF_NUM=4096 +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_COAL_PKTS=64 +CONFIG_MV_ETH_RX_COAL_USEC=200 +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +CONFIG_MV_ETH_RX_POLL_WEIGHT=128 +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +CONFIG_MV_CESA_CHANNELS=1 +# CONFIG_SWP_EMULATE is not set +# CONFIG_SHEEVA_ERRATA_ARM_CPU_5980 is not set +# CONFIG_SHEEVA_ERRATA_ARM_CPU_6043 is not set +# CONFIG_SHEEVA_ERRATA_ARM_CPU_6075 is not set +# CONFIG_SHEEVA_ERRATA_ARM_CPU_6076 is not set +# CONFIG_SHEEVA_ERRATA_ARM_CPU_6136 is not set +CONFIG_PCI_DEBUG=y +CONFIG_SMP=y +CONFIG_AEABI=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IPV6 is not set +CONFIG_BRIDGE=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_ATA=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_E100=y +CONFIG_E1000E=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_DMADEVICES=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_xp_v7amp_defconfig b/arch/arm/configs/armada_xp_v7amp_defconfig new file mode 100755 index 000000000..887763501 --- /dev/null +++ b/arch/arm/configs/armada_xp_v7amp_defconfig @@ -0,0 +1,206 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA_XP=y +# CONFIG_MV_INCLUDE_SWITCH is not set +CONFIG_MV_ETH_PORTS_NUM=4 +CONFIG_MV_ETH_RXQ=8 +CONFIG_MV_ETH_TXQ=8 +CONFIG_NET_SKB_HEADROOM=96 +CONFIG_MV_INCLUDE_PCI=y +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +CONFIG_MV_AMP_ENABLE=y +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_PCI_DEBUG=y +CONFIG_NO_HZ=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_E100=y +CONFIG_E1000E=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_PPP=y +CONFIG_PPPOE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_FRAME_WARN=0 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_xp_v7smp_be8_defconfig b/arch/arm/configs/armada_xp_v7smp_be8_defconfig new file mode 100755 index 000000000..d29bd7022 --- /dev/null +++ b/arch/arm/configs/armada_xp_v7smp_be8_defconfig @@ -0,0 +1,209 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA_XP=y +# CONFIG_MV_INCLUDE_SWITCH is not set +CONFIG_MV_ETH_PORTS_NUM=4 +CONFIG_MV_ETH_RXQ=8 +CONFIG_MV_ETH_TXQ=8 +CONFIG_NET_SKB_HEADROOM=96 +CONFIG_MV_INCLUDE_PCI=y +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_BE8_ON_LE=y +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_SHEEVA_DEEP_IDLE=y +CONFIG_STANDBY_UART_WAKE=y +CONFIG_PCI_DEBUG=y +CONFIG_NO_HZ=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_E100=y +CONFIG_E1000E=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_PPP=y +CONFIG_PPPOE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_FRAME_WARN=0 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_xp_v7smp_defconfig b/arch/arm/configs/armada_xp_v7smp_defconfig new file mode 100755 index 000000000..ee6946e26 --- /dev/null +++ b/arch/arm/configs/armada_xp_v7smp_defconfig @@ -0,0 +1,208 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA_XP=y +# CONFIG_MV_INCLUDE_SWITCH is not set +CONFIG_MV_ETH_PORTS_NUM=4 +CONFIG_MV_ETH_RXQ=8 +CONFIG_MV_ETH_TXQ=8 +CONFIG_NET_SKB_HEADROOM=96 +CONFIG_MV_INCLUDE_PCI=y +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_SHEEVA_DEEP_IDLE=y +CONFIG_STANDBY_UART_WAKE=y +CONFIG_PCI_DEBUG=y +CONFIG_NO_HZ=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_E100=y +CONFIG_E1000E=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_PPP=y +CONFIG_PPPOE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_CIFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_FRAME_WARN=0 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_xp_v7smp_nas_64k_defconfig b/arch/arm/configs/armada_xp_v7smp_nas_64k_defconfig new file mode 100755 index 000000000..402806095 --- /dev/null +++ b/arch/arm/configs/armada_xp_v7smp_nas_64k_defconfig @@ -0,0 +1,208 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +# CONFIG_PERF_EVENTS is not set +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA_XP=y +# CONFIG_MV_INCLUDE_SWITCH is not set +CONFIG_MV_ETH_PORTS_NUM=4 +CONFIG_NET_SKB_HEADROOM=96 +CONFIG_MV_INCLUDE_PCI=y +# CONFIG_MV_INCLUDE_XOR is not set +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +CONFIG_MV_ETH_NAPI_GROUPS=4 +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_SHEEVA_DEEP_IDLE=y +CONFIG_STANDBY_UART_WAKE=y +CONFIG_MV_SUPPORT_64KB_PAGE_SIZE=y +CONFIG_PCI_DEBUG=y +CONFIG_NO_HZ=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_VMSPLIT_2G=y +CONFIG_AEABI=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IPV6 is not set +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_MV_STAGGERED_SPINUP=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_E100=y +CONFIG_E1000E=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_PPP=y +CONFIG_PPPOE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_xp_v7smp_nas_defconfig b/arch/arm/configs/armada_xp_v7smp_nas_defconfig new file mode 100755 index 000000000..d374bc4f1 --- /dev/null +++ b/arch/arm/configs/armada_xp_v7smp_nas_defconfig @@ -0,0 +1,206 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA_XP=y +# CONFIG_MV_INCLUDE_SWITCH is not set +CONFIG_MV_ETH_PORTS_NUM=4 +CONFIG_NET_SKB_HEADROOM=96 +CONFIG_MV_INCLUDE_PCI=y +# CONFIG_MV_INCLUDE_XOR is not set +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +CONFIG_MV_ETH_NAPI_GROUPS=4 +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_SHEEVA_DEEP_IDLE=y +CONFIG_STANDBY_UART_WAKE=y +CONFIG_PCI_DEBUG=y +CONFIG_NO_HZ=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_VMSPLIT_2G=y +CONFIG_AEABI=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IPV6 is not set +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_MV_STAGGERED_SPINUP=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_E100=y +CONFIG_E1000E=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_PPP=y +CONFIG_PPPOE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/armada_xp_v7smp_nat_defconfig b/arch/arm/configs/armada_xp_v7smp_nat_defconfig new file mode 100755 index 000000000..701e8f80a --- /dev/null +++ b/arch/arm/configs/armada_xp_v7smp_nat_defconfig @@ -0,0 +1,236 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_ARMADA_XP=y +# CONFIG_MV_INCLUDE_SWITCH is not set +CONFIG_MV_ETH_PORTS_NUM=4 +CONFIG_MV_ETH_RXQ=8 +CONFIG_MV_ETH_TXQ=8 +CONFIG_NET_SKB_HEADROOM=96 +CONFIG_MV_INCLUDE_PCI=y +# CONFIG_MV_INCLUDE_LEGACY_NAND is not set +CONFIG_MTD_NAND_NFC_INIT_RESET=y +CONFIG_MV_PMU_PROC=y +CONFIG_MV_ETH_NETA=y +# CONFIG_MV_ETH_BM is not set +# CONFIG_MV_ETH_PNC is not set +CONFIG_MV_ETH_GRO_DEF=y +CONFIG_MV_ETH_TSO_DEF=y +# CONFIG_MV_ETH_STAT_INF is not set +CONFIG_MV_ETH_RX_DESC_PREFETCH=y +CONFIG_MV_ETH_RX_PKT_PREFETCH=y +# CONFIG_MV_ETH_REDUCE_BURST_SIZE_WA is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET=y +CONFIG_SHEEVA_DEEP_IDLE=y +CONFIG_STANDBY_UART_WAKE=y +CONFIG_PCI_DEBUG=y +CONFIG_NO_HZ=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_ADVANCED is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_MANGLE is not set +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_TARGET_LOG is not set +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +# CONFIG_IP6_NF_MANGLE is not set +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_PKTGEN=m +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_E100=y +CONFIG_E1000E=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_PPP=y +CONFIG_PPPOE=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_JC42=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/c2kasic_defconfig b/arch/arm/configs/c2kasic_defconfig new file mode 100755 index 000000000..21cf3801c --- /dev/null +++ b/arch/arm/configs/c2kasic_defconfig @@ -0,0 +1,1046 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.2.2 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_FREEZER is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EXPERT is not set +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_COMCERTO=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set + +# +# System MMU +# + +# +# Comcerto Implementation Options +# +CONFIG_ARCH_M86XXX=y +# CONFIG_C2K_EVM is not set +CONFIG_C2K_ASIC=y +# CONFIG_RTSM_C2K is not set +CONFIG_MTD_COMCERTO_NOR=y +CONFIG_COMCERTO_TDM_CLOCK=y +# CONFIG_PCI is not set +CONFIG_COMCERTO_NUM_PCIES=2 +CONFIG_COMCERTO_FP=y +CONFIG_COMCERTO_UART0_SUPPORT=y +CONFIG_COMCERTO_UART1_SUPPORT=y +CONFIG_COMCERTO_USB0_SUPPORT=y +# CONFIG_COMCERTO_USB1_SUPPORT is not set +CONFIG_COMCERTO_IPSEC_SUPPORT=y +CONFIG_COMCERTO_SPI_SUPPORT=y +CONFIG_COMCERTO_FAST_SPI_SUPPORT=y +CONFIG_COMCERTO_I2C_SUPPORT=y +CONFIG_COMCERTO_DW_DMA_SUPPORT=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_ARM_ERRATA_742230=y +CONFIG_ARM_ERRATA_742231=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_751472=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +# CONFIG_ARM_ERRATA_754327 is not set +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_GIC=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +# CONFIG_HOTPLUG_CPU is not set +CONFIG_LOCAL_TIMERS=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0x00608000 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM=y +CONFIG_CMDLINE="" +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_MISC_DEVICES is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_SMBUS=y + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +# CONFIG_I2C_ALGOPCF is not set +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_COMCERTO=y +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PXA_PCI is not set +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_PARPORT_LIGHT=m +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set +CONFIG_SPI_MSPD=y +CONFIG_COMCERTO_SPI=y + +# +# Miscellaneous I2C Chip support +# +CONFIG_EEPROM_AT=y +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=y +# CONFIG_SSB_DEBUG is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_DRM=m +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=m + +# +# Display hardware drivers +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=1 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set diff --git a/arch/arm/configs/c2kevm_defconfig b/arch/arm/configs/c2kevm_defconfig new file mode 100755 index 000000000..caba88d57 --- /dev/null +++ b/arch/arm/configs/c2kevm_defconfig @@ -0,0 +1,1046 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.2.2 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_FREEZER is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EXPERT is not set +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_COMCERTO=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set + +# +# System MMU +# + +# +# Comcerto Implementation Options +# +CONFIG_ARCH_M86XXX=y +CONFIG_C2K_EVM=y +# CONFIG_C2K_ASIC is not set +# CONFIG_RTSM_C2K is not set +CONFIG_MTD_COMCERTO_NOR=y +CONFIG_COMCERTO_TDM_CLOCK=y +# CONFIG_PCI is not set +CONFIG_COMCERTO_NUM_PCIES=2 +CONFIG_COMCERTO_FP=y +# CONFIG_COMCERTO_UART0_SUPPORT is not set +CONFIG_COMCERTO_UART1_SUPPORT=y +CONFIG_COMCERTO_USB0_SUPPORT=y +# CONFIG_COMCERTO_USB1_SUPPORT is not set +CONFIG_COMCERTO_IPSEC_SUPPORT=y +CONFIG_COMCERTO_SPI_SUPPORT=y +CONFIG_COMCERTO_FAST_SPI_SUPPORT=y +CONFIG_COMCERTO_I2C_SUPPORT=y +CONFIG_COMCERTO_DW_DMA_SUPPORT=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_ARM_ERRATA_742230=y +CONFIG_ARM_ERRATA_742231=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_751472=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +# CONFIG_ARM_ERRATA_754327 is not set +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_GIC=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +# CONFIG_HOTPLUG_CPU is not set +CONFIG_LOCAL_TIMERS=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0x00608000 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM=y +CONFIG_CMDLINE="" +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_MISC_DEVICES is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_SMBUS=y + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +# CONFIG_I2C_ALGOPCF is not set +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_COMCERTO=y +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PXA_PCI is not set +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_PARPORT_LIGHT=m +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set +CONFIG_SPI_MSPD=y +CONFIG_COMCERTO_SPI=y + +# +# Miscellaneous I2C Chip support +# +CONFIG_EEPROM_AT=y +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=y +# CONFIG_SSB_DEBUG is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_DRM=m +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=m + +# +# Display hardware drivers +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=1 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set diff --git a/arch/arm/configs/c2klv_defconfig b/arch/arm/configs/c2klv_defconfig new file mode 100755 index 000000000..79e3d9ace --- /dev/null +++ b/arch/arm/configs/c2klv_defconfig @@ -0,0 +1,924 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.2.2 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_FREEZER is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EXPERT is not set +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_COMCERTO=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set + +# +# System MMU +# + +# +# Comcerto Implementation Options +# +CONFIG_ARCH_M86XXX=y +# CONFIG_C2K_EVM is not set +# CONFIG_C2K_ASIC is not set +CONFIG_RTSM_C2K=y +CONFIG_MTD_COMCERTO_NOR=y +CONFIG_COMCERTO_TDM_CLOCK=y +CONFIG_COMCERTO_NUM_PCIES=2 +CONFIG_COMCERTO_FP=y +# CONFIG_COMCERTO_UART0_SUPPORT is not set +CONFIG_COMCERTO_UART1_SUPPORT=y +CONFIG_COMCERTO_USB0_SUPPORT=y +# CONFIG_COMCERTO_USB1_SUPPORT is not set +CONFIG_COMCERTO_IPSEC_SUPPORT=y +CONFIG_COMCERTO_SPI_SUPPORT=y +CONFIG_COMCERTO_FAST_SPI_SUPPORT=y +CONFIG_COMCERTO_I2C_SUPPORT=y +CONFIG_COMCERTO_DW_DMA_SUPPORT=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +CONFIG_PL310_ERRATA_588369=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +CONFIG_PL310_ERRATA_753970=y +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_GIC=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +# CONFIG_HOTPLUG_CPU is not set +CONFIG_LOCAL_TIMERS=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +# CONFIG_HW_PERF_EVENTS is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_AUTO_ZRELADDR is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_MISC_DEVICES is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_SMBUS=y + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +# CONFIG_I2C_ALGOPCF is not set +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PXA_PCI is not set +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_PARPORT_LIGHT=m +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=y +# CONFIG_SSB_DEBUG is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_DRM=m +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=m + +# +# Display hardware drivers +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set diff --git a/arch/arm/configs/c2krtsm_defconfig b/arch/arm/configs/c2krtsm_defconfig new file mode 100755 index 000000000..987f396af --- /dev/null +++ b/arch/arm/configs/c2krtsm_defconfig @@ -0,0 +1,1034 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.2.2 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_FHANDLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_FREEZER is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EXPERT is not set +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_COMCERTO=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set + +# +# System MMU +# + +# +# Comcerto Implementation Options +# +CONFIG_ARCH_M86XXX=y +# CONFIG_C2K_EVM is not set +# CONFIG_C2K_ASIC is not set +CONFIG_RTSM_C2K=y +CONFIG_MTD_COMCERTO_NOR=y +CONFIG_COMCERTO_TDM_CLOCK=y +CONFIG_COMCERTO_NUM_PCIES=2 +CONFIG_COMCERTO_FP=y +# CONFIG_COMCERTO_UART0_SUPPORT is not set +CONFIG_COMCERTO_UART1_SUPPORT=y +CONFIG_COMCERTO_USB0_SUPPORT=y +# CONFIG_COMCERTO_USB1_SUPPORT is not set +CONFIG_COMCERTO_IPSEC_SUPPORT=y +CONFIG_COMCERTO_SPI_SUPPORT=y +CONFIG_COMCERTO_FAST_SPI_SUPPORT=y +CONFIG_COMCERTO_I2C_SUPPORT=y +CONFIG_COMCERTO_DW_DMA_SUPPORT=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_ARM_ERRATA_742230=y +CONFIG_ARM_ERRATA_742231=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_751472=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +# CONFIG_ARM_ERRATA_754327 is not set +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_GIC=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +# CONFIG_HOTPLUG_CPU is not set +CONFIG_LOCAL_TIMERS=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +# CONFIG_HW_PERF_EVENTS is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0x00608000 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM=y +CONFIG_CMDLINE="" +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_MISC_DEVICES is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_SMBUS=y + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +# CONFIG_I2C_ALGOPCF is not set +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PXA_PCI is not set +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_PARPORT_LIGHT=m +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=y +# CONFIG_SSB_DEBUG is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_DRM=m +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=m + +# +# Display hardware drivers +# +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_STAGING is not set + +# +# Hardware Spinlock drivers +# +CONFIG_IOMMU_SUPPORT=y +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FSNOTIFY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=1 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set diff --git a/arch/arm/configs/db88f5281_vfp_defconfig b/arch/arm/configs/db88f5281_vfp_defconfig new file mode 100755 index 000000000..76882d7cd --- /dev/null +++ b/arch/arm/configs/db88f5281_vfp_defconfig @@ -0,0 +1,1326 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Mon Nov 12 17:24:45 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +CONFIG_MV88F5181=y +# CONFIG_MV88F5181L is not set +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PCI=y +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set +CONFIG_USE_DSP=y +CONFIG_MV_USE_IDMA_ENGINE=y +CONFIG_MV_IDMA_COPYUSER=y +CONFIG_MV_IDMA_COPYUSER_THRESHOLD=1260 +CONFIG_MV_IDMA_MEMZERO=y +CONFIG_MV_IDMA_MEMZERO_THRESHOLD=192 +CONFIG_MV_IDMA_MEMCOPY=y +CONFIG_MV_IDMA_MEMCOPY_THRESHOLD=128 +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +# CONFIG_MV_GATEWAY is not set +CONFIG_MV_ETH_NAME="egiga" +# CONFIG_ETH_MULTI_Q is not set +# CONFIG_EGIGA_STATIS is not set +CONFIG_ETH_0_MACADDR="000000000051" +CONFIG_EGIGA_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +# CONFIG_MV_SATA_SUPPORT_ATAPI is not set +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +# CONFIG_NFTL_RW is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND_MUSEUM_IDS=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_DISKONCHIP=y +# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 +# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_CRYPT is not set +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=m +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=m +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=m +CONFIG_SKY2=m +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=m +CONFIG_SK98LIN_NAPI=y +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +# CONFIG_HID is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_KARMA=y +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_DUMMY_HCD=y +CONFIG_USB_DUMMY_HCD=m +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig old mode 100644 new mode 100755 index aeb3af541..c5171192a --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -15,9 +15,9 @@ CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_ESATA_SHEEVAPLUG=y CONFIG_MACH_GURUPLUG=y -CONFIG_MACH_DOCKSTAR=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y +CONFIG_MACH_DOCKSTAR=y CONFIG_MACH_OPENRD_BASE=y CONFIG_MACH_OPENRD_CLIENT=y CONFIG_MACH_OPENRD_ULTIMATE=y @@ -52,8 +52,9 @@ CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y @@ -69,7 +70,6 @@ CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ORION=y CONFIG_BLK_DEV_LOOP=y -# CONFIG_MISC_DEVICES is not set # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m @@ -78,22 +78,19 @@ CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_MV=y CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_NET_ETHERNET=y CONFIG_MII=y -CONFIG_NET_PCI=y CONFIG_MV643XX_ETH=y -# CONFIG_NETDEV_10000 is not set +CONFIG_MARVELL_PHY=y CONFIG_LIBERTAS=y CONFIG_LIBERTAS_SDIO=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_DEVKMEM is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_HW_RANDOM is not set CONFIG_I2C=y # CONFIG_I2C_COMPAT is not set @@ -103,7 +100,6 @@ CONFIG_SPI=y CONFIG_SPI_ORION=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set CONFIG_HID_DRAGONRISE=y CONFIG_HID_GYRATION=y CONFIG_HID_TWINHAN=y @@ -122,7 +118,6 @@ CONFIG_USB=y CONFIG_USB_DEVICEFS=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_PRINTER=m CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE_DATAFAB=y @@ -148,7 +143,6 @@ CONFIG_MV_XOR=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_UDF_FS=m @@ -171,11 +165,9 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y CONFIG_CRYPTO_CBC=m CONFIG_CRYPTO_PCBC=m diff --git a/arch/arm/configs/mv76100_defconfig b/arch/arm/configs/mv76100_defconfig new file mode 100755 index 000000000..3b1bd82b7 --- /dev/null +++ b/arch/arm/configs/mv76100_defconfig @@ -0,0 +1,1674 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Wed Apr 1 15:52:47 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_DDUO_FAMILY=y +# CONFIG_MV632X_FAMILY is not set +# CONFIG_MV78100 is not set +# CONFIG_MV78200 is not set +CONFIG_MV76100=y +# CONFIG_MV78XX0_Z0 is not set +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv78200_defconfig b/arch/arm/configs/mv78200_defconfig new file mode 100755 index 000000000..9792d367b --- /dev/null +++ b/arch/arm/configs/mv78200_defconfig @@ -0,0 +1,1678 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Wed Apr 1 15:52:47 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_DDUO_FAMILY=y +# CONFIG_MV632X_FAMILY is not set +# CONFIG_MV78100 is not set +CONFIG_MV78200=y +# CONFIG_MV76100 is not set +# CONFIG_MV78XX0_Z0 is not set +CONFIG_MV78XX0_SUPPORT_2GB_RAM=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=4 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" +CONFIG_MV_ETH_2_MTU=1500 +CONFIG_MV_ETH_2_MACADDR="64:00:00:00:00:03" +CONFIG_MV_ETH_3_MTU=1500 +CONFIG_MV_ETH_3_MACADDR="64:00:00:00:00:04" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv78xx0_2gb_ram_defconfig b/arch/arm/configs/mv78xx0_2gb_ram_defconfig new file mode 100755 index 000000000..1288fd628 --- /dev/null +++ b/arch/arm/configs/mv78xx0_2gb_ram_defconfig @@ -0,0 +1,1674 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Wed Apr 1 15:52:47 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_DDUO_FAMILY=y +# CONFIG_MV632X_FAMILY is not set +CONFIG_MV78100=y +# CONFIG_MV78200 is not set +# CONFIG_MV76100 is not set +# CONFIG_MV78XX0_Z0 is not set +CONFIG_MV78XX0_SUPPORT_2GB_RAM=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv78xx0_base_defconfig b/arch/arm/configs/mv78xx0_base_defconfig new file mode 100755 index 000000000..20cc90a0e --- /dev/null +++ b/arch/arm/configs/mv78xx0_base_defconfig @@ -0,0 +1,1577 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Wed Apr 1 15:52:47 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_DDUO_FAMILY=y +# CONFIG_MV632X_FAMILY is not set +CONFIG_MV78100=y +# CONFIG_MV78200 is not set +# CONFIG_MV76100 is not set +# CONFIG_MV78XX0_Z0 is not set +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv78xx0_be_defconfig b/arch/arm/configs/mv78xx0_be_defconfig new file mode 100755 index 000000000..5a585a153 --- /dev/null +++ b/arch/arm/configs/mv78xx0_be_defconfig @@ -0,0 +1,1674 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Wed Apr 1 15:52:47 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_DDUO_FAMILY=y +# CONFIG_MV632X_FAMILY is not set +CONFIG_MV78100=y +# CONFIG_MV78200 is not set +# CONFIG_MV76100 is not set +# CONFIG_MV78XX0_Z0 is not set +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv78xx0_defconfig_bsp b/arch/arm/configs/mv78xx0_defconfig_bsp new file mode 100755 index 000000000..1d978ec64 --- /dev/null +++ b/arch/arm/configs/mv78xx0_defconfig_bsp @@ -0,0 +1,1673 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Wed Apr 1 15:52:47 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_DDUO_FAMILY=y +# CONFIG_MV632X_FAMILY is not set +CONFIG_MV78100=y +# CONFIG_MV78200 is not set +# CONFIG_MV76100 is not set +# CONFIG_MV78XX0_Z0 is not set +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv78xx0_net_defconfig b/arch/arm/configs/mv78xx0_net_defconfig new file mode 100755 index 000000000..7203b6d81 --- /dev/null +++ b/arch/arm/configs/mv78xx0_net_defconfig @@ -0,0 +1,1466 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Thu May 7 19:42:20 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_DDUO_FAMILY=y +# CONFIG_MV632X_FAMILY is not set +CONFIG_MV78100=y +# CONFIG_MV78200 is not set +# CONFIG_MV76100 is not set +# CONFIG_MV78XX0_Z0 is not set +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_USB_PHY_OVERRIDE_SETTINGS is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +# CONFIG_MV_INCLUDE_TDM is not set +CONFIG_MV_INCLUDE_GIG_ETH=y +# CONFIG_MV_INCLUDE_SPI is not set +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +# CONFIG_MV_FLASH_CTRL is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +# CONFIG_FEROCEON_PROC is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +# CONFIG_MV_ETH_STATS_ERROR is not set +# CONFIG_MV_ETH_STATS_INFO is not set +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv78xx0_z0_defconfig b/arch/arm/configs/mv78xx0_z0_defconfig new file mode 100755 index 000000000..ba7cd6bbf --- /dev/null +++ b/arch/arm/configs/mv78xx0_z0_defconfig @@ -0,0 +1,1669 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Wed Apr 1 15:52:47 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_DDUO_FAMILY=y +# CONFIG_MV632X_FAMILY is not set +CONFIG_MV78100=y +# CONFIG_MV78200 is not set +# CONFIG_MV76100 is not set +CONFIG_MV78XX0_Z0=y +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +# CONFIG_MV_FLASH_CTRL is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +CONFIG_CPU_L2_DCACHE_WRITETHROUGH=y +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f5082_defconfig b/arch/arm/configs/mv88f5082_defconfig new file mode 100755 index 000000000..583c84c09 --- /dev/null +++ b/arch/arm/configs/mv88f5082_defconfig @@ -0,0 +1,1342 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Mon Oct 15 10:27:26 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +# CONFIG_MV88F5181 is not set +# CONFIG_MV88F5181L is not set +# CONFIG_MV88F5182 is not set +CONFIG_MV88F5082=y +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set +# CONFIG_USE_DSP is not set +CONFIG_MV_USE_IDMA_ENGINE=y +CONFIG_MV_IDMA_COPYUSER=y +CONFIG_MV_IDMA_COPYUSER_THRESHOLD=1260 +CONFIG_MV_IDMA_MEMZERO=y +CONFIG_MV_IDMA_MEMZERO_THRESHOLD=192 +CONFIG_MV_IDMA_MEMCOPY=y +CONFIG_MV_IDMA_MEMCOPY_THRESHOLD=128 +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +# CONFIG_MV_GATEWAY is not set +CONFIG_MV_ETH_NAME="egiga" +# CONFIG_ETH_MULTI_Q is not set +# CONFIG_EGIGA_STATIS is not set +CONFIG_ETH_0_MACADDR="000000000051" +# CONFIG_EGIGA_PROC is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_TOOL=y +# CONFIG_MV_CESA_TEST is not set +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +CONFIG_FPE_FASTFPE=y +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +# CONFIG_MD_RAID456 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=m +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=m +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_DUMMY_HCD=y +CONFIG_USB_DUMMY_HCD=m +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_ECB is not set +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +# CONFIG_OCF_OCF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f5181_defconfig b/arch/arm/configs/mv88f5181_defconfig new file mode 100755 index 000000000..e4921f0c1 --- /dev/null +++ b/arch/arm/configs/mv88f5181_defconfig @@ -0,0 +1,1310 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Mon Nov 12 17:31:39 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +CONFIG_MV88F5181=y +# CONFIG_MV88F5181L is not set +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PCI=y +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +# CONFIG_MV_NAND is not set +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set +# CONFIG_USE_DSP is not set +CONFIG_MV_USE_IDMA_ENGINE=y +CONFIG_MV_IDMA_COPYUSER=y +CONFIG_MV_IDMA_COPYUSER_THRESHOLD=1260 +CONFIG_MV_IDMA_MEMZERO=y +CONFIG_MV_IDMA_MEMZERO_THRESHOLD=192 +CONFIG_MV_IDMA_MEMCOPY=y +CONFIG_MV_IDMA_MEMCOPY_THRESHOLD=128 +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +# CONFIG_MV_GATEWAY is not set +CONFIG_MV_ETH_NAME="egiga" +# CONFIG_ETH_MULTI_Q is not set +# CONFIG_EGIGA_STATIS is not set +CONFIG_ETH_0_MACADDR="000000000051" +CONFIG_EGIGA_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +# CONFIG_MV_SATA_SUPPORT_ATAPI is not set +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_CRYPT is not set +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=m +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=m +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=m +CONFIG_SKY2=m +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=m +CONFIG_SK98LIN_NAPI=y +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +# CONFIG_HID is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_DUMMY_HCD=y +CONFIG_USB_DUMMY_HCD=m +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f5182_defconfig b/arch/arm/configs/mv88f5182_defconfig new file mode 100755 index 000000000..09ea29bd2 --- /dev/null +++ b/arch/arm/configs/mv88f5182_defconfig @@ -0,0 +1,1384 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Mon Nov 12 17:30:51 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON_ORION=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +# CONFIG_MV88F5181 is not set +# CONFIG_MV88F5181L is not set +CONFIG_MV88F5182=y +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PCI=y +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +# CONFIG_MV_NAND is not set +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set +# CONFIG_USE_DSP is not set +# CONFIG_MV_USE_IDMA_ENGINE is not set +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_RAID5_XOR_OFFLOAD=y +CONFIG_MV_XORMEMCOPY=y +CONFIG_MV_XOR_MEMCOPY_THRESHOLD=128 +CONFIG_MV_XORMEMZERO=y +CONFIG_MV_XOR_MEMZERO_THRESHOLD=192 +CONFIG_MV_USE_XOR_FOR_COPY_USER_BUFFERS=y +CONFIG_MV_XOR_COPYUSER_THRESHOLD=1260 +# CONFIG_ENABLE_XOR_INTERRUPTS is not set +CONFIG_USE_TWO_ENGINES=y +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +# CONFIG_MV_GATEWAY is not set +CONFIG_MV_ETH_NAME="egiga" +# CONFIG_ETH_MULTI_Q is not set +# CONFIG_EGIGA_STATIS is not set +CONFIG_ETH_0_MACADDR="000000000051" +CONFIG_EGIGA_PROC=y + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=m +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=m +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=m +CONFIG_SKY2=m +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=m +CONFIG_SK98LIN_NAPI=y +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +# CONFIG_HID is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_DUMMY_HCD=y +CONFIG_USB_DUMMY_HCD=m +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6082_defconfig b/arch/arm/configs/mv88f6082_defconfig new file mode 100755 index 000000000..703607419 --- /dev/null +++ b/arch/arm/configs/mv88f6082_defconfig @@ -0,0 +1,1019 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Sun Oct 28 19:37:18 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +# CONFIG_MV88F5181 is not set +# CONFIG_MV88F5181L is not set +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +CONFIG_MV88F6082=y +# CONFIG_MV88W8660 is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +# CONFIG_MV_INCLUDE_CESA is not set +# CONFIG_MV_INCLUDE_NAND is not set +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +# CONFIG_MV_INCLUDE_INTEG_MFLASH is not set +# CONFIG_MV_INCLUDE_SPI is not set +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set +# CONFIG_USE_DSP is not set +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +# CONFIG_MV_GATEWAY is not set +CONFIG_MV_ETH_NAME="egiga" +# CONFIG_ETH_MULTI_Q is not set +# CONFIG_EGIGA_STATIS is not set +CONFIG_ETH_0_MACADDR="000000000051" +# CONFIG_EGIGA_PROC is not set +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +# CONFIG_MV_SATA_SUPPORT_ATAPI is not set +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +CONFIG_FPE_FASTFPE=y +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_MV_THOR is not set +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=m +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6082_extra_defconfig b/arch/arm/configs/mv88f6082_extra_defconfig new file mode 100755 index 000000000..f07659e89 --- /dev/null +++ b/arch/arm/configs/mv88f6082_extra_defconfig @@ -0,0 +1,1303 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Mon Oct 15 13:12:48 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +# CONFIG_MV88F5181 is not set +# CONFIG_MV88F5181L is not set +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +CONFIG_MV88F6082=y +# CONFIG_MV88W8660 is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_INTEG_MFLASH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +# CONFIG_MV_INCLUDE_SFLASH_MTD is not set +CONFIG_MV_INCLUDE_MFLASH_MTD=y +CONFIG_MV_NAND=y +CONFIG_MV_NAND_BOOT=y +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set +# CONFIG_USE_DSP is not set +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +# CONFIG_MV_GATEWAY is not set +CONFIG_MV_ETH_NAME="egiga" +# CONFIG_ETH_MULTI_Q is not set +CONFIG_EGIGA_STATIS=y +CONFIG_ETH_0_MACADDR="000000000051" +CONFIG_EGIGA_PROC=y + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +# CONFIG_MV_SATA_SUPPORT_ATAPI is not set +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +CONFIG_FPE_FASTFPE=y +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +CONFIG_FTL=y +CONFIG_NFTL=y +# CONFIG_NFTL_RW is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_NAND_ECC_SMC=y +CONFIG_MTD_NAND_MUSEUM_IDS=y +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=y +CONFIG_SKY2=y +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_KARMA=y +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=m +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_WP512=y +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6183_defconfig b/arch/arm/configs/mv88f6183_defconfig new file mode 100755 index 000000000..ea8711333 --- /dev/null +++ b/arch/arm/configs/mv88f6183_defconfig @@ -0,0 +1,1628 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Tue Apr 21 17:50:16 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON_ORION=y +# CONFIG_ARCH_FEROCEON_KW is not set +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +# CONFIG_MV88F5181 is not set +# CONFIG_MV88F5181L is not set +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set +CONFIG_MV88F6183=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_GPP_MAX_PINS=32 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_SPI_BOOT=y +# CONFIG_MV_NAND is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +# CONFIG_USE_DSP is not set +# CONFIG_FEROCEON_PROC is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# +CONFIG_MV_USE_IDMA_ENGINE=y +CONFIG_MV_IDMA_COPYUSER=y +CONFIG_MV_IDMA_COPYUSER_THRESHOLD=1260 +CONFIG_MV_IDMA_MEMCOPY=y +CONFIG_MV_IDMA_MEMCOPY_THRESHOLD=128 + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=1 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +#CONFIG_MV_ETH_STATS_ERROR=y +# CONFIG_MV_ETH_STATS_INFO is not set +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_NFP_STATS=y +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + +# +# Marvell SDIOMMC driver +# +CONFIG_MMC_MVSDMMC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT=y +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_COPY_USER_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIUSB is not set +# CONFIG_BT_HCIBTUSB is not set +CONFIG_BT_HCIBTSDIO=m +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=m +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=m +# CONFIG_E1000_NAPI is not set +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=y +CONFIG_SKY2=m +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +CONFIG_WLAN_PRE80211=y +# CONFIG_STRIP is not set +CONFIG_WLAN_80211=y +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +CONFIG_TCG_TPM=m +# CONFIG_TCG_ATMEL is not set +CONFIG_DEVPORT=y +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_AT25=y +# CONFIG_SPI_SPIDEV is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_SEQ_DUMMY=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_SEQUENCER_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +CONFIG_SND_PCM_XRUN_DEBUG=y + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# +CONFIG_SND_MRVL_AUDIO=y + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_MRVL is not set +CONFIG_USB_GADGET_DUMMY_HCD=y +CONFIG_USB_DUMMY_HCD=m +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_SDHCI=m +# CONFIG_MMC_RICOH_MMC is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6281_be_gw_defconfig b/arch/arm/configs/mv88f6281_be_gw_defconfig new file mode 100755 index 000000000..10ac0fcc5 --- /dev/null +++ b/arch/arm/configs/mv88f6281_be_gw_defconfig @@ -0,0 +1,1739 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Wed Aug 5 10:56:38 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +CONFIG_ARCH_FEROCEON_KW=y +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV88F6281=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_INCLUDE_TS=y +CONFIG_MV_GPP_MAX_PINS=64 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_NAND=y +CONFIG_MV_NAND_BOOT=y +CONFIG_NAND_RS_ECC_SUPPORT=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_MV_SP_I_FTCH_DB_INV=y +# CONFIG_MV_SP_I_FTCH_LCK_L2_ICACHE is not set +# CONFIG_MV_SP_I_FTCH_NONE is not set +CONFIG_MV_INTERNAL_REGS_SELECTIVE_MAPPING=y +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +CONFIG_MV_REAL_TIME=y +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=4 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="00:00:00:00:00:81" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=4 +CONFIG_MV_ETH_TX_Q_NUM=2 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +CONFIG_MV_ETH_NFP_FDB_SUPPORT=y +# CONFIG_MV_NFP_STATS is not set +CONFIG_MV_GATEWAY=y + +# +# Gateway Interface Configuration +# +CONFIG_MV_GTW_CONFIG="(00:11:66:11:66:11,0)(00:22:77:22:77:22,1:2:3:4),mtu=1500" + +# +# Gateway Features +# +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_LINEAR_MODE=y +# CONFIG_MV_TDM_ULAW_MODE is not set +# CONFIG_MV_TDM_5CHANNELS is not set +# CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE is not set + +# +# Marvell SDIOMMC driver +# +CONFIG_MMC_MVSDMMC=m + +# +# TSU options +# +CONFIG_MV_TSU=y +# CONFIG_TSU_SERIAL_IF is not set +CONFIG_TSU_PARALLEL_IF=y +# CONFIG_TSU_CORE_CLK_71MHZ is not set +CONFIG_TSU_CORE_CLK_83MHZ=y +# CONFIG_TSU_CORE_CLK_91MHZ is not set +# CONFIG_TSU_CORE_CLK_100MHZ is not set +CONFIG_MV_TSU_PKT_SIZE=188 +CONFIG_MV_TSU_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_FEROCEON_KW=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +CONFIG_MV_SCATTERED_SPINUP=y +# CONFIG_MV_DISKS_POWERUP_TO_STANDBY is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +CONFIG_SK98LIN_NAPI=y +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_MV64XXX is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_MIXER_OSS is not set +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +CONFIG_SND_PCM_XRUN_DEBUG=y + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# +CONFIG_SND_MRVL_AUDIO=y + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_RICOH_MMC is not set +# CONFIG_MMC_TIFM_SD is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_LZO=y + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6281_defconfig b/arch/arm/configs/mv88f6281_defconfig new file mode 100755 index 000000000..ccf70bfef --- /dev/null +++ b/arch/arm/configs/mv88f6281_defconfig @@ -0,0 +1,1889 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31.8 +# Thu May 6 11:53:54 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +# CONFIG_CLASSIC_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +CONFIG_ARCH_FEROCEON_KW=y +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV88F6281=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_INCLUDE_TS=y +# CONFIG_MV_INCLUDE_LCD is not set +CONFIG_MV_GPP_MAX_PINS=64 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_NAND=y +CONFIG_MV_NAND_BOOT=y +# CONFIG_NAND_RS_ECC_SUPPORT is not set +# CONFIG_MV_NAND_8BYTE_READ is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_MV_SP_I_FTCH_DB_INV=y +# CONFIG_MV_SP_I_FTCH_LCK_L2_ICACHE is not set +# CONFIG_MV_SP_I_FTCH_NONE is not set +CONFIG_MV_INTERNAL_REGS_SELECTIVE_MAPPING=y +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=4 + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="00:00:00:00:00:81" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RXQ=1 +CONFIG_MV_ETH_TXQ=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_ETH_SKB_REUSE=y +CONFIG_MV_ETH_SKB_REUSE_DEF=0 +CONFIG_NET_SKB_HEADROOM=64 +CONFIG_NET_SKB_RECYCLE=y +CONFIG_NET_SKB_RECYCLE_DEF=0 +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_DEF=0 +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_2CHANNELS=y +# CONFIG_MV_TDM_32CHANNELS is not set +# CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE is not set +CONFIG_MV_PHONE_TEST_MODULE=m + +# +# TSU options +# +CONFIG_MV_TSU=y +# CONFIG_TSU_SERIAL_IF is not set +CONFIG_TSU_PARALLEL_IF=y +# CONFIG_TSU_CORE_CLK_71MHZ is not set +CONFIG_TSU_CORE_CLK_83MHZ=y +# CONFIG_TSU_CORE_CLK_91MHZ is not set +# CONFIG_TSU_CORE_CLK_100MHZ is not set +CONFIG_MV_TSU_PKT_SIZE=188 +CONFIG_MV_TSU_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +CONFIG_CPU_FEROCEON_OLD_ID=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set +CONFIG_ARM_ARMV5_L2_CACHE_COHERENCY_FIX=y + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set +# CONFIG_REORDER is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_FEROCEON_KW=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID6_PQ=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_KS8842 is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MV64XXX=m +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +# CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_MIXER_OSS is not set +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SND_ARM=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_MRVL_AUDIO=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_CS42L51=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +# CONFIG_DRAGONRISE_FF is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_SMARTJOYPLUS=y +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_HID_ZEROPLUS=y +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MMC_MVSDIO=y +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_XOR_BLOCKS=y +CONFIG_ASYNC_CORE=y +CONFIG_ASYNC_MEMCPY=y +CONFIG_ASYNC_XOR=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +# CONFIG_OCF_SAFE is not set +# CONFIG_OCF_IXP4XX is not set +# CONFIG_OCF_HIFN is not set +# CONFIG_OCF_HIFNHIPP is not set +# CONFIG_OCF_TALITOS is not set +# CONFIG_OCF_EP80579 is not set +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/mv88f6281_gw_defconfig b/arch/arm/configs/mv88f6281_gw_defconfig new file mode 100755 index 000000000..aa6a3f0da --- /dev/null +++ b/arch/arm/configs/mv88f6281_gw_defconfig @@ -0,0 +1,1938 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31.8 +# Thu May 6 12:22:31 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +CONFIG_ARCH_FEROCEON_KW=y +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV88F6281=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_INCLUDE_TS=y +# CONFIG_MV_INCLUDE_LCD is not set +CONFIG_MV_GPP_MAX_PINS=64 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_NAND=y +CONFIG_MV_NAND_BOOT=y +CONFIG_NAND_RS_ECC_SUPPORT=y +# CONFIG_MV_NAND_8BYTE_READ is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_MV_SP_I_FTCH_DB_INV=y +# CONFIG_MV_SP_I_FTCH_LCK_L2_ICACHE is not set +# CONFIG_MV_SP_I_FTCH_NONE is not set +# CONFIG_MV_INTERNAL_REGS_SELECTIVE_MAPPING is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +CONFIG_MV_REAL_TIME=y +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=4 + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="00:00:00:00:00:81" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RXQ=4 +CONFIG_MV_ETH_TXQ=2 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_ETH_SKB_REUSE=y +CONFIG_MV_ETH_SKB_REUSE_DEF=0 +CONFIG_NET_SKB_HEADROOM=64 +CONFIG_NET_SKB_RECYCLE=y +CONFIG_NET_SKB_RECYCLE_DEF=0 +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_DEF=0 +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +CONFIG_MV_ETH_NFP_FDB_SUPPORT=y +# CONFIG_MV_NFP_STATS is not set +CONFIG_MV_GATEWAY=y + +# +# Gateway Interface Configuration +# +CONFIG_MV_GTW_CONFIG="(00:11:66:11:66:11,0)(00:22:77:22:77:22,1:2:3:4),mtu=1500" + +# +# Gateway Features +# +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=m + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_2CHANNELS=y +# CONFIG_MV_TDM_32CHANNELS is not set +# CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE is not set +CONFIG_MV_PHONE_TEST_MODULE=m + +# +# TSU options +# +CONFIG_MV_TSU=y +# CONFIG_TSU_SERIAL_IF is not set +CONFIG_TSU_PARALLEL_IF=y +# CONFIG_TSU_CORE_CLK_71MHZ is not set +CONFIG_TSU_CORE_CLK_83MHZ=y +# CONFIG_TSU_CORE_CLK_91MHZ is not set +# CONFIG_TSU_CORE_CLK_100MHZ is not set +CONFIG_MV_TSU_PKT_SIZE=188 +CONFIG_MV_TSU_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set +CONFIG_ARM_ARMV5_L2_CACHE_COHERENCY_FIX=y + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set +# CONFIG_REORDER is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_FEROCEON_KW=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID6_PQ=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_KS8842 is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000E=y +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MV64XXX=m +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +# CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_MIXER_OSS is not set +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SND_ARM=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_MRVL_AUDIO=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_CS42L51=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MMC_MVSDIO=y +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_XOR_BLOCKS=y +CONFIG_ASYNC_CORE=y +CONFIG_ASYNC_MEMCPY=y +CONFIG_ASYNC_XOR=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +# CONFIG_OCF_SAFE is not set +# CONFIG_OCF_IXP4XX is not set +# CONFIG_OCF_HIFN is not set +# CONFIG_OCF_HIFNHIPP is not set +# CONFIG_OCF_TALITOS is not set +# CONFIG_OCF_EP80579 is not set +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/mv88f6281_gw_defconfig_new b/arch/arm/configs/mv88f6281_gw_defconfig_new new file mode 100755 index 000000000..d19f63c6c --- /dev/null +++ b/arch/arm/configs/mv88f6281_gw_defconfig_new @@ -0,0 +1,1931 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31.4 +# Mon Oct 19 16:10:18 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +CONFIG_ARCH_FEROCEON_KW=y +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV88F6281=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_INCLUDE_TS=y +CONFIG_MV_GPP_MAX_PINS=64 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_NAND=y +CONFIG_MV_NAND_BOOT=y +CONFIG_NAND_RS_ECC_SUPPORT=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_MV_SP_I_FTCH_DB_INV=y +# CONFIG_MV_SP_I_FTCH_LCK_L2_ICACHE is not set +# CONFIG_MV_SP_I_FTCH_NONE is not set +# CONFIG_MV_INTERNAL_REGS_SELECTIVE_MAPPING is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +CONFIG_MV_XOR_COPY_TO_USER=y +CONFIG_MV_XOR_COPY_TO_USER_THRESHOLD=1260 +CONFIG_MV_XOR_COPY_FROM_USER=y +CONFIG_MV_XOR_COPY_FROM_USER_THRESHOLD=1260 +CONFIG_MV_XOR_CHANNELS=4 + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="00:00:00:00:00:81" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=4 +CONFIG_MV_ETH_TX_Q_NUM=2 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +# CONFIG_MV_ETH_NFP is not set +CONFIG_MV_GATEWAY=y + +# +# Gateway Interface Configuration +# +CONFIG_MV_GTW_CONFIG="(00:11:66:11:66:11,0)(00:22:77:22:77:22,1:2:3:4),mtu=1500" + +# +# Gateway Features +# +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=m + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_LINEAR_MODE=y +# CONFIG_MV_TDM_ULAW_MODE is not set +# CONFIG_MV_TDM_5CHANNELS is not set +# CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE is not set + +# +# Marvell SDIOMMC driver +# +# CONFIG_MMC_MVSDMMC is not set + +# +# TSU options +# +CONFIG_MV_TSU=y +# CONFIG_TSU_SERIAL_IF is not set +CONFIG_TSU_PARALLEL_IF=y +# CONFIG_TSU_CORE_CLK_71MHZ is not set +CONFIG_TSU_CORE_CLK_83MHZ=y +# CONFIG_TSU_CORE_CLK_91MHZ is not set +# CONFIG_TSU_CORE_CLK_100MHZ is not set +CONFIG_MV_TSU_PKT_SIZE=188 +CONFIG_MV_TSU_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +CONFIG_CPU_FEROCEON_OLD_ID=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set +CONFIG_REORDER=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_FEROCEON_KW=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID6_PQ=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_KS8842 is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +# CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_MIXER_OSS is not set +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SND_ARM=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_MRVL_AUDIO=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_CS42L51=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MMC_MVSDIO=y +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_XOR_BLOCKS=y +CONFIG_ASYNC_CORE=y +CONFIG_ASYNC_MEMCPY=y +CONFIG_ASYNC_XOR=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +# CONFIG_OCF_SAFE is not set +# CONFIG_OCF_IXP4XX is not set +# CONFIG_OCF_HIFN is not set +# CONFIG_OCF_HIFNHIPP is not set +# CONFIG_OCF_TALITOS is not set +# CONFIG_OCF_EP80579 is not set +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/mv88f6281_nfpsec_kw1_defconfig b/arch/arm/configs/mv88f6281_nfpsec_kw1_defconfig new file mode 100755 index 000000000..0c83cfc3e --- /dev/null +++ b/arch/arm/configs/mv88f6281_nfpsec_kw1_defconfig @@ -0,0 +1,1586 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Thu Feb 26 15:34:59 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +CONFIG_ARCH_FEROCEON_KW=y +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV88F6281=y +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_INCLUDE_TS=y +CONFIG_MV_GPP_MAX_PINS=64 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_NAND=y +CONFIG_MV_NAND_BOOT=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_RAID5_XOR_OFFLOAD=y +CONFIG_MV_XORMEMCOPY=y +CONFIG_MV_XOR_MEMCOPY_THRESHOLD=128 +CONFIG_MV_XORMEMZERO=y +CONFIG_MV_XOR_MEMZERO_THRESHOLD=192 +# CONFIG_MV_USE_XOR_FOR_COPY_USER_BUFFERS is not set +# CONFIG_USE_TWO_ENGINES is not set +CONFIG_USE_FOUR_ENGINES=y + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="00:00:00:00:00:81" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_SEC=y +CONFIG_MV_CESA_CHAIN_MODE_SUPPORT=y +# CONFIG_MV_NFP_SEC_5TUPLE_KEY_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +CONFIG_MV_GATEWAY=y + +# +# Gateway Interface Configuration +# +CONFIG_MV_GTW_CONFIG="(00:11:66:11:66:11,0)(00:22:77:22:77:22,1:2:3:4),mtu=1500" + +# +# Gateway Features +# +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y + +# +# cesa options +# +CONFIG_MV_CESA=y +# CONFIG_MV_CESA_OCF is not set +CONFIG_MV_CESA_TOOL=y +# CONFIG_MV_CESA_TEST is not set + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_LINEAR_MODE=y +# CONFIG_MV_TDM_ULAW_MODE is not set + +# +# Marvell SDIOMMC driver +# +CONFIG_MMC_MVSDMMC=m + +# +# TSU options +# +CONFIG_MV_TSU=y +# CONFIG_TSU_SERIAL_IF is not set +CONFIG_TSU_PARALLEL_IF=y +# CONFIG_TSU_CORE_CLK_71MHZ is not set +CONFIG_TSU_CORE_CLK_83MHZ=y +# CONFIG_TSU_CORE_CLK_91MHZ is not set +# CONFIG_TSU_CORE_CLK_100MHZ is not set +CONFIG_MV_TSU_PKT_SIZE=188 +CONFIG_MV_TSU_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +CONFIG_SK98LIN_NAPI=y +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +CONFIG_I2C_MV64XXX=m + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_MIXER_OSS is not set +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +CONFIG_SND_PCM_XRUN_DEBUG=y + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# +CONFIG_SND_MRVL_AUDIO=y + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_RICOH_MMC is not set +# CONFIG_MMC_TIFM_SD is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6281_nfpsec_kw2_defconfig b/arch/arm/configs/mv88f6281_nfpsec_kw2_defconfig new file mode 100755 index 000000000..b5255a6fa --- /dev/null +++ b/arch/arm/configs/mv88f6281_nfpsec_kw2_defconfig @@ -0,0 +1,1586 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Thu Feb 26 17:33:58 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +CONFIG_ARCH_FEROCEON_KW=y +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV88F6281=y +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_INCLUDE_TS=y +CONFIG_MV_GPP_MAX_PINS=64 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_NAND=y +CONFIG_MV_NAND_BOOT=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_RAID5_XOR_OFFLOAD=y +CONFIG_MV_XORMEMCOPY=y +CONFIG_MV_XOR_MEMCOPY_THRESHOLD=128 +CONFIG_MV_XORMEMZERO=y +CONFIG_MV_XOR_MEMZERO_THRESHOLD=192 +# CONFIG_MV_USE_XOR_FOR_COPY_USER_BUFFERS is not set +# CONFIG_USE_TWO_ENGINES is not set +CONFIG_USE_FOUR_ENGINES=y + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="00:00:00:00:00:81" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=532 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_SEC=y +CONFIG_MV_CESA_CHAIN_MODE_SUPPORT=y +# CONFIG_MV_NFP_SEC_5TUPLE_KEY_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +CONFIG_MV_GATEWAY=y + +# +# Gateway Interface Configuration +# +CONFIG_MV_GTW_CONFIG="(00:11:66:11:66:11,0)(00:22:77:22:77:22,1:2:3:4),mtu=1500" + +# +# Gateway Features +# +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y + +# +# cesa options +# +CONFIG_MV_CESA=y +# CONFIG_MV_CESA_OCF is not set +CONFIG_MV_CESA_TOOL=y +# CONFIG_MV_CESA_TEST is not set + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_LINEAR_MODE=y +# CONFIG_MV_TDM_ULAW_MODE is not set + +# +# Marvell SDIOMMC driver +# +CONFIG_MMC_MVSDMMC=m + +# +# TSU options +# +CONFIG_MV_TSU=y +# CONFIG_TSU_SERIAL_IF is not set +CONFIG_TSU_PARALLEL_IF=y +# CONFIG_TSU_CORE_CLK_71MHZ is not set +CONFIG_TSU_CORE_CLK_83MHZ=y +# CONFIG_TSU_CORE_CLK_91MHZ is not set +# CONFIG_TSU_CORE_CLK_100MHZ is not set +CONFIG_MV_TSU_PKT_SIZE=188 +CONFIG_MV_TSU_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +CONFIG_SK98LIN_NAPI=y +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +CONFIG_I2C_MV64XXX=m + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_MIXER_OSS is not set +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +CONFIG_SND_PCM_XRUN_DEBUG=y + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# +CONFIG_SND_MRVL_AUDIO=y + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_RICOH_MMC is not set +# CONFIG_MMC_TIFM_SD is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6321_defconfig b/arch/arm/configs/mv88f6321_defconfig new file mode 100755 index 000000000..e81ab89af --- /dev/null +++ b/arch/arm/configs/mv88f6321_defconfig @@ -0,0 +1,1674 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Thu May 14 14:42:29 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_MV632X=y +# CONFIG_DDUO_FAMILY is not set +CONFIG_MV632X_FAMILY=y +CONFIG_MV6321=y +# CONFIG_MV6322 is not set +# CONFIG_MV6323 is not set +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_USB_PHY_OVERRIDE_SETTINGS is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +# CONFIG_MV_INCLUDE_INTEG_SATA is not set +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_LINEAR_MODE=y +# CONFIG_MV_TDM_ULAW_MODE is not set +# CONFIG_MV_TDM_5CHANNELS is not set + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6322_defconfig b/arch/arm/configs/mv88f6322_defconfig new file mode 100755 index 000000000..3eba2463f --- /dev/null +++ b/arch/arm/configs/mv88f6322_defconfig @@ -0,0 +1,1674 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Thu May 14 14:42:29 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_MV632X=y +# CONFIG_DDUO_FAMILY is not set +CONFIG_MV632X_FAMILY=y +# CONFIG_MV6321 is not set +CONFIG_MV6322=y +# CONFIG_MV6323 is not set +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_USB_PHY_OVERRIDE_SETTINGS is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +# CONFIG_MV_INCLUDE_INTEG_SATA is not set +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_LINEAR_MODE=y +# CONFIG_MV_TDM_ULAW_MODE is not set +# CONFIG_MV_TDM_5CHANNELS is not set + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv88f6323_defconfig b/arch/arm/configs/mv88f6323_defconfig new file mode 100755 index 000000000..62f26eec7 --- /dev/null +++ b/arch/arm/configs/mv88f6323_defconfig @@ -0,0 +1,1673 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Thu May 14 14:42:29 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +# CONFIG_ARCH_FEROCEON_KW is not set +CONFIG_ARCH_FEROCEON_MV78XX0=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV78XX0=y +CONFIG_MV632X=y +# CONFIG_DDUO_FAMILY is not set +CONFIG_MV632X_FAMILY=y +# CONFIG_MV6321 is not set +# CONFIG_MV6322 is not set +CONFIG_MV6323=y +# CONFIG_MV78XX0_SUPPORT_2GB_RAM is not set +# CONFIG_USB_PHY_OVERRIDE_SETTINGS is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +# CONFIG_MV_SPI_BOOT is not set +CONFIG_MV_NAND=y +# CONFIG_MV_NAND_BOOT is not set +# CONFIG_NAND_RS_ECC_SUPPORT is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_L2_CACHE_ENABLE=y +# CONFIG_CPU_L2_DCACHE_WRITETHROUGH is not set +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_XOR_NET_DMA=y +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +# CONFIG_MV_XOR_COPY_TO_USER is not set +# CONFIG_MV_XOR_COPY_FROM_USER is not set +CONFIG_MV_XOR_CHANNELS=2 + +# +# DMA Engine support +# +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +CONFIG_NET_DMA=y + +# +# DMA Devices +# +# CONFIG_INTEL_IOATDMA is not set + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=3 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="64:00:00:00:00:01" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="64:00:00:00:00:02" +CONFIG_MV_ETH_2_MTU=1500 +CONFIG_MV_ETH_2_MACADDR="64:00:00:00:00:03" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_ETH_STATS_INFO=y +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +# CONFIG_MV_ETH_NFP_FDB_SUPPORT is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_LINEAR_MODE=y +# CONFIG_MV_TDM_ULAW_MODE is not set +# CONFIG_MV_TDM_5CHANNELS is not set + + +# +# Sata options +# +CONFIG_SCSI_MVSATA=y +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_COPY_USER_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0 root=/dev/nfs rw nfsroot=10.4.50.31:/mnt/armFS mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +# CONFIG_VFP_FASTVFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=y +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +CONFIG_NF_CONNTRACK_PPTP=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_MATROX=y +CONFIG_FB_MATROX_MILLENIUM=y +# CONFIG_FB_MATROX_MYSTIQUE is not set +CONFIG_FB_MATROX_G=y +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX_MULTIHEAD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# ALSA ARM devices +# + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=y +CONFIG_USB_MICROTEK=y +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=y +CONFIG_USB_EMI26=y +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +CONFIG_OCF_DM_CRYPT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv_kw_be_gtw_defconfig b/arch/arm/configs/mv_kw_be_gtw_defconfig new file mode 100755 index 000000000..5366b884b --- /dev/null +++ b/arch/arm/configs/mv_kw_be_gtw_defconfig @@ -0,0 +1,214 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_KIRKWOOD=y +CONFIG_MACH_DB88F6281_BP=y +CONFIG_MACH_XCAT98DX=y +CONFIG_MACH_RD88F6192_NAS=y +CONFIG_MACH_RD88F6281=y +CONFIG_MACH_RD88F6282_A=y +CONFIG_MACH_MV88F6281GTW_GE=y +CONFIG_MACH_SHEEVAPLUG=y +CONFIG_MACH_ESATA_SHEEVAPLUG=y +CONFIG_MACH_GURUPLUG=y +CONFIG_MACH_TS219=y +CONFIG_MACH_TS41X=y +CONFIG_MACH_DOCKSTAR=y +CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_OPENRD_ULTIMATE=y +CONFIG_MACH_NETSPACE_V2=y +CONFIG_MACH_INETSPACE_V2=y +CONFIG_MACH_NETSPACE_MAX_V2=y +CONFIG_MACH_D2NET_V2=y +CONFIG_MACH_NET2BIG_V2=y +CONFIG_MACH_NET5BIG_V2=y +CONFIG_MACH_T5325=y +# CONFIG_MV_INCLUDE_TDM is not set +CONFIG_MV_INCLUDE_TS=y +CONFIG_MV_REAL_TIME=y +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_LINUX_COUNTERS_DISABLE=y +# CONFIG_NET_SKB_RECYCLE is not set +# CONFIG_MV_ETH_NFP is not set +CONFIG_MV_GATEWAY=y +CONFIG_MV_CESA_TOOL=y +CONFIG_MV_TSU=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NET_PKTGEN=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_MV_THOR=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID456=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_SKGE=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_MARVELL_PHY=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_PHONE=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_ORION=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ORION_WATCHDOG=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_HID_DRAGONRISE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_ZEROPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_STAGING=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_DEBUG=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/mv_kw_defconfig b/arch/arm/configs/mv_kw_defconfig new file mode 100755 index 000000000..0bf813964 --- /dev/null +++ b/arch/arm/configs/mv_kw_defconfig @@ -0,0 +1,219 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_KIRKWOOD=y +CONFIG_MACH_DB88F6281_BP=y +CONFIG_MACH_XCAT98DX=y +CONFIG_MACH_RD88F6192_NAS=y +CONFIG_MACH_RD88F6281=y +CONFIG_MACH_RD88F6282_A=y +CONFIG_MACH_MV88F6281GTW_GE=y +CONFIG_MACH_SHEEVAPLUG=y +CONFIG_MACH_ESATA_SHEEVAPLUG=y +CONFIG_MACH_GURUPLUG=y +CONFIG_MACH_TS219=y +CONFIG_MACH_TS41X=y +CONFIG_MACH_DOCKSTAR=y +CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_OPENRD_ULTIMATE=y +CONFIG_MACH_NETSPACE_V2=y +CONFIG_MACH_INETSPACE_V2=y +CONFIG_MACH_NETSPACE_MAX_V2=y +CONFIG_MACH_D2NET_V2=y +CONFIG_MACH_NET2BIG_V2=y +CONFIG_MACH_NET5BIG_V2=y +CONFIG_MACH_T5325=y +CONFIG_MV_INCLUDE_TS=y +CONFIG_KIRKWOOD_PROC=y +CONFIG_MV_REAL_TIME=y +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_LINUX_COUNTERS_DISABLE=y +CONFIG_NET_SKB_HEADROOM=96 +# CONFIG_NET_SKB_RECYCLE is not set +# CONFIG_MV_ETH_NFP is not set +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_NET_PKTGEN=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_MV_THOR=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID456=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_SKGE=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_MARVELL_PHY=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_PHONE=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_ORION=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ORION_WATCHDOG=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_DB88F6281_BP=y +CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_HID_DRAGONRISE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_ZEROPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_SPLICE_NET_DMA_SUPPORT=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_STAGING=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_DEBUG=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/mv_kw_gtw_defconfig b/arch/arm/configs/mv_kw_gtw_defconfig new file mode 100755 index 000000000..bed88e933 --- /dev/null +++ b/arch/arm/configs/mv_kw_gtw_defconfig @@ -0,0 +1,212 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_KIRKWOOD=y +CONFIG_MACH_DB88F6281_BP=y +CONFIG_MACH_XCAT98DX=y +CONFIG_MACH_RD88F6192_NAS=y +CONFIG_MACH_RD88F6281=y +CONFIG_MACH_RD88F6282_A=y +CONFIG_MACH_MV88F6281GTW_GE=y +CONFIG_MACH_SHEEVAPLUG=y +CONFIG_MACH_ESATA_SHEEVAPLUG=y +CONFIG_MACH_GURUPLUG=y +CONFIG_MACH_TS219=y +CONFIG_MACH_TS41X=y +CONFIG_MACH_DOCKSTAR=y +CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_OPENRD_ULTIMATE=y +CONFIG_MACH_NETSPACE_V2=y +CONFIG_MACH_INETSPACE_V2=y +CONFIG_MACH_NETSPACE_MAX_V2=y +CONFIG_MACH_D2NET_V2=y +CONFIG_MACH_NET2BIG_V2=y +CONFIG_MACH_NET5BIG_V2=y +CONFIG_MACH_T5325=y +CONFIG_MV_INCLUDE_TS=y +CONFIG_MV_REAL_TIME=y +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_LINUX_COUNTERS_DISABLE=y +# CONFIG_NET_SKB_RECYCLE is not set +# CONFIG_MV_ETH_NFP is not set +CONFIG_MV_GATEWAY=y +CONFIG_MV_CESA_TOOL=y +CONFIG_MV_TSU=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NET_PKTGEN=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_MV_THOR=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID456=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_SKGE=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_MARVELL_PHY=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_PHONE=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_ORION=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ORION_WATCHDOG=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_HID_DRAGONRISE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_ZEROPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_STAGING=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_DEBUG=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/mv_kw_nas_defconfig b/arch/arm/configs/mv_kw_nas_defconfig new file mode 100755 index 000000000..67953afb0 --- /dev/null +++ b/arch/arm/configs/mv_kw_nas_defconfig @@ -0,0 +1,216 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_KIRKWOOD=y +CONFIG_MACH_DB88F6281_BP=y +CONFIG_MACH_XCAT98DX=y +CONFIG_MACH_RD88F6192_NAS=y +CONFIG_MACH_RD88F6281=y +CONFIG_MACH_RD88F6282_A=y +CONFIG_MACH_MV88F6281GTW_GE=y +CONFIG_MACH_SHEEVAPLUG=y +CONFIG_MACH_ESATA_SHEEVAPLUG=y +CONFIG_MACH_GURUPLUG=y +CONFIG_MACH_TS219=y +CONFIG_MACH_TS41X=y +CONFIG_MACH_DOCKSTAR=y +CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_OPENRD_ULTIMATE=y +CONFIG_MACH_NETSPACE_V2=y +CONFIG_MACH_INETSPACE_V2=y +CONFIG_MACH_NETSPACE_MAX_V2=y +CONFIG_MACH_D2NET_V2=y +CONFIG_MACH_NET2BIG_V2=y +CONFIG_MACH_NET5BIG_V2=y +CONFIG_MACH_T5325=y +CONFIG_MV_INCLUDE_TS=y +CONFIG_MV_REAL_TIME=y +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_LINUX_COUNTERS_DISABLE=y +CONFIG_NET_SKB_HEADROOM=96 +# CONFIG_NET_SKB_RECYCLE is not set +# CONFIG_MV_ETH_NFP is not set +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NET_PKTGEN=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_MV_STAGGERED_SPINUP=y +CONFIG_SCSI_MV_THOR=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID456=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_SKGE=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_MARVELL_PHY=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_PHONE=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_ORION=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ORION_WATCHDOG=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_HID_DRAGONRISE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_ZEROPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_SPLICE_NET_DMA_SUPPORT=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_STAGING=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_DEBUG=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/mv_kw_nfpsec_demo_defconfig b/arch/arm/configs/mv_kw_nfpsec_demo_defconfig new file mode 100755 index 000000000..bdf6adefe --- /dev/null +++ b/arch/arm/configs/mv_kw_nfpsec_demo_defconfig @@ -0,0 +1,1994 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31.8 +# Fri Nov 12 13:17:35 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +# CONFIG_CLASSIC_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_FEROCEON_ORION is not set +CONFIG_ARCH_FEROCEON_KW=y +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +CONFIG_MV88F6281=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_XOR=y +CONFIG_MV_INCLUDE_CESA=y +CONFIG_MV_INCLUDE_NAND=y +CONFIG_MV_INCLUDE_INTEG_SATA=y +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_INCLUDE_TS=y +# CONFIG_MV_INCLUDE_LCD is not set +CONFIG_MV_GPP_MAX_PINS=64 +CONFIG_MV_DCACHE_SIZE=0x4000 +CONFIG_MV_ICACHE_SIZE=0x4000 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_NAND=y +CONFIG_MV_NAND_BOOT=y +# CONFIG_NAND_RS_ECC_SUPPORT is not set +# CONFIG_MV_NAND_8BYTE_READ is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_USE_DSP=y +CONFIG_MV_SP_I_FTCH_DB_INV=y +# CONFIG_MV_SP_I_FTCH_LCK_L2_ICACHE is not set +# CONFIG_MV_SP_I_FTCH_NONE is not set +CONFIG_MV_INTERNAL_REGS_SELECTIVE_MAPPING=y +CONFIG_FEROCEON_PROC=y +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +CONFIG_MV_CPU_PERF_CNTRS=y +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# +CONFIG_MV_USE_XOR_ENGINE=y +CONFIG_MV_XOR_MEMXOR=y +CONFIG_MV_XOR_MEMXOR_THRESHOLD=4096 +CONFIG_MV_XOR_CHANNELS=4 + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" +CONFIG_MV_ETH_1_MTU=1500 +CONFIG_MV_ETH_1_MACADDR="00:00:00:00:00:81" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RXQ=1 +CONFIG_MV_ETH_TXQ=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +CONFIG_MV_ETH_STATS_ERROR=y +# CONFIG_MV_ETH_STATS_INFO is not set +# CONFIG_MV_ETH_STATS_DEBUG is not set +CONFIG_MV_LINUX_COUNTERS_DISABLE=y + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_ETH_SKB_REUSE=y +CONFIG_MV_ETH_SKB_REUSE_DEF=0 +CONFIG_NET_SKB_HEADROOM=64 +CONFIG_NET_SKB_RECYCLE=y +CONFIG_NET_SKB_RECYCLE_DEF=0 +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_DEF=0 +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_SEC=y +# CONFIG_MV_NFP_SEC_5TUPLE_KEY_SUPPORT is not set +# CONFIG_MV_ETH_NFP_SEC_HUB is not set +# CONFIG_MV_NFP_STATS is not set +# CONFIG_MV_GATEWAY is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +# CONFIG_MV_CESA_OCF is not set +CONFIG_MV_CESA_TOOL=y +CONFIG_MV_CESA_CHAIN_MODE_SUPPORT=y +# CONFIG_MV_CESA_TEST is not set + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_2CHANNELS=y +# CONFIG_MV_TDM_32CHANNELS is not set +# CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE is not set +CONFIG_MV_PHONE_TEST_MODULE=m + +# +# TSU options +# +CONFIG_MV_TSU=y +# CONFIG_TSU_SERIAL_IF is not set +CONFIG_TSU_PARALLEL_IF=y +# CONFIG_TSU_CORE_CLK_71MHZ is not set +CONFIG_TSU_CORE_CLK_83MHZ=y +# CONFIG_TSU_CORE_CLK_91MHZ is not set +# CONFIG_TSU_CORE_CLK_100MHZ is not set +CONFIG_MV_TSU_PKT_SIZE=188 +CONFIG_MV_TSU_PROC=y +CONFIG_SCSI_MVSATA=y + +# +# Sata options +# +CONFIG_MV_SATA_SUPPORT_ATAPI=y +CONFIG_MV_SATA_ENABLE_1MB_IOS=y +CONFIG_SATA_NO_DEBUG=y +# CONFIG_SATA_DEBUG_ON_ERROR is not set +# CONFIG_SATA_FULL_DEBUG is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +CONFIG_CPU_FEROCEON_OLD_ID=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set +CONFIG_ARM_ARMV5_L2_CACHE_COHERENCY_FIX=y +CONFIG_FORCE_MAX_ZONEORDER=19 + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set +CONFIG_REORDER=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +CONFIG_UACCESS_WITH_MEMCPY=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_FEROCEON_KW=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_MV_THOR=m +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +# CONFIG_MD_RAID10 is not set +CONFIG_MD_RAID456=y +CONFIG_MD_RAID6_PQ=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_KS8842 is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000E=y +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_SK98LIN=y +# CONFIG_SK98LIN_NAPI is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_XTKBD=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +# CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_DDC=y +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_FB_DOVE=y +CONFIG_FB_DOVE_CONSISTENT_DMA_SIZE=46 +CONFIG_FB_DOVE_CLCD=y +# CONFIG_FB_DOVE_CLCD1 is not set +CONFIG_FB_DOVE_CLCD_EDID=y +CONFIG_DOVEFB_FORCE_EDID_RES=y +# CONFIG_FB_DOVE_DCON is not set + +# +# DOVE LCD clock source +# +# CONFIG_FB_DOVE_CLCD_USE_PLL_CLK is not set +CONFIG_FB_DOVE_CLCD_SCLK_VALUE=266 +# CONFIG_FB_DOVE_OPTIMIZED_FB_MEM_ALLOC is not set +CONFIG_FB_DOVE_CLCD_DEFAULT_OPTION="lcd0:1280x720-16@60" +# CONFIG_FB_DOVE_CLCD_FLAREON_GV is not set +# CONFIG_FB_MUSTANG_CLCD is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +CONFIG_ADI9889=y +CONFIG_THS8200=y + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_MIXER_OSS is not set +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SND_ARM=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_MRVL_AUDIO=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_CS42L51=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +# CONFIG_DRAGONRISE_FF is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_SMARTJOYPLUS=y +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_HID_ZEROPLUS=y +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MMC_MVSDIO=y +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4DEV_COMPAT is not set +# CONFIG_EXT4_FS_XATTR is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_XOR_BLOCKS=y +CONFIG_ASYNC_CORE=y +CONFIG_ASYNC_MEMCPY=y +CONFIG_ASYNC_XOR=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +# CONFIG_OCF_SAFE is not set +# CONFIG_OCF_IXP4XX is not set +# CONFIG_OCF_HIFN is not set +# CONFIG_OCF_HIFNHIPP is not set +# CONFIG_OCF_TALITOS is not set +# CONFIG_OCF_EP80579 is not set +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/mv_kw_switch_kernel_drv_defconfig b/arch/arm/configs/mv_kw_switch_kernel_drv_defconfig new file mode 100755 index 000000000..3b10934df --- /dev/null +++ b/arch/arm/configs/mv_kw_switch_kernel_drv_defconfig @@ -0,0 +1,207 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_KIRKWOOD=y +CONFIG_MACH_DB88F6281_BP=y +CONFIG_MACH_XCAT98DX=y +CONFIG_MACH_RD88F6192_NAS=y +CONFIG_MACH_RD88F6281=y +CONFIG_MACH_RD88F6282_A=y +CONFIG_MACH_MV88F6281GTW_GE=y +CONFIG_MACH_SHEEVAPLUG=y +CONFIG_MACH_ESATA_SHEEVAPLUG=y +CONFIG_MACH_GURUPLUG=y +CONFIG_MACH_TS219=y +CONFIG_MACH_TS41X=y +CONFIG_MACH_DOCKSTAR=y +CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_OPENRD_ULTIMATE=y +CONFIG_MACH_NETSPACE_V2=y +CONFIG_MACH_INETSPACE_V2=y +CONFIG_MACH_NETSPACE_MAX_V2=y +CONFIG_MACH_D2NET_V2=y +CONFIG_MACH_NET2BIG_V2=y +CONFIG_MACH_NET5BIG_V2=y +CONFIG_MACH_T5325=y +# CONFIG_MV_INCLUDE_GIG_ETH is not set +CONFIG_MV_INCLUDE_TS=y +# CONFIG_MV_INCLUDE_SWITCH is not set +CONFIG_MV_REAL_TIME=y +CONFIG_MV_CESA_TOOL=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MV88E6171R=y +CONFIG_NET_PKTGEN=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_MV_THOR=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID456=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_MV643XX_ETH=y +CONFIG_SKGE=y +CONFIG_SKY2=y +CONFIG_MARVELL_PHY=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_PHONE=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_GPIO_SYSFS=y +CONFIG_SENSORS_ORION=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ORION_WATCHDOG=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_HID_DRAGONRISE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_ZEROPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_STAGING=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_DEBUG=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/mv_xcat_defconfig b/arch/arm/configs/mv_xcat_defconfig new file mode 100755 index 000000000..b3569aed8 --- /dev/null +++ b/arch/arm/configs/mv_xcat_defconfig @@ -0,0 +1,211 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_KIRKWOOD=y +CONFIG_MACH_DB88F6281_BP=y +CONFIG_MACH_XCAT98DX=y +CONFIG_MACH_RD88F6192_NAS=y +CONFIG_MACH_RD88F6281=y +CONFIG_MACH_RD88F6282_A=y +CONFIG_MACH_MV88F6281GTW_GE=y +CONFIG_MACH_SHEEVAPLUG=y +CONFIG_MACH_ESATA_SHEEVAPLUG=y +CONFIG_MACH_GURUPLUG=y +CONFIG_MACH_TS219=y +CONFIG_MACH_TS41X=y +CONFIG_MACH_DOCKSTAR=y +CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_OPENRD_ULTIMATE=y +CONFIG_MACH_NETSPACE_V2=y +CONFIG_MACH_INETSPACE_V2=y +CONFIG_MACH_NETSPACE_MAX_V2=y +CONFIG_MACH_D2NET_V2=y +CONFIG_MACH_NET2BIG_V2=y +CONFIG_MACH_NET5BIG_V2=y +CONFIG_MACH_T5325=y +# CONFIG_MV_INCLUDE_TDM is not set +CONFIG_KIRKWOOD_PROC=y +CONFIG_MV_REAL_TIME=y +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=2 +CONFIG_MV_ETH_STATS_ERROR=y +CONFIG_MV_LINUX_COUNTERS_DISABLE=y +CONFIG_NET_SKB_HEADROOM=96 +# CONFIG_NET_SKB_RECYCLE is not set +# CONFIG_MV_ETH_NFP is not set +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_IDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_NET_PKTGEN=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_MV_THOR=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MV=y +CONFIG_NETDEVICES=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_SKGE=y +CONFIG_SKY2=y +CONFIG_PHYLIB=y +CONFIG_MARVELL_PHY=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_PHONE=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y +CONFIG_SPI=y +CONFIG_SPI_ORION=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ORION_WATCHDOG=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_HID_DRAGONRISE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_ZEROPLUS=y +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_TEST=m +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_NET_DMA=y +CONFIG_SPLICE_NET_DMA_SUPPORT=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_STAGING=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_XFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_DEBUG=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_OCF_OCF=y +CONFIG_OCF_CRYPTODEV=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/rd2_88f5181L_defconfig b/arch/arm/configs/rd2_88f5181L_defconfig new file mode 100755 index 000000000..483cb12e5 --- /dev/null +++ b/arch/arm/configs/rd2_88f5181L_defconfig @@ -0,0 +1,1130 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Mon Oct 29 10:34:05 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +# CONFIG_MV88F5181 is not set +CONFIG_MV88F5181L=y +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PCI=y +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_CESA=y +# CONFIG_MV_INCLUDE_NAND is not set +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set +# CONFIG_USE_DSP is not set +CONFIG_MV_USE_IDMA_ENGINE=y +CONFIG_MV_IDMA_COPYUSER=y +CONFIG_MV_IDMA_COPYUSER_THRESHOLD=1260 +# CONFIG_MV_IDMA_MEMZERO is not set +# CONFIG_MV_IDMA_MEMCOPY is not set +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# SoC Networking support +# +# CONFIG_MV_ETHERNET is not set +CONFIG_MV_GATEWAY=y +CONFIG_ETH_MULTI_Q=y +CONFIG_MV_GTW_QOS=y +CONFIG_MV_GTW_QOS_NET_IF="eth0" +CONFIG_MV_GTW_QOS_VOIP=y +CONFIG_MV_GTW_QOS_VOIP_TOS="0xA0" +CONFIG_MV_GTW_QOS_ROUTING=y +CONFIG_MV_GTW_QOS_ROUTING_TOS="0x11;0x22" +CONFIG_EGIGA_STATIS=y +CONFIG_MV_NET_CONFIG="(eth0,00:11:66:11:66:11,0)(eth1,00:22:77:22:77:22,1:2:3:4)" +CONFIG_ETH_FLOW_CONTROL=y +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y +# CONFIG_HAVE_ARCH_DEV_ALLOC_SKB is not set +# CONFIG_MV_GTW_PROC is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_TOOL=y +# CONFIG_MV_CESA_TEST is not set +# CONFIG_SCSI_MVSATA is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +CONFIG_FPE_FASTFPE=y +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_MV_THOR is not set +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=m +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/rd2_88f5181_defconfig b/arch/arm/configs/rd2_88f5181_defconfig new file mode 100755 index 000000000..35a4ae279 --- /dev/null +++ b/arch/arm/configs/rd2_88f5181_defconfig @@ -0,0 +1,1122 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Mon Oct 29 10:42:28 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON=y +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +CONFIG_MV88F5181=y +# CONFIG_MV88F5181L is not set +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PCI=y +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +# CONFIG_MV_INCLUDE_NAND is not set +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +# CONFIG_ARCH_SUPPORTS_BIG_ENDIAN is not set +# CONFIG_USE_DSP is not set +CONFIG_MV_USE_IDMA_ENGINE=y +CONFIG_MV_IDMA_COPYUSER=y +CONFIG_MV_IDMA_COPYUSER_THRESHOLD=1260 +# CONFIG_MV_IDMA_MEMZERO is not set +# CONFIG_MV_IDMA_MEMCOPY is not set +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# SoC Networking support +# +# CONFIG_MV_ETHERNET is not set +CONFIG_MV_GATEWAY=y +CONFIG_ETH_MULTI_Q=y +CONFIG_MV_GTW_QOS=y +CONFIG_MV_GTW_QOS_NET_IF="eth0" +CONFIG_MV_GTW_QOS_VOIP=y +CONFIG_MV_GTW_QOS_VOIP_TOS="0xA0" +CONFIG_MV_GTW_QOS_ROUTING=y +CONFIG_MV_GTW_QOS_ROUTING_TOS="0x11;0x22" +CONFIG_EGIGA_STATIS=y +CONFIG_MV_NET_CONFIG="(eth0,00:11:66:11:66:11,0)(eth1,00:22:77:22:77:22,1:2:3:4)" +CONFIG_ETH_FLOW_CONTROL=y +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y +# CONFIG_HAVE_ARCH_DEV_ALLOC_SKB is not set +# CONFIG_MV_GTW_PROC is not set +# CONFIG_SCSI_MVSATA is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +CONFIG_FPE_FASTFPE=y +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_MV_THOR is not set +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=m +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/rd_88f5181L_fxo_defconfig b/arch/arm/configs/rd_88f5181L_fxo_defconfig new file mode 100755 index 000000000..47a697fb1 --- /dev/null +++ b/arch/arm/configs/rd_88f5181L_fxo_defconfig @@ -0,0 +1,1153 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.7 +# Mon Jan 28 15:07:11 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON_ORION=y +# CONFIG_ARCH_FEROCEON_KW is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +# CONFIG_MV88F5181 is not set +CONFIG_MV88F5181L=y +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set +# CONFIG_MV88F6183 is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PCI=y +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_CESA=y +# CONFIG_MV_INCLUDE_NAND is not set +CONFIG_MV_INCLUDE_TDM=y +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_GPP_MAX_PINS=32 +CONFIG_MV_DCACHE_SIZE=0x8000 +CONFIG_MV_ICACHE_SIZE=0x8000 + +# +# Feroceon SoC MTD support +# +# CONFIG_MV_FLASH_CTRL is not set +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +# CONFIG_USE_DSP is not set +CONFIG_FEROCEON_PROC=y +# CONFIG_MV_GENERIC_NAS_FS is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set + +# +# Soc DMA accelerations +# +CONFIG_USE_TWO_ENGINES=y +# CONFIG_USE_FOUR_ENGINES is not set +# CONFIG_MV_USE_IDMA_ENGINE is not set + +# +# SoC Networking support +# +# CONFIG_MV_ETHERNET is not set +CONFIG_MV_GATEWAY=y +CONFIG_ETH_MULTI_Q=y +CONFIG_EGIGA_STATIS=y +CONFIG_MV_GTW_QOS=y +CONFIG_MV_GTW_QOS_NET_IF="eth0" +CONFIG_MV_GTW_QOS_VOIP=y +CONFIG_MV_GTW_QOS_VOIP_TOS="0xA0" +CONFIG_MV_GTW_QOS_ROUTING=y +CONFIG_MV_GTW_QOS_ROUTING_TOS="0x11;0x22" +CONFIG_MV_NET_CONFIG="(eth0,00:11:66:11:66:11,0)(eth1,00:22:77:22:77:22,1:2:3:4)" +CONFIG_ETH_FLOW_CONTROL=y +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y +# CONFIG_HAVE_ARCH_DEV_ALLOC_SKB is not set +# CONFIG_MV_GTW_PROC is not set +# CONFIG_GTW_LOADABLE_DRV is not set + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_TOOL=y +# CONFIG_MV_CESA_TEST is not set + +# +# Telephony options +# +CONFIG_MV_PHONE=y +CONFIG_MV_TDM_LINEAR_MODE=y +# CONFIG_MV_TDM_ULAW_MODE is not set +# CONFIG_SCSI_MVSATA is not set +CONFIG_MV_FAST_PATH_ETHERNET=y +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +CONFIG_FPE_FASTFPE=y +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_MV_THOR is not set +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +CONFIG_PHONE=y +# CONFIG_PHONE_IXJ is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +CONFIG_USB_GADGET_NET2280=y +CONFIG_USB_NET2280=m +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_MRVL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/rd_88f6183_ap_defconfig b/arch/arm/configs/rd_88f6183_ap_defconfig new file mode 100755 index 000000000..737884509 --- /dev/null +++ b/arch/arm/configs/rd_88f6183_ap_defconfig @@ -0,0 +1,1457 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22.18 +# Tue Apr 21 18:31:34 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_FEROCEON_ORION=y +# CONFIG_ARCH_FEROCEON_KW is not set +# CONFIG_ARCH_FEROCEON_MV78XX0 is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Feroceon SoC options +# +# CONFIG_MV88F1181 is not set +# CONFIG_MV88F1281 is not set +# CONFIG_MV88F5181 is not set +# CONFIG_MV88F5181L is not set +# CONFIG_MV88F5182 is not set +# CONFIG_MV88F5082 is not set +# CONFIG_MV88F5180N is not set +# CONFIG_MV88F6082 is not set +# CONFIG_MV88W8660 is not set +CONFIG_MV88F6183=y +# CONFIG_JTAG_DEBUG is not set + +# +# Feroceon SoC Included Features +# +CONFIG_MV_INCLUDE_PEX=y +CONFIG_MV_INCLUDE_IDMA=y +CONFIG_MV_INCLUDE_USB=y +CONFIG_MV_INCLUDE_CESA=y +# CONFIG_MV_INCLUDE_NAND is not set +CONFIG_MV_INCLUDE_GIG_ETH=y +CONFIG_MV_INCLUDE_SPI=y +CONFIG_MV_INCLUDE_SDIO=y +CONFIG_MV_INCLUDE_AUDIO=y +CONFIG_MV_GPP_MAX_PINS=32 + +# +# Feroceon SoC MTD support +# +CONFIG_MV_FLASH_CTRL=y +CONFIG_MV_INCLUDE_SFLASH_MTD=y +CONFIG_MV_SPI_BOOT=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +# CONFIG_USE_DSP is not set +# CONFIG_FEROCEON_PROC is not set +CONFIG_UBOOT_STRUCT=y +# CONFIG_MV_DBG_TRACE is not set +# CONFIG_MV_REAL_TIME is not set +# CONFIG_MV_CPU_PERF_CNTRS is not set +# CONFIG_MV_CPU_L2_PERF_CNTRS is not set + +# +# Soc DMA accelerations +# + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# +CONFIG_MV_USE_IDMA_ENGINE=y +CONFIG_MV_IDMA_COPYUSER=y +CONFIG_MV_IDMA_COPYUSER_THRESHOLD=1260 +CONFIG_MV_IDMA_MEMCOPY=y +CONFIG_MV_IDMA_MEMCOPY_THRESHOLD=128 + +# +# SoC Networking support +# +CONFIG_MV_ETHERNET=y +CONFIG_MV_ETH_PORTS_NUM=1 + +# +# Network Interface Configuration +# +# CONFIG_OVERRIDE_ETH_CMDLINE is not set +CONFIG_MV_ETH_0_MTU=1500 +CONFIG_MV_ETH_0_MACADDR="00:00:00:00:00:80" + +# +# Rx/Tx Queue Configuration +# +CONFIG_MV_ETH_RX_Q_NUM=1 +CONFIG_MV_ETH_TX_Q_NUM=1 +CONFIG_MV_ETH_NUM_OF_RX_DESCR=128 +CONFIG_MV_ETH_NUM_OF_TX_DESCR=532 + +# +# TCP/UDP Offloading +# +CONFIG_MV_ETH_TSO=y +# CONFIG_MV_ETH_UFO is not set + +# +# Control and Statistics +# +CONFIG_MV_ETH_TOOL=y +CONFIG_MV_ETH_PROC=y +# CONFIG_MV_ETH_STATS_ERROR is not set +# CONFIG_MV_ETH_STATS_INFO is not set +# CONFIG_MV_ETH_STATS_DEBUG is not set +# CONFIG_MV_LINUX_COUNTERS_DISABLE is not set + +# +# Advanced Features +# +CONFIG_MV_ETH_TIMER_PERIOD=10 +CONFIG_MV_SKB_HEADROOM=96 +CONFIG_MV_SKB_REUSE=y +CONFIG_MV_ETH_NFP=y +CONFIG_MV_ETH_NFP_AGING_TIMER=15 +CONFIG_MV_ETH_NFP_NAT_SUPPORT=y +CONFIG_MV_NFP_STATS=y +CONFIG_MV_GATEWAY=y + +# +# Gateway Interface Configuration +# +CONFIG_MV_GTW_CONFIG="(00:11:66:11:66:11,0)(00:22:77:22:77:22,1:2:3:4),mtu=1500" + +# +# Gateway Features +# +CONFIG_MV_GTW_IGMP=y +CONFIG_MV_GTW_LINK_STATUS=y + +# +# cesa options +# +CONFIG_MV_CESA=y +CONFIG_MV_CESA_OCF=y +CONFIG_MV_CESA_TOOL=y + +# +# Marvell SDIOMMC driver +# +# CONFIG_SCSI_MVSATA is not set +# CONFIG_PCIE_VIRTUAL_BRIDGE_SUPPORT is not set +CONFIG_ARCH_FEROCEON=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_PCI=y +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_REORDER=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_COPY_USER_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0 root=/dev/nfs rw nfsroot=10.4.50.31:/home/rshitrit/cramfs-1.1/cramfs-1.1/shoko2 mem=32M ip=10.4.50.99:10.4.50.31:::ARM:eth0:none" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_NET_SKB_RECYCLING=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_CT_ACCT is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +CONFIG_NETFILTER_XT_MATCH_STATE=y +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_IPRANGE is not set +# CONFIG_IP_NF_MATCH_TOS is not set +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +CONFIG_IP_NF_FILTER=y +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_REDIRECT is not set +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_FTP=y +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +# CONFIG_IEEE80211_CRYPT_CCMP is not set +CONFIG_IEEE80211_CRYPT_TKIP=y +# CONFIG_IEEE80211_SOFTMAC is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m +CONFIG_MV_SCSI_COMMAND_TIMEOUT=0 +# CONFIG_MV_SCATTERED_SPINUP is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_MV_THOR is not set +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +CONFIG_SKGE=y +CONFIG_SKY2=y +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set +# CONFIG_HWMON is not set + +# +# Misc devices +# +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_MRVL=y +CONFIG_USB_MRVL=m +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Hardware crypto devices +# + +# +# OCF Configuration +# +CONFIG_OCF_OCF=y +# CONFIG_OCF_RANDOMHARVEST is not set +CONFIG_OCF_CRYPTODEV=y +CONFIG_OCF_CRYPTOSOFT=y +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_BENCH is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig old mode 100644 new mode 100755 index ecf253152..b4384af1b --- a/arch/arm/configs/sam9_l9260_defconfig +++ b/arch/arm/configs/sam9_l9260_defconfig @@ -39,7 +39,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_RESERVE=3 +CONFIG_MTD_UBI_BEB_LIMIT=25 CONFIG_MTD_UBI_GLUEBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild old mode 100644 new mode 100755 index 960abceb8..af5759235 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -1,7 +1,9 @@ include include/asm-generic/Kbuild.asm header-y += hwcap.h - +unifdef-y += page-nommu.h +unifdef-y += memory.h +unifdef-y += sizes.h generic-y += auxvec.h generic-y += bitsperlong.h generic-y += cputime.h diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h old mode 100644 new mode 100755 index 7bb8bf972..b37c2a43d --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -191,6 +191,19 @@ #define ALT_UP_B(label) b label #endif +#ifdef CONFIG_SYNO_ARMADA_ARCH +/* + * Instruction barrier + */ + .macro instr_sync +#if __LINUX_ARM_ARCH__ >= 7 + isb +#elif __LINUX_ARM_ARCH__ == 6 + mcr p15, 0, r0, c7, c5, 4 +#endif + .endm +#endif + /* * SMP data memory barrier */ @@ -198,9 +211,17 @@ #ifdef CONFIG_SMP #if __LINUX_ARM_ARCH__ >= 7 .ifeqs "\mode","arm" +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_6075) + ALT_SMP(dsb) +#else ALT_SMP(dmb) +#endif .else +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_6075) + ALT_SMP(W(dsb)) +#else ALT_SMP(W(dmb)) +#endif .endif #elif __LINUX_ARM_ARCH__ == 6 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h old mode 100644 new mode 100755 index 1252a2675..29c003def --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -249,8 +249,19 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr * Harvard caches are synchronised for the user space address range. * This is used for the ARM private sys_cacheflush system call. */ +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#define local_flush_cache_user_range(start,end) \ + __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) + +#if defined(CONFIG_SMP) && defined(CONFIG_CPU_V6) +extern void flush_cache_user_range(unsigned long start, unsigned long end); +#else +#define flush_cache_user_range local_flush_cache_user_range +#endif +#else #define flush_cache_user_range(start,end) \ __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) +#endif /* * Perform necessary cache operations to ensure that data previously @@ -262,7 +273,14 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr * Perform necessary cache operations to ensure that the TLB will * see data written in the specified area. */ +#if defined(CONFIG_SYNO_ARMADA_ARCH) && (defined (CONFIG_CACHE_AURORA_L2) && defined (CONFIG_AURORA_L2_OUTER) && !defined (CONFIG_AURORA_L2_PT_WALK)) +/*#warning "clean_dcache_area: Using D$ FLUSH instead of CLEAN. To be Checked\n"*/ +extern void aurora_l2_flush_range(unsigned long start, unsigned long end); +#define clean_dcache_area(start,size) do {cpu_dcache_clean_area(start, size); \ + aurora_l2_flush_range(__pa(start), __pa(start) + size);} while (0) +#else #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) +#endif /* * flush_dcache_page is used when the kernel has written to the page diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h old mode 100644 new mode 100755 index cb3b7c981..f11a923ff --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -81,7 +81,11 @@ static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size, extern void ___dma_single_cpu_to_dev(const void *, size_t, enum dma_data_direction); +#ifdef CONFIG_SYNO_ARMADA_ARCH + if (!arch_is_coherent() && size > 0) +#else if (!arch_is_coherent()) +#endif ___dma_single_cpu_to_dev(kaddr, size, dir); } @@ -91,8 +95,16 @@ static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size, extern void ___dma_single_dev_to_cpu(const void *, size_t, enum dma_data_direction); +#ifdef CONFIG_SYNO_ARMADA_ARCH + if (!arch_is_coherent() && size > 0) +#else if (!arch_is_coherent()) +#endif ___dma_single_dev_to_cpu(kaddr, size, dir); +#ifdef CONFIG_SYNO_ARMADA_ARCH + else if (dir != DMA_TO_DEVICE) + dma_io_sync(); +#endif } static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off, @@ -101,7 +113,11 @@ static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off, extern void ___dma_page_cpu_to_dev(struct page *, unsigned long, size_t, enum dma_data_direction); +#ifdef CONFIG_SYNO_ARMADA_ARCH + if (!arch_is_coherent() && size > 0) +#else if (!arch_is_coherent()) +#endif ___dma_page_cpu_to_dev(page, off, size, dir); } @@ -111,8 +127,16 @@ static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off, extern void ___dma_page_dev_to_cpu(struct page *, unsigned long, size_t, enum dma_data_direction); +#ifdef CONFIG_SYNO_ARMADA_ARCH + if (!arch_is_coherent() && size > 0) +#else if (!arch_is_coherent()) +#endif ___dma_page_dev_to_cpu(page, off, size, dir); +#ifdef CONFIG_SYNO_ARMADA_ARCH + else if (dir != DMA_TO_DEVICE) + dma_io_sync(); +#endif } extern int dma_supported(struct device *, u64); diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h old mode 100644 new mode 100755 index 0e9ce8d96..13327ba3c --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -109,7 +109,11 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define ELF_CORE_COPY_TASK_REGS dump_task_regs #define CORE_DUMP_USE_REGSET +#if defined(CONFIG_SYNO_COMCERTO) || (defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE)) +#define ELF_EXEC_PAGESIZE PAGE_SIZE +#else #define ELF_EXEC_PAGESIZE 4096 +#endif /* This is the location that an ET_DYN program is loaded if exec'ed. Typical use of this is to invoke "./ld.so someprog" to test out a new version of @@ -130,8 +134,4 @@ struct mm_struct; extern unsigned long arch_randomize_brk(struct mm_struct *mm); #define arch_randomize_brk arch_randomize_brk -extern int vectors_user_mapping(void); -#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping() -#define ARCH_HAS_SETUP_ADDITIONAL_PAGES - #endif diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S old mode 100644 new mode 100755 index 88d61815f..c964444cc --- a/arch/arm/include/asm/entry-macro-multi.S +++ b/arch/arm/include/asm/entry-macro-multi.S @@ -20,6 +20,12 @@ * this macro assumes that irqstat (r2) and base (r6) are * preserved from get_irqnr_and_base above */ +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_MV_IPC_DRIVER) + test_for_ipc r0, r2, r6, lr + movne r1, sp + adrne lr, BSYM(1b) + bne do_ipc_rx_irq +#endif ALT_SMP(test_for_ipi r0, r2, r6, lr) ALT_UP_B(9997f) movne r1, sp diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h old mode 100644 new mode 100755 index bbae919bc..64831508c --- a/arch/arm/include/asm/fixmap.h +++ b/arch/arm/include/asm/fixmap.h @@ -13,8 +13,13 @@ * 0xfffe0000 and 0xfffeffff. */ +#if defined(CONFIG_SYNO_ARMADA_ARCH) && (defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE) && defined(CONFIG_HIGHMEM)) +#define FIXADDR_START 0xffc00000UL +#define FIXADDR_TOP 0xfff00000UL +#else #define FIXADDR_START 0xfff00000UL #define FIXADDR_TOP 0xfffe0000UL +#endif #define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START) #define FIX_KMAP_BEGIN 0 diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h old mode 100644 new mode 100755 index e2be7f142..7eff9b118 --- a/arch/arm/include/asm/glue-proc.h +++ b/arch/arm/include/asm/glue-proc.h @@ -248,6 +248,26 @@ # endif #endif +#ifdef CONFIG_SYNO_ARMADA_ARCH +#ifdef CONFIG_CPU_SHEEVA_PJ4B_V6 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_sheeva_pj4b_v6 +# endif +#endif + +#ifdef CONFIG_CPU_SHEEVA_PJ4B_V7 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_sheeva_pj4b_v7 +# endif +#endif +#endif + #ifndef MULTI_CPU #define cpu_proc_init __glue(CPU_NAME,_proc_init) #define cpu_proc_fin __glue(CPU_NAME,_proc_fin) diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h old mode 100644 new mode 100755 index ddf07a92a..2a86ca107 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h @@ -9,6 +9,9 @@ typedef struct { unsigned int __softirq_pending; +#ifdef CONFIG_SYNO_ARMADA_ARCH + unsigned int local_pmu_irqs; +#endif #ifdef CONFIG_SMP unsigned int ipi_irqs[NR_IPI]; #endif diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S old mode 100644 new mode 100755 index 74ebc8039..284da5df4 --- a/arch/arm/include/asm/hardware/entry-macro-gic.S +++ b/arch/arm/include/asm/hardware/entry-macro-gic.S @@ -34,6 +34,22 @@ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_MSP) + ldr \irqstat, [\base, #GIC_CPU_HIGHPRI] + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #33 + cmpne \irqnr, #66 + cmpne \irqnr, #87 + cmpeq \irqnr, \irqnr + bne 1001f + + mov \irqnr, \irqnr /* breakpoint here */ + + beq 1002f + +1001: +#endif /* CONFIG_SYNO_COMCERTO && CONFIG_COMCERTO_MSP */ + ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ @@ -43,6 +59,11 @@ cmpcc \irqnr, \irqnr cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr + +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_MSP) +1002: +#endif /* CONFIG_SYNO_COMCERTO && CONFIG_COMCERTO_MSP */ + .endm /* We assume that irqstat (the raw value of the IRQ acknowledge diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h old mode 100644 new mode 100755 index 3e91f2204..950bab171 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -22,6 +22,9 @@ #define GIC_DIST_CTRL 0x000 #define GIC_DIST_CTR 0x004 +#if defined(CONFIG_SYNO_COMCERTO) +#define GIC_DIST_SECURITY_BIT 0x080 +#endif #define GIC_DIST_ENABLE_SET 0x100 #define GIC_DIST_ENABLE_CLEAR 0x180 #define GIC_DIST_PENDING_SET 0x200 diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h old mode 100644 new mode 100755 index c2b9b4bde..3a016976f --- a/arch/arm/include/asm/kexec.h +++ b/arch/arm/include/asm/kexec.h @@ -10,7 +10,11 @@ /* Maximum address we can use for the control code buffer */ #define KEXEC_CONTROL_MEMORY_LIMIT (-1UL) +#if defined(CONFIG_SYNO_COMCERTO) +#define KEXEC_CONTROL_PAGE_SIZE (PAGE_SIZE) +#else #define KEXEC_CONTROL_PAGE_SIZE 4096 +#endif #define KEXEC_ARCH KEXEC_ARCH_ARM diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h old mode 100644 new mode 100755 index b36f3654b..89d87b941 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -30,6 +30,10 @@ struct map_desc { #define MT_MEMORY_DTCM 12 #define MT_MEMORY_ITCM 13 #define MT_MEMORY_SO 14 +#if defined(CONFIG_SYNO_COMCERTO) +#define MT_MSP 15 +#define MT_MSP_NCNB 16 +#endif #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h old mode 100644 new mode 100755 index 186efd4e0..4b10d9f50 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -46,6 +46,9 @@ struct pci_sys_data { /* IRQ mapping */ int (*map_irq)(const struct pci_dev *, u8, u8); struct hw_pci *hw; +#ifdef CONFIG_SYNO_ARMADA + int mv_controller_num; +#endif void *private_data; /* platform controller private data */ }; diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h old mode 100644 new mode 100755 index a8997d710..ea5b73e3c --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -35,30 +35,44 @@ * TASK_SIZE - the maximum size of a user space task. * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area */ +#if defined(CONFIG_SYNO_COMCERTO) +#include +#endif +#if defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE) && defined(CONFIG_SYNO_ARMADA_ARCH) +#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET) +#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(0x01C00000)) +#define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3) +#elif defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_64K_PAGES) +#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET) +#define TASK_SIZE ((UL(CONFIG_PAGE_OFFSET) - UL(0x01000000)) & ~(UL((1 << PMD_SHIFT)-1))) // Must be aligned on PMD size (kernel/user space can share same PMD) +#define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3) +#else #define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET) #define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000)) #define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3) - +#endif /* * The maximum size of a 26-bit user space task. */ #define TASK_SIZE_26 UL(0x04000000) +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_ZONE_DMA_NCNB) /* * The module space lives between the addresses given by TASK_SIZE * and PAGE_OFFSET - it must be within 32MB of the kernel text. */ #ifndef CONFIG_THUMB2_KERNEL +/* 28MB is heuristic setting. */ +#if defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE) && defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARCH_ARMADA370) +#define MODULES_VADDR (PAGE_OFFSET - 28*1024*1024) +#else #define MODULES_VADDR (PAGE_OFFSET - 16*1024*1024) +#endif #else /* smaller range for Thumb-2 symbols relocation (2^24)*/ #define MODULES_VADDR (PAGE_OFFSET - 8*1024*1024) #endif -#if TASK_SIZE > MODULES_VADDR -#error Top of user space clashes with start of module space -#endif - /* * The highmem pkmap virtual space shares the end of the module area. */ @@ -68,6 +82,22 @@ #define MODULES_END (PAGE_OFFSET) #endif +#else +/* Move module space into the hole reserved for MSP/PFE so we can have a bigger DMA zone */ +#define MODULES_END ((COMCERTO_DDR_SHARED_BASE + COMCERTO_DDR_SHARED_SIZE - PLAT_PHYS_OFFSET + PAGE_OFFSET) & PMD_MASK) // convert SHARED_END to virt and align on lower PMD boundary + +#ifndef CONFIG_THUMB2_KERNEL +#define MODULES_VADDR (MODULES_END - 16*1024*1024) +#else +#define MODULES_VADDR (MODULES_END - 10*1024*1024) // Relocations will be guaranteed to work as long as kernel size is less than 6MB +#endif + +#endif + +#if TASK_SIZE > MODULES_VADDR +#error Top of user space clashes with start of module space +#endif + /* * The XIP kernel gets mapped at the bottom of the module vm area. * Since we use sections to map it, this macro replaces the physical address @@ -80,7 +110,11 @@ */ #define IOREMAP_MAX_ORDER 24 +#if defined(CONFIG_SYNO_ARMADA_ARCH) && (defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE) && defined(CONFIG_HIGHMEM)) +#define CONSISTENT_END (0xffc00000UL) +#else #define CONSISTENT_END (0xffe00000UL) +#endif #else /* CONFIG_MMU */ @@ -181,10 +215,15 @@ static inline unsigned long __phys_to_virt(unsigned long x) return t; } #else +#ifdef CONFIG_SYNO_ARMADA_ARCH +#define __virt_to_phys(x) ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((unsigned long)(x) - PHYS_OFFSET + PAGE_OFFSET) +#else #define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) #define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) #endif #endif +#endif #ifndef PHYS_OFFSET #ifdef PLAT_PHYS_OFFSET diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h old mode 100644 new mode 100755 index 71605d9f8..a0b3cac05 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -18,6 +18,7 @@ #include #include #include +#include void __check_kvm_seq(struct mm_struct *mm); @@ -133,32 +134,4 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #define deactivate_mm(tsk,mm) do { } while (0) #define activate_mm(prev,next) switch_mm(prev, next, NULL) -/* - * We are inserting a "fake" vma for the user-accessible vector page so - * gdb and friends can get to it through ptrace and /proc//mem. - * But we also want to remove it before the generic code gets to see it - * during process exit or the unmapping of it would cause total havoc. - * (the macro is used as remove_vma() is static to mm/mmap.c) - */ -#define arch_exit_mmap(mm) \ -do { \ - struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \ - if (high_vma) { \ - BUG_ON(high_vma->vm_next); /* it should be last */ \ - if (high_vma->vm_prev) \ - high_vma->vm_prev->vm_next = NULL; \ - else \ - mm->mmap = NULL; \ - rb_erase(&high_vma->vm_rb, &mm->mm_rb); \ - mm->mmap_cache = NULL; \ - mm->map_count--; \ - remove_vma(high_vma); \ - } \ -} while (0) - -static inline void arch_dup_mmap(struct mm_struct *oldmm, - struct mm_struct *mm) -{ -} - #endif diff --git a/arch/arm/include/asm/neon.h b/arch/arm/include/asm/neon.h new file mode 100755 index 000000000..8f730fe70 --- /dev/null +++ b/arch/arm/include/asm/neon.h @@ -0,0 +1,36 @@ +/* + * linux/arch/arm/include/asm/neon.h + * + * Copyright (C) 2013 Linaro Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#define cpu_has_neon() (!!(elf_hwcap & HWCAP_NEON)) + +#ifdef __ARM_NEON__ + +/* + * If you are affected by the BUILD_BUG below, it probably means that you are + * using NEON code /and/ calling the kernel_neon_begin() function from the same + * compilation unit. To prevent issues that may arise from GCC reordering or + * generating(1) NEON instructions outside of these begin/end functions, the + * only supported way of using NEON code in the kernel is by isolating it in a + * separate compilation unit, and calling it from another unit from inside a + * kernel_neon_begin/kernel_neon_end pair. + * + * (1) Current GCC (4.7) might generate NEON instructions at O3 level if + * -mpfu=neon is set. + */ + +#define kernel_neon_begin() \ + BUILD_BUG_ON_MSG(1, "kernel_neon_begin() called from NEON code") + +#else +void kernel_neon_begin(void); +#endif +void kernel_neon_end(void); diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h old mode 100644 new mode 100755 index ca94653f1..594ada1ea --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -11,7 +11,11 @@ #define _ASMARM_PAGE_H /* PAGE_SHIFT determines the page size */ +#if (defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_64K_PAGES)) || (defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE)) +#define PAGE_SHIFT 16 +#else #define PAGE_SHIFT 12 +#endif #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) @@ -151,7 +155,13 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from, #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) extern void copy_page(void *to, const void *from); +#define __HAVE_ARCH_GATE_AREA 1 + +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) +#include +#else #include +#endif #endif /* CONFIG_MMU */ diff --git a/arch/arm/include/asm/param.h b/arch/arm/include/asm/param.h old mode 100644 new mode 100755 index 8b24bf94c..6ec6b6546 --- a/arch/arm/include/asm/param.h +++ b/arch/arm/include/asm/param.h @@ -18,7 +18,11 @@ # define HZ 100 #endif +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) #define EXEC_PAGESIZE 4096 +#else +#define EXEC_PAGESIZE 65536 +#endif #ifndef NOGROUP #define NOGROUP (-1) diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h old mode 100644 new mode 100755 index 0f8e3827a..e7f004751 --- a/arch/arm/include/asm/perf_event.h +++ b/arch/arm/include/asm/perf_event.h @@ -27,6 +27,9 @@ enum arm_perf_pmu_ids { ARM_PERF_PMU_ID_CA5, ARM_PERF_PMU_ID_CA15, ARM_NUM_PMU_IDS, +#ifdef CONFIG_SYNO_ARMADA_ARCH + MRVL_PERF_PMU_ID_PJ4B, +#endif }; extern enum arm_perf_pmu_ids diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h old mode 100644 new mode 100755 index 3e08fd3fb..0245f581a --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h @@ -25,12 +25,38 @@ #define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) + +static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) +{ + return (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT); +} + +static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd) +{ + BUG_ON((unsigned long)pmd & (PAGE_SIZE-1)); + free_page((unsigned long)pmd); +} + +static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) +{ + set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE)); +} + +#else /* !CONFIG_ARM_LPAE */ + /* * Since we have only two-level page tables, these are trivial */ #define pmd_alloc_one(mm,addr) ({ BUG(); ((pmd_t *)2); }) #define pmd_free(mm, pmd) do { } while (0) +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#define pud_populate(mm,pmd,pte) BUG() +#else #define pgd_populate(mm,pmd,pte) BUG() +#endif + +#endif /* CONFIG_ARM_LPAE */ extern pgd_t *pgd_alloc(struct mm_struct *mm); extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); @@ -108,8 +134,20 @@ static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte, pmdval_t prot) { pmdval_t pmdval = (pte + PTE_HWTABLE_OFF) | prot; +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) pmdp[0] = __pmd(pmdval); +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) +#else pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); +#endif +#else + int i, off = 0; + for (i = 0; i < LINKED_PMDS; i++) { + pmdp[i] = __pmd(pmdval + off); + off += 1024; // Each PMD points to a 1kB 2nd-level table + } + +#endif flush_pmd_entry(pmdp); } diff --git a/arch/arm/include/asm/pgtable-2level-hwdef.h b/arch/arm/include/asm/pgtable-2level-hwdef.h old mode 100644 new mode 100755 index 5cfba15cb..ed878c448 --- a/arch/arm/include/asm/pgtable-2level-hwdef.h +++ b/arch/arm/include/asm/pgtable-2level-hwdef.h @@ -65,7 +65,11 @@ /* * - extended small page/tiny page */ +#if (defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_64K_PAGES)) || (defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE)) +#define PTE_EXT_XN (_AT(pteval_t, 1) << 15) /* v6 */ +#else #define PTE_EXT_XN (_AT(pteval_t, 1) << 0) /* v6 */ +#endif #define PTE_EXT_AP_MASK (_AT(pteval_t, 3) << 4) #define PTE_EXT_AP0 (_AT(pteval_t, 1) << 4) #define PTE_EXT_AP1 (_AT(pteval_t, 2) << 4) @@ -73,7 +77,11 @@ #define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) #define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) +#if (defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_COMCERTO_64K_PAGES)) || (defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE)) +#define PTE_EXT_TEX(x) (_AT(pteval_t, (x)) << 12) /* Large Page */ +#else #define PTE_EXT_TEX(x) (_AT(pteval_t, (x)) << 6) /* v5 */ +#endif #define PTE_EXT_APX (_AT(pteval_t, 1) << 9) /* v6 */ #define PTE_EXT_COHERENT (_AT(pteval_t, 1) << 9) /* XScale3 */ #define PTE_EXT_SHARED (_AT(pteval_t, 1) << 10) /* v6 */ diff --git a/arch/arm/include/asm/pgtable-2level-types.h b/arch/arm/include/asm/pgtable-2level-types.h old mode 100644 new mode 100755 index 66cb5b0e8..9b6549175 --- a/arch/arm/include/asm/pgtable-2level-types.h +++ b/arch/arm/include/asm/pgtable-2level-types.h @@ -24,12 +24,17 @@ typedef u32 pteval_t; typedef u32 pmdval_t; +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) #undef STRICT_MM_TYPECHECKS +#else +#define STRICT_MM_TYPECHECKS 1 +#endif #ifdef STRICT_MM_TYPECHECKS /* * These are used to make use of C type-checking.. */ +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) typedef struct { pteval_t pte; } pte_t; typedef struct { pmdval_t pmd; } pmd_t; typedef struct { pmdval_t pgd[2]; } pgd_t; @@ -44,6 +49,23 @@ typedef struct { pteval_t pgprot; } pgprot_t; #define __pmd(x) ((pmd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) +#else +#include +typedef struct { pteval_t pte[16]; } pte_t; +typedef struct { pmdval_t pmd; } pmd_t; +typedef struct { pmdval_t pgd[LINKED_PMDS]; } pgd_t; +typedef struct { pteval_t pgprot; } pgprot_t; + +#define pte_val(x) ((x).pte[0]) +#define pmd_val(x) ((x).pmd) +#define pgd_val(x) ((x).pgd[0]) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { {(x)} } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) +#endif + #else /* * .. while these make it easier on the compiler diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h old mode 100644 new mode 100755 index 470457e1c..b2b877367 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -28,6 +28,17 @@ * which contain the state information Linux needs. We, therefore, end up * with 512 entries in the "PTE" level. * +#if defined(CONFIG_SYNO_COMCERTO) + * 64k pages support (Mindspeed COMCERTO): + * We cheat even more and tell Linux that we have 256 entries in the first + * level, each of which is 64 bytes (16 hardware pointers). The 2nd level + * contains 16 hardware PTE tables, or 4096 hardware entries. However, + * since 64kB pages are done by duplicating 4kB entries, there will only by + * 256 entries in the Linux "PTE" level (and the PTE entry will be larger). + * All defines are now also derived from the LINKED_PMDS_SHIFT macro, which + * determines how many PMDs point into a single 2nd-level table. + * +#endif * This leads to the page tables having the following layout: * * pgd pte @@ -68,13 +79,32 @@ * until either the TLB entry is evicted under pressure, or a context * switch which changes the user space mapping occurs. */ + + +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) +#ifdef CONFIG_SYNO_ARMADA_ARCH +#ifdef CONFIG_MV_SUPPORT_64KB_PAGE_SIZE +#define PTRS_PER_PTE 32 /* (512 / (64K / 4K)) */ +#define PTE_HWTABLE_PTRS (512) +#else +#define PTRS_PER_PTE 512 +#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) +#endif +#else #define PTRS_PER_PTE 512 +#endif + #define PTRS_PER_PMD 1 #define PTRS_PER_PGD 2048 +#ifdef CONFIG_SYNO_ARMADA_ARCH +#define PTE_HWTABLE_OFF (512 * sizeof(pte_t)) +#define PTE_HWTABLE_SIZE (PTE_HWTABLE_PTRS * sizeof(u32)) +#else #define PTE_HWTABLE_PTRS (PTRS_PER_PTE) #define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) +#endif /* * PMD_SHIFT determines the size of the area a second-level page table can map @@ -82,6 +112,21 @@ */ #define PMD_SHIFT 21 #define PGDIR_SHIFT 21 +#else +#define LINKED_PMDS_SHIFT 4 +#define LINKED_PMDS (1 << LINKED_PMDS_SHIFT) /* number of PMDs pointing to the same 2nd-level page */ +#define PTRS_PER_PGD (4096 / LINKED_PMDS) /* one pgdir table contains 4096 entries */ +#define PGDIR_SHIFT (20 + LINKED_PMDS_SHIFT) /* one pgdir entry can map 1MB (2^20) */ +#define PMD_SHIFT (PGDIR_SHIFT) +#define PTET_SIZE_SHIFT 6 /* a HW PTE entry is 16*4bytes */ +#define PTE_HWTABLE_PTRS (1 << (10 + LINKED_PMDS_SHIFT - PTET_SIZE_SHIFT)) /* one HW PTE table is 1kB (2^10) */ + +#define PTRS_PER_PTE (PTE_HWTABLE_PTRS) +#define PTRS_PER_PMD 1 + +#define PTE_HWTABLE_OFF 32768 //(PTRS_PER_PTE * sizeof(pte_t)) +#define PTE_HWTABLE_SIZE (1 << (10 + LINKED_PMDS_SHIFT)) +#endif #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h new file mode 100755 index 000000000..7c238a3b4 --- /dev/null +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h @@ -0,0 +1,82 @@ +/* + * arch/arm/include/asm/pgtable-3level-hwdef.h + * + * Copyright (C) 2011 ARM Ltd. + * Author: Catalin Marinas + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H +#define _ASM_PGTABLE_3LEVEL_HWDEF_H + +/* + * Hardware page table definitions. + * + * + Level 1/2 descriptor + * - common + */ +#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) +#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) +#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) +#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) +#define PMD_BIT4 (_AT(pmdval_t, 0)) +#define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) + +/* + * - section + */ +#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) +#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) +#define PMD_SECT_S (_AT(pmdval_t, 3) << 8) +#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) +#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) +#ifdef __ASSEMBLY__ +/* avoid 'shift count out of range' warning */ +#define PMD_SECT_XN (0) +#else +#define PMD_SECT_XN ((pmdval_t)1 << 54) +#endif +#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) +#define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) +#define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) + +/* + * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). + */ +#define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */ +#define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */ +#define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */ +#define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */ +#define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */ + +/* + * + Level 3 descriptor (PTE) + */ +#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) +#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) +#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) +#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ +#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ +#define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ +#define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ +#define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ +#define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ + +/* + * 40-bit physical address supported. + */ +#define PHYS_MASK_SHIFT (40) +#define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1) + +#endif diff --git a/arch/arm/include/asm/pgtable-3level-types.h b/arch/arm/include/asm/pgtable-3level-types.h new file mode 100755 index 000000000..921aa3025 --- /dev/null +++ b/arch/arm/include/asm/pgtable-3level-types.h @@ -0,0 +1,70 @@ +/* + * arch/arm/include/asm/pgtable-3level-types.h + * + * Copyright (C) 2011 ARM Ltd. + * Author: Catalin Marinas + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _ASM_PGTABLE_3LEVEL_TYPES_H +#define _ASM_PGTABLE_3LEVEL_TYPES_H + +#include + +typedef u64 pteval_t; +typedef u64 pmdval_t; +typedef u64 pgdval_t; + +#undef STRICT_MM_TYPECHECKS + +#ifdef STRICT_MM_TYPECHECKS + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { pteval_t pte; } pte_t; +typedef struct { pmdval_t pmd; } pmd_t; +typedef struct { pgdval_t pgd; } pgd_t; +typedef struct { pteval_t pgprot; } pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((x).pmd) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +#else /* !STRICT_MM_TYPECHECKS */ + +typedef pteval_t pte_t; +typedef pmdval_t pmd_t; +typedef pgdval_t pgd_t; +typedef pteval_t pgprot_t; + +#define pte_val(x) (x) +#define pmd_val(x) (x) +#define pgd_val(x) (x) +#define pgprot_val(x) (x) + +#define __pte(x) (x) +#define __pmd(x) (x) +#define __pgd(x) (x) +#define __pgprot(x) (x) + +#endif /* STRICT_MM_TYPECHECKS */ + +#endif /* _ASM_PGTABLE_3LEVEL_TYPES_H */ diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h new file mode 100755 index 000000000..a6261f517 --- /dev/null +++ b/arch/arm/include/asm/pgtable-3level.h @@ -0,0 +1,107 @@ +/* + * arch/arm/include/asm/pgtable-3level.h + * + * Copyright (C) 2011 ARM Ltd. + * Author: Catalin Marinas + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _ASM_PGTABLE_3LEVEL_H +#define _ASM_PGTABLE_3LEVEL_H + +/* + * With LPAE, there are 3 levels of page tables. Each level has 512 entries of + * 8 bytes each, occupying a 4K page. The first level table covers a range of + * 512GB, each entry representing 1GB. Since we are limited to 4GB input + * address range, only 4 entries in the PGD are used. + * + * There are enough spare bits in a page table entry for the kernel specific + * state. + */ +#define PTRS_PER_PTE 512 +#define PTRS_PER_PMD 512 +#define PTRS_PER_PGD 4 + +#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) +#define PTE_HWTABLE_OFF (0) +#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) + +/* + * PGDIR_SHIFT determines the size a top-level page table entry can map. + */ +#define PGDIR_SHIFT 30 + +/* + * PMD_SHIFT determines the size a middle-level page table entry can map. + */ +#define PMD_SHIFT 21 + +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * section address mask and size definitions. + */ +#define SECTION_SHIFT 21 +#define SECTION_SIZE (1UL << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) + +#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE) + +/* + * "Linux" PTE definitions for LPAE. + * + * These bits overlap with the hardware bits but the naming is preserved for + * consistency with the classic page table format. + */ +#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Valid */ +#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ +#define L_PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ +#define L_PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ +#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ +#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ +#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ +#define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ +#define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ +#define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) /* unused */ +#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */ + +/* + * To be used in assembly code with the upper page attributes. + */ +#define L_PTE_XN_HIGH (1 << (54 - 32)) +#define L_PTE_DIRTY_HIGH (1 << (55 - 32)) + +/* + * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). + */ +#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ +#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ +#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ +#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ +#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ +#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ +#define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ +#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ +#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) + +/* + * Software PGD flags. + */ +#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */ + +#endif /* _ASM_PGTABLE_3LEVEL_H */ diff --git a/arch/arm/include/asm/pgtable-hwdef.h b/arch/arm/include/asm/pgtable-hwdef.h old mode 100644 new mode 100755 index 183111164..a830285c1 --- a/arch/arm/include/asm/pgtable-hwdef.h +++ b/arch/arm/include/asm/pgtable-hwdef.h @@ -10,6 +10,10 @@ #ifndef _ASMARM_PGTABLE_HWDEF_H #define _ASMARM_PGTABLE_HWDEF_H +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) +#include +#else #include +#endif #endif diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h old mode 100644 new mode 100755 index 9b419abd1..248dd3426 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -11,20 +11,33 @@ #define _ASMARM_PGTABLE_H #include +#ifdef CONFIG_SYNO_ARMADA_ARCH +#else #include +#endif #include #ifndef CONFIG_MMU +#ifdef CONFIG_SYNO_ARMADA_ARCH +#include +#endif #include "pgtable-nommu.h" #else +#ifdef CONFIG_SYNO_ARMADA_ARCH +#include +#endif #include #include #include +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) +#include +#else #include +#endif /* * Just any arbitrary offset to the start of the vmalloc VM area: the @@ -163,6 +176,45 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#ifdef CONFIG_ARM_LPAE + +#define pud_none(pud) (!pud_val(pud)) +#define pud_bad(pud) (!(pud_val(pud) & 2)) +#define pud_present(pud) (pud_val(pud)) + +#define pud_clear(pudp) \ + do { \ + *pudp = __pud(0); \ + clean_pmd_entry(pudp); \ + } while (0) + +#define set_pud(pudp, pud) \ + do { \ + *pudp = pud; \ + flush_pmd_entry(pudp); \ + } while (0) + +static inline pmd_t *pud_page_vaddr(pud_t pud) +{ + return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); +} + +#else /* !CONFIG_ARM_LPAE */ + +/* + * The "pud_xxx()" functions here are trivial when the pmd is folded into + * the pud: the pud entry is never bad, always exists, and can't be set or + * cleared. + */ +#define pud_none(pud) (0) +#define pud_bad(pud) (0) +#define pud_present(pud) (1) +#define pud_clear(pudp) do { } while (0) +#define set_pud(pud,pudp) do { } while (0) + +#endif /* CONFIG_ARM_LPAE */ +#else /* * The "pgd_xxx()" functions here are trivial for a folded two-level * setup: the pgd is never bad, and a pmd always exists (as it's folded @@ -175,14 +227,50 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; #define set_pgd(pgd,pgdp) do { } while (0) #define set_pud(pud,pudp) do { } while (0) +#endif /* Find an entry in the second-level page table.. */ +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#ifdef CONFIG_ARM_LPAE +#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) +static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) +{ + return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); +} +#else +static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) +{ + return (pmd_t *)pud; +} +#endif +#else #define pmd_offset(dir, addr) ((pmd_t *)(dir)) +#endif #define pmd_none(pmd) (!pmd_val(pmd)) #define pmd_present(pmd) (pmd_val(pmd)) + +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) + +#define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) + +#define copy_pmd(pmdpd,pmdps) \ + do { \ + *pmdpd = *pmdps; \ + flush_pmd_entry(pmdpd); \ + } while (0) + +#define pmd_clear(pmdp) \ + do { \ + *pmdp = __pmd(0); \ + clean_pmd_entry(pmdp); \ + } while (0) + +#else /* !CONFIG_ARM_LPAE */ + #define pmd_bad(pmd) (pmd_val(pmd) & 2) +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) #define copy_pmd(pmdpd,pmdps) \ do { \ pmdpd[0] = pmdps[0]; \ @@ -197,16 +285,46 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; clean_pmd_entry(pmdp); \ } while (0) +#else +#define copy_pmd(pmdpd,pmdps) \ + do { \ + int i; \ + for(i = 0; i < LINKED_PMDS; i++) \ + pmdpd[i] = pmdps[i]; \ + flush_pmd_entry(pmdpd); \ + } while (0) + +#define pmd_clear(pmdp) \ + do { \ + int i; \ + for(i = 0; i < LINKED_PMDS; i++) \ + pmdp[i] = __pmd(0); \ + clean_pmd_entry(pmdp); \ + } while (0) + +#endif +#endif /* CONFIG_ARM_LPAE */ + +#if defined(CONFIG_SYNO_COMCERTO) +#define PMD_PAGE_ADDR_MASK (~((1 << 10) - 1)) +#endif static inline pte_t *pmd_page_vaddr(pmd_t pmd) { +#if defined(CONFIG_SYNO_COMCERTO) + return __va((pmd_val(pmd) & PHYS_MASK & (s32)PMD_PAGE_ADDR_MASK) - PTE_HWTABLE_OFF); +#else return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); +#endif } #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#else /* we don't need complex calculations here as the pmd is folded into the pgd */ #define pmd_addr_end(addr,end) (end) +#endif #ifndef CONFIG_HIGHPTE #define __pte_map(pmd) pmd_page_vaddr(*(pmd)) @@ -229,8 +347,12 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) #define pte_page(pte) pfn_to_page(pte_pfn(pte)) #define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot) -#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) + +#if defined(CONFIG_SYNO_COMCERTO) +#define pte_clear(mm,addr,ptep) do {__sync_outer_cache(ptep, __pte(0)); set_pte_ext(ptep, __pte(0), 0); } while (0) +#else #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) +#endif #define pte_none(pte) (!pte_val(pte)) #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) @@ -244,6 +366,23 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \ (L_PTE_PRESENT | L_PTE_USER)) +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) +#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext))) +#elif defined(CONFIG_SYNO_COMCERTO) +#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte_val(pte),ext) +#else +#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) +#endif + +#if defined(CONFIG_SYNO_COMCERTO) +#if !defined(CONFIG_L2X0_INSTRUCTION_ONLY) +static inline void __sync_outer_cache(pte_t *ptep, pte_t pteval) +{ +} +#else +extern void __sync_outer_cache(pte_t *ptep, pte_t pteval); +#endif +#endif #if __LINUX_ARM_ARCH__ < 6 static inline void __sync_icache_dcache(pte_t pteval) { @@ -257,6 +396,10 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, { unsigned long ext = 0; +#if defined(CONFIG_SYNO_COMCERTO) + __sync_outer_cache(ptep, pteval); +#endif + if (addr < TASK_SIZE && pte_present_user(pteval)) { __sync_icache_dcache(pteval); ext |= PTE_EXT_NG; @@ -305,7 +448,11 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#if defined(CONFIG_SYNO_COMCERTO) +#define __swp_entry_to_pte(swp) ((pte_t) { { (swp).val } }) +#else #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) +#endif /* * It is an error for the kernel to have more swap files than we can diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h old mode 100644 new mode 100755 index 9e92cb205..088c131ce --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -65,7 +65,13 @@ extern struct processor { * Set a possibly extended PTE. Non-extended PTEs should * ignore 'ext'. */ +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) + void (*set_pte_ext)(pte_t *ptep, pte_t pte); +#elif defined(CONFIG_SYNO_COMCERTO) + void (*set_pte_ext)(pte_t *ptep, pteval_t pte, unsigned int ext); +#else void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext); +#endif /* Suspend/resume */ unsigned int suspend_size; @@ -79,7 +85,13 @@ extern void cpu_proc_fin(void); extern int cpu_do_idle(void); extern void cpu_dcache_clean_area(void *, int); extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) +extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte); +#elif defined(CONFIG_SYNO_COMCERTO) +extern void cpu_set_pte_ext(pte_t *ptep, pteval_t pte, unsigned int ext); +#else extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); +#endif extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); /* These three are private to arch/arm/kernel/suspend.c */ @@ -105,8 +117,34 @@ extern void cpu_resume(void); #ifdef CONFIG_MMU +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SMP) + +#define cpu_switch_mm(pgd,mm) \ + ({ \ + unsigned long flags; \ + local_irq_save(flags); \ + cpu_do_switch_mm(virt_to_phys(pgd),mm); \ + local_irq_restore(flags); \ + }) + +#else /* SMP */ + #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm) +#endif + +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) +#define cpu_get_pgd() \ + ({ \ + unsigned long pg, pg2; \ + __asm__("mrrc p15, 0, %0, %1, c2" \ + : "=r" (pg), "=r" (pg2) \ + : \ + : "cc"); \ + pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \ + (pgd_t *)phys_to_virt(pg); \ + }) +#else #define cpu_get_pgd() \ ({ \ unsigned long pg; \ @@ -117,6 +155,7 @@ extern void cpu_resume(void); }) #endif +#endif #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h old mode 100644 new mode 100755 index 915696dd9..97f74e1b7 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -43,6 +43,15 @@ struct tag_mem32 { __u32 start; /* physical start address */ }; +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#define ATAG_MEM64 0x54420002 + +struct tag_mem64 { + __u64 size; + __u64 start; /* physical start address */ +}; +#endif + /* VGA text type displays */ #define ATAG_VIDEOTEXT 0x54410003 @@ -143,11 +152,39 @@ struct tag_memclk { __u32 fmemclk; }; + +#if defined(CONFIG_SYNO_ARMADA) +/* Marvell uboot parameters */ +#define ATAG_MV_UBOOT 0x41000403 +#define MV_UBOOT_ETH_PORTS 4 +struct tag_mv_uboot { + __u32 uboot_version; + __u32 tclk; + __u32 sysclk; + __u32 isUsbHost; + __u8 macAddr[MV_UBOOT_ETH_PORTS][6]; + __u16 mtu[MV_UBOOT_ETH_PORTS]; + __u32 nand_ecc; +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#if !defined (CONFIG_ARCH_ARMADA370) + __u32 rgmii0Src; + __u32 feGeSrc; +#endif +#if defined (CONFIG_ARCH_ARMADA370) + __u32 bit_mask_config; +#endif +#endif +}; +#endif + struct tag { struct tag_header hdr; union { struct tag_core core; struct tag_mem32 mem; +#if defined(CONFIG_SYNO_ARMADA_ARCH) + struct tag_mem64 mem64; +#endif struct tag_videotext videotext; struct tag_ramdisk ramdisk; struct tag_initrd initrd; @@ -165,6 +202,12 @@ struct tag { * DC21285 specific */ struct tag_memclk memclk; +#if defined(CONFIG_SYNO_ARMADA) + /* + * Marvell specific + */ + struct tag_mv_uboot mv_uboot; +#endif } u; }; @@ -173,15 +216,35 @@ struct tagtable { int (*parse)(const struct tag *); }; +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#ifdef CONFIG_BE8_ON_LE +#define read_tag(a) le32_to_cpu(a) +#else +#define read_tag(a) a +#endif +#endif + +#if defined(CONFIG_SYNO_ARMADA_ARCH) #define tag_member_present(tag,member) \ ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= read_tag((tag)->hdr.size) * 4) +#define tag_next(t) ((struct tag *)((__u32 *)(t) + read_tag((t)->hdr.size))) +#else +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ <= (tag)->hdr.size * 4) #define tag_next(t) ((struct tag *)((__u32 *)(t) + (t)->hdr.size)) +#endif #define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#define for_each_tag(t,base) \ + for (t = base; read_tag((t)->hdr.size); t = tag_next(t)) +#else #define for_each_tag(t,base) \ for (t = base; t->hdr.size; t = tag_next(t)) +#endif #ifdef __KERNEL__ diff --git a/arch/arm/include/asm/shmparam.h b/arch/arm/include/asm/shmparam.h old mode 100644 new mode 100755 index a5223b3a9..dc04e945d --- a/arch/arm/include/asm/shmparam.h +++ b/arch/arm/include/asm/shmparam.h @@ -6,7 +6,15 @@ * or page size, whichever is greater since the cache aliases * every size/ways bytes. */ +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE) +#define SHMLBA (16 << 10) /* attach addr a multiple of this */ +#else #define SHMLBA (4 * PAGE_SIZE) /* attach addr a multiple of this */ +#endif +#else +#define SHMLBA (PAGE_SIZE) /* attach addr a multiple of this */ +#endif /* * Enforce SHMLBA in shmat diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h old mode 100644 new mode 100755 index 1e5717afc..6b7973735 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -99,4 +99,8 @@ extern void platform_cpu_enable(unsigned int cpu); extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARCH_ARMADA_XP) && defined(CONFIG_PERF_EVENTS) +extern void show_local_pmu_irqs(struct seq_file *, int); +#endif + #endif /* ifndef __ASM_ARM_SMP_H */ diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h old mode 100644 new mode 100755 index ef9ffba97..0ed6518f1 --- a/arch/arm/include/asm/smp_twd.h +++ b/arch/arm/include/asm/smp_twd.h @@ -24,5 +24,8 @@ extern void __iomem *twd_base; void twd_timer_setup(struct clock_event_device *); void twd_timer_stop(struct clock_event_device *); +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_LOCAL_TIMERS) +int twd_timer_ack(void); +#endif #endif diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h old mode 100644 new mode 100755 index 65fa3c880..2b911f342 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h @@ -83,7 +83,10 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) __asm__ __volatile__( "1: ldrex %0, [%1]\n" " teq %0, #0\n" +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_BTS61) +#else WFE("ne") +#endif " strexeq %0, %2, [%1]\n" " teqeq %0, #0\n" " bne 1b" @@ -139,10 +142,16 @@ static inline void arch_write_lock(arch_rwlock_t *rw) { unsigned long tmp; +#if defined(CONFIG_SYNO_ARMADA_ARCH) + do{ +#endif __asm__ __volatile__( "1: ldrex %0, [%1]\n" " teq %0, #0\n" +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_BTS61) +#else WFE("ne") +#endif " strexeq %0, %2, [%1]\n" " teq %0, #0\n" " bne 1b" @@ -150,6 +159,9 @@ static inline void arch_write_lock(arch_rwlock_t *rw) : "r" (&rw->lock), "r" (0x80000000) : "cc"); +#if defined(CONFIG_SYNO_ARMADA_ARCH) + } while (tmp && atomic_backoff_delay()); +#endif smp_mb(); } @@ -169,6 +181,9 @@ static inline int arch_write_trylock(arch_rwlock_t *rw) smp_mb(); return 1; } else { +#if defined(CONFIG_SYNO_ARMADA_ARCH) + atomic_backoff_delay(); +#endif return 0; } } @@ -209,7 +224,10 @@ static inline void arch_read_lock(arch_rwlock_t *rw) "1: ldrex %0, [%2]\n" " adds %0, %0, #1\n" " strexpl %1, %0, [%2]\n" +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_BTS61) +#else WFE("mi") +#endif " rsbpls %0, %1, #0\n" " bmi 1b" : "=&r" (tmp), "=&r" (tmp2) diff --git a/arch/arm/include/asm/stat.h b/arch/arm/include/asm/stat.h old mode 100644 new mode 100755 index 42c0c1399..5a4270948 --- a/arch/arm/include/asm/stat.h +++ b/arch/arm/include/asm/stat.h @@ -48,6 +48,7 @@ struct stat { unsigned long __unused5; }; + /* This matches struct stat64 in glibc2.1, hence the absolutely * insane amounts of padding around dev_t's. * Note: The kernel zero's the padded region because glibc might read them diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h old mode 100644 new mode 100755 index cf4f3aad0..4e174b7ec --- a/arch/arm/include/asm/string.h +++ b/arch/arm/include/asm/string.h @@ -13,6 +13,7 @@ extern char * strrchr(const char * s, int c); extern char * strchr(const char * s, int c); #define __HAVE_ARCH_MEMCPY + extern void * memcpy(void *, const void *, __kernel_size_t); #define __HAVE_ARCH_MEMMOVE diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h old mode 100644 new mode 100755 index 984014b92..794c513b8 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -127,7 +127,11 @@ extern unsigned int user_debug; #if __LINUX_ARM_ARCH__ >= 7 #define isb() __asm__ __volatile__ ("isb" : : : "memory") #define dsb() __asm__ __volatile__ ("dsb" : : : "memory") +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_6075) +#define dmb() __asm__ __volatile__ ("dsb" : : : "memory") +#else #define dmb() __asm__ __volatile__ ("dmb" : : : "memory") +#endif #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") @@ -255,6 +259,26 @@ do { \ #define swp_is_buggy #endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) +static inline int atomic_backoff_delay(void) +{ +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_ADD_DELAY_FOR_STREX + unsigned int delay; + + __asm__ __volatile__( + " mrc p15, 0, %0, c0, c0, 5\n" + " and %0, %0, #0xf\n" + " mov %0, %0, lsl #8\n" + "1: subs %0, %0, #1\n" + " bpl 1b\n" + : "=&r" (delay) + : + : "cc"); +#endif + return 1; +} +#endif + static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) { extern void __bad_xchg(volatile void *, int); diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h old mode 100644 new mode 100755 index 7b5cc8dae..1d6bc8056 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -15,8 +15,13 @@ #include #include +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) #define THREAD_SIZE_ORDER 1 #define THREAD_SIZE 8192 +#else +#define THREAD_SIZE_ORDER 0 +#define THREAD_SIZE 65536 +#endif #define THREAD_START_SP (THREAD_SIZE - 8) #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h old mode 100644 new mode 100755 index 265f908c4..71f874425 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -202,8 +202,24 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, tlb_remove_page(tlb, pte); } +#if defined(CONFIG_SYNO_ARMADA_ARCH) +static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, + unsigned long addr) +{ +#ifdef CONFIG_ARM_LPAE + tlb_add_flush(tlb, addr); + tlb_remove_page(tlb, virt_to_page(pmdp)); +#endif +} +#endif + #define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr) +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#define pmd_free_tlb(tlb, pmdp, addr) __pmd_free_tlb(tlb, pmdp, addr) +#define pud_free_tlb(tlb, pudp, addr) pud_free((tlb)->mm, pudp) +#else #define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp) +#endif #define tlb_migrate_finish(mm) do { } while (0) diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h old mode 100644 new mode 100755 index 02b2f8203..e43272922 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -168,8 +168,13 @@ TLB_V6_I_ASID | TLB_V6_D_ASID) #ifdef CONFIG_CPU_TLB_V6 +#if defined(CONFIG_SYNO_ARMADA_ARCH) && (defined (CONFIG_ARCH_ARMADA_XP) && !defined (CONFIG_AURORA_L2_PT_WALK)) +# define v6wbi_possible_flags (v6wbi_tlb_flags | TLB_L2CLEAN_FR) +# define v6wbi_always_flags (v6wbi_tlb_flags | TLB_L2CLEAN_FR) +#else # define v6wbi_possible_flags v6wbi_tlb_flags # define v6wbi_always_flags v6wbi_tlb_flags +#endif # ifdef _TLB # define MULTI_TLB 1 # else @@ -215,6 +220,9 @@ #include +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_CACHE_AURORA_L2) +extern void l2_clean_pa(unsigned int pa); +#endif struct cpu_tlb_fns { void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *); void (*flush_kern_range)(unsigned long, unsigned long); @@ -471,18 +479,39 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) * these operations. This is typically used when we are removing * PMD entries. */ +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) static inline void flush_pmd_entry(void *pmd) { const unsigned int __tlb_flag = __cpu_tlb_flags; if (tlb_flag(TLB_DCLEAN)) +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_4611) + { + unsigned long flags; + raw_local_irq_save(flags); + dmb(); +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && (defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_6043) || defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_6124)) + asm("mcr p15, 0, %0, c7, c14, 1 @ flush_pmd" + : : "r" (pmd) : "cc"); +#else asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" : : "r" (pmd) : "cc"); +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_4611) + raw_local_irq_restore(flags); + } +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_CACHE_AURORA_L2) + if (tlb_flag(TLB_L2CLEAN_FR)) + l2_clean_pa(__pa((unsigned long)pmd)); +#else if (tlb_flag(TLB_L2CLEAN_FR)) asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" : : "r" (pmd) : "cc"); +#endif if (tlb_flag(TLB_WB)) dsb(); } @@ -492,14 +521,68 @@ static inline void clean_pmd_entry(void *pmd) const unsigned int __tlb_flag = __cpu_tlb_flags; if (tlb_flag(TLB_DCLEAN)) +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_4611) + { + unsigned long flags; + raw_local_irq_save(flags); + dmb(); +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && (defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_6043) || defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_6124)) + asm("mcr p15, 0, %0, c7, c14, 1 @ flush_pmd" + : : "r" (pmd) : "cc"); +#else asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" : : "r" (pmd) : "cc"); +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_SHEEVA_ERRATA_ARM_CPU_4611) + raw_local_irq_restore(flags); + } +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_CACHE_AURORA_L2) + if (tlb_flag(TLB_L2CLEAN_FR)) + l2_clean_pa(__pa((unsigned long)pmd)); +#else if (tlb_flag(TLB_L2CLEAN_FR)) asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" : : "r" (pmd) : "cc"); +#endif +} +#else +static inline void flush_pmd_entry(void *pmd) +{ + const unsigned int __tlb_flag = __cpu_tlb_flags; + char *p = (char *)pmd; + + if (tlb_flag(TLB_DCLEAN)) { + while (p < ((char *)pmd + (LINKED_PMDS * sizeof(u32)))) { // A PMD contains LINKED_PMDS pointers to the 2nd-level table + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" + : : "r" (p) : "cc"); + p += 32; //Next cache line + } + } + + if (tlb_flag(TLB_WB)) + dsb(); } +static inline void clean_pmd_entry(void *pmd) +{ + const unsigned int __tlb_flag = __cpu_tlb_flags; + char *p = (char *)pmd; + + if (tlb_flag(TLB_DCLEAN)) { + while (p < ((char *)pmd + (LINKED_PMDS * sizeof(u32)))) { // A PMD contains LINKED_PMDS pointers to the 2nd-level table + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" + : : "r" (p) : "cc"); + p += 32; //Next cache line + } + } +} + +#endif + + #undef tlb_flag #undef always_tlb_flags #undef possible_tlb_flags diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h old mode 100644 new mode 100755 index 48192ac3a..46af0d7c1 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -1,6 +1,9 @@ #ifndef __ASM_ARM_TYPES_H #define __ASM_ARM_TYPES_H +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#include +#else #include #ifndef __ASSEMBLY__ @@ -12,6 +15,8 @@ typedef unsigned short umode_t; /* * These aren't exported outside the kernel to avoid name space clashes */ +#endif + #ifdef __KERNEL__ #define BITS_PER_LONG 32 diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h old mode 100644 new mode 100755 index 4a1123783..8539d7812 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -13,6 +13,10 @@ #ifndef __ASM_ARM_UNISTD_H #define __ASM_ARM_UNISTD_H +#if 1 //SYNO +#include +#endif + #define __NR_OABI_SYSCALL_BASE 0x900000 #if defined(__thumb__) || defined(__ARM_EABI__) @@ -405,6 +409,109 @@ #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) +#ifdef MY_ABC_HERE +#define __NR_SYNOUtime (__NR_SYSCALL_BASE+402) +#define SYNOUtime(arg1, arg2) syscall(__NR_SYNOUtime, arg1, arg2) +#endif + +#ifdef MY_ABC_HERE +#define __NR_SYNOArchiveBit (__NR_SYSCALL_BASE+403) +#define SYNOArchiveBit(arg1, arg2) syscall(__NR_SYNOArchiveBit, arg1, arg2) +#endif + +#ifdef MY_ABC_HERE +#define __NR_recvfile (__NR_SYSCALL_BASE+404) +#define recvfile(arg1,arg2,arg3,arg4,arg5) syscall(__NR_recvfile,arg1,arg2,arg3,arg4,arg5) +#endif + +#ifdef MY_ABC_HERE +#define __NR_SYNOMTDAlloc (__NR_SYSCALL_BASE+405) +#define SYNOMTDAlloc(x) syscall(__NR_SYNOMTDAlloc, x) +#endif + +#ifdef MY_ABC_HERE +#define __NR_SYNOCaselessStat64 (__NR_SYSCALL_BASE+406) +#define __NR_SYNOCaselessLStat64 (__NR_SYSCALL_BASE+407) +#define __NR_SYNOCaselessStat (__NR_SYSCALL_BASE+408) +#define __NR_SYNOCaselessLStat (__NR_SYSCALL_BASE+409) + +#if !defined(__KERNEL__) +/* direct SYNOCaselessStat to stat64 in 32-bit platform + * 64-bits arch has no stat64 support */ +#include +#if __WORDSIZE == 64 +#define SYNOCaselessStat(arg1,arg2) syscall(__NR_SYNOCaselessStat , arg1,arg2) +#define SYNOCaselessLStat(arg1,arg2) syscall(__NR_SYNOCaselessLStat , arg1,arg2) +#elif (_FILE_OFFSET_BITS == 64) +#define SYNOCaselessStat(arg1,arg2) syscall(__NR_SYNOCaselessStat64 , arg1,arg2) +#define SYNOCaselessLStat(arg1,arg2) syscall(__NR_SYNOCaselessLStat64 , arg1,arg2) +#endif +/* define stat64 interface for compatibility + These should be removed after AP modification */ +#define SYNOCaselessStat64(arg1,arg2) syscall(__NR_SYNOCaselessStat64 , arg1,arg2) +#define SYNOCaselessLStat64(arg1,arg2) syscall(__NR_SYNOCaselessLStat64 , arg1,arg2) +#endif +#endif /* MY_ABC_HERE */ + +#ifdef MY_ABC_HERE +#define __NR_SYNOEcryptName (__NR_SYSCALL_BASE+410) +#define __NR_SYNODecryptName (__NR_SYSCALL_BASE+411) +#define SYNOEcryptName(arg1, arg2) syscall(__NR_SYNOEcryptName, arg1, arg2) +#define SYNODecryptName(arg1, arg2, arg3) syscall(__NR_SYNODecryptName, arg1, arg2, arg3) +#endif + +#ifdef MY_ABC_HERE +#define __NR_SYNOACLCheckPerm (__NR_SYSCALL_BASE+412) +#define SYNOACLSysCheckPerm(arg1, arg2) syscall(__NR_SYNOACLCheckPerm, arg1, arg2) +#define __NR_SYNOACLIsSupport (__NR_SYSCALL_BASE+413) +#define SYNOACLSysIsSupport(arg1, arg2, arg3) syscall(__NR_SYNOACLIsSupport, arg1, arg2, arg3) +#define __NR_SYNOACLGetPerm (__NR_SYSCALL_BASE+414) +#define SYNOACLSysGetPerm(arg1, arg2) syscall(__NR_SYNOACLGetPerm, arg1, arg2) +#endif + + +#ifdef MY_ABC_HERE +#define __NR_SYNOStat (__NR_SYSCALL_BASE+416) +#define __NR_SYNOFStat (__NR_SYSCALL_BASE+417) +#define __NR_SYNOLStat (__NR_SYSCALL_BASE+418) +#define __NR_SYNOStat64 (__NR_SYSCALL_BASE+419) +#define __NR_SYNOFStat64 (__NR_SYSCALL_BASE+420) +#define __NR_SYNOLStat64 (__NR_SYSCALL_BASE+421) + +#if !defined(__KERNEL__) +/* direct SYNOStat to stat64 in 32-bit platform + * 64-bits arch has no stat64 support */ +#include +#if __WORDSIZE == 64 +#define SYNOStat(arg1, arg2, arg3) syscall(__NR_SYNOStat, arg1, arg2, arg3) +#define SYNOFStat(arg1, arg2, arg3) syscall(__NR_SYNOFStat, arg1, arg2, arg3) +#define SYNOLStat(arg1, arg2, arg3) syscall(__NR_SYNOLStat, arg1, arg2, arg3) +#elif (_FILE_OFFSET_BITS == 64) +#define SYNOStat(arg1, arg2, arg3) syscall(__NR_SYNOStat64, arg1, arg2, arg3) +#define SYNOFStat(arg1, arg2, arg3) syscall(__NR_SYNOFStat64, arg1, arg2, arg3) +#define SYNOLStat(arg1, arg2, arg3) syscall(__NR_SYNOLStat64, arg1, arg2, arg3) +#endif +#endif /* __KERNEL__ */ + +#endif /* MY_ABC_HERE */ +#ifdef CONFIG_SYNO_NOTIFY +#define __NR_SYNONotifyInit (__NR_SYSCALL_BASE+422) +#define SYNONotifyInit(arg1) syscall(__NR_SYNONotifyInit, arg1) +#define __NR_SYNONotifyAddWatch (__NR_SYSCALL_BASE+423) +#define SYNONotifyAddWatch(arg1, arg2, arg3) syscall(__NR_SYNONotifyAddWatch, arg1, arg2, arg3) +#define __NR_SYNONotifyRemoveWatch (__NR_SYSCALL_BASE+424) +#define SYNONotifyRemoveWatch(arg1, arg2, arg3) syscall(__NR_SYNONotifyRemoveWatch, arg1, arg2, arg3) +#define __NR_SYNONotifyAddWatch32 (__NR_SYSCALL_BASE+425) +#define SYNONotifyAddWatch32(arg1, arg2, arg3) syscall(__NR_SYNONotifyAddWatch32, arg1, arg2, arg3) +#define __NR_SYNONotifyRemoveWatch32 (__NR_SYSCALL_BASE+426) +#define SYNONotifyRemoveWatch32(arg1, arg2, arg3) syscall(__NR_SYNONotifyRemoveWatch32, arg1, arg2, arg3) +#endif /* CONFIG_SYNO_NOTIFY */ + +#ifdef MY_ABC_HERE +#define __NR_SYNOArchiveOverwrite (__NR_SYSCALL_BASE+427) +#define SYNOArchiveOverwrite(arg1, arg2) syscall(__NR_SYNOArchiveOverwrite, arg1, arg2) +#endif + /* * The following SWIs are ARM private. */ diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h old mode 100644 new mode 100755 index f4ab34fd4..f20a5759b --- a/arch/arm/include/asm/vfp.h +++ b/arch/arm/include/asm/vfp.h @@ -82,3 +82,10 @@ #define VFPOPDESC_UNUSED_BIT (24) #define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT) #define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK)) + +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#ifndef __ASSEMBLY__ +extern void vfp_save(void); +extern void vfp_restore(void); +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h old mode 100644 new mode 100755 index 7604673dc..4ffb26d4c --- a/arch/arm/include/asm/xor.h +++ b/arch/arm/include/asm/xor.h @@ -7,7 +7,10 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include +#include +#include #define __XOR(a1, a2) a1 ^= a2 @@ -138,4 +141,74 @@ static struct xor_block_template xor_block_arm4regs = { xor_speed(&xor_block_arm4regs); \ xor_speed(&xor_block_8regs); \ xor_speed(&xor_block_32regs); \ + NEON_TEMPLATES; \ } while (0) + +#ifdef CONFIG_KERNEL_MODE_NEON + +extern struct xor_block_template const xor_block_neon_inner; + +static void +xor_neon_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) +{ + if (in_interrupt()) { + xor_arm4regs_2(bytes, p1, p2); + } else { + kernel_neon_begin(); + xor_block_neon_inner.do_2(bytes, p1, p2); + kernel_neon_end(); + } +} + +static void +xor_neon_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, + unsigned long *p3) +{ + if (in_interrupt()) { + xor_arm4regs_3(bytes, p1, p2, p3); + } else { + kernel_neon_begin(); + xor_block_neon_inner.do_3(bytes, p1, p2, p3); + kernel_neon_end(); + } +} + +static void +xor_neon_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, + unsigned long *p3, unsigned long *p4) +{ + if (in_interrupt()) { + xor_arm4regs_4(bytes, p1, p2, p3, p4); + } else { + kernel_neon_begin(); + xor_block_neon_inner.do_4(bytes, p1, p2, p3, p4); + kernel_neon_end(); + } +} + +static void +xor_neon_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, + unsigned long *p3, unsigned long *p4, unsigned long *p5) +{ + if (in_interrupt()) { + xor_arm4regs_5(bytes, p1, p2, p3, p4, p5); + } else { + kernel_neon_begin(); + xor_block_neon_inner.do_5(bytes, p1, p2, p3, p4, p5); + kernel_neon_end(); + } +} + +static struct xor_block_template xor_block_neon = { + .name = "neon", + .do_2 = xor_neon_2, + .do_3 = xor_neon_3, + .do_4 = xor_neon_4, + .do_5 = xor_neon_5 +}; + +#define NEON_TEMPLATES \ + do { if (cpu_has_neon()) xor_speed(&xor_block_neon); } while (0) +#else +#define NEON_TEMPLATES +#endif diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile old mode 100644 new mode 100755 index 16eed6aeb..3daee56c7 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -12,10 +12,21 @@ endif CFLAGS_REMOVE_return_address.o = -pg # Object file lists. +ifeq ($(CONFIG_SYNO_ARMADA_ARCH),y) +ifneq ($(MACHINE),) +include $(srctree)/$(MACHINE)/config/mvRules.mk +endif +endif +ifeq ($(CONFIG_SYNO_ARMADA_ARCH),y) +obj-y := elf.o entry-armv-armada.o entry-common-armada.o irq.o \ + process.o ptrace.o return_address.o setup.o signal.o \ + sys_arm.o stacktrace.o time.o traps.o +else obj-y := elf.o entry-armv.o entry-common.o irq.o \ process.o ptrace.o return_address.o setup.o signal.o \ sys_arm.o stacktrace.o time.o traps.o +endif obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c old mode 100644 new mode 100755 index b530e9116..ad673da63 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -12,7 +12,6 @@ #include #include -#include #include static int debug_pci; diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S old mode 100644 new mode 100755 index 463ff4a0e..e0e8b9b51 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -9,6 +9,7 @@ * * This file is included thrice in entry-common.S */ + /* 0 */ CALL(sys_restart_syscall) CALL(sys_exit) CALL(sys_fork_wrapper) @@ -387,6 +388,114 @@ /* 375 */ CALL(sys_setns) CALL(sys_process_vm_readv) CALL(sys_process_vm_writev) +#ifdef MY_ABC_HERE + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +/* 380 */ CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +/* 385 */ CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +/* 390 */ CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +/* 395 */ CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +#ifdef MY_ABC_HERE + CALL(sys_SYNOUtime) /* 402 */ +#else + CALL(sys_ni_syscall) +#endif +#ifdef MY_ABC_HERE + CALL(sys_SYNOArchiveBit) /* 403 */ +#else + CALL(sys_ni_syscall) +#endif +#ifdef MY_ABC_HERE + CALL(sys_recvfile) /* 404 */ +#else + CALL(sys_ni_syscall) +#endif +#ifdef MY_ABC_HERE + CALL(sys_SYNOMTDAlloc) /* 405 */ +#else + CALL(sys_ni_syscall) +#endif +#ifdef MY_ABC_HERE + CALL(sys_SYNOCaselessStat64) /* 406 */ + CALL(sys_SYNOCaselessLStat64) /* 407 */ + CALL(sys_SYNOCaselessStat) /* 408 */ + CALL(sys_SYNOCaselessLStat) /* 409 */ +#else + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +#endif +#ifdef MY_ABC_HERE + CALL(sys_SYNOEcryptName) /* 410 */ + CALL(sys_SYNODecryptName) /* 411 */ +#else + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +#endif +#endif +#ifdef CONFIG_FS_SYNO_ACL + CALL(sys_SYNOACLCheckPerm) /* 412 */ + CALL(sys_SYNOACLIsSupport) /* 413 */ + CALL(sys_SYNOACLGetPerm) /* 414 */ +#else + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +#endif + CALL(sys_ni_syscall) +#ifdef MY_ABC_HERE + CALL(sys_SYNOStat) /* 416 */ + CALL(sys_SYNOFStat) /* 417 */ + CALL(sys_SYNOLStat) /* 418 */ + CALL(sys_SYNOStat64) /* 419 */ + CALL(sys_SYNOFStat64) /* 420 */ + CALL(sys_SYNOLStat64) /* 421 */ +#else + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +#endif /* MY_ABC_HERE */ +#ifdef CONFIG_SYNO_NOTIFY + CALL(sys_SYNONotifyInit) /* 422 */ + CALL(sys_SYNONotifyAddWatch) /* 423 */ + CALL(sys_SYNONotifyRemoveWatch) /* 424 */ + CALL(sys_SYNONotifyAddWatch32) /* 425 */ + CALL(sys_SYNONotifyRemoveWatch32) /* 426 */ +#else + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) + CALL(sys_ni_syscall) +#endif /* CONFIG_SYNO_NOTIFY */ +#ifdef MY_ABC_HERE + CALL(sys_SYNOArchiveOverwrite) /* 427 */ +#else + CALL(sys_ni_syscall) +#endif + #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/entry-armv-armada.S b/arch/arm/kernel/entry-armv-armada.S new file mode 100755 index 000000000..d1ba84e01 --- /dev/null +++ b/arch/arm/kernel/entry-armv-armada.S @@ -0,0 +1,1228 @@ +/* + * linux/arch/arm/kernel/entry-armv.S + * + * Copyright (C) 1996,1997,1998 Russell King. + * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) + * nommu support by Hyok S. Choi (hyok.choi@samsung.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Low-level vector interface routines + * + * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction + * that causes it to save wrong values... Be aware! + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "entry-header.S" +#include + +/* + * Interrupt handling. + */ + .macro irq_handler +#ifdef CONFIG_MULTI_IRQ_HANDLER + ldr r1, =handle_arch_irq + mov r0, sp + ldr r1, [r1] + adr lr, BSYM(9997f) + teq r1, #0 + movne pc, r1 +#endif + arch_irq_handler_default +9997: + .endm + + .macro pabt_helper + @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 +#ifdef MULTI_PABORT + ldr ip, .LCprocfns + mov lr, pc + ldr pc, [ip, #PROCESSOR_PABT_FUNC] +#else + bl CPU_PABORT_HANDLER +#endif + .endm + + .macro dabt_helper + + @ + @ Call the processor-specific abort handler: + @ + @ r2 - pt_regs + @ r4 - aborted context pc + @ r5 - aborted context psr + @ + @ The abort handler must return the aborted address in r0, and + @ the fault status register in r1. r9 must be preserved. + @ +#ifdef MULTI_DABORT + ldr ip, .LCprocfns + mov lr, pc + ldr pc, [ip, #PROCESSOR_DABT_FUNC] +#else + bl CPU_DABORT_HANDLER +#endif + .endm + +#ifdef CONFIG_KPROBES + .section .kprobes.text,"ax",%progbits +#else + .text +#endif + +/* + * Invalid mode handlers + */ + .macro inv_entry, reason + sub sp, sp, #S_FRAME_SIZE + ARM( stmib sp, {r1 - lr} ) + THUMB( stmia sp, {r0 - r12} ) + THUMB( str sp, [sp, #S_SP] ) + THUMB( str lr, [sp, #S_LR] ) + mov r1, #\reason + .endm + +__pabt_invalid: + inv_entry BAD_PREFETCH + b common_invalid +ENDPROC(__pabt_invalid) + +__dabt_invalid: + inv_entry BAD_DATA + b common_invalid +ENDPROC(__dabt_invalid) + +__irq_invalid: + inv_entry BAD_IRQ + b common_invalid +ENDPROC(__irq_invalid) + +__und_invalid: + inv_entry BAD_UNDEFINSTR + + @ + @ XXX fall through to common_invalid + @ + +@ +@ common_invalid - generic code for failed exception (re-entrant version of handlers) +@ +common_invalid: + zero_fp + + ldmia r0, {r4 - r6} + add r0, sp, #S_PC @ here for interlock avoidance + mov r7, #-1 @ "" "" "" "" + str r4, [sp] @ save preserved r0 + stmia r0, {r5 - r7} @ lr_, + @ cpsr_, "old_r0" + + mov r0, sp + b bad_mode +ENDPROC(__und_invalid) + +/* + * SVC mode handlers + */ + +#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) +#define SPFIX(code...) code +#else +#define SPFIX(code...) +#endif + + .macro svc_entry, stack_hole=0 + UNWIND(.fnstart ) + UNWIND(.save {r0 - pc} ) + sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) +#ifdef CONFIG_THUMB2_KERNEL + SPFIX( str r0, [sp] ) @ temporarily saved + SPFIX( mov r0, sp ) + SPFIX( tst r0, #4 ) @ test original stack alignment + SPFIX( ldr r0, [sp] ) @ restored +#else + SPFIX( tst sp, #4 ) +#endif + SPFIX( subeq sp, sp, #4 ) + stmia sp, {r1 - r12} + + ldmia r0, {r3 - r5} + add r7, sp, #S_SP - 4 @ here for interlock avoidance + mov r6, #-1 @ "" "" "" "" + add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) + SPFIX( addeq r2, r2, #4 ) + str r3, [sp, #-4]! @ save the "real" r0 copied + @ from the exception stack + + mov r3, lr + + @ + @ We are now ready to fill in the remaining blanks on the stack: + @ + @ r2 - sp_svc + @ r3 - lr_svc + @ r4 - lr_, already fixed up for correct return/restart + @ r5 - spsr_ + @ r6 - orig_r0 (see pt_regs definition in ptrace.h) + @ + stmia r7, {r2 - r6} + +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif + .endm + + .align 5 +__dabt_svc: + svc_entry + mov r2, sp + dabt_helper + + @ + @ IRQs off again before pulling preserved data off the stack + @ + disable_irq_notrace + +#ifdef CONFIG_TRACE_IRQFLAGS + tst r5, #PSR_I_BIT + bleq trace_hardirqs_on + tst r5, #PSR_I_BIT + blne trace_hardirqs_off +#endif + svc_exit r5 @ return from exception + UNWIND(.fnend ) +ENDPROC(__dabt_svc) + + .align 5 +__irq_svc: + svc_entry + irq_handler + +#ifdef CONFIG_PREEMPT + get_thread_info tsk + ldr r8, [tsk, #TI_PREEMPT] @ get preempt count + ldr r0, [tsk, #TI_FLAGS] @ get flags + teq r8, #0 @ if preempt count != 0 + movne r0, #0 @ force flags to 0 + tst r0, #_TIF_NEED_RESCHED + blne svc_preempt +#endif + +#ifdef CONFIG_TRACE_IRQFLAGS + @ The parent context IRQs must have been enabled to get here in + @ the first place, so there's no point checking the PSR I bit. + bl trace_hardirqs_on +#endif + svc_exit r5 @ return from exception + UNWIND(.fnend ) +ENDPROC(__irq_svc) + + .ltorg + +#ifdef CONFIG_PREEMPT +svc_preempt: + mov r8, lr +1: bl preempt_schedule_irq @ irq en/disable is done inside + ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS + tst r0, #_TIF_NEED_RESCHED + moveq pc, r8 @ go again + b 1b +#endif + +__und_fault: + @ Correct the PC such that it is pointing at the instruction + @ which caused the fault. If the faulting instruction was ARM + @ the PC will be pointing at the next instruction, and have to + @ subtract 4. Otherwise, it is Thumb, and the PC will be + @ pointing at the second half of the Thumb instruction. We + @ have to subtract 2. + ldr r2, [r0, #S_PC] + sub r2, r2, r1 + str r2, [r0, #S_PC] + b do_undefinstr +ENDPROC(__und_fault) + + .align 5 +__und_svc: +#ifdef CONFIG_KPROBES + @ If a kprobe is about to simulate a "stmdb sp..." instruction, + @ it obviously needs free stack space which then will belong to + @ the saved context. + svc_entry 64 +#else + svc_entry +#endif + @ + @ call emulation code, which returns using r9 if it has emulated + @ the instruction, or the more conventional lr if we are to treat + @ this as a real undefined instruction + @ + @ r0 - instruction + @ +#ifndef CONFIG_THUMB2_KERNEL + ldr r0, [r4, #-4] +#else + mov r1, #2 + ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 + cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 + blo __und_svc_fault + ldrh r9, [r4] @ bottom 16 bits + add r4, r4, #2 + str r4, [sp, #S_PC] + orr r0, r9, r0, lsl #16 +#endif + adr r9, BSYM(__und_svc_finish) + mov r2, r4 + bl call_fpe + + mov r1, #4 @ PC correction to apply +__und_svc_fault: + mov r0, sp @ struct pt_regs *regs + bl __und_fault + + @ + @ IRQs off again before pulling preserved data off the stack + @ +__und_svc_finish: + disable_irq_notrace + + @ + @ restore SPSR and restart the instruction + @ + ldr r5, [sp, #S_PSR] @ Get SVC cpsr +#ifdef CONFIG_TRACE_IRQFLAGS + tst r5, #PSR_I_BIT + bleq trace_hardirqs_on + tst r5, #PSR_I_BIT + blne trace_hardirqs_off +#endif + svc_exit r5 @ return from exception + UNWIND(.fnend ) +ENDPROC(__und_svc) + + .align 5 +__pabt_svc: + svc_entry + mov r2, sp @ regs + pabt_helper + + @ + @ IRQs off again before pulling preserved data off the stack + @ + disable_irq_notrace + +#ifdef CONFIG_TRACE_IRQFLAGS + tst r5, #PSR_I_BIT + bleq trace_hardirqs_on + tst r5, #PSR_I_BIT + blne trace_hardirqs_off +#endif + svc_exit r5 @ return from exception + UNWIND(.fnend ) +ENDPROC(__pabt_svc) + + .align 5 +.LCcralign: + .word cr_alignment +#ifdef MULTI_DABORT +.LCprocfns: + .word processor +#endif +.LCfp: + .word fp_enter + +/* + * User mode handlers + * + * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE + */ + +#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) +#error "sizeof(struct pt_regs) must be a multiple of 8" +#endif + + .macro usr_entry + UNWIND(.fnstart ) + UNWIND(.cantunwind ) @ don't unwind the user space + sub sp, sp, #S_FRAME_SIZE + ARM( stmib sp, {r1 - r12} ) + THUMB( stmia sp, {r0 - r12} ) + + ldmia r0, {r3 - r5} + add r0, sp, #S_PC @ here for interlock avoidance + mov r6, #-1 @ "" "" "" "" + + str r3, [sp] @ save the "real" r0 copied + @ from the exception stack + + @ + @ We are now ready to fill in the remaining blanks on the stack: + @ + @ r4 - lr_, already fixed up for correct return/restart + @ r5 - spsr_ + @ r6 - orig_r0 (see pt_regs definition in ptrace.h) + @ + @ Also, separately save sp_usr and lr_usr + @ + stmia r0, {r4 - r6} + ARM( stmdb r0, {sp, lr}^ ) + THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) + + @ + @ Enable the alignment trap while in kernel mode + @ + alignment_trap r0 + + @ + @ Clear FP to mark the first stack frame + @ + zero_fp + +#ifdef CONFIG_IRQSOFF_TRACER + bl trace_hardirqs_off +#endif + .endm + + .macro kuser_cmpxchg_check +#if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) +#ifndef CONFIG_MMU +#warning "NPTL on non MMU needs fixing" +#else + @ Make sure our user space atomic helper is restarted + @ if it was interrupted in a critical region. Here we + @ perform a quick test inline since it should be false + @ 99.9999% of the time. The rest is done out of line. + cmp r4, #TASK_SIZE + blhs kuser_cmpxchg64_fixup +#endif +#endif + .endm + + .align 5 +__dabt_usr: + usr_entry + kuser_cmpxchg_check + mov r2, sp + dabt_helper + b ret_from_exception + UNWIND(.fnend ) +ENDPROC(__dabt_usr) + + .align 5 +__irq_usr: + usr_entry + kuser_cmpxchg_check + irq_handler + get_thread_info tsk + mov why, #0 + b ret_to_user_from_irq + UNWIND(.fnend ) +ENDPROC(__irq_usr) + + .ltorg + + .align 5 +__und_usr: + usr_entry + + mov r2, r4 + mov r3, r5 + + @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the + @ faulting instruction depending on Thumb mode. + @ r3 = regs->ARM_cpsr + @ + @ The emulation code returns using r9 if it has emulated the + @ instruction, or the more conventional lr if we are to treat + @ this as a real undefined instruction + @ + adr r9, BSYM(ret_from_exception) + + tst r3, #PSR_T_BIT @ Thumb mode? + bne __und_usr_thumb + sub r4, r2, #4 @ ARM instr at LR - 4 +1: ldrt r0, [r4] +#ifdef CONFIG_CPU_ENDIAN_BE8 + rev r0, r0 @ little endian instruction +#endif + @ r0 = 32-bit ARM instruction which caused the exception + @ r2 = PC value for the following instruction (:= regs->ARM_pc) + @ r4 = PC value for the faulting instruction + @ lr = 32-bit undefined instruction function + adr lr, BSYM(__und_usr_fault_32) + b call_fpe + +__und_usr_thumb: + @ Thumb instruction + sub r4, r2, #2 @ First half of thumb instr at LR - 2 +#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 +/* + * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms + * can never be supported in a single kernel, this code is not applicable at + * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be + * made about .arch directives. + */ +#if __LINUX_ARM_ARCH__ < 7 +/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ +#define NEED_CPU_ARCHITECTURE + ldr r5, .LCcpu_architecture + ldr r5, [r5] + cmp r5, #CPU_ARCH_ARMv7 + blo __und_usr_fault_16 @ 16bit undefined instruction +/* + * The following code won't get run unless the running CPU really is v7, so + * coding round the lack of ldrht on older arches is pointless. Temporarily + * override the assembler target arch with the minimum required instead: + */ + .arch armv6t2 +#endif +2: ldrht r5, [r4] + cmp r5, #0xe800 @ 32bit instruction if xx != 0 + blo __und_usr_fault_16 @ 16bit undefined instruction +3: ldrht r0, [r2] + add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 + str r2, [sp, #S_PC] @ it's a 2x16bit instr, update + orr r0, r0, r5, lsl #16 + adr lr, BSYM(__und_usr_fault_32) + @ r0 = the two 16-bit Thumb instructions which caused the exception + @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) + @ r4 = PC value for the first 16-bit Thumb instruction + @ lr = 32bit undefined instruction function + +#if __LINUX_ARM_ARCH__ < 7 +/* If the target arch was overridden, change it back: */ +#ifdef CONFIG_CPU_32v6K + .arch armv6k +#else + .arch armv6 +#endif +#endif /* __LINUX_ARM_ARCH__ < 7 */ +#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ + b __und_usr_fault_16 +#endif + UNWIND(.fnend) +ENDPROC(__und_usr) + +/* + * The out of line fixup for the ldrt instructions above. + */ + .pushsection .fixup, "ax" +4: mov pc, r9 + .popsection + .pushsection __ex_table,"a" + .long 1b, 4b +#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 + .long 2b, 4b + .long 3b, 4b +#endif + .popsection + +/* + * Check whether the instruction is a co-processor instruction. + * If yes, we need to call the relevant co-processor handler. + * + * Note that we don't do a full check here for the co-processor + * instructions; all instructions with bit 27 set are well + * defined. The only instructions that should fault are the + * co-processor instructions. However, we have to watch out + * for the ARM6/ARM7 SWI bug. + * + * NEON is a special case that has to be handled here. Not all + * NEON instructions are co-processor instructions, so we have + * to make a special case of checking for them. Plus, there's + * five groups of them, so we have a table of mask/opcode pairs + * to check against, and if any match then we branch off into the + * NEON handler code. + * + * Emulators may wish to make use of the following registers: + * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) + * r2 = PC value to resume execution after successful emulation + * r9 = normal "successful" return address + * r10 = this threads thread_info structure + * lr = unrecognised instruction return address + * IRQs disabled, FIQs enabled. + */ + @ + @ Fall-through from Thumb-2 __und_usr + @ +#ifdef CONFIG_NEON + adr r6, .LCneon_thumb_opcodes + b 2f +#endif +call_fpe: +#ifdef CONFIG_NEON + adr r6, .LCneon_arm_opcodes +2: + ldr r7, [r6], #4 @ mask value + cmp r7, #0 @ end mask? + beq 1f + and r8, r0, r7 + ldr r7, [r6], #4 @ opcode bits matching in mask + cmp r8, r7 @ NEON instruction? + bne 2b + get_thread_info r10 + mov r7, #1 + strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used + strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used + b do_vfp @ let VFP handler handle this +1: +#endif + tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 + tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 +#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) + and r8, r0, #0x0f000000 @ mask out op-code bits + teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? +#endif + moveq pc, lr + get_thread_info r10 @ get current thread + and r8, r0, #0x00000f00 @ mask out CP number + THUMB( lsr r8, r8, #8 ) + mov r7, #1 + add r6, r10, #TI_USED_CP + ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] + THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] +#ifdef CONFIG_IWMMXT + @ Test if we need to give access to iWMMXt coprocessors + ldr r5, [r10, #TI_FLAGS] + rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only + movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) + bcs iwmmxt_task_enable +#endif + ARM( add pc, pc, r8, lsr #6 ) + THUMB( lsl r8, r8, #2 ) + THUMB( add pc, r8 ) + nop + + movw_pc lr @ CP#0 + W(b) do_fpe @ CP#1 (FPE) + W(b) do_fpe @ CP#2 (FPE) + movw_pc lr @ CP#3 +#ifdef CONFIG_CRUNCH + b crunch_task_enable @ CP#4 (MaverickCrunch) + b crunch_task_enable @ CP#5 (MaverickCrunch) + b crunch_task_enable @ CP#6 (MaverickCrunch) +#else + movw_pc lr @ CP#4 + movw_pc lr @ CP#5 + movw_pc lr @ CP#6 +#endif + movw_pc lr @ CP#7 + movw_pc lr @ CP#8 + movw_pc lr @ CP#9 +#ifdef CONFIG_VFP + W(b) do_vfp @ CP#10 (VFP) + W(b) do_vfp @ CP#11 (VFP) +#else + movw_pc lr @ CP#10 (VFP) + movw_pc lr @ CP#11 (VFP) +#endif + movw_pc lr @ CP#12 + movw_pc lr @ CP#13 + movw_pc lr @ CP#14 (Debug) + movw_pc lr @ CP#15 (Control) + +#ifdef NEED_CPU_ARCHITECTURE + .align 2 +.LCcpu_architecture: + .word __cpu_architecture +#endif + +#ifdef CONFIG_NEON + .align 6 + +.LCneon_arm_opcodes: + .word 0xfe000000 @ mask + .word 0xf2000000 @ opcode + + .word 0xff100000 @ mask + .word 0xf4000000 @ opcode + + .word 0x00000000 @ mask + .word 0x00000000 @ opcode + +.LCneon_thumb_opcodes: + .word 0xef000000 @ mask + .word 0xef000000 @ opcode + + .word 0xff100000 @ mask + .word 0xf9000000 @ opcode + + .word 0x00000000 @ mask + .word 0x00000000 @ opcode +#endif + +do_fpe: + enable_irq + ldr r4, .LCfp + add r10, r10, #TI_FPSTATE @ r10 = workspace + ldr pc, [r4] @ Call FP module USR entry point + +/* + * The FP module is called with these registers set: + * r0 = instruction + * r2 = PC+4 + * r9 = normal "successful" return address + * r10 = FP workspace + * lr = unrecognised FP instruction return address + */ + + .pushsection .data +ENTRY(fp_enter) + .word no_fp + .popsection + +ENTRY(no_fp) + mov pc, lr +ENDPROC(no_fp) + +__und_usr_fault_32: + mov r1, #4 + b 1f +__und_usr_fault_16: + mov r1, #2 +1: enable_irq + mov r0, sp + adr lr, BSYM(ret_from_exception) + b __und_fault +ENDPROC(__und_usr_fault_32) +ENDPROC(__und_usr_fault_16) + + .align 5 +__pabt_usr: + usr_entry + mov r2, sp @ regs + pabt_helper + UNWIND(.fnend ) + /* fall through */ +/* + * This is the return code to user mode for abort handlers + */ +ENTRY(ret_from_exception) + UNWIND(.fnstart ) + UNWIND(.cantunwind ) + get_thread_info tsk + mov why, #0 + b ret_to_user + UNWIND(.fnend ) +ENDPROC(__pabt_usr) +ENDPROC(ret_from_exception) + +/* + * Register switch for ARMv3 and ARMv4 processors + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info + * previous and next are guaranteed not to be the same. + */ +ENTRY(__switch_to) + UNWIND(.fnstart ) + UNWIND(.cantunwind ) + add ip, r1, #TI_CPU_SAVE + ldr r3, [r2, #TI_TP_VALUE] + ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack + THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack + THUMB( str sp, [ip], #4 ) + THUMB( str lr, [ip], #4 ) +#ifdef CONFIG_CPU_USE_DOMAINS + ldr r6, [r2, #TI_CPU_DOMAIN] +#endif + set_tls r3, r4, r5 +#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) + ldr r7, [r2, #TI_TASK] + ldr r8, =__stack_chk_guard + ldr r7, [r7, #TSK_STACK_CANARY] +#endif +#ifdef CONFIG_CPU_USE_DOMAINS + mcr p15, 0, r6, c3, c0, 0 @ Set domain register +#endif + mov r5, r0 + add r4, r2, #TI_CPU_SAVE + ldr r0, =thread_notify_head + mov r1, #THREAD_NOTIFY_SWITCH + bl atomic_notifier_call_chain +#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) + str r7, [r8] +#endif + THUMB( mov ip, r4 ) + mov r0, r5 + ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously + THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously + THUMB( ldr sp, [ip], #4 ) + THUMB( ldr pc, [ip] ) + UNWIND(.fnend ) +ENDPROC(__switch_to) + + __INIT + +/* + * User helpers. + * + * Each segment is 32-byte aligned and will be moved to the top of the high + * vector page. New segments (if ever needed) must be added in front of + * existing ones. This mechanism should be used only for things that are + * really small and justified, and not be abused freely. + * + * See Documentation/arm/kernel_user_helpers.txt for formal definitions. + */ + THUMB( .arm ) + + .macro usr_ret, reg +#ifdef CONFIG_ARM_THUMB + bx \reg +#else + mov pc, \reg +#endif + .endm + + .align 5 + .globl __kuser_helper_start +__kuser_helper_start: + +#ifdef CONFIG_ARMADA_XP_A0_WITH_B0 +/* + * Due to the sheeva arm errata 6075 - DMB must be replaced with DSB when using revision A0 of the Armada-XP + * In order to make the revision check on runtime, we added the following functions that implement the custom memory barrier + */ +__kuser_memory_barrier_errata_6075_1: @ 0xffff0f20 + ldr r3, [pc, #0x1C] + teqeq r3, #0x2 @ MV_78XX0_B0_REV + beq 1f + dsb + b errata_6075_barrier_return +1: dmb + b errata_6075_barrier_return + .word 0 + + .align 5 + +__kuser_memory_barrier_errata_6075_2: @ 0xffff0f40 + ldr r3, [pc, #0x1C] + teqeq r3, #0x2 @ MV_78XX0_B0_REV + beq 1f + dsb + usr_ret lr +1: dmb + usr_ret lr + .word 0 + .align 5 +#endif + +__kuser_cmpxchg64: @ 0xffff0f60 + +#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) + + /* + * Poor you. No fast solution possible... + * The kernel itself must perform the operation. + * A special ghost syscall is used for that (see traps.c). + */ + stmfd sp!, {r7, lr} + ldr r7, 1f @ it's 20 bits + swi __ARM_NR_cmpxchg64 + ldmfd sp!, {r7, pc} +1: .word __ARM_NR_cmpxchg64 + +#elif defined(CONFIG_CPU_32v6K) + + stmfd sp!, {r4, r5, r6, r7} + ldrd r4, r5, [r0] @ load old val + ldrd r6, r7, [r1] @ load new val + smp_dmb arm +1: ldrexd r0, r1, [r2] @ load current val + eors r3, r0, r4 @ compare with oldval (1) + eoreqs r3, r1, r5 @ compare with oldval (2) + strexdeq r3, r6, r7, [r2] @ store newval if eq + teqeq r3, #1 @ success? + beq 1b @ if no then retry + smp_dmb arm + rsbs r0, r3, #0 @ set returned val and C flag + ldmfd sp!, {r4, r5, r6, r7} + bx lr + +#elif !defined(CONFIG_SMP) + +#ifdef CONFIG_MMU + + /* + * The only thing that can break atomicity in this cmpxchg64 + * implementation is either an IRQ or a data abort exception + * causing another process/thread to be scheduled in the middle of + * the critical sequence. The same strategy as for cmpxchg is used. + */ + stmfd sp!, {r4, r5, r6, lr} + ldmia r0, {r4, r5} @ load old val + ldmia r1, {r6, lr} @ load new val +1: ldmia r2, {r0, r1} @ load current val + eors r3, r0, r4 @ compare with oldval (1) + eoreqs r3, r1, r5 @ compare with oldval (2) +2: stmeqia r2, {r6, lr} @ store newval if eq + rsbs r0, r3, #0 @ set return val and C flag + ldmfd sp!, {r4, r5, r6, pc} + + .text +kuser_cmpxchg64_fixup: + @ Called from kuser_cmpxchg_fixup. + @ r4 = address of interrupted insn (must be preserved). + @ sp = saved regs. r7 and r8 are clobbered. + @ 1b = first critical insn, 2b = last critical insn. + @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. + mov r7, #0xffff0fff + sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) + subs r8, r4, r7 + rsbcss r8, r8, #(2b - 1b) + strcs r7, [sp, #S_PC] +#if __LINUX_ARM_ARCH__ < 6 + bcc kuser_cmpxchg32_fixup +#endif + mov pc, lr + .previous + +#else +#warning "NPTL on non MMU needs fixing" + mov r0, #-1 + adds r0, r0, #0 + usr_ret lr +#endif + +#else +#error "incoherent kernel configuration" +#endif + + /* pad to next slot */ + .rept (16 - (. - __kuser_cmpxchg64)/4) + .word 0 + .endr + + .align 5 + +__kuser_memory_barrier: @ 0xffff0fa0 + smp_dmb arm + usr_ret lr + + .align 5 + +__kuser_cmpxchg: @ 0xffff0fc0 + +#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) + + /* + * Poor you. No fast solution possible... + * The kernel itself must perform the operation. + * A special ghost syscall is used for that (see traps.c). + */ + stmfd sp!, {r7, lr} + ldr r7, 1f @ it's 20 bits + swi __ARM_NR_cmpxchg + ldmfd sp!, {r7, pc} +1: .word __ARM_NR_cmpxchg + +#elif __LINUX_ARM_ARCH__ < 6 + +#ifdef CONFIG_MMU + + /* + * The only thing that can break atomicity in this cmpxchg + * implementation is either an IRQ or a data abort exception + * causing another process/thread to be scheduled in the middle + * of the critical sequence. To prevent this, code is added to + * the IRQ and data abort exception handlers to set the pc back + * to the beginning of the critical section if it is found to be + * within that critical section (see kuser_cmpxchg_fixup). + */ +1: ldr r3, [r2] @ load current val + subs r3, r3, r0 @ compare with oldval +2: streq r1, [r2] @ store newval if eq + rsbs r0, r3, #0 @ set return val and C flag + usr_ret lr + + .text +kuser_cmpxchg32_fixup: + @ Called from kuser_cmpxchg_check macro. + @ r4 = address of interrupted insn (must be preserved). + @ sp = saved regs. r7 and r8 are clobbered. + @ 1b = first critical insn, 2b = last critical insn. + @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. + mov r7, #0xffff0fff + sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) + subs r8, r4, r7 + rsbcss r8, r8, #(2b - 1b) + strcs r7, [sp, #S_PC] + mov pc, lr + .previous + +#else +#warning "NPTL on non MMU needs fixing" + mov r0, #-1 + adds r0, r0, #0 + usr_ret lr +#endif + +#else + +#ifdef CONFIG_ARMADA_XP_A0_WITH_B0 + ALT_SMP(b __kuser_memory_barrier_errata_6075_1) +#else + smp_dmb arm +#endif + +errata_6075_barrier_return: + ldrex r3, [r2] + subs r3, r3, r0 + strexeq r3, r1, [r2] + teqeq r3, #1 + beq errata_6075_barrier_return + rsbs r0, r3, #0 + /* beware -- each __kuser slot must be 8 instructions max */ +#ifdef CONFIG_ARMADA_XP_A0_WITH_B0 + ALT_SMP(b __kuser_memory_barrier_errata_6075_2) +#else + ALT_SMP(b __kuser_memory_barrier) +#endif + ALT_UP(usr_ret lr) + +#endif + + .align 5 + +__kuser_get_tls: @ 0xffff0fe0 + ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init + usr_ret lr + mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code + .rep 4 + .word 0 @ 0xffff0ff0 software TLS value, then + .endr @ pad up to __kuser_helper_version + +__kuser_helper_version: @ 0xffff0ffc + .word ((__kuser_helper_end - __kuser_helper_start) >> 5) + + .globl __kuser_helper_end +__kuser_helper_end: + + THUMB( .thumb ) + +/* + * Vector stubs. + * + * This code is copied to 0xffff0200 so we can use branches in the + * vectors, rather than ldr's. Note that this code must not + * exceed 0x300 bytes. + * + * Common stub entry macro: + * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC + * + * SP points to a minimal amount of processor-private memory, the address + * of which is copied into r0 for the mode specific abort handler. + */ + .macro vector_stub, name, mode, correction=0 + .align 5 + +vector_\name: + .if \correction + sub lr, lr, #\correction + .endif + + @ + @ Save r0, lr_ (parent PC) and spsr_ + @ (parent CPSR) + @ + stmia sp, {r0, lr} @ save r0, lr + mrs lr, spsr + str lr, [sp, #8] @ save spsr + + @ + @ Prepare for SVC32 mode. IRQs remain disabled. + @ + mrs r0, cpsr + eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) + msr spsr_cxsf, r0 + + @ + @ the branch table must immediately follow this code + @ + and lr, lr, #0x0f + THUMB( adr r0, 1f ) + THUMB( ldr lr, [r0, lr, lsl #2] ) + mov r0, sp + ARM( ldr lr, [pc, lr, lsl #2] ) + movs pc, lr @ branch to handler in SVC mode +ENDPROC(vector_\name) + + .align 2 + @ handler addresses follow this label +1: + .endm + + .globl __stubs_start +__stubs_start: +/* + * Interrupt dispatcher + */ + vector_stub irq, IRQ_MODE, 4 + + .long __irq_usr @ 0 (USR_26 / USR_32) + .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) + .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) + .long __irq_svc @ 3 (SVC_26 / SVC_32) + .long __irq_invalid @ 4 + .long __irq_invalid @ 5 + .long __irq_invalid @ 6 + .long __irq_invalid @ 7 + .long __irq_invalid @ 8 + .long __irq_invalid @ 9 + .long __irq_invalid @ a + .long __irq_invalid @ b + .long __irq_invalid @ c + .long __irq_invalid @ d + .long __irq_invalid @ e + .long __irq_invalid @ f + +/* + * Data abort dispatcher + * Enter in ABT mode, spsr = USR CPSR, lr = USR PC + */ + vector_stub dabt, ABT_MODE, 8 + + .long __dabt_usr @ 0 (USR_26 / USR_32) + .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) + .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) + .long __dabt_svc @ 3 (SVC_26 / SVC_32) + .long __dabt_invalid @ 4 + .long __dabt_invalid @ 5 + .long __dabt_invalid @ 6 + .long __dabt_invalid @ 7 + .long __dabt_invalid @ 8 + .long __dabt_invalid @ 9 + .long __dabt_invalid @ a + .long __dabt_invalid @ b + .long __dabt_invalid @ c + .long __dabt_invalid @ d + .long __dabt_invalid @ e + .long __dabt_invalid @ f + +/* + * Prefetch abort dispatcher + * Enter in ABT mode, spsr = USR CPSR, lr = USR PC + */ + vector_stub pabt, ABT_MODE, 4 + + .long __pabt_usr @ 0 (USR_26 / USR_32) + .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) + .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) + .long __pabt_svc @ 3 (SVC_26 / SVC_32) + .long __pabt_invalid @ 4 + .long __pabt_invalid @ 5 + .long __pabt_invalid @ 6 + .long __pabt_invalid @ 7 + .long __pabt_invalid @ 8 + .long __pabt_invalid @ 9 + .long __pabt_invalid @ a + .long __pabt_invalid @ b + .long __pabt_invalid @ c + .long __pabt_invalid @ d + .long __pabt_invalid @ e + .long __pabt_invalid @ f + +/* + * Undef instr entry dispatcher + * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC + */ + vector_stub und, UND_MODE + + .long __und_usr @ 0 (USR_26 / USR_32) + .long __und_invalid @ 1 (FIQ_26 / FIQ_32) + .long __und_invalid @ 2 (IRQ_26 / IRQ_32) + .long __und_svc @ 3 (SVC_26 / SVC_32) + .long __und_invalid @ 4 + .long __und_invalid @ 5 + .long __und_invalid @ 6 + .long __und_invalid @ 7 + .long __und_invalid @ 8 + .long __und_invalid @ 9 + .long __und_invalid @ a + .long __und_invalid @ b + .long __und_invalid @ c + .long __und_invalid @ d + .long __und_invalid @ e + .long __und_invalid @ f + + .align 5 + +/*============================================================================= + * Undefined FIQs + *----------------------------------------------------------------------------- + * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC + * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. + * Basically to switch modes, we *HAVE* to clobber one register... brain + * damage alert! I don't think that we can execute any code in here in any + * other mode than FIQ... Ok you can switch to another mode, but you can't + * get out of that mode without clobbering one register. + */ +vector_fiq: + disable_fiq + subs pc, lr, #4 + +/*============================================================================= + * Address exception handler + *----------------------------------------------------------------------------- + * These aren't too critical. + * (they're not supposed to happen, and won't happen in 32-bit data mode). + */ + +vector_addrexcptn: + b vector_addrexcptn + +/* + * We group all the following data together to optimise + * for CPUs with separate I & D caches. + */ + .align 5 + +.LCvswi: + .word vector_swi + + .globl __stubs_end +__stubs_end: + + .equ stubs_offset, __vectors_start + 0x200 - __stubs_start + + .globl __vectors_start +__vectors_start: + ARM( swi SYS_ERROR0 ) + THUMB( svc #0 ) + THUMB( nop ) + W(b) vector_und + stubs_offset + W(ldr) pc, .LCvswi + stubs_offset + W(b) vector_pabt + stubs_offset + W(b) vector_dabt + stubs_offset + W(b) vector_addrexcptn + stubs_offset + W(b) vector_irq + stubs_offset + W(b) vector_fiq + stubs_offset + + .globl __vectors_end +__vectors_end: + + .data + + .globl cr_alignment + .globl cr_no_alignment +cr_alignment: + .space 4 +cr_no_alignment: + .space 4 + +#ifdef CONFIG_MULTI_IRQ_HANDLER + .globl handle_arch_irq +handle_arch_irq: + .space 4 +#endif diff --git a/arch/arm/kernel/entry-common-armada.S b/arch/arm/kernel/entry-common-armada.S new file mode 100755 index 000000000..6e928f82e --- /dev/null +++ b/arch/arm/kernel/entry-common-armada.S @@ -0,0 +1,647 @@ +/* + * linux/arch/arm/kernel/entry-common.S + * + * Copyright (C) 2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include "entry-header.S" + + + .align 5 +/* + * This is the fast syscall return path. We do as little as + * possible here, and this includes saving r0 back into the SVC + * stack. + */ +ret_fast_syscall: + UNWIND(.fnstart ) + UNWIND(.cantunwind ) + disable_irq @ disable interrupts + ldr r1, [tsk, #TI_FLAGS] + tst r1, #_TIF_WORK_MASK + bne fast_work_pending +#if defined(CONFIG_IRQSOFF_TRACER) + asm_trace_hardirqs_on +#endif + + /* perform architecture specific actions before user return */ + arch_ret_to_user r1, lr + + restore_user_regs fast = 1, offset = S_OFF + UNWIND(.fnend ) + +/* + * Ok, we need to do extra processing, enter the slow path. + */ +fast_work_pending: + str r0, [sp, #S_R0+S_OFF]! @ returned r0 +work_pending: + tst r1, #_TIF_NEED_RESCHED + bne work_resched + tst r1, #_TIF_SIGPENDING|_TIF_NOTIFY_RESUME + beq no_work_pending + mov r0, sp @ 'regs' + mov r2, why @ 'syscall' + tst r1, #_TIF_SIGPENDING @ delivering a signal? + movne why, #0 @ prevent further restarts + bl do_notify_resume + b ret_slow_syscall @ Check work again + +work_resched: + bl schedule +/* + * "slow" syscall return path. "why" tells us if this was a real syscall. + */ +ENTRY(ret_to_user) +ret_slow_syscall: + disable_irq @ disable interrupts +ENTRY(ret_to_user_from_irq) + ldr r1, [tsk, #TI_FLAGS] + tst r1, #_TIF_WORK_MASK + bne work_pending +no_work_pending: +#if defined(CONFIG_IRQSOFF_TRACER) + asm_trace_hardirqs_on +#endif + /* perform architecture specific actions before user return */ + arch_ret_to_user r1, lr + + restore_user_regs fast = 0, offset = 0 +ENDPROC(ret_to_user_from_irq) +ENDPROC(ret_to_user) + +/* + * This is how we return from a fork. + */ +ENTRY(ret_from_fork) + bl schedule_tail + get_thread_info tsk + ldr r1, [tsk, #TI_FLAGS] @ check for syscall tracing + mov why, #1 + tst r1, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? + beq ret_slow_syscall + mov r1, sp + mov r0, #1 @ trace exit [IP = 1] + bl syscall_trace + b ret_slow_syscall +ENDPROC(ret_from_fork) + + .equ NR_syscalls,0 +#define CALL(x) .equ NR_syscalls,NR_syscalls+1 +#include "calls.S" +#undef CALL +#define CALL(x) .long x + +#ifdef CONFIG_FUNCTION_TRACER +/* + * When compiling with -pg, gcc inserts a call to the mcount routine at the + * start of every function. In mcount, apart from the function's address (in + * lr), we need to get hold of the function's caller's address. + * + * Older GCCs (pre-4.4) inserted a call to a routine called mcount like this: + * + * bl mcount + * + * These versions have the limitation that in order for the mcount routine to + * be able to determine the function's caller's address, an APCS-style frame + * pointer (which is set up with something like the code below) is required. + * + * mov ip, sp + * push {fp, ip, lr, pc} + * sub fp, ip, #4 + * + * With EABI, these frame pointers are not available unless -mapcs-frame is + * specified, and if building as Thumb-2, not even then. + * + * Newer GCCs (4.4+) solve this problem by introducing a new version of mcount, + * with call sites like: + * + * push {lr} + * bl __gnu_mcount_nc + * + * With these compilers, frame pointers are not necessary. + * + * mcount can be thought of as a function called in the middle of a subroutine + * call. As such, it needs to be transparent for both the caller and the + * callee: the original lr needs to be restored when leaving mcount, and no + * registers should be clobbered. (In the __gnu_mcount_nc implementation, we + * clobber the ip register. This is OK because the ARM calling convention + * allows it to be clobbered in subroutines and doesn't use it to hold + * parameters.) + * + * When using dynamic ftrace, we patch out the mcount call by a "mov r0, r0" + * for the mcount case, and a "pop {lr}" for the __gnu_mcount_nc case (see + * arch/arm/kernel/ftrace.c). + */ + +#ifndef CONFIG_OLD_MCOUNT +#if (__GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 4)) +#error Ftrace requires CONFIG_FRAME_POINTER=y with GCC older than 4.4.0. +#endif +#endif + +.macro __mcount suffix + mcount_enter + ldr r0, =ftrace_trace_function + ldr r2, [r0] + adr r0, .Lftrace_stub + cmp r0, r2 + bne 1f + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + ldr r1, =ftrace_graph_return + ldr r2, [r1] + cmp r0, r2 + bne ftrace_graph_caller\suffix + + ldr r1, =ftrace_graph_entry + ldr r2, [r1] + ldr r0, =ftrace_graph_entry_stub + cmp r0, r2 + bne ftrace_graph_caller\suffix +#endif + + mcount_exit + +1: mcount_get_lr r1 @ lr of instrumented func + mov r0, lr @ instrumented function + sub r0, r0, #MCOUNT_INSN_SIZE + adr lr, BSYM(2f) + mov pc, r2 +2: mcount_exit +.endm + +.macro __ftrace_caller suffix + mcount_enter + + mcount_get_lr r1 @ lr of instrumented func + mov r0, lr @ instrumented function + sub r0, r0, #MCOUNT_INSN_SIZE + + .globl ftrace_call\suffix +ftrace_call\suffix: + bl ftrace_stub + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + .globl ftrace_graph_call\suffix +ftrace_graph_call\suffix: + mov r0, r0 +#endif + + mcount_exit +.endm + +.macro __ftrace_graph_caller + sub r0, fp, #4 @ &lr of instrumented routine (&parent) +#ifdef CONFIG_DYNAMIC_FTRACE + @ called from __ftrace_caller, saved in mcount_enter + ldr r1, [sp, #16] @ instrumented routine (func) +#else + @ called from __mcount, untouched in lr + mov r1, lr @ instrumented routine (func) +#endif + sub r1, r1, #MCOUNT_INSN_SIZE + mov r2, fp @ frame pointer + bl prepare_ftrace_return + mcount_exit +.endm + +#ifdef CONFIG_OLD_MCOUNT +/* + * mcount + */ + +.macro mcount_enter + stmdb sp!, {r0-r3, lr} +.endm + +.macro mcount_get_lr reg + ldr \reg, [fp, #-4] +.endm + +.macro mcount_exit + ldr lr, [fp, #-4] + ldmia sp!, {r0-r3, pc} +.endm + +ENTRY(mcount) +#ifdef CONFIG_DYNAMIC_FTRACE + stmdb sp!, {lr} + ldr lr, [fp, #-4] + ldmia sp!, {pc} +#else + __mcount _old +#endif +ENDPROC(mcount) + +#ifdef CONFIG_DYNAMIC_FTRACE +ENTRY(ftrace_caller_old) + __ftrace_caller _old +ENDPROC(ftrace_caller_old) +#endif + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER +ENTRY(ftrace_graph_caller_old) + __ftrace_graph_caller +ENDPROC(ftrace_graph_caller_old) +#endif + +.purgem mcount_enter +.purgem mcount_get_lr +.purgem mcount_exit +#endif + +/* + * __gnu_mcount_nc + */ + +.macro mcount_enter + stmdb sp!, {r0-r3, lr} +.endm + +.macro mcount_get_lr reg + ldr \reg, [sp, #20] +.endm + +.macro mcount_exit + ldmia sp!, {r0-r3, ip, lr} + mov pc, ip +.endm + +ENTRY(__gnu_mcount_nc) +#ifdef CONFIG_DYNAMIC_FTRACE + mov ip, lr + ldmia sp!, {lr} + mov pc, ip +#else + __mcount +#endif +ENDPROC(__gnu_mcount_nc) + +#ifdef CONFIG_DYNAMIC_FTRACE +ENTRY(ftrace_caller) + __ftrace_caller +ENDPROC(ftrace_caller) +#endif + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER +ENTRY(ftrace_graph_caller) + __ftrace_graph_caller +ENDPROC(ftrace_graph_caller) +#endif + +.purgem mcount_enter +.purgem mcount_get_lr +.purgem mcount_exit + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + .globl return_to_handler +return_to_handler: + stmdb sp!, {r0-r3} + mov r0, fp @ frame pointer + bl ftrace_return_to_handler + mov lr, r0 @ r0 has real ret addr + ldmia sp!, {r0-r3} + mov pc, lr +#endif + +ENTRY(ftrace_stub) +.Lftrace_stub: + mov pc, lr +ENDPROC(ftrace_stub) + +#endif /* CONFIG_FUNCTION_TRACER */ + +/*============================================================================= + * SWI handler + *----------------------------------------------------------------------------- + */ + + /* If we're optimising for StrongARM the resulting code won't + run on an ARM7 and we can save a couple of instructions. + --pb */ +#ifdef CONFIG_CPU_ARM710 +#define A710(code...) code +.Larm710bug: + ldmia sp, {r0 - lr}^ @ Get calling r0 - lr + mov r0, r0 + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 +#else +#define A710(code...) +#endif + + .align 5 +ENTRY(vector_swi) + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0 - r12 + ARM( add r8, sp, #S_PC ) + ARM( stmdb r8, {sp, lr}^ ) @ Calling sp, lr + THUMB( mov r8, sp ) + THUMB( store_user_sp_lr r8, r10, S_SP ) @ calling sp, lr + mrs r8, spsr @ called from non-FIQ mode, so ok. + str lr, [sp, #S_PC] @ Save calling PC + str r8, [sp, #S_PSR] @ Save CPSR + str r0, [sp, #S_OLD_R0] @ Save OLD_R0 + zero_fp + + /* + * Get the system call number. + */ + +#if defined(CONFIG_OABI_COMPAT) + + /* + * If we have CONFIG_OABI_COMPAT then we need to look at the swi + * value to determine if it is an EABI or an old ABI call. + */ +#ifdef CONFIG_ARM_THUMB + tst r8, #PSR_T_BIT + movne r10, #0 @ no thumb OABI emulation + ldreq r10, [lr, #-4] @ get SWI instruction +#else + ldr r10, [lr, #-4] @ get SWI instruction + A710( and ip, r10, #0x0f000000 @ check for SWI ) + A710( teq ip, #0x0f000000 ) + A710( bne .Larm710bug ) +#endif +#ifdef CONFIG_CPU_ENDIAN_BE8 + rev r10, r10 @ little endian instruction +#endif + +#elif defined(CONFIG_AEABI) + + /* + * Pure EABI user space always put syscall number into scno (r7). + */ + A710( ldr ip, [lr, #-4] @ get SWI instruction ) + A710( and ip, ip, #0x0f000000 @ check for SWI ) + A710( teq ip, #0x0f000000 ) + A710( bne .Larm710bug ) + +#elif defined(CONFIG_ARM_THUMB) + + /* Legacy ABI only, possibly thumb mode. */ + tst r8, #PSR_T_BIT @ this is SPSR from save_user_regs + addne scno, r7, #__NR_SYSCALL_BASE @ put OS number in + ldreq scno, [lr, #-4] + +#else + + /* Legacy ABI only. */ + ldr scno, [lr, #-4] @ get SWI instruction + A710( and ip, scno, #0x0f000000 @ check for SWI ) + A710( teq ip, #0x0f000000 ) + A710( bne .Larm710bug ) + +#endif + +#ifdef CONFIG_ALIGNMENT_TRAP + ldr ip, __cr_alignment + ldr ip, [ip] + mcr p15, 0, ip, c1, c0 @ update control register +#endif + enable_irq + + get_thread_info tsk + adr tbl, sys_call_table @ load syscall table pointer + +#if defined(CONFIG_OABI_COMPAT) + /* + * If the swi argument is zero, this is an EABI call and we do nothing. + * + * If this is an old ABI call, get the syscall number into scno and + * get the old ABI syscall table address. + */ + bics r10, r10, #0xff000000 + eorne scno, r10, #__NR_OABI_SYSCALL_BASE + ldrne tbl, =sys_oabi_call_table +#elif !defined(CONFIG_AEABI) + bic scno, scno, #0xff000000 @ mask off SWI op-code + eor scno, scno, #__NR_SYSCALL_BASE @ check OS number +#endif + + ldr r10, [tsk, #TI_FLAGS] @ check for syscall tracing + stmdb sp!, {r4, r5} @ push fifth and sixth args + +#ifdef CONFIG_SECCOMP + tst r10, #_TIF_SECCOMP + beq 1f + mov r0, scno + bl __secure_computing + add r0, sp, #S_R0 + S_OFF @ pointer to regs + ldmia r0, {r0 - r3} @ have to reload r0 - r3 +1: +#endif + + tst r10, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? + bne __sys_trace + + cmp scno, #NR_syscalls @ check upper syscall limit + adr lr, BSYM(ret_fast_syscall) @ return address + ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine + + add r1, sp, #S_OFF +2: mov why, #0 @ no longer a real syscall + cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE) + eor r0, scno, #__NR_SYSCALL_BASE @ put OS number back + bcs arm_syscall + b sys_ni_syscall @ not private func +ENDPROC(vector_swi) + + /* + * This is the really slow path. We're going to be doing + * context switches, and waiting for our parent to respond. + */ +__sys_trace: + mov r2, scno + add r1, sp, #S_OFF + mov r0, #0 @ trace entry [IP = 0] + bl syscall_trace + + adr lr, BSYM(__sys_trace_return) @ return address + mov scno, r0 @ syscall number (possibly new) + add r1, sp, #S_R0 + S_OFF @ pointer to regs + cmp scno, #NR_syscalls @ check upper syscall limit + ldmccia r1, {r0 - r3} @ have to reload r0 - r3 + ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine + b 2b + +__sys_trace_return: + str r0, [sp, #S_R0 + S_OFF]! @ save returned r0 + mov r2, scno + mov r1, sp + mov r0, #1 @ trace exit [IP = 1] + bl syscall_trace + b ret_slow_syscall + + .align 5 +#ifdef CONFIG_ALIGNMENT_TRAP + .type __cr_alignment, #object +__cr_alignment: + .word cr_alignment +#endif + .ltorg + +/* + * This is the syscall table declaration for native ABI syscalls. + * With EABI a couple syscalls are obsolete and defined as sys_ni_syscall. + */ +#define ABI(native, compat) native +#ifdef CONFIG_AEABI +#define OBSOLETE(syscall) sys_ni_syscall +#else +#define OBSOLETE(syscall) syscall +#endif + + .type sys_call_table, #object +ENTRY(sys_call_table) +#include "calls.S" +#undef ABI +#undef OBSOLETE + +/*============================================================================ + * Special system call wrappers + */ +@ r0 = syscall number +@ r8 = syscall table +sys_syscall: + bic scno, r0, #__NR_OABI_SYSCALL_BASE + cmp scno, #__NR_syscall - __NR_SYSCALL_BASE + cmpne scno, #NR_syscalls @ check range + stmloia sp, {r5, r6} @ shuffle args + movlo r0, r1 + movlo r1, r2 + movlo r2, r3 + movlo r3, r4 + ldrlo pc, [tbl, scno, lsl #2] + b sys_ni_syscall +ENDPROC(sys_syscall) + +sys_fork_wrapper: + add r0, sp, #S_OFF + b sys_fork +ENDPROC(sys_fork_wrapper) + +sys_vfork_wrapper: + add r0, sp, #S_OFF + b sys_vfork +ENDPROC(sys_vfork_wrapper) + +sys_execve_wrapper: + add r3, sp, #S_OFF + b sys_execve +ENDPROC(sys_execve_wrapper) + +sys_clone_wrapper: + add ip, sp, #S_OFF + str ip, [sp, #4] + b sys_clone +ENDPROC(sys_clone_wrapper) + +sys_sigreturn_wrapper: + add r0, sp, #S_OFF + mov why, #0 @ prevent syscall restart handling + b sys_sigreturn +ENDPROC(sys_sigreturn_wrapper) + +sys_rt_sigreturn_wrapper: + add r0, sp, #S_OFF + mov why, #0 @ prevent syscall restart handling + b sys_rt_sigreturn +ENDPROC(sys_rt_sigreturn_wrapper) + +sys_sigaltstack_wrapper: + ldr r2, [sp, #S_OFF + S_SP] + b do_sigaltstack +ENDPROC(sys_sigaltstack_wrapper) + +sys_statfs64_wrapper: + teq r1, #88 + moveq r1, #84 + b sys_statfs64 +ENDPROC(sys_statfs64_wrapper) + +sys_fstatfs64_wrapper: + teq r1, #88 + moveq r1, #84 + b sys_fstatfs64 +ENDPROC(sys_fstatfs64_wrapper) + +/* + * Note: off_4k (r5) is always units of 4K. If we can't do the requested + * offset, we return EINVAL. + */ +sys_mmap2: +#ifdef CONFIG_MV_SUPPORT_64KB_PAGE_SIZE + tst r5, #0xF + moveq r5, r5, lsr #4 + streq r5, [sp, #4] + beq sys_mmap_pgoff + mov r0, #-EINVAL + mov pc, lr +#else + str r5, [sp, #4] + b sys_mmap_pgoff +#endif +ENDPROC(sys_mmap2) + +#ifdef CONFIG_OABI_COMPAT + +/* + * These are syscalls with argument register differences + */ + +sys_oabi_pread64: + stmia sp, {r3, r4} + b sys_pread64 +ENDPROC(sys_oabi_pread64) + +sys_oabi_pwrite64: + stmia sp, {r3, r4} + b sys_pwrite64 +ENDPROC(sys_oabi_pwrite64) + +sys_oabi_truncate64: + mov r3, r2 + mov r2, r1 + b sys_truncate64 +ENDPROC(sys_oabi_truncate64) + +sys_oabi_ftruncate64: + mov r3, r2 + mov r2, r1 + b sys_ftruncate64 +ENDPROC(sys_oabi_ftruncate64) + +sys_oabi_readahead: + str r3, [sp] + mov r3, r2 + mov r2, r1 + b sys_readahead +ENDPROC(sys_oabi_readahead) + +/* + * Let's declare a second syscall table for old ABI binaries + * using the compatibility syscall entries. + */ +#define ABI(native, compat) compat +#define OBSOLETE(syscall) syscall + + .type sys_oabi_call_table, #object +ENTRY(sys_oabi_call_table) +#include "calls.S" +#undef ABI +#undef OBSOLETE + +#endif + diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S old mode 100644 new mode 100755 index b2a27b6b0..28dbe6733 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -14,7 +14,9 @@ #include #include "entry-header.S" - +#if defined(CONFIG_SYNO_COMCERTO) +#include +#endif .align 5 /* @@ -583,6 +585,9 @@ ENDPROC(sys_fstatfs64_wrapper) */ sys_mmap2: #if PAGE_SHIFT > 12 +#if defined(CONFIG_SYNO_COMCERTO) +#define PGOFF_MASK ((1 << (PAGE_SHIFT - 12)) - 1) +#endif tst r5, #PGOFF_MASK moveq r5, r5, lsr #PAGE_SHIFT - 12 streq r5, [sp, #4] diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S old mode 100644 new mode 100755 index 9a8531ead..2a5ec0f92 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -108,11 +108,17 @@ movs pc, lr @ return & move spsr_svc into cpsr .endm +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) .macro get_thread_info, rd mov \rd, sp, lsr #13 mov \rd, \rd, lsl #13 .endm - +#else + .macro get_thread_info, rd + mov \rd, sp, lsr #16 + mov \rd, \rd, lsl #16 + .endm +#endif @ @ 32-bit wide "mov pc, reg" @ @@ -148,11 +154,18 @@ movs pc, lr @ return & move spsr_svc into cpsr .endm +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_64K_PAGES) .macro get_thread_info, rd mov \rd, sp lsr \rd, \rd, #13 mov \rd, \rd, lsl #13 .endm +#else + .macro get_thread_info, rd + mov \rd, sp, lsr #16 + mov \rd, \rd, lsl #16 + .endm +#endif @ @ 32-bit wide "mov pc, reg" diff --git a/arch/arm/kernel/functionlist b/arch/arm/kernel/functionlist new file mode 100755 index 000000000..24d71acf2 --- /dev/null +++ b/arch/arm/kernel/functionlist @@ -0,0 +1,41 @@ +*(.text.net_rx_action) +*(.text.net_tx_action) +*(.text.eth_poll) +*(.text.mv_l2_inv_range) +*(.text.mvFpProcess) +*(.text.skb_put) +*(.text.eth_type_trans) +*(.text.skb_pull) +*(.text.local_bh_disable) +*(.text.local_bh_enable) +*(.text.netif_receive_skb) +*(.text.memset) +*(.text.memcpy) +*(.text.memmove) +*(.text.__memzero) +*(.text.ip_rcv) +*(.text.ip_route_input) +*(.text.ip_forward) +*(.text.ip_output) +*(.text.ip_finish_output) +*(.text.ip_finish_output2) +*(.text.dev_queue_xmit) +*(.text.dev_hard_start_xmit) +*(.text.eth_tx) +*(.text.dma_cache_maint) +*(.text.feroceon_dma_inv_range) +*(.text.feroceon_range_dma_inv_range) +*(.text.feroceon_dma_clean_range) +*(.text.feroceon_range_dma_clean_range) +*(.text.feroceon_dma_flush_range) +*(.text.feroceon_range_dma_flush_range) +*(.text.outer_flush_range) +*(.text.outer_clean_range) +*(.text.outer_inv_range) +*(.text.feroceon_l2_flush_range) +*(.text.feroceon_l2_clean_range) +*(.text.feroceon_l2_inv_range) +*(.text.eth_skb_recycle) +*(.text.skb_recycle_check) +*(.text.pfifo_fast_enqueue) +*(.text.__qdisc_run) diff --git a/arch/arm/kernel/functionlist_routing b/arch/arm/kernel/functionlist_routing new file mode 100755 index 000000000..24d71acf2 --- /dev/null +++ b/arch/arm/kernel/functionlist_routing @@ -0,0 +1,41 @@ +*(.text.net_rx_action) +*(.text.net_tx_action) +*(.text.eth_poll) +*(.text.mv_l2_inv_range) +*(.text.mvFpProcess) +*(.text.skb_put) +*(.text.eth_type_trans) +*(.text.skb_pull) +*(.text.local_bh_disable) +*(.text.local_bh_enable) +*(.text.netif_receive_skb) +*(.text.memset) +*(.text.memcpy) +*(.text.memmove) +*(.text.__memzero) +*(.text.ip_rcv) +*(.text.ip_route_input) +*(.text.ip_forward) +*(.text.ip_output) +*(.text.ip_finish_output) +*(.text.ip_finish_output2) +*(.text.dev_queue_xmit) +*(.text.dev_hard_start_xmit) +*(.text.eth_tx) +*(.text.dma_cache_maint) +*(.text.feroceon_dma_inv_range) +*(.text.feroceon_range_dma_inv_range) +*(.text.feroceon_dma_clean_range) +*(.text.feroceon_range_dma_clean_range) +*(.text.feroceon_dma_flush_range) +*(.text.feroceon_range_dma_flush_range) +*(.text.outer_flush_range) +*(.text.outer_clean_range) +*(.text.outer_inv_range) +*(.text.feroceon_l2_flush_range) +*(.text.feroceon_l2_clean_range) +*(.text.feroceon_l2_inv_range) +*(.text.eth_skb_recycle) +*(.text.skb_recycle_check) +*(.text.pfifo_fast_enqueue) +*(.text.__qdisc_run) diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S old mode 100644 new mode 100755 index 854bd2238..847ae0d7e --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -48,6 +48,12 @@ __vet_atags: bne 1f ldr r5, [r2, #0] + +#ifdef CONFIG_SYNO_ARMADA_ARCH +#ifdef CONFIG_BE8_ON_LE + rev r5, r5 +#endif +#endif #ifdef CONFIG_OF_FLATTREE ldr r6, =OF_DT_MAGIC @ is it a DTB? cmp r5, r6 @@ -57,6 +63,11 @@ __vet_atags: cmpne r5, #ATAG_CORE_SIZE_EMPTY bne 1f ldr r5, [r2, #4] +#ifdef CONFIG_SYNO_ARMADA_ARCH +#ifdef CONFIG_BE8_ON_LE + rev r5, r5 +#endif +#endif ldr r6, =ATAG_CORE cmp r5, r6 bne 1f diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S old mode 100644 new mode 100755 index 3606e85cf..2ad927355 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -39,14 +39,34 @@ #error KERNEL_RAM_VADDR must start at 0xXXXX8000 #endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) + /* LPAE requires an additional page for the PGD */ +#define PG_DIR_SIZE 0x5000 +#define PMD_ORDER 3 +#else #define PG_DIR_SIZE 0x4000 #define PMD_ORDER 2 +#endif .globl swapper_pg_dir .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE - +#if defined(CONFIG_SYNO_COMCERTO) +/* +* Mindspeed: +* Need to break the function in case text offset is too big +* this is the case when using zone_dma +* There is probably a more elegant way to to that +* original code: +* add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE +*/ +#endif .macro pgtbl, rd, phys +#if defined(CONFIG_SYNO_COMCERTO) + ldr \rd, =TEXT_OFFSET - PG_DIR_SIZE + add \rd, \phys, \rd +#else add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE +#endif .endm #ifdef CONFIG_XIP_KERNEL @@ -164,6 +184,25 @@ __create_page_tables: teq r0, r6 bne 1b +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) + /* + * Build the PGD table (first level) to point to the PMD table. A PGD + * entry is 64-bit wide. + */ + mov r0, r4 + add r3, r4, #0x1000 @ first PMD table address + orr r3, r3, #3 @ PGD block type + mov r6, #4 @ PTRS_PER_PGD + mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER +1: str r3, [r0], #4 @ set bottom PGD entry bits + str r7, [r0], #4 @ set top PGD entry bits + add r3, r3, #0x1000 @ next PMD table + subs r6, r6, #1 + bne 1b + + add r4, r4, #0x1000 @ point to the PMD tables +#endif + ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags /* @@ -254,7 +293,15 @@ __create_page_tables: mov r3, r7, lsr #SECTION_SHIFT ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags orr r3, r7, r3, lsl #SECTION_SHIFT +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) +mov r7, #1 << (54 - 32) @ XN +#endif 1: str r3, [r0], #4 +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#ifdef CONFIG_ARM_LPAE + str r7, [r0], #4 +#endif +#endif add r3, r3, #1 << SECTION_SHIFT cmp r0, r6 blo 1b @@ -285,6 +332,9 @@ __create_page_tables: add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) str r3, [r0] #endif +#endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) + sub r4, r4, #0x1000 @ point to the PGD table #endif mov pc, lr ENDPROC(__create_page_tables) @@ -377,12 +427,17 @@ __enable_mmu: #ifdef CONFIG_CPU_ICACHE_DISABLE bic r0, r0, #CR_I #endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARM_LPAE) + mov r5, #0 + mcrr p15, 0, r4, r5, c2 @ load TTBR0 +#else mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ domain_val(DOMAIN_IO, DOMAIN_CLIENT)) mcr p15, 0, r5, c3, c0, 0 @ load domain access register mcr p15, 0, r4, c2, c0, 0 @ load page table pointer +#endif b __turn_mmu_on ENDPROC(__enable_mmu) @@ -403,8 +458,14 @@ ENDPROC(__enable_mmu) .align 5 __turn_mmu_on: mov r0, r0 +#if defined(CONFIG_SYNO_ARMADA_ARCH) + instr_sync +#endif mcr p15, 0, r0, c1, c0, 0 @ write control reg mrc p15, 0, r3, c0, c0, 0 @ read id reg +#if defined(CONFIG_SYNO_ARMADA_ARCH) + instr_sync +#endif mov r3, r3 mov r3, r13 mov pc, r3 diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c old mode 100644 new mode 100755 index 2bc1a8e92..569e48037 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -1050,7 +1050,10 @@ static int __init arch_hw_breakpoint_init(void) register_cpu_notifier(&dbg_reset_nb); return 0; } +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#else arch_initcall(arch_hw_breakpoint_init); +#endif void hw_breakpoint_pmu_read(struct perf_event *bp) { diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c old mode 100644 new mode 100755 index 87c8be59a..38f13e0d0 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -57,6 +57,9 @@ int arch_show_interrupts(struct seq_file *p, int prec) #endif #ifdef CONFIG_SMP show_ipi_list(p, prec); +#if defined(CONFIG_SYNO_ARMADA_ARCH) && (defined(CONFIG_ARCH_ARMADA_XP) && defined(CONFIG_PERF_EVENTS)) + show_local_pmu_irqs(p, prec); +#endif #endif seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); return 0; diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c old mode 100644 new mode 100755 index 1e9be5d25..464ab4236 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -45,6 +45,20 @@ void *module_alloc(unsigned long size) } #endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#ifdef CONFIG_CPU_ENDIAN_BE8 +#define read_instr32(c) __swab32(*(u32 *)c) +#define read_instr16(c) __swab16(*(u16 *)c) +#define write_instr32(v,a) (*(u32 *)(a) = __swab32((__force __u32)(v))) +#define write_instr16(v,a) (*(u16 *)(a) = __swab16((__force __u16)(v))) +#else +#define read_instr32(c) (*(u32 *)c) +#define read_instr16(c) (*(u16 *)c) +#define write_instr32(v,a) (*(u32 *)(a) = (v)) +#define write_instr16(v,a) (*(u16 *)(a) = (v)) +#endif +#endif + int apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, unsigned int relindex, struct module *module) @@ -80,6 +94,11 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, rel->r_offset, dstsec->sh_size); return -ENOEXEC; } +#if defined(CONFIG_SYNO_COMCERTO) + if ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) && + ELF_ST_BIND(sym->st_info) == STB_WEAK) + continue; +#endif loc = dstsec->sh_addr + rel->r_offset; @@ -95,7 +114,11 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, case R_ARM_PC24: case R_ARM_CALL: case R_ARM_JUMP24: +#if defined(CONFIG_SYNO_ARMADA_ARCH) + offset = (read_instr32(loc) & 0x00ffffff) << 2; +#else offset = (*(u32 *)loc & 0x00ffffff) << 2; +#endif if (offset & 0x02000000) offset -= 0x04000000; @@ -112,8 +135,13 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, offset >>= 2; +#if defined(CONFIG_SYNO_ARMADA_ARCH) + write_instr32((read_instr32(loc) & 0xff000000) | + (offset & 0x00ffffff), loc); +#else *(u32 *)loc &= 0xff000000; *(u32 *)loc |= offset & 0x00ffffff; +#endif break; case R_ARM_V4BX: @@ -121,6 +149,11 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, * other bits to re-code instruction as * MOV PC,Rm. */ + +#if defined(CONFIG_SYNO_ARMADA_ARCH) + write_instr32((read_instr32(loc) & 0xf000000f) | + 0x01a0f000, loc); +#endif *(u32 *)loc &= 0xf000000f; *(u32 *)loc |= 0x01a0f000; break; @@ -132,7 +165,12 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, case R_ARM_MOVW_ABS_NC: case R_ARM_MOVT_ABS: +#if defined(CONFIG_SYNO_ARMADA_ARCH) + offset = read_instr32(loc); +#else offset = *(u32 *)loc; +#endif + offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff); offset = (offset ^ 0x8000) - 0x8000; @@ -140,16 +178,26 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS) offset >>= 16; +#if defined(CONFIG_SYNO_ARMADA_ARCH) + write_instr32((read_instr32(loc) & 0xfff0f000) | + ((offset & 0xf000) << 4) | + (offset & 0x0fff), loc); +#else *(u32 *)loc &= 0xfff0f000; *(u32 *)loc |= ((offset & 0xf000) << 4) | (offset & 0x0fff); +#endif break; #ifdef CONFIG_THUMB2_KERNEL case R_ARM_THM_CALL: case R_ARM_THM_JUMP24: upper = *(u16 *)loc; +#if defined(CONFIG_SYNO_ARMADA_ARCH) + lower = read_instr16(loc + 2); +#else lower = *(u16 *)(loc + 2); +#endif /* * 25 bit signed address range (Thumb-2 BL and B.W @@ -198,17 +246,31 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, sign = (offset >> 24) & 1; j1 = sign ^ (~(offset >> 23) & 1); j2 = sign ^ (~(offset >> 22) & 1); +#if defined(CONFIG_SYNO_ARMADA_ARCH) + write_instr16((u16)((upper & 0xf800) | (sign << 10) | + ((offset >> 12) & 0x03ff)),loc); + write_instr16((u16)((lower & 0xd000) | + (j1 << 13) | (j2 << 11) | + ((offset >> 1) & 0x07ff)),loc + 2); +#else *(u16 *)loc = (u16)((upper & 0xf800) | (sign << 10) | ((offset >> 12) & 0x03ff)); *(u16 *)(loc + 2) = (u16)((lower & 0xd000) | (j1 << 13) | (j2 << 11) | ((offset >> 1) & 0x07ff)); +#endif break; case R_ARM_THM_MOVW_ABS_NC: case R_ARM_THM_MOVT_ABS: +#if defined(CONFIG_SYNO_ARMADA_ARCH) + upper = read_instr16(loc); + + lower = read_instr16(loc + 2); +#else upper = *(u16 *)loc; lower = *(u16 *)(loc + 2); +#endif /* * MOVT/MOVW instructions encoding in Thumb-2: @@ -229,12 +291,23 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS) offset >>= 16; +#if defined(CONFIG_SYNO_ARMADA_ARCH) + write_instr16((u16)((upper & 0xfbf0) | + ((offset & 0xf000) >> 12) | + ((offset & 0x0800) >> 1)), + doc); + write_instr16((u16)((lower & 0x8f00) | + ((offset & 0x0700) << 4) | + (offset & 0x00ff)), + doc + 2); +#else *(u16 *)loc = (u16)((upper & 0xfbf0) | ((offset & 0xf000) >> 12) | ((offset & 0x0800) >> 1)); *(u16 *)(loc + 2) = (u16)((lower & 0x8f00) | ((offset & 0x0700) << 4) | (offset & 0x00ff)); +#endif break; #endif diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c old mode 100644 new mode 100755 index ecebb893f..0e9de0380 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -435,8 +435,13 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu) } err = request_irq(irq, handle_irq, +#if defined(CONFIG_SYNO_ARMADA_ARCH) + IRQF_NOBALANCING | IRQF_SHARED, + "armpmu", handle_irq); +#else IRQF_DISABLED | IRQF_NOBALANCING, "arm-pmu", armpmu); +#endif if (err) { pr_err("unable to request IRQ%d for ARM PMU counters\n", irq); @@ -608,6 +613,9 @@ int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type) #include "perf_event_xscale.c" #include "perf_event_v6.c" #include "perf_event_v7.c" +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#include "perf_event_pj4b.c" +#endif /* * Ensure the PMU has sane values out of reset. @@ -725,7 +733,22 @@ init_hw_perf_events(void) cpu_pmu = xscale2pmu_init(); break; } +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARCH_ARMADA_XP) + /* Marvell Armada XP CPUs */ + } else if (0x56 == implementor) { + part_number = (cpuid >> 4) & 0xFFF; + switch (part_number) { + case 0x581: + case 0x584: + printk(KERN_INFO "Armada-XP Performance Monitor Unit detected (Marvell ID)!!!\n"); + mrvl_pj4b_read_reset_pmnc(); + cpu_pmu=mrvl_pj4b_pmu_init(); + break; + } + } +#else } +#endif if (cpu_pmu) { pr_info("enabled with %s PMU driver, %d counters available\n", diff --git a/arch/arm/kernel/perf_event_pj4b.c b/arch/arm/kernel/perf_event_pj4b.c new file mode 100755 index 000000000..246f91269 --- /dev/null +++ b/arch/arm/kernel/perf_event_pj4b.c @@ -0,0 +1,627 @@ +/* + * Marvell Sheeva PJ4B CPU support + */ + +#ifdef CONFIG_ARCH_ARMADA_XP +#include + +#define MRVL_PJ4B_PMU_ENABLE 0x001 /* Enable counters */ +#define MRVL_PJ4B_PMN_RESET 0x002 /* Reset event counters */ +#define MRVL_PJ4B_CCNT_RESET 0x004 /* Reset cycles counter */ +#define MRVL_PJ4B_PMU_RESET (MRVL_PJ4B_CCNT_RESET | MRVL_PJ4B_PMN_RESET) +#define MRVL_PJ4B_PMU_CNT64 0x008 /* Make CCNT count every 64th cycle */ + + + + +#define PJ4BV7_PMNC_P (1 << 1) /* Reset all counters */ +#define PJ4BV7_PMNC_C (1 << 2) /* Cycle counter reset */ + +/* +* Different types of events that can be counted by the Marvell PJ4 Performance Monitor +* +*/ +enum mrvl_pj4b_perf_types { + MRVL_PJ4B_SOFTWARE_INCR = 0x00, /* software increment */ + MRVL_PJ4B_IFU_IFETCH_REFILL = 0x01, /* instruction fetch that cause a refill at the lowest level of instruction or unified cache */ + MRVL_PJ4B_IF_TLB_REFILL = 0x02, /* instruction fetch that cause a TLB refill at the lowest level of TLB */ + MRVL_PJ4B_DATA_RW_CACHE_REFILL = 0x03, /* data read or write operation that causes a refill of at the lowest level of data or unified cache */ + MRVL_PJ4B_DATA_RW_CACHE_ACCESS = 0x04, /* data read or write operation that causes a cache access at the lowest level of data or unified cache */ + MRVL_PJ4B_DATA_RW_TLB_REFILL = 0x05, /* data read or write operation that causes a TLB refill at the lowest level of TLB */ + MRVL_PJ4B_DATA_READ_INST_EXEC = 0x06, /* data read architecturally executed */ + MRVL_PJ4B_DATA_WRIT_INST_EXEC = 0x07, /* data write architecturally executed */ + MRVL_PJ4B_INSN_EXECUTED = 0x08, /* instruction architecturally executed */ + MRVL_PJ4B_EXCEPTION_TAKEN = 0x09, /* exception taken */ + MRVL_PJ4B_EXCEPTION_RETURN = 0x0a, /* exception return architecturally executed */ + MRVL_PJ4B_INSN_WR_CONTEXTIDR = 0x0b, /* instruction that writes to the Context ID Register architecturally executed */ + MRVL_PJ4B_SW_CHANGE_PC = 0x0c, /* software change of PC, except by an exception, architecturally executed */ + MRVL_PJ4B_BR_EXECUTED = 0x0d, /* immediate branch architecturally executed, taken or not taken */ + MRVL_PJ4B_PROCEDURE_RETURN = 0x0e, /* procedure return architecturally executed */ + MRVL_PJ4B_UNALIGNED_ACCESS = 0x0f, /* unaligned access architecturally executed */ + MRVL_PJ4B_BR_INST_MISS_PRED = 0x10, /* branch mispredicted or not predicted */ + MRVL_PJ4B_CYCLE_COUNT = 0x11, /* cycle count */ + MRVL_PJ4B_BR_PRED_TAKEN = 0x12, /* branches or other change in the program flow that could have been predicted by the branch prediction resources of the processor */ + MRVL_PJ4B_DCACHE_READ_HIT = 0x40, /* counts the number of Data Cache read hits */ + MRVL_PJ4B_DCACHE_READ_MISS = 0x41, /* connts the number of Data Cache read misses */ + MRVL_PJ4B_DCACHE_WRITE_HIT = 0x42, /* counts the number of Data Cache write hits */ + MRVL_PJ4B_DCACHE_WRITE_MISS = 0x43, /* counts the number of Data Cache write misses */ + MRVL_PJ4B_MMU_BUS_REQUEST = 0x44, /* counts the number of cycles of request to the MMU Bus */ + MRVL_PJ4B_ICACHE_BUS_REQUEST = 0x45, /* counts the number of cycles the Instruction Cache requests the bus until the data return */ + MRVL_PJ4B_WB_WRITE_LATENCY = 0x46, /* counts the number of cycles the Write Buffer requests the bus */ + MRVL_PJ4B_HOLD_LDM_STM = 0x47, /* counts the number of cycles the pipeline is held because of a load/store multiple instruction */ + MRVL_PJ4B_NO_DUAL_CFLAG = 0x48, /* counts the number of cycles the processor cannot dual issue because of a Carry flag dependency */ + MRVL_PJ4B_NO_DUAL_REGISTER_PLUS = 0x49, /* counts the number of cycles the processor cannot dual issue because the register file does not have enough read ports and at least one other reason */ + MRVL_PJ4B_LDST_ROB0_ON_HOLD = 0x4a, /* counts the number of cycles a load or store instruction waits to retire from ROB0 */ + MRVL_PJ4B_LDST_ROB1_ON_HOLD = 0x4b, /* counts the number of cycles a load or store instruction waits to retire from ROB0=1 */ + MRVL_PJ4B_DATA_WRITE_ACCESS_COUNT = 0x4c, /* counts the number of any Data write access */ + MRVL_PJ4B_DATA_READ_ACCESS_COUNT = 0x4d, /* counts the number of any Data read access */ + MRVL_PJ4B_A2_STALL = 0x4e, /* counts the number of cycles ALU A2 is stalled */ + /*TODO: implement with fabric counters*/ + MRVL_PJ4B_L2C_WRITE_HIT = 0x4f, /* counts the number of write accesses to addresses already in the L2C */ + MRVL_PJ4B_L2C_WRITE_MISS = 0x50, /* counts the number of write accesses to addresses not in the L2C */ + MRVL_PJ4B_L2C_READ_COUNT = 0x51, /* counts the number of L2C cache-to-bus external read request */ + /*TODO: end*/ + MRVL_PJ4B_ICACHE_READ_MISS = 0x60, /* counts the number of Instruction Cache read misses */ + MRVL_PJ4B_ITLB_MISS = 0x61, /* counts the number of instruction TLB miss */ + MRVL_PJ4B_SINGLE_ISSUE = 0x62, /* counts the number of cycles the processor single issues */ + MRVL_PJ4B_BR_RETIRED = 0x63, /* counts the number of times one branch retires */ + MRVL_PJ4B_ROB_FULL = 0x64, /* counts the number of cycles the Re-order Buffer (ROB) is full */ + MRVL_PJ4B_MMU_READ_BEAT = 0x65, /* counts the number of times the bus returns RDY to the MMU */ + MRVL_PJ4B_WB_WRITE_BEAT = 0x66, /* counts the number times the bus returns ready to the Write Buffer */ + MRVL_PJ4B_DUAL_ISSUE = 0x67, /* counts the number of cycles the processor dual issues */ + MRVL_PJ4B_NO_DUAL_RAW = 0x68, /* counts the number of cycles the processor cannot dual issue because of a Read after Write hazard */ + MRVL_PJ4B_HOLD_IS = 0x69, /* counts the number of cycles the issue is held */ + /*TODO: implement with fabric counters*/ + MRVL_PJ4B_L2C_LATENCY = 0x6a, /* counts the latency for the most recent L2C read from the external bus Counts cycles */ + /*TODO: end*/ + MRVL_PJ4B_DCACHE_ACCESS = 0x70, /* counts the number of times the Data cache is accessed */ + MRVL_PJ4B_DTLB_MISS = 0x71, /* counts the number of data TLB misses */ + MRVL_PJ4B_BR_PRED_MISS = 0x72, /* counts the number of mispredicted branches */ + MRVL_PJ4B_A1_STALL = 0x74, /* counts the number of cycles ALU A1 is stalled */ + MRVL_PJ4B_DCACHE_READ_LATENCY = 0x75, /* counts the number of cycles the Data cache requests the bus for a read */ + MRVL_PJ4B_DCACHE_WRITE_LATENCY = 0x76, /* counts the number of cycles the Data cache requests the bus for a write */ + MRVL_PJ4B_NO_DUAL_REGISTER_FILE = 0x77, /* counts the number of cycles the processor cannot dual issue because the register file doesn't have enough read ports */ + MRVL_PJ4B_BIU_SIMULTANEOUS_ACCESS = 0x78, /* BIU Simultaneous Access */ + MRVL_PJ4B_L2C_READ_HIT = 0x79, /* counts the number of L2C cache-to-bus external read requests */ + MRVL_PJ4B_L2C_READ_MISS = 0x7a, /* counts the number of L2C read accesses that resulted in an external read request */ + MRVL_PJ4B_L2C_EVICTION = 0x7b, /* counts the number of evictions (CastOUT) of a line from the L2 cache */ + MRVL_PJ4B_TLB_MISS = 0x80, /* counts the number of instruction and data TLB misses */ + MRVL_PJ4B_BR_TAKEN = 0x81, /* counts the number of taken branches */ + MRVL_PJ4B_WB_FULL = 0x82, /* counts the number of cycles WB is full */ + MRVL_PJ4B_DCACHE_READ_BEAT = 0x83, /* counts the number of times the bus returns Data to the Data cache during read request */ + MRVL_PJ4B_DCACHE_WRITE_BEAT = 0x84, /* counts the number of times the bus returns ready to the Data cache during write request */ + MRVL_PJ4B_NO_DUAL_HW = 0x85, /* counts the number of cycles the processor cannot dual issue because of hardware conflict */ + MRVL_PJ4B_NO_DUAL_MULTIPLE = 0x86, /* counts the number of cycles the processor cannot dual issue because of multiple reasons */ + MRVL_PJ4B_BIU_ANY_ACCESS = 0x87, /* counts the number of cycles the BIU is accessed by any unit */ + MRVL_PJ4B_MAIN_TLB_REFILL_BY_ICACHE = 0x88, /* counts the number of instruction fetch operations that causes a Main TLB walk */ + MRVL_PJ4B_MAIN_TLB_REFILL_BY_DCACHE = 0x89, /* counts the number of Data read or write operations that causes a Main TLB walk */ + MRVL_PJ4B_ICACHE_READ_BEAT = 0x8a, /* counts the number of times the bus returns RDY to the instruction cache */ + MRVL_PJ4B_PMUEXT_IN0 = 0x90, /* counts any event from external input source PMUEXTIN[0] */ + MRVL_PJ4B_PMUEXT_IN1 = 0x91, /* counts any event from external input source PMUEXTIN[1] */ + MRVL_PJ4B_PMUEXT_IN0_IN1 = 0x92, /* counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1] */ + MRVL_PJ4B_WMMX2_STORE_FIFO_FULL = 0xc0, /* counts the number of cycles when the WMMX2 store FIFO is full */ + MRVL_PJ4B_WMMX2_FINISH_FIFO_FULL = 0xc1, /* counts the number of cycles when the WMMX2 finish FIFO is full */ + MRVL_PJ4B_WMMX2_INST_FIFO_FULL = 0xc2, /* counts the number of cycles when the WMMX2 instruction FIFO is full */ + MRVL_PJ4B_WMMX2_INST_RETIRED = 0xc3, /* counts the number of retired WMMX2 instructions */ + MRVL_PJ4B_WMMX2_BUSY = 0xc4, /* counts the number of cycles when the WMMX2 is busy */ + MRVL_PJ4B_WMMX2_HOLD_MI = 0xc5, /* counts the number of cycles when WMMX2 holds the issue stage */ + MRVL_PJ4B_WMMX2_HOLD_MW = 0xc6, /* counts the number of cycles when WMMX2 holds the write back stage */ + /* EVT_CCNT is not hardware defined */ + MRVL_PJ4B_EVT_CCNT = 0xFE, /* CPU_CYCLE */ + MRVL_PJ4B_EVT_UNUSED = 0xFF, +}; + +enum pj4b_pmu_counters {MRVL_PJ4B_CCNT=0, + MRVL_PJ4B_PMN0, + MRVL_PJ4B_PMN1, + MRVL_PJ4B_PMN2, + MRVL_PJ4B_PMN3, + MRVL_PJ4B_PMN4, + MRVL_PJ4B_PMN5, + MRVL_PJ4B_MAX_COUNTERS}; + +#define MRVL_PJ4B_CCNT_BIT_OFFSET 31 +#define MRVL_PJ4B_PMN_BIT_OFFSET 0 + +#define MRVL_PJ4B_ALL_CNTRS (0x8000003F) + +/* + * The hardware events that we support. We do support cache operations but + * we have harvard caches and no way to combine instruction and data + * accesses/misses in hardware. + */ +static const unsigned mrvl_pj4b_perf_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = MRVL_PJ4B_EVT_CCNT, + [PERF_COUNT_HW_INSTRUCTIONS] = MRVL_PJ4B_INSN_EXECUTED, + [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = MRVL_PJ4B_BR_RETIRED, + [PERF_COUNT_HW_BRANCH_MISSES] = MRVL_PJ4B_BR_PRED_MISS, + [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, +}; + +static const unsigned mrvl_pj4b_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + [C(L1D)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = MRVL_PJ4B_DCACHE_ACCESS, + [C(RESULT_MISS)] = MRVL_PJ4B_DCACHE_READ_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = MRVL_PJ4B_DCACHE_ACCESS, + [C(RESULT_MISS)] = MRVL_PJ4B_DCACHE_WRITE_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = MRVL_PJ4B_ICACHE_READ_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + /*TODO add L2 counters*/ + [C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(DTLB)] = { + /* + * The ARM performance counters can count micro DTLB misses, + * micro ITLB misses and main TLB misses. There isn't an event + * for TLB misses, so use the micro misses here and if users + * want the main TLB misses they can use a raw counter. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = MRVL_PJ4B_DTLB_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = MRVL_PJ4B_DTLB_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = MRVL_PJ4B_ITLB_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = MRVL_PJ4B_ITLB_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(BPU)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = MRVL_PJ4B_BR_RETIRED, + [C(RESULT_MISS)] = MRVL_PJ4B_BR_PRED_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = MRVL_PJ4B_BR_RETIRED, + [C(RESULT_MISS)] = MRVL_PJ4B_BR_PRED_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(NODE)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, +}; + +static int mrvl_pj4b_map_event(struct perf_event *event) +{ + return map_cpu_event(event, &mrvl_pj4b_perf_map, + &mrvl_pj4b_perf_cache_map, 0xFF); +} + + +/*Helper functions*/ +static inline void mrvl_pj4b_pmu_cntr_disable(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(val)); + asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r"(val)); +} + +static inline void mrvl_pj4b_pmu_cntr_enable(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r"(val)); + asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r"(val)); +} + +static inline void mrvl_pj4b_pmu_select_event(u32 cntr, u32 evt) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r"(cntr)); + asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r"(evt)); +} + +static inline void mrvl_pj4b_pmu_clear_events(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r"(val)); +} + +static inline void mrvl_pj4b_pmu_enable_events(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 1": : "r"(val)); +} + +static inline u32 mrvl_pj4b_pmu_read_events(void) +{ + u32 val; + asm volatile("mcr p15, 0, %0, c9, c12, 1": "=r"(val)); + return val; +} + + +static inline void mrvl_pj4b_write_pmnc(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 0": : "r"(val)); +} + +static inline u32 mrvl_pj4b_read_pmnc(void) +{ + u32 val; + + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); + + return val; +} + +static inline void mrvl_pj4b_pmu_clear_overflow(u32 val) +{ + /* writeback clears overflow bits */ + asm volatile("mcr p15, 0, %0, c9, c12, 3": : "r"(val)); +} + +static inline int mrvl_pj4b_pmu_counter_has_overflowed(unsigned long val, + enum pj4b_pmu_counters counter) +{ + int ret = 0; + + if (counter == MRVL_PJ4B_CCNT) + ret = (val & (1 << MRVL_PJ4B_CCNT_BIT_OFFSET)); + else if (counter < MRVL_PJ4B_MAX_COUNTERS) + ret = (val & (1 << (counter-MRVL_PJ4B_PMN0))); + else + WARN_ONCE(1, "invalid counter number (%d)\n", counter); + + return ret; + +} + +static inline u32 mrvl_pj4b_pmu_read_overflow(void) +{ + u32 val; + /* check counter */ + asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r"(val)); + return val; +} + + +/*API functions*/ +static u32 mrvl_pj4b_pmu_read_counter(int counter) +{ + u32 val = 0; + + switch (counter) { + case MRVL_PJ4B_CCNT: + asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); + break; + case MRVL_PJ4B_PMN0: + case MRVL_PJ4B_PMN1: + case MRVL_PJ4B_PMN2: + case MRVL_PJ4B_PMN3: + case MRVL_PJ4B_PMN4: + case MRVL_PJ4B_PMN5: + asm volatile("mcr p15, 0, %0, c9, c12, 5": : "r"(counter - MRVL_PJ4B_PMN0)); + asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r"(val)); + break; + } + return val; +} + +static void mrvl_pj4b_pmu_write_counter(int counter, u32 val) +{ + switch (counter) { + case MRVL_PJ4B_CCNT: + asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val)); + break; + case MRVL_PJ4B_PMN0: + case MRVL_PJ4B_PMN1: + case MRVL_PJ4B_PMN2: + case MRVL_PJ4B_PMN3: + case MRVL_PJ4B_PMN4: + case MRVL_PJ4B_PMN5: + asm volatile("mcr p15, 0, %0, c9, c12, 5": : "r"(counter - MRVL_PJ4B_PMN0)); + asm volatile("mcr p15, 0, %0, c9, c13, 2": : "r"(val)); + break; + } +} + + +static inline int mrvl_pj4b_pmu_event_map(int config) +{ + int mapping = mrvl_pj4b_perf_map[config]; + if (HW_OP_UNSUPPORTED == mapping) + mapping = -EOPNOTSUPP; + return mapping; +} + +static int mrvl_pj4b_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct hw_perf_event *event) +{ + int idx; + /* Always place a cycle counter into the cycle counter. */ + if (event->config_base == MRVL_PJ4B_EVT_CCNT) { + if (test_and_set_bit(MRVL_PJ4B_CCNT, cpuc->used_mask)) { + return -EAGAIN; + } + return MRVL_PJ4B_CCNT; + } else { + /* + * For anything other than a cycle counter, try and use + * the events counters + */ + for (idx = MRVL_PJ4B_PMN0; idx < cpu_pmu->num_events; ++idx) { + if (!test_and_set_bit(idx, cpuc->used_mask)) { + return idx; + } + } + /* The counters are all in use. */ + return -EAGAIN; + } +} + +void mrvl_pj4b_pmu_enable_event(struct hw_perf_event *hwc, int idx) +{ + u32 enable; + unsigned long flags; + struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + raw_spin_lock_irqsave(&events->pmu_lock, flags); + if (idx == MRVL_PJ4B_CCNT) { + enable = (1 << MRVL_PJ4B_CCNT_BIT_OFFSET); + } + else if (idx < MRVL_PJ4B_MAX_COUNTERS) { + enable = (1 << (idx - MRVL_PJ4B_PMN0)); + } + else { + WARN_ONCE(1, "invalid counter number (%d)\n", idx); + return; + } + mrvl_pj4b_pmu_cntr_disable(enable); + /*select event*/ + if (idx != MRVL_PJ4B_CCNT) { + /*select event*/ + u32 evt = (hwc->config_base & 0xFF); + mrvl_pj4b_pmu_select_event((idx-MRVL_PJ4B_PMN0), evt); + } + mrvl_pj4b_pmu_cntr_enable(enable); + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); +} + + +void mrvl_pj4b_pmu_disable_event(struct hw_perf_event *hwc, int idx) +{ + u32 enable; + unsigned long flags; + struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + raw_spin_lock_irqsave(&events->pmu_lock, flags); + if (idx == MRVL_PJ4B_CCNT) { + enable = (1 << MRVL_PJ4B_CCNT_BIT_OFFSET); + } + else if (idx < MRVL_PJ4B_MAX_COUNTERS) { + enable = (1 << (idx - MRVL_PJ4B_PMN0)); + } + else { + WARN_ONCE(1, "invalid counter number (%d)\n", idx); + return; + } + mrvl_pj4b_pmu_cntr_disable(enable); + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); +} + + +static irqreturn_t mrvl_pj4b_pmu_handle_irq(int irq, void *arg) +{ + int i = 0; + u32 flag; + struct pt_regs *regs; + struct perf_sample_data data; + struct pmu_hw_events *cpuc; + u32 pmnc; + + if(!(readl(INTER_REGS_BASE| 0x20260)&&0xF)) + return IRQ_NONE; + pmnc = mrvl_pj4b_read_pmnc(); + pmnc &= ~MRVL_PJ4B_PMU_ENABLE; + mrvl_pj4b_write_pmnc(pmnc); + + flag = mrvl_pj4b_pmu_read_overflow(); + mrvl_pj4b_pmu_clear_overflow(flag); + + /* + * Did an overflow occur? + */ + if (!flag) { + pmnc |= MRVL_PJ4B_PMU_ENABLE; + mrvl_pj4b_write_pmnc(pmnc); + return IRQ_NONE; + } + /* + * Handle the counter(s) overflow(s) + */ + regs = get_irq_regs(); + perf_sample_data_init(&data, 0); + + cpuc = &__get_cpu_var(cpu_hw_events); + + for (i = MRVL_PJ4B_CCNT; i < cpu_pmu->num_events; i++) { + + struct perf_event *event = cpuc->events[i]; + struct hw_perf_event *hwc; + +/* if (!test_bit(i, cpuc->active_mask)) { + continue; + } +*/ + if (!mrvl_pj4b_pmu_counter_has_overflowed(flag, i)) { + continue; + } + + hwc = &event->hw; + armpmu_event_update(event, hwc, i); + data.period = event->hw.last_period; + + if (!armpmu_event_set_period(event, hwc, i)) { + continue; + } + + if (perf_event_overflow(event, &data, regs)) + cpu_pmu->disable(hwc, i); + } + pmnc |= MRVL_PJ4B_PMU_ENABLE; + mrvl_pj4b_write_pmnc(pmnc); + + /* + * Handle the pending perf events. + * + * Note: this call *must* be run with interrupts enabled. For + * platforms that can have the PMU interrupts raised as a PMI, this + * will not work. + */ + //perf_event_do_pending(); + irq_work_run(); + + return IRQ_HANDLED; +} + +#if 0 +asmlinkage void __exception_irq_entry do_mrvl_pj4b_pmu_event(struct pt_regs *regs) +{ + struct pt_regs *old_regs = set_irq_regs(regs); + int cpu = smp_processor_id(); + irq_enter(); + irq_stat[cpu].local_pmu_irqs++; + cpu_pmu->handle_irq(IRQ_AURORA_MP, NULL); + irq_exit(); + set_irq_regs(old_regs); +} + +#endif + +static void mrvl_pj4b_pmu_stop(void) +{ + u32 pmnc; + unsigned long flags; + struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + raw_spin_lock_irqsave(&events->pmu_lock, flags); + pmnc = mrvl_pj4b_read_pmnc(); + pmnc &= ~MRVL_PJ4B_PMU_ENABLE; + mrvl_pj4b_write_pmnc(pmnc); + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); +} + + +static void mrvl_pj4b_pmu_start(void) +{ + u32 pmnc; + unsigned long flags; + struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + raw_spin_lock_irqsave(&events->pmu_lock, flags); + pmnc = mrvl_pj4b_read_pmnc(); + pmnc |= (MRVL_PJ4B_PMU_ENABLE); + mrvl_pj4b_write_pmnc(pmnc); + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); +} + +static u32 __init mrvl_pj4b_read_reset_pmnc(void) +{ + u32 pmnc = mrvl_pj4b_read_pmnc(); +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_PMU_RESET + mrvl_pj4b_write_pmnc(pmnc); /* WA - need to write 0 to bit 2 before + write*/ +#endif + pmnc |= (MRVL_PJ4B_PMU_RESET); + mrvl_pj4b_write_pmnc(pmnc); + return ((pmnc >> 11) & 0x1F)+1; +} + +static void mrvl_pj4b_pmu_reset(void *info) +{ + u32 idx, nb_cnt = cpu_pmu->num_events; + + /* The counter and interrupt enable registers are unknown at reset. */ + for (idx = 1; idx < nb_cnt; ++idx) + mrvl_pj4b_pmu_disable_event(NULL, idx); + + /* Initialize & Reset PMNC: C and P bits */ + mrvl_pj4b_write_pmnc(PJ4BV7_PMNC_P | PJ4BV7_PMNC_C); + +} + + +static struct arm_pmu mrvl_pj4b_pmu = { + + .id = MRVL_PERF_PMU_ID_PJ4B, + .name = "Armada PJ4", + .stop = mrvl_pj4b_pmu_stop, /*v*/ + .start = mrvl_pj4b_pmu_start, /*v*/ + .enable = mrvl_pj4b_pmu_enable_event, /*v*/ + .disable = mrvl_pj4b_pmu_disable_event, /*v*/ + .read_counter = mrvl_pj4b_pmu_read_counter, /*v*/ + .write_counter = mrvl_pj4b_pmu_write_counter, /*v*/ + .get_event_idx = mrvl_pj4b_pmu_get_event_idx,/*v*/ + .handle_irq = mrvl_pj4b_pmu_handle_irq, /*v*/ + .reset = mrvl_pj4b_pmu_reset, + .map_event = mrvl_pj4b_map_event, + .num_events = MRVL_PJ4B_MAX_COUNTERS, + .max_period = (1LLU << 32) - 1, +}; + +static struct arm_pmu *__init mrvl_pj4b_pmu_init(void) +{ + return &mrvl_pj4b_pmu; +} + +#endif /*#ifdef CONFIG_ARCH_ARMADA_XP*/ diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c old mode 100644 new mode 100755 index e68d2512f..ccc37c994 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -495,22 +495,40 @@ unsigned long arch_randomize_brk(struct mm_struct *mm) #ifdef CONFIG_MMU /* * The vectors page is always readable from user space for the - * atomic helpers and the signal restart code. Let's declare a mapping - * for it so it is visible through ptrace and /proc//mem. + * atomic helpers and the signal restart code. Insert it into the + * gate_vma so that it is visible through ptrace and /proc//mem. */ +static struct vm_area_struct gate_vma; -int vectors_user_mapping(void) +static int __init gate_vma_init(void) { - struct mm_struct *mm = current->mm; - return install_special_mapping(mm, 0xffff0000, PAGE_SIZE, - VM_READ | VM_EXEC | - VM_MAYREAD | VM_MAYEXEC | - VM_ALWAYSDUMP | VM_RESERVED, - NULL); + gate_vma.vm_start = 0xffff0000; + gate_vma.vm_end = 0xffff0000 + PAGE_SIZE; + gate_vma.vm_page_prot = PAGE_READONLY_EXEC; + gate_vma.vm_flags = VM_READ | VM_EXEC | + VM_MAYREAD | VM_MAYEXEC | + VM_ALWAYSDUMP; + return 0; +} +arch_initcall(gate_vma_init); + +struct vm_area_struct *get_gate_vma(struct mm_struct *mm) +{ + return &gate_vma; +} + +int in_gate_area(struct mm_struct *mm, unsigned long addr) +{ + return (addr >= gate_vma.vm_start) && (addr < gate_vma.vm_end); +} + +int in_gate_area_no_mm(unsigned long addr) +{ + return in_gate_area(NULL, addr); } const char *arch_vma_name(struct vm_area_struct *vma) { - return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL; + return (vma == &gate_vma) ? "[vectors]" : NULL; } #endif diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c old mode 100644 new mode 100755 index 8fc2c8fcb..2e4c2bea3 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -59,10 +59,81 @@ #include "atags.h" #include "tcm.h" + +#ifdef MY_ABC_HERE +extern char gszSynoHWVersion[]; +#endif + +#ifdef MY_ABC_HERE +extern char gszSynoHWRevision[]; +#endif + +#ifdef MY_ABC_HERE +extern long g_internal_hd_num; +#endif + +#ifdef MY_ABC_HERE +extern long g_internal_netif_num; +long g_egiga = 1; +#endif + +#ifdef MY_ABC_HERE +extern long g_sata_led_special; +#endif + +#ifdef MY_ABC_HERE +extern long g_hdd_hotplug; +#endif + +#ifdef MY_ABC_HERE +extern unsigned char grgbLanMac[4][16]; +#endif + +#ifdef MY_ABC_HERE +extern char gszSerialNum[32]; +extern char gszCustomSerialNum[32]; +#endif + +#ifdef MY_DEF_HERE +extern long g_esata_7042; +#endif #ifndef MEM_SIZE #define MEM_SIZE (16*1024*1024) #endif +#ifdef MY_ABC_HERE +extern char gszDiskIdxMap[16]; +#endif + +#ifdef MY_ABC_HERE +extern char giDiskSeqReverse[8]; +#endif + +#ifdef MY_ABC_HERE +extern unsigned int gSwitchDev; +extern char gDevPCIName[SYNO_MAX_SWITCHABLE_NET_DEVICE][SYNO_NET_DEVICE_ENCODING_LENGTH]; +#endif + +#ifdef MY_ABC_HERE +extern int gSynoHasDynModule; +#endif + +#ifdef MY_DEF_HERE +extern long gSynoFlashMemorySize; +#endif + +#ifdef MY_ABC_HERE +extern int gSynoFactoryUSBFastReset; +#endif + +#ifdef MY_ABC_HERE +extern int gSynoFactoryUSB3Disable; +#endif + +#ifdef MY_ABC_HERE +extern int gSynoNoEhci; +#endif + #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE) char fpe_type[8]; @@ -75,6 +146,330 @@ static int __init fpe_setup(char *line) __setup("fpe=", fpe_setup); #endif + + +#ifdef MY_ABC_HERE +static int __init early_hw_version(char *p) +{ + char *szPtr; + + snprintf(gszSynoHWVersion, 16, "%s", p); + + szPtr = gszSynoHWVersion; + while ((*szPtr != ' ') && (*szPtr != '\t') && (*szPtr != '\0')) { + szPtr++; + } + *szPtr = 0; + strcat(gszSynoHWVersion, "-j"); + + printk("Synology Hardware Version: %s\n", gszSynoHWVersion); + + return 1; +} +__setup("syno_hw_version=", early_hw_version); +#endif + +#ifdef MY_ABC_HERE +static int __init early_hw_revision(char *p) +{ + snprintf(gszSynoHWRevision, 4, "%s", p); + + printk("Synology Hardware Revision: %s\n", gszSynoHWRevision); + + return 1; +} +__setup("rev=", early_hw_revision); +#endif + +#ifdef MY_ABC_HERE +static int __init early_internal_hd_num(char *p) +{ + g_internal_hd_num = simple_strtol(p, NULL, 10); + + printk("Internal HD num: %d\n", (int)g_internal_hd_num); + + return 1; +} +__setup("ihd_num=", early_internal_hd_num); +#endif + +#ifdef MY_ABC_HERE +static int __init early_internal_netif_num(char *p) +{ + g_internal_netif_num = simple_strtol(p, NULL, 10); + + if ( g_internal_netif_num >= 0 ) { + printk("Internal netif num: %d\n", (int)g_internal_netif_num); + } + + return 1; +} +__setup("netif_num=", early_internal_netif_num); + +static void __init early_egiga(char *p) +{ + g_egiga = simple_strtol(p, NULL, 10); + + if ( g_egiga == 0 ) { + printk("egiga port is disabled\n"); + } +} +__setup("egiga=", early_egiga); +#endif + +#ifdef MY_ABC_HERE +static int __init early_sataled_special(char *p) +{ + g_sata_led_special = simple_strtol(p, NULL, 10); + + if ( g_sata_led_special >= 0 ) { + printk("Special Sata LEDs.\n"); + } + + return 1; +} +__setup("SataLedSpecial=", early_sataled_special); +#endif + +#ifdef MY_ABC_HERE +static int __init early_hdd_hotplug(char *p) +{ + g_hdd_hotplug = simple_strtol(p, NULL, 10); + + if ( g_hdd_hotplug > 0 ) { + printk("Support HDD Hotplug.\n"); + } + + return 1; +} +__setup("HddHotplug=", early_hdd_hotplug); +#endif + +#ifdef MY_ABC_HERE +static int __init early_mac1(char *p) +{ + snprintf(grgbLanMac[0], sizeof(grgbLanMac[0]), "%s", p); + + printk("Mac1: %s\n", grgbLanMac[0]); + + return 1; +} +__setup("mac1=", early_mac1); + +static int __init early_mac2(char *p) +{ + snprintf(grgbLanMac[1], sizeof(grgbLanMac[1]), "%s", p); + + printk("Mac2: %s\n", grgbLanMac[1]); + + return 1; +} +__setup("mac2=", early_mac2); + +static int __init early_mac3(char *p) +{ + snprintf(grgbLanMac[2], sizeof(grgbLanMac[2]), "%s", p); + + printk("Mac3: %s\n", grgbLanMac[2]); + + return 1; +} +__setup("mac3=", early_mac3); + +static int __init early_mac4(char *p) +{ + snprintf(grgbLanMac[3], sizeof(grgbLanMac[3]), "%s", p); + + printk("Mac4: %s\n", grgbLanMac[3]); + + return 1; +} +__setup("mac4=", early_mac4); +#endif + +#ifdef MY_ABC_HERE +static int __init early_netif_seq(char *p) +{ + int len; + int netDevCount; + + // no net device switch required + if ((NULL == p) || (0 == (len = strlen(p)))) { + return 1; + } + + /** + * We change the way that we represent the net device name is due to a truth that + * when a PCIE extension card is plugged in, the pcie name will change + * So we give up the pci-name as our matching condition, we use NIC up sequence instead. + * Because the NIC layout is fixed on our board, we the NIC up sequence won't change. + * And according to this sequence, we assign the device name to NIC + * + * Following codes are designed to compatible with bromolow/x64 which has already been produced. + * Based on the truth that our bromolow/x64 has at least 2 internal lan so far (2011/5/24) + * And 2 internal lan needs netif_seq whose length is 12 + * So we judge that if netif_seq is less than 12, then it should be new version of netif_seq + * 2411+ has 2 internal lans now so we use 12 as our boundary condition + */ + if (len <= SYNO_MAX_SWITCHABLE_NET_DEVICE) { + netDevCount = len; + for(gSwitchDev = 0 ; gSwitchDev < netDevCount && gSwitchDev < SYNO_MAX_SWITCHABLE_NET_DEVICE ; gSwitchDev++) { + gDevPCIName[gSwitchDev][0] = *p++; + } + return 1; + } + + netDevCount = len/SYNO_NET_DEVICE_ENCODING_LENGTH; + if (0 == netDevCount) { + return 1; + } + + for(gSwitchDev = 0 ; gSwitchDev < netDevCount && gSwitchDev < SYNO_MAX_SWITCHABLE_NET_DEVICE ; gSwitchDev++) { + // the format of netif_seq string is device seq (1 character) + device pci name (last 5 characters only) + memcpy(gDevPCIName[gSwitchDev], p, SYNO_NET_DEVICE_ENCODING_LENGTH); + p += SYNO_NET_DEVICE_ENCODING_LENGTH; + } + return 1; +} + +__setup("netif_seq=",early_netif_seq); +#endif + +#ifdef MY_ABC_HERE +static int __init early_sn(char *p) +{ + snprintf(gszSerialNum, sizeof(gszSerialNum), "%s", p); + printk("Serial Number: %s\n", gszSerialNum); + return 1; +} +__setup("sn=", early_sn); + +static int __init early_custom_sn(char *p) +{ + snprintf(gszCustomSerialNum, sizeof(gszCustomSerialNum), "%s", p); + printk("Custom Serial Number: %s\n", gszCustomSerialNum); + return 1; +} +__setup("custom_sn=", early_custom_sn); +#endif + +#ifdef MY_DEF_HERE +static int __init early_esata_7042(char *p) +{ + g_esata_7042 = simple_strtol(p, NULL, 10); + + printk("Esata chip use 7042: %d\n", (int)g_esata_7042); + + return 1; +} +__setup("esata_7042=", early_esata_7042); +#endif + +#ifdef MY_ABC_HERE +static int __init early_disk_idx_map(char *p) +{ + snprintf(gszDiskIdxMap, sizeof(gszDiskIdxMap), "%s", p); + + if('\0' != gszDiskIdxMap[0]) { + printk("Disk Index Map: %s\n", gszDiskIdxMap); + } + + return 1; +} +__setup("DiskIdxMap=", early_disk_idx_map); +#endif + +#ifdef MY_ABC_HERE +static int __init early_disk_seq_reserve(char *p) +{ + snprintf(giDiskSeqReverse, sizeof(giDiskSeqReverse), "%s", p); + + if('\0' != giDiskSeqReverse[0]) { + printk("Disk Sequence Reverse: %s\n", giDiskSeqReverse); + } + + return 1; +} +__setup("DiskSeqReverse=", early_disk_seq_reserve); +#endif + +#ifdef MY_ABC_HERE +static int __init early_is_dyn_module(char *p) +{ + int iLen = 0; + + gSynoHasDynModule = 0; + + if ((NULL == p) || (0 == (iLen = strlen(p)))) { + goto END; + } + + if ( 0 == strcmp (p, "y")) { + gSynoHasDynModule = 1; + printk("Synology Dynamic Module support.\n"); + } + +END: + return 1; +} +__setup("syno_dyn_module=", early_is_dyn_module); +#endif + +#ifdef MY_DEF_HERE +static int __init early_flash_memory_size(char *p) +{ + int iLen = 0; + + if ((NULL == p) || (0 == (iLen = strlen(p)))) { + gSynoFlashMemorySize = 4; + } else { + gSynoFlashMemorySize = simple_strtol(p, NULL, 10); + } + + printk("Flash Memory Size: %d MB\n", (int)gSynoFlashMemorySize); + +END: + return 1; +} +__setup("flash_size=", early_flash_memory_size); +#endif + +#ifdef MY_ABC_HERE +static int __init early_factory_usb_fast_reset(char *p) +{ + gSynoFactoryUSBFastReset = simple_strtol(p, NULL, 10); + + printk("Factory USB Fast Reset: %d\n", (int)gSynoFactoryUSBFastReset); + + return 1; +} +__setup("syno_usb_fast_reset=", early_factory_usb_fast_reset); +#endif + +#ifdef MY_ABC_HERE +static int __init early_factory_usb3_disable(char *p) +{ + gSynoFactoryUSB3Disable = simple_strtol(p, NULL, 10); + + printk("Factory USB3 Disable: %d\n", (int)gSynoFactoryUSB3Disable); + + return 1; +} +__setup("syno_disable_usb3=", early_factory_usb3_disable); +#endif + +#ifdef MY_ABC_HERE +static int __init early_no_ehci(char *p) +{ + gSynoNoEhci = simple_strtol(p, NULL, 10); + + printk("No Ehci: %d\n", gSynoNoEhci); + + return 1; +} +__setup("syno_no_ehci=", early_no_ehci); +#endif + extern void paging_init(struct machine_desc *desc); extern void sanity_check_meminfo(void); extern void reboot_setup(char *str); @@ -623,11 +1018,19 @@ static void __init request_standard_resources(struct machine_desc *mdesc) */ static int __init parse_tag_core(const struct tag *tag) { +#if defined(CONFIG_SYNO_ARMADA_ARCH) + if (read_tag(tag->hdr.size) > 2) { + if ((read_tag(tag->u.core.flags) & 1) == 0) + root_mountflags &= ~MS_RDONLY; + ROOT_DEV = old_decode_dev(read_tag(tag->u.core.rootdev)); + } +#else if (tag->hdr.size > 2) { if ((tag->u.core.flags & 1) == 0) root_mountflags &= ~MS_RDONLY; ROOT_DEV = old_decode_dev(tag->u.core.rootdev); } +#endif return 0; } @@ -635,11 +1038,43 @@ __tagtable(ATAG_CORE, parse_tag_core); static int __init parse_tag_mem32(const struct tag *tag) { +#if defined(CONFIG_SYNO_ARMADA_ARCH) + return arm_add_memory(read_tag(tag->u.mem.start), read_tag(tag->u.mem.size)); +#else return arm_add_memory(tag->u.mem.start, tag->u.mem.size); +#endif } __tagtable(ATAG_MEM, parse_tag_mem32); +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_PHYS_ADDR_T_64BIT) +static int __init parse_tag_mem64(const struct tag *tag) +{ +#ifdef CONFIG_ARM_LPAE + /* We might have 4GB on a single CS. */ + if (tag->u.mem64.size >= 0x100000000ll) { + u64 tmp_size = tag->u.mem64.size; + phys_addr_t tmp_start = tag->u.mem64.start; + u32 blk_size; + int ret; + while (tmp_size > 0ll) { + blk_size = ((tmp_size < 0x100000000ll) ? (u32)tmp_size : (2ll << 30ll)); + ret = arm_add_memory(tmp_start, blk_size); + if (ret) + return ret; + tmp_start += (u64)blk_size; + tmp_size -= (u64)blk_size; + } + return 0; + } +#endif + /* We only use 32-bits for the size. */ + return arm_add_memory(tag->u.mem64.start, (unsigned long)tag->u.mem64.size); +} + +__tagtable(ATAG_MEM64, parse_tag_mem64); +#endif /* CONFIG_PHYS_ADDR_T_64BIT */ + #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) struct screen_info screen_info = { .orig_video_lines = 30, @@ -688,7 +1123,11 @@ __tagtable(ATAG_SERIAL, parse_tag_serialnr); static int __init parse_tag_revision(const struct tag *tag) { +#if defined(CONFIG_SYNO_ARMADA_ARCH) + system_rev = read_tag(tag->u.revision.rev); +#else system_rev = tag->u.revision.rev; +#endif return 0; } @@ -722,7 +1161,11 @@ static int __init parse_tag(const struct tag *tag) struct tagtable *t; for (t = &__tagtable_begin; t < &__tagtable_end; t++) +#if defined(CONFIG_SYNO_ARMADA_ARCH) + if ((read_tag(tag->hdr.tag) == t->tag)) { +#else if (tag->hdr.tag == t->tag) { +#endif t->parse(tag); break; } @@ -736,9 +1179,17 @@ static int __init parse_tag(const struct tag *tag) */ static void __init parse_tags(const struct tag *t) { +#if defined(CONFIG_SYNO_ARMADA_ARCH) + for (; read_tag(t->hdr.size); t = tag_next(t)) +#else for (; t->hdr.size; t = tag_next(t)) +#endif if (!parse_tag(t)) +#if defined(CONFIG_SYNO_ARMADA_ARCH) + early_printk(KERN_WARNING +#else printk(KERN_WARNING +#endif "Ignoring unrecognised tag 0x%08x\n", t->hdr.tag); } @@ -859,11 +1310,19 @@ static struct machine_desc * __init setup_machine_tags(unsigned int nr) * If we have the old style parameters, convert them to * a tag list. */ +#if defined(CONFIG_SYNO_ARMADA_ARCH) +if (read_tag(tags->hdr.tag) != ATAG_CORE) +#else if (tags->hdr.tag != ATAG_CORE) +#endif convert_to_tag_list(tags); #endif +#if defined(CONFIG_SYNO_ARMADA_ARCH) + if (read_tag(tags->hdr.tag) != ATAG_CORE) { +#else if (tags->hdr.tag != ATAG_CORE) { +#endif #if defined(CONFIG_OF) /* * If CONFIG_OF is set, then assume this is a reasonably @@ -877,7 +1336,11 @@ static struct machine_desc * __init setup_machine_tags(unsigned int nr) if (mdesc->fixup) mdesc->fixup(tags, &from, &meminfo); +#if defined(CONFIG_SYNO_ARMADA_ARCH) + if (read_tag(tags->hdr.tag) == ATAG_CORE) { +#else if (tags->hdr.tag == ATAG_CORE) { +#endif if (meminfo.nr_banks != 0) squash_mem_tags(tags); save_atags(tags); @@ -926,6 +1389,12 @@ void __init setup_arch(char **cmdline_p) arm_memblock_init(&meminfo, mdesc); paging_init(mdesc); +#ifdef CONFIG_DEBUG_LL + { + extern int ll_debug; + ll_debug=1; + } +#endif request_standard_resources(mdesc); unflatten_device_tree(); diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S old mode 100644 new mode 100755 index 020e99c84..006885676 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -56,8 +56,14 @@ ENDPROC(cpu_suspend_abort) .align 5 ENTRY(cpu_resume_mmu) ldr r3, =cpu_resume_after_mmu +#if defined(CONFIG_SYNO_ARMADA_ARCH) + instr_sync +#endif mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc mrc p15, 0, r0, c0, c0, 0 @ read id reg +#if defined(CONFIG_SYNO_ARMADA_ARCH) + instr_sync +#endif mov r0, r0 mov r0, r0 mov pc, r3 @ jump to virtual address diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c old mode 100644 new mode 100755 index bfa0eeb5e..dfe9666aa --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -50,6 +50,9 @@ struct secondary_data secondary_data; enum ipi_msg_type { +#if defined(CONFIG_SYNO_ARMADA_ARCH) + IPI_WAKE = 0, +#endif IPI_TIMER = 2, IPI_RESCHEDULE, IPI_CALL_FUNC, @@ -305,6 +308,15 @@ asmlinkage void __cpuinit secondary_start_kernel(void) enter_lazy_tlb(mm, current); local_flush_tlb_all(); +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#ifdef CONFIG_MACH_ARMADA_XP_FPGA + unsigned int cpurev; + + __asm__ __volatile__("mrc p15, 1, %0, c0, c0, 7 @ read CPU ID reg\n" + : "=r" (cpurev) :: "memory"); +#endif +#endif + /* * All kernel threads share the same mm context; grab a * reference and switch to it. @@ -314,7 +326,11 @@ asmlinkage void __cpuinit secondary_start_kernel(void) current->active_mm = mm; cpumask_set_cpu(cpu, mm_cpumask(mm)); +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_MACH_ARMADA_XP_FPGA) + printk("CPU%u: FPGA Booted secondary processor (ID 0x%04x)\n", cpu, (cpurev & 0xFFFF)); +#else printk("CPU%u: Booted secondary processor\n", cpu); +#endif cpu_init(); preempt_disable(); @@ -351,7 +367,10 @@ asmlinkage void __cpuinit secondary_start_kernel(void) * now. */ local_irq_enable(); + +#if !defined(CONFIG_SYNO_COMCERTO) || !defined(CONFIG_COMCERTO_MSP) local_fiq_enable(); +#endif /* !CONFIG_COMCERTO_MSP */ /* * OK, it's off to the idle thread for us @@ -474,6 +493,22 @@ u64 smp_irq_stat_cpu(unsigned int cpu) */ static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent); +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#if defined(CONFIG_ARCH_ARMADA_XP) && defined(CONFIG_PERF_EVENTS) +void show_local_pmu_irqs(struct seq_file *p, int prec) +{ + unsigned int cpu; + + seq_printf(p, "PMU: "); + + for_each_present_cpu(cpu) + seq_printf(p, "%10u ", irq_stat[cpu].local_pmu_irqs); + + seq_putc(p, '\n'); +} +#endif +#endif + static void ipi_timer(void) { struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent); @@ -575,6 +610,11 @@ void handle_IPI(int ipinr, struct pt_regs *regs) __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]); switch (ipinr) { +#if defined(CONFIG_SYNO_ARMADA_ARCH) + case IPI_WAKE: + break; +#endif + case IPI_TIMER: irq_enter(); ipi_timer(); diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c old mode 100644 new mode 100755 index 8f5dd7963..5508a8a12 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -52,6 +52,10 @@ void scu_enable(void __iomem *scu_base) if (scu_ctrl & 1) return; +#if defined(CONFIG_SYNO_COMCERTO) && defined(CONFIG_SCU_SPECULATIVE_LINE_FILLS) + scu_ctrl |= (1 << 3); +#endif + scu_ctrl |= 1; __raw_writel(scu_ctrl, scu_base + SCU_CTRL); diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c old mode 100644 new mode 100755 index 7dcb35285..93eaa6a89 --- a/arch/arm/kernel/smp_tlb.c +++ b/arch/arm/kernel/smp_tlb.c @@ -13,6 +13,9 @@ #include #include +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#include +#endif static void on_each_cpu_mask(void (*func)(void *), void *info, int wait, const struct cpumask *mask) { @@ -137,3 +140,31 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end) local_flush_tlb_kernel_range(start, end); } +#if defined(CONFIG_SYNO_ARMADA_ARCH) && ( ( ( defined( CONFIG_SMP ) && defined( CONFIG_CPU_V6 ) ) || ( defined( CONFIG_SMP ) && defined( CONFIG_CPU_V6K ) ) ) ) +static inline void ipi_flush_cache_user_range(void *arg) +{ +#if 0 + struct tlb_args *ta = (struct tlb_args *)arg; + printk("function %s line %d\n", __func__,__LINE__); + local_flush_cache_user_range((struct vm_area_struct *)ta->ta_vma, ta->ta_start, ta->ta_end); +#else /* To verify that JAVA is working */ + __cpuc_flush_kern_all(); +#endif +} + +//#if defined(CONFIG_SMP) && defined(CONFIG_CPU_V6) + +void flush_cache_user_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ + if (tlb_ops_need_broadcast()) { + struct tlb_args ta; + ta.ta_vma = vma; + ta.ta_start = start; + ta.ta_end = end; + on_each_cpu_mask(ipi_flush_cache_user_range, &ta, 1, mm_cpumask(vma->vm_mm)); + } else{ + local_flush_cache_user_range(vma, start, end); + } +} +#endif diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c old mode 100644 new mode 100755 index 76cbb055d..3951736b4 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -26,7 +26,8 @@ #include #include #include -#include + +#include /* Fork a new task - this creates a new program thread. * This is called indirectly via a small wrapper diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c old mode 100644 new mode 100755 index 7ac5dfd8a..fb47de579 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -788,6 +788,9 @@ void __init early_trap_init(void) extern char __stubs_start[], __stubs_end[]; extern char __vectors_start[], __vectors_end[]; extern char __kuser_helper_start[], __kuser_helper_end[]; +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARMADA_XP_A0_WITH_B0) + extern unsigned int soc_revision; +#endif int kuser_sz = __kuser_helper_end - __kuser_helper_start; /* @@ -799,6 +802,11 @@ void __init early_trap_init(void) memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start); memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz); +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_ARMADA_XP_A0_WITH_B0) + *(unsigned int*)(vectors + 0x1000 - kuser_sz + 0x1C) = soc_revision; + *(unsigned int*)(vectors + 0x1000 - kuser_sz + 0x3C) = soc_revision; +#endif + /* * Do processor specific fixups for the kuser helpers */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile old mode 100644 new mode 100755 index cf73a7f74..aa32b85ff --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -45,3 +45,9 @@ lib-$(CONFIG_ARCH_SHARK) += io-shark.o $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S $(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S + +ifeq ($(CONFIG_KERNEL_MODE_NEON),y) + NEON_FLAGS := -mfloat-abi=softfp -mfpu=neon + CFLAGS_xor-neon.o += $(NEON_FLAGS) + lib-$(CONFIG_XOR_BLOCKS) += xor-neon.o +endif diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S old mode 100644 new mode 100755 index 6ee2f6706..0ccc6af64 --- a/arch/arm/lib/copy_page.S +++ b/arch/arm/lib/copy_page.S @@ -28,7 +28,13 @@ ENTRY(copy_page) stmfd sp!, {r4, lr} @ 2 PLD( pld [r1, #0] ) PLD( pld [r1, #L1_CACHE_BYTES] ) +#if defined(CONFIG_SYNO_ARMADA_ARCH) && defined(CONFIG_MV_SUPPORT_64KB_PAGE_SIZE) + ldr r2, =COPY_COUNT +#elif defined(CONFIG_SYNO_COMCERTO) + ldr r2, =COPY_COUNT @ 1 +#else mov r2, #COPY_COUNT @ 1 +#endif ldmia r1!, {r3, r4, ip, lr} @ 4+1 1: PLD( pld [r1, #2 * L1_CACHE_BYTES]) PLD( pld [r1, #3 * L1_CACHE_BYTES]) diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c old mode 100644 new mode 100755 index 025f742dd..4622b77d3 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -117,7 +117,7 @@ __copy_to_user(void __user *to, const void *from, unsigned long n) return __copy_to_user_std(to, from, n); return __copy_to_user_memcpy(to, from, n); } - + static unsigned long noinline __clear_user_memset(void __user *addr, unsigned long n) { diff --git a/arch/arm/lib/xor-neon.c b/arch/arm/lib/xor-neon.c new file mode 100755 index 000000000..f485e5a2a --- /dev/null +++ b/arch/arm/lib/xor-neon.c @@ -0,0 +1,42 @@ +/* + * linux/arch/arm/lib/xor-neon.c + * + * Copyright (C) 2013 Linaro Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#ifndef __ARM_NEON__ +#error You should compile this file with '-mfloat-abi=softfp -mfpu=neon' +#endif + +/* + * Pull in the reference implementations while instructing GCC (through + * -ftree-vectorize) to attempt to exploit implicit parallelism and emit + * NEON instructions. + */ +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) +#pragma GCC optimize "tree-vectorize" +#else +/* + * While older versions of GCC do not generate incorrect code, they fail to + * recognize the parallel nature of these functions, and emit plain ARM code, + * which is known to be slower than the optimized ARM code in asm-arm/xor.h. + */ +#warning This code requires at least version 4.6 of GCC +#endif + +#pragma GCC diagnostic ignored "-Wunused-variable" +#include + +struct xor_block_template const xor_block_neon_inner = { + .name = "__inner_neon__", + .do_2 = xor_8regs_2, + .do_3 = xor_8regs_3, + .do_4 = xor_8regs_4, + .do_5 = xor_8regs_5, +}; diff --git a/arch/arm/mach-alpine/include/mach/io.h b/arch/arm/mach-alpine/include/mach/io.h new file mode 100755 index 000000000..eab72ac6d --- /dev/null +++ b/arch/arm/mach-alpine/include/mach/io.h @@ -0,0 +1,29 @@ +/* + * arch/arm/mach-alpine/include/mach/io.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-alpine/include/mach/irqs.h b/arch/arm/mach-alpine/include/mach/irqs.h new file mode 100755 index 000000000..7c13872bf --- /dev/null +++ b/arch/arm/mach-alpine/include/mach/irqs.h @@ -0,0 +1,19 @@ +/* + * linux/arch/arm/mach-algen1/include/mach/irqs.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define NR_IRQS 16 diff --git a/arch/arm/mach-alpine/include/mach/memory.h b/arch/arm/mach-alpine/include/mach/memory.h new file mode 100755 index 000000000..db6b0900a --- /dev/null +++ b/arch/arm/mach-alpine/include/mach/memory.h @@ -0,0 +1,27 @@ +/* + * Alpine arch-specific memory + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#ifndef __ASSEMBLER__ + +extern int __alpine_is_coherent(void); +#define arch_is_coherent() (__alpine_is_coherent()) + +#endif +#endif diff --git a/arch/arm/mach-alpine/include/mach/timex.h b/arch/arm/mach-alpine/include/mach/timex.h new file mode 100755 index 000000000..c0442ebcd --- /dev/null +++ b/arch/arm/mach-alpine/include/mach/timex.h @@ -0,0 +1,20 @@ +/* + * linux/arch/arm/mach-alpine/include/mach/timex.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-alpine/include/mach/vmalloc.h b/arch/arm/mach-alpine/include/mach/vmalloc.h new file mode 100755 index 000000000..4143c5df7 --- /dev/null +++ b/arch/arm/mach-alpine/include/mach/vmalloc.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-alpine/include/mach/vmalloc.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define VMALLOC_END 0xf0000000UL diff --git a/arch/arm/mach-armada370/Kconfig b/arch/arm/mach-armada370/Kconfig new file mode 100755 index 000000000..88dcc305d --- /dev/null +++ b/arch/arm/mach-armada370/Kconfig @@ -0,0 +1,13 @@ +if ARCH_ARMADA370 + +config ARMADA_370 + bool "Armada-370 SoC Family" +# select ARMADA_XP_DEEP_IDLE_UNMASK_INTS_WA + select SHEEVA_ERRATA_ARM_CPU_5114 if (CPU_V6) + select SHEEVA_ERRATA_ARM_CPU_4742 + select SHEEVA_ERRATA_ARM_CPU_4659 + select SHEEVA_ERRATA_ARM_CPU_4611 + select MACH_ARMADA_370 + default y + +endif diff --git a/arch/arm/mach-armada370/Makefile b/arch/arm/mach-armada370/Makefile new file mode 100755 index 000000000..f04d7b47a --- /dev/null +++ b/arch/arm/mach-armada370/Makefile @@ -0,0 +1,210 @@ +#******************************************************************************* +# Marvell GPL License Option +# +# If you received this File from Marvell, you may opt to use, redistribute and/or +# modify this File in accordance with the terms and conditions of the General +# Public License Version 2, June 1991 (the "GPL License"), a copy of which is +# available along with the File in the license.txt file or by writing to the Free +# Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +# on the worldwide web at http://www.gnu.org/licenses/gpl.txt. +# +# THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +# DISCLAIMED. The GPL License provides additional details about this warranty +# disclaimer. +#*******************************************************************************/ +ifneq ($(MACHINE),) +include $(srctree)/$(MACHINE)/config/mvRules.mk +endif + +ifdef CONFIG_MV_ETH_NFP + NFPOBJS += $(LSP_NFP_MGR_DIR)/mv_nfp_mgr.o $(LSP_NFP_MGR_DIR)/nfp_sysfs.o $(LSP_NFP_MGR_DIR)/mv_nfp_hooks.o \ + $(LSP_NET_DEV_DIR)/mv_eth_nfp.o +endif + +ifdef CONFIG_MV_ETH_NFP_FIB + NFPOBJS += $(LSP_NFP_MGR_DIR)/nfp_fib_arp_sysfs.o +ifdef CONFIG_IPV6 + NFPOBJS += $(LSP_NFP_MGR_DIR)/ipv6_parsing.o $(LSP_NFP_MGR_DIR)/nfp_fib6_arp_sysfs.o +endif +endif + +ifdef CONFIG_MV_ETH_NFP_CT + NFPOBJS += $(LSP_NFP_MGR_DIR)/nfp_ct_sysfs.o +ifdef CONFIG_IPV6 + NFPOBJS += $(LSP_NFP_MGR_DIR)/nfp_ct6_sysfs.o +endif +endif + +ifdef CONFIG_MV_ETH_NFP_CLASSIFY + NFPOBJS += $(LSP_NFP_MGR_DIR)/nfp_classification_sysfs.o $(LSP_NFP_MGR_DIR)/nfp_exact_classification_sysfs.o \ + $(LSP_NFP_MGR_DIR)/nfp_prio_classification_sysfs.o +endif + +ifdef CONFIG_MV_ETH_NFP_BRIDGE + NFPOBJS += $(LSP_NFP_MGR_DIR)/nfp_bridge_sysfs.o +endif + +ifdef CONFIG_MV_ETH_NFP_VLAN + NFPOBJS += $(LSP_NFP_MGR_DIR)/nfp_vlan_sysfs.o +endif + +ifdef CONFIG_MV_ETH_NFP_PPP + NFPOBJS += $(LSP_NFP_MGR_DIR)/nfp_ppp_sysfs.o +endif + +ifdef CONFIG_MV_ETH_NFP + NFPOBJS += $(HAL_ETH_NFP_DIR)/mvNfp.o +endif + +ifdef CONFIG_MV_ETH_NFP_CT + NFPOBJS += $(HAL_ETH_NFP_DIR)/mvNfpCt.o +endif + +ifdef CONFIG_MV_ETH_NFP_BRIDGE +ifdef CONFIG_MV_ETH_NFP_FDB_MODE + NFPOBJS += $(HAL_ETH_NFP_DIR)/mvNfpFdb.o +else + NFPOBJS += $(HAL_ETH_NFP_DIR)/mvNfpBridge.o +endif +endif + +ifdef CONFIG_MV_ETH_NFP_FIB + NFPOBJS += $(HAL_ETH_NFP_DIR)/mvNfpFib.o +endif + +ifeq ($(CONFIG_MV_ETH_NFP),m) +nfp-objs = $(NFPOBJS) +obj-m := nfp.o +endif + +# Objects list +COMMON_OBJS = $(COMMON_DIR)/mvDebug.o $(COMMON_DIR)/mvCommon.o $(COMMON_DIR)/mvStack.o $(COMMON_DIR)/mvList.o + +OSSERVICES_OBJS = $(OSSERV_DIR)/mvOs.o + +HAL_OBJS = $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o $(HAL_IF_DIR)/mvSysCntmr.o \ + $(HAL_TWSI_DIR)/mvTwsi.o $(HAL_IF_DIR)/mvSysTwsi.o \ + $(HAL_UART_DIR)/mvUart.o $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_DRAM_DIR)/mvDramIf.o \ + $(HAL_IF_DIR)/mvSysDdr.o + +ARMADA_FAM_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvSpec.o $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o \ + $(SOC_SYS_DIR)/mvAhbToMbus.o $(SOC_SYS_DIR)/mvCpuIf.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o + +QD_OBJS = $(HAL_QD_DIR)/src/driver/gtDrvConfig.o $(HAL_QD_DIR)/src/driver/gtDrvEvents.o \ + $(HAL_QD_DIR)/src/driver/gtHwCntl.o $(HAL_QD_DIR)/src/platform/gtMiiSmiIf.o \ + $(HAL_QD_DIR)/src/platform/platformDeps.o $(HAL_QD_DIR)/src/platform/gtSem.o \ + $(HAL_QD_DIR)/src/platform/gtDebug.o $(HAL_QD_DIR)/src/msapi/gtBrgFdb.o \ + $(HAL_QD_DIR)/src/msapi/gtBrgStp.o $(HAL_QD_DIR)/src/msapi/gtBrgVlan.o \ + $(HAL_QD_DIR)/src/msapi/gtEvents.o $(HAL_QD_DIR)/src/msapi/gtPortCtrl.o \ + $(HAL_QD_DIR)/src/msapi/gtPortStat.o $(HAL_QD_DIR)/src/msapi/gtPortStatus.o \ + $(HAL_QD_DIR)/src/msapi/gtQosMap.o $(HAL_QD_DIR)/src/msapi/gtPIRL.o \ + $(HAL_QD_DIR)/src/msapi/gtPhyCtrl.o $(HAL_QD_DIR)/src/msapi/gtPhyInt.o \ + $(HAL_QD_DIR)/src/msapi/gtSysConfig.o $(HAL_QD_DIR)/src/msapi/gtSysCtrl.o \ + $(HAL_QD_DIR)/src/msapi/gtVersion.o $(HAL_QD_DIR)/src/msapi/gtUtils.o \ + $(HAL_QD_DIR)/src/msapi/gtBrgVtu.o $(HAL_QD_DIR)/src/msapi/gtPortRmon.o \ + $(HAL_QD_DIR)/src/msapi/gtSysStatus.o $(HAL_QD_DIR)/src/msapi/gtPortRateCtrl.o\ + $(HAL_QD_DIR)/src/msapi/gtPortPav.o $(HAL_QD_DIR)/src/msapi/gtVct.o \ + $(HAL_QD_DIR)/src/msapi/gtPIRL2.o $(HAL_QD_DIR)/src/msapi/gtCCPVT.o \ + $(HAL_QD_DIR)/src/msapi/gtPCSCtrl.o $(HAL_QD_DIR)/src/msapi/gtBrgStu.o + +LSP_OBJS = core.o irq.o time.o leds.o sysmap.o export.o clock.o synology-gpio.o synology-platform.o + +obj-y := armada370.o +armada370-objs :=$(LSP_OBJS) $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) \ + $(ARMADA_FAM_OBJS) + +armada370-$(CONFIG_MV_INCLUDE_SDIO) += $(HAL_SDMMC_DIR)/mvSdmmcAddrDec.o +armada370-$(CONFIG_MV_INCLUDE_XOR) += $(HAL_XOR_DIR)/mvXor.o $(HAL_XOR_DIR)/mvXorAddrDec.o \ + $(HAL_IF_DIR)/mvSysXor.o +armada370-$(CONFIG_MV_INCLUDE_PEX) += $(HAL_PEX_DIR)/mvPex.o \ + $(HAL_IF_DIR)/mvSysPex.o $(HAL_PEX_DIR)/mvPexAddrDec.o +armada370-$(CONFIG_MV_INCLUDE_PCI) += $(HAL_PCI_DIR)/mvPci.o $(HAL_IF_DIR)/mvSysPci.o +armada370-$(CONFIG_MV_INCLUDE_USB) += $(HAL_USB_DIR)/mvUsb.o $(HAL_USB_DIR)/mvUsbAddrDec.o \ + $(HAL_IF_DIR)/mvSysUsb.o +armada370-y += $(HAL_ETHPHY_DIR)/mvEthPhy.o $(HAL_IF_DIR)/mvSysEthPhy.o + +ifneq ($(CONFIG_MV_ETH_NFP),m) + armada370-y += $(NFPOBJS) +endif + +# Legacy Giga driver +ifeq ($(CONFIG_MV_ETH_LEGACY),y) +armada370-$(CONFIG_MV_ETH_LEGACY) += $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_ETH_GBE_DIR)/mvEthDebug.o \ + $(HAL_ETH_GBE_DIR)/mvEthAddrDec.o $(HAL_IF_DIR)/mvSysEth.o +armada370-$(CONFIG_MV_ETH_NFP) += $(HAL_ETH_NFP_DIR)/mvNfp.o +armada370-$(CONFIG_MV_ETH_NFP_NAT) += $(HAL_ETH_NFP_DIR)/mvNfpNat.o +armada370-$(CONFIG_MV_ETH_NFP_FDB) += $(HAL_ETH_NFP_DIR)/mvNfpFdb.o +armada370-$(CONFIG_MV_ETH_NFP_PPP) += $(HAL_ETH_NFP_DIR)/mvNfpPpp.o +armada370-$(CONFIG_MV_ETH_NFP_SEC) += $(HAL_ETH_NFP_DIR)/mvNfpSec.o + +endif + +# NETA Giga driver +ifeq ($(CONFIG_MV_ETH_NETA),y) +armada370-$(CONFIG_MV_ETH_NETA) += $(HAL_ETH_GBE_DIR)/mvNeta.o $(HAL_ETH_GBE_DIR)/mvNetaDebug.o \ + $(HAL_ETH_GBE_DIR)/mvNetaAddrDec.o $(HAL_IF_DIR)/mvSysNeta.o +armada370-$(CONFIG_MV_ETH_PNC) += $(HAL_ETH_PNC_DIR)/mvTcam.o $(HAL_ETH_PNC_DIR)/mvPnc.o +armada370-$(CONFIG_MV_ETH_BM) += $(HAL_ETH_BM_DIR)/mvBm.o +armada370-$(CONFIG_MV_ETH_PMT) += $(HAL_ETH_PMT_DIR)/mvPmt.o +armada370-$(CONFIG_MV_ETH_HWF) += $(HAL_ETH_GBE_DIR)/mvHwf.o +endif + +armada370-$(CONFIG_MV_INCLUDE_CESA) += $(HAL_CESA_DIR)/mvCesa.o $(HAL_CESA_DIR)/mvCesaDebug.o \ + $(HAL_CESA_DIR)/mvCesaAddrDec.o \ + $(HAL_CESA_DIR)/mvMD5.o $(HAL_CESA_DIR)/mvSHA1.o \ + $(HAL_CESA_DIR)/mvSHA256.o \ + $(HAL_CESA_AES_DIR)/mvAesAlg.o $(HAL_CESA_AES_DIR)/mvAesApi.o\ + $(HAL_IF_DIR)/mvSysCesa.o +armada370-$(CONFIG_MV_INCLUDE_INTEG_SATA)+= $(HAL_IF_DIR)/mvSysSata.o $(HAL_SATA_DIR)/mvSataSoc.o \ + $(HAL_SATA_DIR)/mvSataAddrDec.o +armada370-$(CONFIG_MV_INCLUDE_SPI) += $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o \ + $(HAL_SFLASH_DIR)/mvSFlash.o $(HAL_IF_DIR)/mvSysSFlash.o \ + $(HAL_IF_DIR)/mvSysSpi.o +armada370-$(CONFIG_MV_INCLUDE_NFC) += $(HAL_NFC_DIR)/mvNfc.o +armada370-$(CONFIG_MV_INCLUDE_AUDIO) += $(HAL_AUDIO_DIR)/mvAudio.o $(HAL_IF_DIR)/mvSysAudio.o \ + $(HAL_AUDIO_DIR)/mvAudioAddrDec.o +armada370-$(CONFIG_MV_INCLUDE_TS) += $(HAL_TS_DIR)/mvTsu.o $(HAL_IF_DIR)/mvSysTs.o \ + $(HAL_TS_DIR)/mvTsuAddrDec.o +armada370-$(CONFIG_MV_CPU_PERF_CNTRS) += $(HAL_CPU_DIR)/mvCpuCntrs.o $(HAL_CPU_DIR)/pj4/mvPJ4Cntrs.o +armada370-$(CONFIG_MV_CPU_L2_PERF_CNTRS) += $(HAL_CPU_DIR)/mvCpuL2Cntrs.o + +obj-$(CONFIG_MV_INCLUDE_SWITCH) += $(QD_OBJS) + +# drivers part +# Legacy Giga driver +ifeq ($(CONFIG_MV_ETH_LEGACY),y) +obj-$(CONFIG_MV_ETH_NFP) += $(LSP_NFP_MGR_DIR)/mv_nfp_mgr.o +obj-$(CONFIG_MV_ETH_NFP_SEC) += $(LSP_NFP_MGR_DIR)/mv_nfp_sec.o +endif + +ifeq ($(CONFIG_MV_ETH_NETA),y) +obj-$(CONFIG_MV_ETH_PNC) += $(LSP_PNC_DIR)/pnc_sysfs.o +obj-$(CONFIG_MV_ETH_BM) += $(LSP_BM_DIR)/bm_sysfs.o $(LSP_BM_DIR)/mv_eth_bm.o +obj-$(CONFIG_MV_ETH_PMT) += $(LSP_PMT_DIR)/pmt_sysfs.o +obj-$(CONFIG_MV_ETH_HWF) += $(LSP_HWF_DIR)/hwf_sysfs.o +obj-$(CONFIG_MV_ETH_L2FW) += $(LSP_L2FW_DIR)/l2fw_sysfs.o $(LSP_L2FW_DIR)/mv_eth_l2fw.o +obj-$(CONFIG_MV_ETH_L2SEC) += $(LSP_L2FW_DIR)/mv_eth_l2sec.o +endif + +obj-$(CONFIG_MV_USE_XOR_ENGINE) += $(PLAT_DRIVERS)/mv_xor/ +obj-$(CONFIG_MV_CESA) += $(PLAT_DRIVERS)/mv_cesa/ +#obj-y += $(PLAT_DRIVERS)/mv_btns/ +obj-y += $(PLAT_DRIVERS)/mv_gpio/ +obj-$(CONFIG_MV_INCLUDE_SWITCH) += $(LSP_SWITCH_DIR)/ +obj-$(CONFIG_SENSORS_ARMADA) += hwmon.o +# The rest of the drivers are compiled through the driver dir directly. + + +# LSP part +armada370-$(CONFIG_MV_INCLUDE_USB) += usb.o +armada370-$(CONFIG_MV_INCLUDE_PCI) += pci.o +armada370-$(CONFIG_MV_INCLUDE_PEX) += pex.o +armada370-$(CONFIG_FEROCEON_PROC) += $(PLAT_DRIVERS)/mv_proc/proc.o +armada370-$(CONFIG_MV_DBG_TRACE) += dbg-trace.o +armada370-$(CONFIG_PROC_FS) += dump_cp15_regs.o + diff --git a/arch/arm/mach-armada370/Makefile.boot b/arch/arm/mach-armada370/Makefile.boot new file mode 100755 index 000000000..67039c3e0 --- /dev/null +++ b/arch/arm/mach-armada370/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvLib.c b/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvLib.c new file mode 100755 index 000000000..4f8a0f906 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvLib.c @@ -0,0 +1,2670 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "cntmr/mvCntmr.h" +#include "gpp/mvGpp.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPex.h" +#include "device/mvDevice.h" +#include "neta/gbe/mvEthRegs.h" +#include "neta/gbe/mvNeta.h" +#include "gpp/mvGppRegs.h" + +/* defines */ +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#define DB1(x) x +#else +#define DB(x) +#define DB1(x) +#endif + +#define CODE_IN_ROM MV_FALSE +#define CODE_IN_RAM MV_TRUE + +#define FILL_TWSI_SLAVE(slv, addr) \ +{ \ + slv.slaveAddr.address = addr; \ + slv.slaveAddr.type = MV_BOARD_MODULES_ADDR_TYPE; \ + slv.validOffset = MV_TRUE; \ + slv.offset = 0; \ + slv.moreThen256 = MV_FALSE; \ +} + +extern MV_BOARD_INFO *boardInfoTbl[]; +#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] + +/* Locals */ +static MV_DEV_CS_INFO *boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +MV_U32 tClkRate = -1; + +MV_U32 gBoardMppType2Index[] = {MV_BOARD_AUTO, MV_BOARD_TDM, MV_BOARD_I2S, MV_BOARD_GMII0, MV_BOARD_SDIO, + MV_BOARD_RGMII0, MV_BOARD_RGMII1}; + +/******************************************************************************* +* mvBoardEnvInit - Init board +* +* DESCRIPTION: +* In this function the board environment take care of device bank +* initialization. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardEnvInit(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_U32 norDev; + MV_U32 i, gppMask; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); + return; + } + +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#else +/* MPP setting only in uboot, so we don't double set again */ + norDev = boardGetDevCSNum(0, BOARD_DEV_NOR_FLASH); + if (norDev != 0xFFFFFFFF) { + /* Set NOR interface access parameters */ + MV_REG_WRITE(DEV_BANK_PARAM_REG(norDev), BOARD_INFO(boardId)->norFlashReadParams); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(norDev), BOARD_INFO(boardId)->norFlashWriteParams); + MV_REG_WRITE(DEV_BUS_SYNC_CTRL, 0x11); + } + + /* Device Bus or NAND Controller selection */ +#ifdef MV_INCLUDE_NOR + MV_REG_BIT_RESET(SOC_DEVICE_MUX_REG, BIT0); +#else + MV_REG_BIT_SET(SOC_DEVICE_MUX_REG, BIT0); +#endif + + MV_REG_WRITE(MV_RUNIT_PMU_REGS_OFFSET + 0x4, BOARD_INFO(boardId)->pmuPwrUpPolarity); + MV_REG_WRITE(MV_RUNIT_PMU_REGS_OFFSET + 0x14, BOARD_INFO(boardId)->pmuPwrUpDelay); + + /* Set GPP Out value */ + MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); + MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValMid); + MV_REG_WRITE(GPP_DATA_OUT_REG(2), BOARD_INFO(boardId)->gppOutValHigh); + + /* set GPP polarity */ + mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); + mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValMid); + mvGppPolaritySet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); + + /* Set GPP Out Enable */ + mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); + mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValMid); + mvGppTypeSet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); + + /* Set GPIO interrupts type & polarity as needed */ + for (i = 0; i < MV_GPP_MAX_GROUP; i++) { + gppMask = mvBoardGpioIntMaskGet(i); + mvGppTypeSet(i, gppMask , (MV_GPP_IN & gppMask)); + mvGppPolaritySet(i, gppMask , (MV_GPP_IN_INVERT & gppMask)); + } +#endif +} + +/******************************************************************************* +* mvBoardModelGet - Get Board model +* +* DESCRIPTION: +* This function returns 16bit describing board model. +* Board model is constructed of one byte major and minor numbers in the +* following manner: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardModelGet(MV_VOID) +{ + return (mvBoardIdGet() >> 16); +} + +/******************************************************************************* +* mbBoardRevlGet - Get Board revision +* +* DESCRIPTION: +* This function returns a 32bit describing the board revision. +* Board revision is constructed of 4bytes. 2bytes describes major number +* and the other 2bytes describes minor munber. +* For example for board revision 3.4 the function will return +* 0x00030004. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardRevGet(MV_VOID) +{ + return (mvBoardIdGet() & 0xFFFF); +} + +/******************************************************************************* +* mvBoardNameGet - Get Board name +* +* DESCRIPTION: +* This function returns a string describing the board model and revision. +* String is extracted from board I2C EEPROM. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvBoardNameGet(char *pNameBuff) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsSPrintf(pNameBuff, "Board unknown.\n"); + return MV_ERROR; + } + + mvOsSPrintf(pNameBuff, "%s", BOARD_INFO(boardId)->boardName); + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) +{ + MV_U32 serdesMode = mvBoardSerdesModeGet(); + + if (ethPortNum == 0) { + if (serdesMode & (SRDS_MOD_SGMII0_LANE1 | SRDS_MOD_SGMII0_LANE2)) + return MV_TRUE; + } + + if (ethPortNum == 1) { + if (serdesMode & (SRDS_MOD_SGMII1_LANE0 | SRDS_MOD_SGMII1_LANE3)) + return MV_TRUE; + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsPortInGmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in GMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in GMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInGmii(MV_U32 ethPortNum) +{ + if (mvBoardIsGMIIConnected() && (ethPortNum ==0)) + return MV_TRUE; + else + return MV_FALSE; +} + + + +/******************************************************************************* +* mvBoardIsPortInRgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in RGMII or MV_FALSE +* for all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in RGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInRgmii(MV_U32 ethPortNum) +{ + + if (ethPortNum == 0) { + if (mvBoardMppModulesCfgGet(1) & MV_BOARD_RGMII0) + return MV_TRUE; + } + + if (ethPortNum == 1) { + if (mvBoardMppModulesCfgGet(1) & MV_BOARD_RGMII1) + return MV_TRUE; + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardSwitchPortGet - Get the mapping between the board connector and the +* Ethernet Switch port +* +* DESCRIPTION: +* This routine returns the matching Switch port. +* +* INPUT: +* boardPortNum - logical number of the connector on the board +* +* OUTPUT: +* None. +* +* RETURN: +* the matching Switch port, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchPortGet(MV_U32 switchIdx, MV_U32 boardPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); + return -1; + } + if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) { + mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); + return -1; + } + if ((BOARD_INFO(boardId)->switchInfoNum == 0) || (switchIdx >= BOARD_INFO(boardId)->switchInfoNum)) + return -1; + + return BOARD_INFO(boardId)->pSwitchInfo[switchIdx].switchPort[boardPortNum]; +} + +/******************************************************************************* +* mvBoardSwitchConnectedPortGet - +* +* DESCRIPTION: +* This routine returns the switch port connected to the ethPort +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_32 mvBoardSwitchConnectedPortGet(MV_U32 ethPort) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardSwitchConnectedPortGet: Board unknown.\n"); + return -1; + } + if (BOARD_INFO(boardId)->switchInfoNum == 0) + return -1; + + return BOARD_INFO(boardId)->pSwitchInfo[0].connectedPort[ethPort]; +} + +/******************************************************************************* +* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port +* +* DESCRIPTION: +* This routine returns the Switch CPU port. +* +* INPUT: +* switchIdx - index of the switch. Only 0 is supported. +* +* OUTPUT: +* None. +* +* RETURN: +* the Switch CPU port, -1 if the switch is not connected. +* +*******************************************************************************/ +MV_32 mvBoardSwitchCpuPortGet(MV_U32 switchIdx) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); + return -1; + } + if ((BOARD_INFO(boardId)->switchInfoNum == 0) || (switchIdx >= BOARD_INFO(boardId)->switchInfoNum)) + return -1; + + return BOARD_INFO(boardId)->pSwitchInfo[switchIdx].cpuPort; +} + +/******************************************************************************* +* mvBoardSwitchIrqGet - Get the IRQ number for the link status indication +* +* DESCRIPTION: +* This routine returns the IRQ number for the link status indication. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* the number of the IRQ for the link status indication, -1 if the port +* number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchIrqGet(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); + return -1; + } + if (BOARD_INFO(boardId)->switchInfoNum == 0) + return -1; + + return BOARD_INFO(boardId)->pSwitchInfo[0].switchIrq; +} + +/******************************************************************************* +* mvBoardIsQsgmiiModuleConnected +* +* DESCRIPTION: +* This routine returns whether the QSGMII module is connected or not. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if QSGMII module is connected, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_BOOL mvBoardIsQsgmiiModuleConnected(MV_VOID) +{ + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardGePhySwitchPortGet +* +* DESCRIPTION: +* This routine returns whether the internal GE PHY is connected to +* Switch Port 0, Switch port 5 or not connected to any Switch port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 0 if the internal GE PHY is connected to Switch Port 0, +* 5 if the internal GE PHY is connected to Switch Port 5, +* -1 otherwise. +* +*******************************************************************************/ +MV_32 mvBoardGePhySwitchPortGet(MV_VOID) +{ + return -1; +} + +/******************************************************************************* +* mvBoardRgmiiASwitchPortGet +* +* DESCRIPTION: +* This routine returns whether RGMII-A is connected to +* Switch Port 5, Switch port 6 or not connected to any Switch port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 5 if the internal GE PHY is connected to Switch Port 5, +* 6 if the internal GE PHY is connected to Switch Port 6, +* -1 otherwise. +* +*******************************************************************************/ +MV_32 mvBoardRgmiiASwitchPortGet(MV_VOID) +{ + return -1; +} + +/******************************************************************************* +* mvBoardSwitchPortMap +* +* DESCRIPTION: +* Map front panel connector number to switch port number. +* +* INPUT: +* switchIdx - The switch index. +* switchPortNum - The switch port number to get the mapping for. +* +* OUTPUT: +* None. +* +* RETURN: +* The switch port mapping. +* OR -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchPortMap(MV_U32 switchIdx, MV_U32 switchPortNum) +{ + int i; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardSwitchPortMap: Board unknown.\n"); + return -1; + } + if ((BOARD_INFO(boardId)->switchInfoNum == 0) || (switchIdx >= BOARD_INFO(boardId)->switchInfoNum)) + return -1; + + for (i = 0; i < BOARD_ETH_SWITCH_PORT_NUM; i++) { + if (BOARD_INFO(boardId)->pSwitchInfo[switchIdx].switchPort[i] == switchPortNum) + return i; + } + return -1; +} + +/******************************************************************************* +* mvBoardPhyAddrGet - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; +} +/******************************************************************************* +* mvBoardQuadPhyAddr0Get - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardQuadPhyAddr0Get(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardQuadPhyAddr0Get: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr0; +} + +/******************************************************************************* +* mvBoardPhyLinkCryptPortAddrGet - Get the phy gbe address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyLinkCryptPortAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardPhyLinkCryptPortAddrGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].LinkCryptPortAddr; +} + + +/******************************************************************************* +* mvBoardMacSpeedGet - Get the Mac speed +* +* DESCRIPTION: +* This routine returns the Mac speed if pre define of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); + return MV_ERROR; + } + + if (ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) { + mvOsPrintf("mvBoardMacSpeedGet: illegal port number\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; +} + +/******************************************************************************* +* mvBoardSpecInitGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, +* otherwise return MV_FALSE. +* +* +*******************************************************************************/ +MV_BOOL mvBoardSpecInitGet(MV_U32 *regOff, MV_U32 *data) +{ + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTclkGet - Get the board Tclk (Controller clock) +* +* DESCRIPTION: +* This routine extract the controller core clock. +* This function uses the controller counters to make identification. +* Note: In order to avoid interference, make sure task context switch +* and interrupts will not occure during this function operation +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardTclkGet(MV_VOID) +{ +#ifdef TCLK_AUTO_DETECT + if ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_TCLK_MASK) != 0) + return MV_BOARD_TCLK_200MHZ; + else + return MV_BOARD_TCLK_166MHZ; +#else + return MV_BOARD_TCLK_200MHZ; +#endif +} + +/******************************************************************************* +* mvBoardSysClkGet - Get the board SysClk (CPU bus clock , i.e. DDR clock) +* +* DESCRIPTION: +* This routine extract the CPU bus clock. +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardSysClkGet(MV_VOID) +{ +#ifdef SYSCLK_AUTO_DETECT + MV_U32 idx; + MV_U32 cpuFreqMhz, ddrFreqMhz; + MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL; + + idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET)); + + if (clockRatioTbl[idx].vco2cpu != 0) { /* valid ratio ? */ + cpuFreqMhz = mvCpuPclkGet() / 1000000; /* obtain CPU freq */ + cpuFreqMhz *= clockRatioTbl[idx].vco2cpu; /* compute VCO freq */ + ddrFreqMhz = cpuFreqMhz / clockRatioTbl[idx].vco2ddr; + /* round up to integer MHz */ + if (((cpuFreqMhz % clockRatioTbl[idx].vco2ddr) * 10 / clockRatioTbl[idx].vco2ddr) >= 5) + ddrFreqMhz++; + + return ddrFreqMhz * 1000000; + } else + return 0; +#else + return MV_BOARD_DEFAULT_SYSCLK; +#endif +} + +/******************************************************************************* +* mvBoardDebugLedNumGet - Get number of debug Leds +* +* DESCRIPTION: +* INPUT: +* boardId +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) +{ + return BOARD_INFO(boardId)->activeLedsNumber; +} + +/******************************************************************************* +* mvBoardDebugLeg - Set the board debug Leds +* +* DESCRIPTION: turn on/off status leds. +* Note: assume MPP leds are part of group 0 only. +* +* INPUT: +* hexNum - Number to be displayed in hex by Leds. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebugLed(MV_U32 hexNum) +{ + MV_U32 val[MV_GPP_MAX_GROUP] = {0}; + MV_U32 mask[MV_GPP_MAX_GROUP] = {0}; + MV_U32 digitMask; + MV_U32 i, pinNum, gppGroup; + MV_U32 boardId = mvBoardIdGet(); + + if (BOARD_INFO(boardId)->pLedGppPin == NULL) + return; + + hexNum &= (1 << BOARD_INFO(boardId)->activeLedsNumber) - 1; + + for (i = 0, digitMask = 1; i < BOARD_INFO(boardId)->activeLedsNumber; i++, digitMask <<= 1) { + pinNum = BOARD_INFO(boardId)->pLedGppPin[i]; + gppGroup = pinNum / 32; + if (hexNum & digitMask) + val[gppGroup] |= (1 << (pinNum - gppGroup * 32)); + mask[gppGroup] |= (1 << (pinNum - gppGroup * 32)); + } + + for (gppGroup = 0; gppGroup < MV_GPP_MAX_GROUP; gppGroup++) { + /* If at least one bit is set in the mask, update the whole GPP group */ + if (mask[gppGroup]) + mvGppValueSet(gppGroup, mask[gppGroup], BOARD_INFO(boardId)->ledsPolarity == 0 ? + val[gppGroup] : ~val[gppGroup]); + } +} + +/******************************************************************************* +* mvBoarGpioPinGet - mvBoarGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* gppClass - MV_BOARD_GPP_CLASS enum. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS gppClass, MV_U32 index) +{ + MV_U32 boardId, i; + MV_U32 indexFound = 0; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) { + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == gppClass) { + if (indexFound == index) + return (MV_U32) BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + else + indexFound++; + } + } + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardReset - mvBoardReset +* +* DESCRIPTION: +* Reset the board +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvBoardReset(MV_VOID) +{ + MV_32 resetPin; + + /* Get gpp reset pin if define */ + resetPin = mvBoardResetGpioPinGet(); + if (resetPin != MV_ERROR) { + MV_REG_BIT_RESET(GPP_DATA_OUT_REG(0), (1 << resetPin)); + MV_REG_BIT_RESET(GPP_DATA_OUT_EN_REG(0), (1 << resetPin)); + } else { + /* No gpp reset pin was found, try to reset ussing + ** system reset out */ + MV_REG_BIT_SET(CPU_RSTOUTN_MASK_REG, BIT0); + MV_REG_BIT_SET(CPU_SYS_SOFT_RST_REG, BIT0); + } +} + +/******************************************************************************* +* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardResetGpioPinGet(MV_VOID) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); +} + +/******************************************************************************* +* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet +* +* DESCRIPTION: +* used for hotswap detection +* INPUT: +* type - Type of SDIO GPP to get. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardSDIOGpioPinGet(MV_BOARD_GPP_CLASS type) +{ + if ((type != BOARD_GPP_SDIO_POWER) && (type != BOARD_GPP_SDIO_DETECT) && (type != BOARD_GPP_SDIO_WP)) + return MV_FAIL; + + return mvBoarGpioPinNumGet(type, 0); +} + +/******************************************************************************* +* mvBoardUSBVbusGpioPinGet - return Vbus input GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); +} + +/******************************************************************************* +* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); +} + +/******************************************************************************* +* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins +* +* DESCRIPTION: +* This function returns a 32-bit mask of GPP pins that connected to +* interrupt generating sources on board. +* For example if UART channel A is hardwired to GPP pin 8 and +* UART channel B is hardwired to GPP pin 4 the fuinction will return +* the value 0x000000110 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* See description. The function return -1 if board is not identified. +* +*******************************************************************************/ +MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + } + + switch (gppGrp) { + case (0): + return BOARD_INFO(boardId)->intsGppMaskLow; + break; + case (1): + return BOARD_INFO(boardId)->intsGppMaskMid; + break; + case (2): + return BOARD_INFO(boardId)->intsGppMaskHigh; + break; + default: + return MV_ERROR; + } +} + +/******************************************************************************* +* mvBoardMppGet - Get board dependent MPP register value +* +* DESCRIPTION: +* MPP settings are derived from board design. +* MPP group consist of 8 MPPs. An MPP group represents MPP +* control register. +* This function retrieves board dependend MPP register value. +* +* INPUT: +* mppGroupNum - MPP group number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit value describing MPP control register value. +* +*******************************************************************************/ +MV_32 mvBoardMppGet(MV_U32 mppGroupNum) +{ + MV_U32 boardId; + MV_U32 mppMod; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + } + + if (mppGroupNum >= BOARD_INFO(boardId)->numBoardMppConfigValue) + mppMod = 0; /* default */ + + return BOARD_INFO(boardId)->pBoardMppConfigValue[mppMod].mppGroup[mppGroupNum]; +} + +/******************************************************************************* +* mvBoardGppConfigGet +* +* DESCRIPTION: +* Get board configuration according to the input configuration GPP's. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The value of the board configuration GPP's. +* +*******************************************************************************/ +MV_U32 mvBoardGppConfigGet(void) +{ + MV_U32 boardId, i; + MV_U32 result = 0; + MV_U32 gpp; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGppConfigGet: Board unknown.\n"); + return 0; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) { + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == BOARD_GPP_CONF) { + gpp = BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + result <<= 1; + result |= (mvGppValueGet(gpp >> 5, 1 << (gpp & 0x1F)) >> (gpp & 0x1F)); + } + } + return result; + +} + +/******************************************************************************* +* mvBoardTdmSpiModeGet - return SLIC/DAA connection +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_32 mvBoardTdmSpiModeGet(MV_VOID) +{ + return DUAL_CHIP_SELECT_MODE; +} + +/******************************************************************************* +* mvBoardTdmDevicesCountGet +* +* DESCRIPTION: +* Return the number of TDM devices on board. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Number of devices. +* +*******************************************************************************/ +MV_U8 mvBoardTdmDevicesCountGet(void) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_16 index; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmDevicesCountGet: Board unknown.\n"); + return 0; + } + + index = BOARD_INFO(boardId)->boardTdmInfoIndex; + if (index == (MV_8)-1) + return 0; + + return BOARD_INFO(boardId)->numBoardTdmInfo[(MV_U8)index]; +} + +/******************************************************************************* +* mvBoardTdmSpiCsGet +* +* DESCRIPTION: +* Return the SPI Chip-select number for a given device. +* +* INPUT: +* devId - The Slic device ID to get the SPI CS for. +* +* OUTPUT: +* None. +* +* RETURN: +* The SPI CS if found, -1 otherwise. +* +*******************************************************************************/ +MV_U8 mvBoardTdmSpiCsGet(MV_U8 devId) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_16 index; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmDevicesCountGet: Board unknown.\n"); + return -1; + } + + index = BOARD_INFO(boardId)->boardTdmInfoIndex; + if (index == (MV_8)-1) + return 0; + + if (devId >= BOARD_INFO(boardId)->numBoardTdmInfo[(MV_U8)index]) + return -1; + + return BOARD_INFO(boardId)->pBoardTdmInt2CsInfo[(MV_U8)index][devId].spiCs; +} + +/******************************************************************************* +* mvBoardTdmSpiIdGet +* +* DESCRIPTION: +* Return SPI port ID per board. +* +* INPUT: +* None +* +* OUTPUT: +* None. +* +* RETURN: +* SPI port ID. +* +*******************************************************************************/ +MV_U8 mvBoardTdmSpiIdGet(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmSpiIdGet: Board unknown.\n"); + return -1; + } + + return BOARD_INFO(boardId)->pBoardTdmSpiInfo[0].spiId; +} + +/******************************************************************************* +* mvBoardSerdesModeGet +* +* DESCRIPTION: +* Return the Serdes lanes configuration. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* A bitmap of the serdes modes. +* +*******************************************************************************/ +MV_U32 mvBoardSerdesModeGet(void) +{ + MV_U32 serdesInfo = MV_REG_READ(SERDES_LINE_MUX_REG_0_3); + MV_U32 serdesMode = 0; + + switch (serdesInfo & 0x0f){ + case 1: + serdesMode |= SRDS_MOD_PCIE0_LANE0; + break; + case 2: + serdesMode |= SRDS_MOD_SATA0_LANE0; + break; + case 3: + serdesMode |= SRDS_MOD_SGMII1_LANE0; + break; + case 0: + default: + break; + } + + switch (serdesInfo & 0x0f0){ + case 0x10: + serdesMode |= SRDS_MOD_PCIE1_LANE1; + break; + case 0x20: + serdesMode |= SRDS_MOD_SGMII0_LANE1; + break; + default: + break; + } + + switch (serdesInfo & 0x0f00){ + case 0x100: + serdesMode |= SRDS_MOD_SATA0_LANE2; + break; + case 0x200: + serdesMode |= SRDS_MOD_SGMII0_LANE2; + break; + default: + break; + } + + switch (serdesInfo & 0xf000){ + case 0x1000: + serdesMode |= SRDS_MOD_SATA1_LANE3; + break; + case 0x2000: + serdesMode |= SRDS_MOD_SGMII1_LANE3; + break; + default: + break; + } + + + return serdesMode; +} +/******************************************************************************* +* mvBoardModuleTypePrint +* +* DESCRIPTION: +* Print on-board detected modules. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardMppModuleTypePrint(MV_VOID) +{ + MV_U32 mppGrp1 = mvBoardMppModulesCfgGet(1); + MV_U32 mppGrp2 = mvBoardMppModulesCfgGet(2); + + mvOsOutput("Modules/Interfaces Detected:\n"); + + /* TDM */ + if (((mppGrp1 & MV_BOARD_TDM) || (mppGrp2 & MV_BOARD_TDM)) && mvCtrlTdmSupport()) + mvOsOutput(" TDM Module\n"); + + /* I2S */ + if ((mppGrp1 & MV_BOARD_I2S) || (mppGrp2 & MV_BOARD_I2S)) + mvOsOutput(" I2S Module\n"); + + /* GMII0 */ + if (mppGrp1 & MV_BOARD_GMII0) + mvOsOutput(" GMII0 Module\n"); + + /* SDIO */ + if (mppGrp1 & MV_BOARD_SDIO) + mvOsOutput(" SDIO\n"); + + /* RGMII0 */ + if (mppGrp1 & MV_BOARD_RGMII0) + mvOsOutput(" RGMII0 Phy\n"); + + /* RGMII1 */ + if (mppGrp1 & MV_BOARD_RGMII1) { + if (mvBoardIsSwitchConnected()) + mvOsOutput(" RGMII1 Switch module\n"); + else + mvOsOutput(" RGMII1 Phy\n"); + } + + return; +} + +MV_VOID mvBoardOtherModuleTypePrint(MV_VOID) +{ + MV_U32 srdsCfg = mvBoardSerdesModeGet(); + + /* PCI-E */ + if (srdsCfg & SRDS_MOD_PCIE0_LANE0) + mvOsOutput(" PEX0 (Lane 0)\n"); + if (srdsCfg & SRDS_MOD_PCIE1_LANE1) + mvOsOutput(" PEX1 (Lane 1)\n"); + + /* SATA */ + if (srdsCfg & SRDS_MOD_SATA0_LANE0) + mvOsOutput(" SATA0 (Lane 0)\n"); + if (srdsCfg & SRDS_MOD_SATA0_LANE2) + mvOsOutput(" SATA0 (Lane 2)\n"); + if (srdsCfg & SRDS_MOD_SATA1_LANE3 && (mvCtrlSataMaxPortGet() == 2)) + mvOsOutput(" SATA1 (Lane 3)\n"); + + /* SGMII */ + if (srdsCfg & SRDS_MOD_SGMII0_LANE1) + mvOsOutput(" SGMII0 Phy module (Lane 1)\n"); + if (srdsCfg & SRDS_MOD_SGMII0_LANE2) + mvOsOutput(" SGMII0 Phy module (Lane 2)\n"); + if (srdsCfg & SRDS_MOD_SGMII1_LANE0) + mvOsOutput(" SGMII1 Phy module (Lane 0)\n"); + if (srdsCfg & SRDS_MOD_SGMII1_LANE3) + mvOsOutput(" SGMII1 Phy module (Lane 3)\n"); + + return; +} + +/******************************************************************************* +* mvBoardIsGbEPortConnected +* +* DESCRIPTION: +* Checks if a given GbE port is actually connected to the GE-PHY, internal Switch or any RGMII module. +* +* INPUT: +* port - GbE port number (0 or 1). +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if port is connected, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_BOOL mvBoardIsGbEPortConnected(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_U32 mppMask; + MV_U32 srdsMask = mvBoardSerdesModeGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardIsGbEPortConnected: Board unknown.\n"); + return -1; + } + + if (ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) + return MV_FALSE; + + mppMask = BOARD_INFO(boardId)->pBoardModTypeValue->boardMppGrp1Mod; + + if ((ethPortNum == 0) && (((mppMask & (MV_BOARD_RGMII0 | MV_BOARD_GMII0))) || + (srdsMask & (SRDS_MOD_SGMII0_LANE1 | SRDS_MOD_SGMII0_LANE2)))) + return MV_TRUE; + + if ((ethPortNum == 1) && ((mppMask & MV_BOARD_RGMII1) || + (srdsMask & (SRDS_MOD_SGMII1_LANE0 | SRDS_MOD_SGMII1_LANE3)))) + return MV_TRUE; + + return MV_FALSE; +} + + +/* Board devices API managments */ + +/******************************************************************************* +* mvBoardGetDeviceNumber - Get number of device of some type on the board +* +* DESCRIPTION: +* +* INPUT: +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* number of those devices else the function returns 0 +* +* +*******************************************************************************/ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, devNum; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); + return 0xFFFFFFFF; + } + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) { + if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) + foundIndex++; + } + + return foundIndex; +} + +/******************************************************************************* +* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Base address else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Bus width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->busWidth; + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceWidth - Get dev width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* window size else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* boardGetDevEntry - returns the entry pointer of a device on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +*******************************************************************************/ +static MV_DEV_CS_INFO *boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, devIndex; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("boardGetDevEntry: Board unknown.\n"); + return NULL; + } + + for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) { + if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) { + if (foundIndex == devNum) + return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); + foundIndex++; + } + } + + /* device not found */ + return NULL; +} + +/******************************************************************************* +* boardGetDevCSNum +* +* DESCRIPTION: +* Return the device's chip-select number. +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +*******************************************************************************/ +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->deviceCS; + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardTwsiAddrTypeGet - +* +* DESCRIPTION: +* Return the TWSI address type for a given twsi device class. +* +* INPUT: +* twsiClass - The TWSI device to return the address type for. +* index - The TWSI device index (Pass 0 in case of a single +* device) +* +* OUTPUT: +* None. +* +* RETURN: +* The TWSI address type. +* +*******************************************************************************/ +MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId = mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) { + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == twsiClass) { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + else + indexFound++; + } + } + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardTwsiAddrGet - +* +* DESCRIPTION: +* Return the TWSI address for a given twsi device class. +* +* INPUT: +* twsiClass - The TWSI device to return the address type for. +* index - The TWSI device index (Pass 0 in case of a single +* device) +* +* OUTPUT: +* None. +* +* RETURN: +* The TWSI address. +* +*******************************************************************************/ +MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId = mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) { + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == twsiClass) { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + else + indexFound++; + } + } + return (0xFF); +} + +/******************************************************************************* +* mvBoardNandWidthGet - +* +* DESCRIPTION: Get the width of the first NAND device in bytes +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: 1, 2, 4 or MV_ERROR +* +* +*******************************************************************************/ +MV_32 mvBoardNandWidthGet(void) +{ + MV_U32 devNum; + MV_U32 devWidth; + MV_U32 boardId = mvBoardIdGet(); + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) { + devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); + if (devWidth != MV_ERROR) + return (devWidth / 8); + } + + /* NAND wasn't found */ + return MV_ERROR; +} + +MV_U32 gBoardId = -1; +/******************************************************************************* +* mvBoardIdSet - Set Board model +* +* DESCRIPTION: +* This function sets the board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* void +* +*******************************************************************************/ +MV_VOID mvBoardIdSet(MV_VOID) +{ + if (gBoardId == -1) { +#if defined(DB_88F6710) + gBoardId = DB_88F6710_BP_ID; +#elif defined(DB_88F6710_PCAC) + gBoardId = DB_88F6710_PCAC_ID; +#elif defined(RD_88F6710) + gBoardId = RD_88F6710_ID; +#else + mvOsPrintf("mvBoardIdSet: Board ID must be defined!\n"); + while (1) { + continue; + } +#endif + } +} +/******************************************************************************* +* mvBoardIdGet - Get Board model +* +* DESCRIPTION: +* This function returns board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board ID number, '-1' if board is undefined. +* +*******************************************************************************/ +MV_U32 mvBoardIdGet(MV_VOID) +{ + if (gBoardId == -1) { +#if defined(DB_88F6710) + gBoardId = DB_88F6710_BP_ID; +#elif defined(DB_88F6710_PCAC) + gBoardId = DB_88F6710_PCAC_ID; +#elif defined(RD_88F6710) + gBoardId = RD_88F6710_ID; +#else + mvOsWarning(); + return INVALID_BAORD_ID; +#endif + } + + + return gBoardId; +} + +/******************************************************************************* +* mvBoardTwsiSatRGet - +* +* DESCRIPTION: +* +* INPUT: +* device num - one of three devices +* reg num - 0 or 1 +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_U8 mvBoardTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U8 data; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: Read S@R device read\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_DEV_TWSI_SATR, devNum); + + twsiSlave.validOffset = MV_TRUE; + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + + if (MV_OK != mvTwsiRead(0, &twsiSlave, &data, 1)) { + DB(mvOsPrintf("Board: Read S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Read S@R succeded\n")); + + return data; +} + +/******************************************************************************* +* mvBoardTwsiSatRSet - +* +* DESCRIPTION: +* +* INPUT: +* devNum - one of three devices +* regNum - 0 or 1 +* regVal - value +* +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.validOffset = MV_TRUE; + DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", + twsiSlave.slaveAddr.address, twsiSlave.slaveAddr.type, regVal)); + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + if (MV_OK != mvTwsiWrite(0, &twsiSlave, ®Val, 1)) { + DB1(mvOsPrintf("Board: Write S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Write S@R succeded\n")); + + return MV_OK; +} + +/******************************************************************************* +* SatR Configuration functions +*******************************************************************************/ +/* Swap input data bits. */ +static MV_U8 mvBoardSatrSwapBits(MV_U8 val, MV_U8 width) +{ + MV_U8 i; + MV_U8 res = 0; + + for (i = 0; i < width; i++) { + if ((1 << i) & val) + res |= (1 << (width - i - 1)); + } + return res; +} + +MV_U8 mvBoardFabFreqGet(MV_VOID) +{ + MV_U8 sar0, sar1, res; + + sar0 = mvBoardTwsiSatRGet(0, 0); + sar1 = mvBoardTwsiSatRGet(1, 0); + + if (((MV_8)MV_ERROR == (MV_8)sar0) || ((MV_8)MV_ERROR == (MV_8)sar1)) + return MV_ERROR; + + res = ((sar0 & 0x10) | (mvBoardSatrSwapBits(sar1, 4) & 0xF)); + return res; +} + +/*******************************************************************************/ +MV_STATUS mvBoardFabFreqSet(MV_U8 freqVal) +{ + MV_U8 sar0, sar1; + + sar0 = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar0) + return MV_ERROR; + + sar1 = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar1) + return MV_ERROR; + + sar0 &= ~0x10; + sar0 |= (freqVal & 0x10); + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar0)) { + DB1(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + sar1 &= ~0xF; + sar1 |= mvBoardSatrSwapBits(freqVal, 4); + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar1)) { + DB1(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write FreqOpt S@R succeeded\n")); + return MV_OK; +} + + +/*******************************************************************************/ +MV_U8 mvBoardCpuFreqGet(MV_VOID) +{ + MV_U8 sar; + MV_U8 res; + + sar = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + res = sar & 0xF; + res = mvBoardSatrSwapBits(res, 4); + return res; +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + freqVal = mvBoardSatrSwapBits(freqVal, 4); + sar &= ~0xF; + sar |= (freqVal & 0xF); + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) { + DB1(mvOsPrintf("Board: Write CpuFreq S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write CpuFreq S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardBootDevGet(MV_VOID) +{ + MV_U8 sar; + MV_U8 result; + + sar = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + result = ((sar & 0x10) << 1); + + sar = mvBoardTwsiSatRGet(2, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + result |= mvBoardSatrSwapBits(sar, 5); + + return result; +} + +/*******************************************************************************/ +MV_STATUS mvBoardBootDevSet(MV_U8 val) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + sar &= ~(0x10); + sar |= ((val & 0x20) >> 1); + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB1(mvOsPrintf("Board: Write BootDev S@R fail\n")); + return MV_ERROR; + } + + if (MV_OK != mvBoardTwsiSatRSet(2, 0, mvBoardSatrSwapBits(val, 5))) { + DB1(mvOsPrintf("Board: Write BootDev S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write BootDev S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_STATUS mvBoardPexCapabilitySet(MV_U16 conf) +{ + if (MV_OK != mvBoardTwsiSatRSet(1, 1, conf)) { + DB(mvOsPrintf("Board: Write confID S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write confID S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U16 mvBoardPexCapabilityGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(1, 1); + return (sar & 0xFF); +} + + +/******************************************************************************* +* End of SatR Configuration functions +*******************************************************************************/ + +/******************************************************************************* +* mvBoardMppModulesScan +* +* DESCRIPTION: +* Scan for modules connected through MPP lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardMppModulesScan(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave, twsiSlaveGMII; + MV_U32 boardId = mvBoardIdGet(); + MV_BOOL scanEn = mvBoardIsModScanEnabled(); + MV_BOARD_MODULE_TYPE_INFO *modInfo; + MV_U8 swCfg; + + /* Perform scan only for DB board */ + if (scanEn == MV_FALSE) + return MV_OK; + + modInfo = BOARD_INFO(boardId)->pBoardModTypeValue; + + modInfo->boardMppGrp1Mod = 0; /* MPP Giga Site */ + modInfo->boardMppGrp2Mod = 0; /* MPP Device Site */ + + /* Giga Site Modules: */ + FILL_TWSI_SLAVE(twsiSlave, MV_BOARD_GIGA_CON_ADDR); + FILL_TWSI_SLAVE(twsiSlaveGMII, MV_BOARD_GIGA_CON_GMII_ADDR); + + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + switch (regVal & MV_BOARD_MODULE_ID_MASK) { + /* Switch module: DB-SGMII_Switch_1512 */ + case (MV_BOARD_SWITCH_MODULE_ID): + modInfo->boardMppGrp1Mod |= MV_BOARD_RGMII0; + modInfo->boardMppGrp1Mod |= MV_BOARD_RGMII1; + break; + /* TDM GMII module: DB-KW40_GMII_TDM_Adapter - TDM Configuration */ + case (MV_BOARD_TDM_GMII_MODULE_TDM_ID): + modInfo->boardMppGrp1Mod |= MV_BOARD_TDM; + break; + /* I2S SPDIF module: DB-KW40-I2S/SPDIF */ + case (MV_BOARD_I2S_SPDIF_MODULE_ID): + modInfo->boardMppGrp1Mod |= MV_BOARD_I2S; + break; + default: + break; + } + + } else if (mvTwsiRead(0, &twsiSlaveGMII, ®Val, 1) == MV_OK) { + if ((regVal & MV_BOARD_MODULE_ID_MASK) == MV_BOARD_TDM_GMII_MODULE_GMII_ID) + modInfo->boardMppGrp1Mod |= MV_BOARD_GMII0; + + } else { /* No module detected */ + /* Check if SDIO or RGMII0 */ + FILL_TWSI_SLAVE(twsiSlave, MV_BOARD_EEPROM_MODULE_ADDR); + mvTwsiRead(0, &twsiSlave, &swCfg, 1); + if (MV_BOARD_CFG_SDIO_MODE(swCfg) == 1) + modInfo->boardMppGrp1Mod |= MV_BOARD_SDIO; + else + modInfo->boardMppGrp1Mod |= MV_BOARD_RGMII0; + /* Set RGMII1 */ + modInfo->boardMppGrp1Mod |= MV_BOARD_RGMII1; + } + + /* Device Site Modules: */ + FILL_TWSI_SLAVE(twsiSlave, MV_BOARD_DEVICE_CON_ADDR); + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + switch (regVal & MV_BOARD_MODULE_ID_MASK) { + /* TDM module: DB-78x60_4xFXS-VX880 */ + case (MV_BOARD_TDM_GMII_MODULE_TDM_ID): + modInfo->boardMppGrp2Mod |= MV_BOARD_TDM; + break; + /* I2S SPDIF module: DB-KW40-I2S/SPDIF */ + case (MV_BOARD_I2S_SPDIF_MODULE_ID): + modInfo->boardMppGrp2Mod |= MV_BOARD_I2S; + break; + default: + break; + } + } else { /* No module detected */ + + } + + /* Check if SGMII module. connected - disable RGMII/GMII (SMI is directed to serdeses) */ + FILL_TWSI_SLAVE(twsiSlave, MV_BOARD_SERDES_CON_ADDR); + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + modInfo->boardMppGrp1Mod &= ~MV_BOARD_RGMII0; + modInfo->boardMppGrp1Mod &= ~MV_BOARD_RGMII1; + modInfo->boardMppGrp1Mod &= ~MV_BOARD_GMII0; + } + + return MV_OK; +} + + +/******************************************************************************* +* mvBoardMppTypeIndexGet +* +* DESCRIPTION: +* Get MPP type index of a given MPP type. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +static MV_U8 mvBoardMppTypeIndexGet(MV_BOARD_MPP_TYPE_CLASS type) +{ + MV_U8 i = 0; + + while (gBoardMppType2Index[i] != 0xFFFFFFFF) { + if (gBoardMppType2Index[i] == type) + return i; + i++; + } + + return 0x0; +} + +/******************************************************************************* +* mvBoardUpdateMppAfterScan +* +* DESCRIPTION: +* Update board MPPs list after modules scan. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardUpdateMppAfterScan(void) +{ + MV_BOOL scanEn = mvBoardIsModScanEnabled(); + MV_U32 boardId = mvBoardIdGet(); + MV_U32 *mppList = BOARD_INFO(boardId)->pBoardMppConfigValue->mppGroup; + MV_U32 mppGroup1[][4][2] = MPP_GROUP_1_TYPE; + MV_U32 mppGroup2[][4][2] = MPP_GROUP_2_TYPE; + MV_BOARD_MODULE_TYPE_INFO *modInfo; + MV_U32 mpp, mppIdx; + MV_U32 bootVal, mask, width; + MV_U8 index, i; + + modInfo = BOARD_INFO(boardId)->pBoardModTypeValue; + + /* Perform update if scan is enabled. */ + if (scanEn == MV_FALSE) + return MV_OK; + + /* First group - Giga Site */ + for (i = 0; i < 32; i++) { + if (!((1 << i) & modInfo->boardMppGrp1Mod)) + continue; + index = mvBoardMppTypeIndexGet((1 << i)); + for (mpp = 0; mpp < 4; mpp++) { + if (mppGroup1[index][mpp][0] != 0x0) { + mppList[mpp] &= ~mppGroup1[index][mpp][0]; + mppList[mpp] |= mppGroup1[index][mpp][1]; + } + } + } + + /* Second group - Device Site */ + for (i = 0; i < 32; i++) { + if (!((1 << i) & modInfo->boardMppGrp2Mod)) + continue; + index = mvBoardMppTypeIndexGet((1 << i)); + for (mpp = 0; mpp <= 4; mpp++) { + mppIdx = mpp + 4; + if (mppGroup2[index][mpp][0] != 0x0) { + mppList[mppIdx] &= ~mppGroup2[index][mpp][0]; + mppList[mppIdx] |= mppGroup2[index][mpp][1]; + } + width = mvCtrlIsBootFromNAND() || mvCtrlIsBootFromNOR(); + mask = 0x0; + if (mvCtrlIsBootFromSPI() == MV_SPI_LOW_MPPS) { + if (mppIdx == 4) + mask = 0xFFFF0; + } else if (mvCtrlIsBootFromSPI() == MV_SPI_HIGH_MPPS) { + switch (mppIdx) { + case 4: + mask = 0xF; + break; + case 7: + mask = 0xF0000000; + break; + case 8: + mask = 0xFF; + break; + default: + mask = 0x0; + break; + } + } else if (width) { + switch (mppIdx) { + case 4: + mask = 0xFFFFFFF0; + break; + case 5: + if (width == MV_NAND_NOR_BOOT_8BIT) + mask = 0x0FFFFFFF; + else + mask = 0xFFFFFFFF; + case 6: + if (width == MV_NAND_NOR_BOOT_16BIT) + mask = 0xFFFFFFFF; + break; + case 7: + if (width == MV_NAND_NOR_BOOT_16BIT) + mask = 0xFFF; + break; + default: + mask = 0x0; + break; + } + } + + if (mask != 0) { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppIdx)); + mppList[mppIdx] &= ~mask; + mppList[mppIdx] |= (bootVal & mask); + } + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsModScanEnabled +* +* DESCRIPTION: +* Check if modules scanning is enabled on this board. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_BOOL mvBoardIsModScanEnabled(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardIsModScanEnabled:Board unknown.\n"); + return MV_FALSE; + } + + return BOARD_INFO(boardId)->enableModuleScan; +} + +/******************************************************************************* +* mvBoardIsSwitchConnected +* +* DESCRIPTION: +* Check if switch module is connected to giga site. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOOL - MV_TRUE, MV_FALSE. +* +*******************************************************************************/ +MV_BOOL mvBoardIsSwitchConnected(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave; + MV_U32 boardId = mvBoardIdGet(); + MV_BOOL scanEn = mvBoardIsModScanEnabled(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardIsSwitchConnected:Board unknown.\n"); + return MV_FALSE; + } + + if (scanEn == MV_FALSE) { + if (BOARD_INFO(boardId)->switchInfoNum > 0) + return MV_TRUE; + return MV_FALSE; + } + + FILL_TWSI_SLAVE(twsiSlave, MV_BOARD_GIGA_CON_ADDR); + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if ((regVal & MV_BOARD_MODULE_ID_MASK) == MV_BOARD_SWITCH_MODULE_ID) + return MV_TRUE; + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsGMIIConnected +* +* DESCRIPTION: +* Check if GMII module is connected to giga site. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOOL - MV_TRUE, MV_FALSE. +* +*******************************************************************************/ +MV_BOOL mvBoardIsGMIIConnected(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave; + MV_U32 boardId = mvBoardIdGet(); + MV_BOOL scanEn = mvBoardIsModScanEnabled(); + + /* Perform update if scan is enabled. */ + if (scanEn == MV_FALSE) + return MV_FALSE; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardIsGMIIConnected:Board unknown.\n"); + return MV_FALSE; + } + + FILL_TWSI_SLAVE(twsiSlave, MV_BOARD_GIGA_CON_GMII_ADDR); + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if ((regVal & MV_BOARD_MODULE_ID_MASK) == MV_BOARD_TDM_GMII_MODULE_GMII_ID) + return MV_TRUE; + } + + return MV_FALSE; +} + + +/******************************************************************************* +* mvBoardSmiScanModeGet - Get Switch SMI scan mode +* +* DESCRIPTION: +* This routine returns Switch SMI scan mode. +* +* INPUT: +* switchIdx - index of the switch. Only 0 is supported. +* +* OUTPUT: +* None. +* +* RETURN: +* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); + return -1; + } + + return BOARD_INFO(boardId)->pSwitchInfo[switchIdx].smiScanMode; +} + +/******************************************************************************* +* mvBoardUpdateEthAfterScan +* +* DESCRIPTION: +* Update board MACs parameters after modules scan. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardUpdateEthAfterScan(void) +{ + MV_BOOL scanEn = mvBoardIsModScanEnabled(); + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardUpdateEthAfterScan:Board unknown.\n"); + return MV_ERROR; + } + + /* Perform update if scan is enabled. */ + if (scanEn == MV_FALSE) + return MV_OK; + + /* Check if switch is connected. */ + if (MV_TRUE == mvBoardIsSwitchConnected()) { + /* Switch is connected - set mac speed manually to 1000 */ + BOARD_INFO(boardId)->pBoardMacInfo[1].boardMacSpeed = BOARD_MAC_SPEED_1000M; + BOARD_INFO(boardId)->pBoardMacInfo[1].boardEthSmiAddr = 0x10; + } else { + BOARD_INFO(boardId)->pSwitchInfo = NULL; + BOARD_INFO(boardId)->switchInfoNum = 0; + } + + if (MV_TRUE == mvBoardIsGMIIConnected()) + BOARD_INFO(boardId)->pBoardMacInfo[0].boardEthSmiAddr = 0x8; + + return MV_OK; +} + + + + +/******************************************************************************* +* mvBoardMppModulesCfgGet +* +* DESCRIPTION: +* Get board MPP options configuration. +* +* INPUT: +* group - MPP group to get the configuration for. +* +* OUTPUT: +* None. +* +* RETURN: +* Bitmap of the MPP configuration. +* +*******************************************************************************/ +MV_U32 mvBoardMppModulesCfgGet(MV_U8 group) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMppModulesCfgGet: Board unknown.\n"); + return MV_ERROR; + } + + if (group == 1) + return BOARD_INFO(boardId)->pBoardModTypeValue->boardMppGrp1Mod; + else + return BOARD_INFO(boardId)->pBoardModTypeValue->boardMppGrp2Mod; +} + +/******************************************************************************* +* mvBoardPexInfoGet - Get board PEX Info +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +*******************************************************************************/ +MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + switch (boardId) { + case DB_88F6710_BP_ID: + case DB_88F6710_PCAC_ID: + case RD_88F6710_ID: +#if defined(CONFIG_SYNO_ARMADA_ARCH) + case SYNO_DS213j_ID: + case SYNO_US3_ID: + case SYNO_RS214_ID: + case SYNO_DS214se_ID: + case SYNO_DS414slim_ID: +#endif + return &BOARD_INFO(boardId)->boardPexInfo; + break; + default: + DB(mvOsPrintf("mvBoardPexInfoGet: Unsupported board!\n")); + return NULL; + } +} + +/******************************************************************************* +* mvBoardBitMaskConfigSet - Set any configuration according to bit mask passed +* from U-Boot. +* +* DESCRIPTION: +* +* INPUT: +* config - 32 bit mask. +* OUTPUT: +* None. +* +* RETURN: +*******************************************************************************/ +MV_VOID mvBoardBitMaskConfigSet(MV_U32 config) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (boardId == RD_88F6710_ID) { + /* HDD Select */ + if (config & BIT0) { + MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT31); + MV_REG_BIT_RESET(GPP_DATA_OUT_REG(2), BIT0); + MV_REG_BIT_SET(GPP_DATA_OUT_REG(2), BIT1); + } else { + MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), BIT31); + MV_REG_BIT_SET(GPP_DATA_OUT_REG(2), BIT0); + MV_REG_BIT_RESET(GPP_DATA_OUT_REG(2), BIT1); + } + } +} diff --git a/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvLib.h b/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvLib.h new file mode 100755 index 000000000..0a8c0d6e0 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvLib.h @@ -0,0 +1,468 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvBoardEnvLibh +#define __INCmvBoardEnvLibh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +/* The below constant macros defines the board I2C EEPROM data offsets */ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + +/* DUART stuff for Tclk detection only */ +#define DUART_BAUD_RATE 115200 +#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ + +/* Voice devices assembly modes */ +#define DAISY_CHAIN_MODE 1 +#define DUAL_CHIP_SELECT_MODE 0 +#define INTERRUPT_TO_MPP 1 +#define INTERRUPT_TO_TDM 0 + +#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS +#define BOARD_ETH_SWITCH_PORT_NUM 5 + +#define MV_BOARD_MAX_USB_IF 2 +#define MV_BOARD_MAX_MPP 9 /* number of MPP conf registers */ +#define MV_BOARD_NAME_LEN 0x20 + +/* EPPROM Modules detection information */ + +#define MV_BOARD_MODULES_ADDR_TYPE ADDR7_BIT + +#define MV_BOARD_DEVICE_CON_ADDR 0x20 +#define MV_BOARD_EEPROM_MODULE_ADDR 0x21 +#define MV_BOARD_GIGA_CON_GMII_ADDR 0x22 +#define MV_BOARD_GIGA_CON_ADDR 0x26 +#define MV_BOARD_SERDES_CON_ADDR 0x27 + +#define MV_BOARD_TDM_GMII_MODULE_TDM_ID 0x1 +#define MV_BOARD_TDM_GMII_MODULE_GMII_ID 0x4 +#define MV_BOARD_SWITCH_MODULE_ID 0xE +#define MV_BOARD_I2S_SPDIF_MODULE_ID 0x2 +#define MV_BOARD_NAND_SDIO_MODULE_ID 0xF +#define MV_BOARD_MODULE_ID_MASK 0xF + +/* Mapping of SW IO Expander bits: +** 0-1: Sata0 Selection +** 0x0: SATA-0 not connected. +** 0x1: SATA-0 on Lane-0 +** 0x2: SATA-0 on Lane-2 +** 2: Sata1 Selection +** 0x0: SATA-1 not connected. +** 0x1: SATA-1 on Lane-3 +** 3-4: PCI-E Selection +** 0x0: No PCIE +** 0x1: PCIE-0 on Lane 0 +** 0x2: PCIE-1 on Lane 1 +** 0x3: PCIE-0 & PCIE-1 +** 5: On board SDIO / RGMII0 +** 0x0: SDIO disabled. +** 0x1: SDIO enabled. +*/ +#define MV_BOARD_CFG_SATA0_MODE(cfg) (cfg & 0x3) +#define MV_BOARD_CFG_SATA1_MODE(cfg) ((cfg >> 2) & 0x1) +#define MV_BOARD_CFG_PCIE_MODE(cfg) ((cfg >> 3) & 0x3) +#define MV_BOARD_CFG_SDIO_MODE(cfg) ((cfg >> 5) & 0x1) + +typedef struct _boardData { + MV_U32 magic; + MV_U16 boardId; + MV_U8 boardVer; + MV_U8 boardRev; + MV_U32 reserved1; + MV_U32 reserved2; +} BOARD_DATA; + +typedef enum _devBoardMppGroupClass { + MV_BOARD_MPP_GROUP_1, + MV_BOARD_MPP_GROUP_2, + MV_BOARD_MPP_GROUP_3, + MV_BOARD_MAX_MPP_GROUP +} MV_BOARD_MPP_GROUP_CLASS; + +typedef enum _devBoardMppTypeClass { + MV_BOARD_AUTO = 0x0, + MV_BOARD_TDM = 0x01, + MV_BOARD_I2S = 0x02, + MV_BOARD_GMII0 = 0x04, + MV_BOARD_SDIO = 0x08, + MV_BOARD_RGMII0 = 0x10, + MV_BOARD_RGMII1 = 0x20, + MV_BOARD_OTHER = 0xFFFFFFFF +} MV_BOARD_MPP_TYPE_CLASS; + +typedef enum { + MV_BOARD_NONE = 0x0001, + MV_BOARD_SGMII0 = 0x0002, + MV_BOARD_SGMII1 = 0x0004, + MV_BOARD_PEX0 = 0x0008, + MV_BOARD_PEX1 = 0x0010, + MV_BOARD_SATA0 = 0x0020, + MV_BOARD_SATA1 = 0x0040, + MV_BOARD_UNKNOWN = 0x80000000 +} MV_BOARD_OTHER_TYPE_CLASS; + +typedef struct _boardModuleTypeInfo { + MV_U32 boardMppGrp1Mod; + MV_U32 boardMppGrp2Mod; +} MV_BOARD_MODULE_TYPE_INFO; + +typedef enum _devBoardClass { + BOARD_DEV_NOR_FLASH, + BOARD_DEV_NAND_FLASH, + BOARD_DEV_SEVEN_SEG, + BOARD_DEV_FPGA, + BOARD_DEV_SRAM, + BOARD_DEV_SPI_FLASH, + BOARD_DEV_OTHER +} MV_BOARD_DEV_CLASS; + +typedef enum _devTwsiBoardClass { + BOARD_TWSI_RTC, + BOARD_DEV_TWSI_EXP, + BOARD_DEV_TWSI_SATR, + BOARD_TWSI_MUX, + BOARD_TWSI_OTHER +} MV_BOARD_TWSI_CLASS; + +typedef enum _devGppBoardClass { + BOARD_GPP_RTC, + BOARD_GPP_MV_SWITCH, + BOARD_GPP_USB_VBUS, + BOARD_GPP_USB_VBUS_EN, + BOARD_GPP_USB_OC, + BOARD_GPP_USB_HOST_DEVICE, + BOARD_GPP_REF_CLCK, + BOARD_GPP_VOIP_SLIC, + BOARD_GPP_LIFELINE, + BOARD_GPP_BUTTON, + BOARD_GPP_TS_BUTTON_C, + BOARD_GPP_TS_BUTTON_U, + BOARD_GPP_TS_BUTTON_D, + BOARD_GPP_TS_BUTTON_L, + BOARD_GPP_TS_BUTTON_R, + BOARD_GPP_POWER_BUTTON, + BOARD_GPP_RESTOR_BUTTON, + BOARD_GPP_WPS_BUTTON, + BOARD_GPP_HDD0_POWER, + BOARD_GPP_HDD1_POWER, + BOARD_GPP_FAN_POWER, + BOARD_GPP_RESET, + BOARD_GPP_POWER_ON_LED, + BOARD_GPP_HDD_POWER, + BOARD_GPP_SDIO_POWER, + BOARD_GPP_SDIO_DETECT, + BOARD_GPP_SDIO_WP, + BOARD_GPP_SWITCH_PHY_INT, + BOARD_GPP_TSU_DIRCTION, + BOARD_GPP_CONF, + BOARD_GPP_OTHER +} MV_BOARD_GPP_CLASS; + +typedef struct _devCsInfo { + MV_U8 deviceCS; + MV_U32 params; + MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ + MV_U8 devWidth; + MV_U8 busWidth; +} MV_DEV_CS_INFO; + +typedef struct _boardSwitchInfo { + MV_32 switchIrq; + MV_32 switchPort[BOARD_ETH_SWITCH_PORT_NUM]; + MV_32 cpuPort; + MV_32 connectedPort[MV_ETH_MAX_PORTS]; + MV_32 smiScanMode; + MV_32 quadPhyAddr; + MV_U32 forceLinkMask; /* Bitmask of switch ports to have force link (1Gbps) */ +} MV_BOARD_SWITCH_INFO; + +typedef struct _boardLedInfo { + MV_U8 activeLedsNumber; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + MV_U8 *gppPinNum; /* Pointer to GPP values */ +} MV_BOARD_LED_INFO; + +typedef struct _boardGppInfo { + MV_BOARD_GPP_CLASS devClass; + MV_U8 gppPinNum; +} MV_BOARD_GPP_INFO; + +typedef struct _boardTwsiInfo { + MV_BOARD_TWSI_CLASS devClass; + MV_U8 twsiDevAddr; + MV_U8 twsiDevAddrType; +} MV_BOARD_TWSI_INFO; + +typedef enum _boardMacSpeed { + BOARD_MAC_SPEED_10M, + BOARD_MAC_SPEED_100M, + BOARD_MAC_SPEED_1000M, + BOARD_MAC_SPEED_AUTO, +} MV_BOARD_MAC_SPEED; + +typedef struct _boardMacInfo { + MV_BOARD_MAC_SPEED boardMacSpeed; + MV_U8 boardEthSmiAddr; + MV_U16 LinkCryptPortAddr; + MV_U8 boardEthSmiAddr0; +} MV_BOARD_MAC_INFO; + +typedef struct _boardMppInfo { + MV_U32 mppGroup[MV_BOARD_MAX_MPP]; +} MV_BOARD_MPP_INFO; + +typedef struct { + MV_U8 spiCs; +} MV_BOARD_TDM_INFO; + +typedef struct { + MV_U8 spiId; +} MV_BOARD_TDM_SPI_INFO; + +typedef struct _boardPexInfo { + MV_PEX_UNIT_CFG pexUnitCfg[MV_PEX_MAX_UNIT]; + MV_U32 boardPexIfNum; +} MV_BOARD_PEX_INFO; + +typedef enum { + BOARD_TDM_SLIC_880 = 0, + BOARD_TDM_SLIC_792, + BOARD_TDM_SLIC_3215, + BOARD_TDM_SLIC_OTHER, + BOARD_TDM_SLIC_COUNT +} MV_BOARD_TDM_SLIC_TYPE; + +typedef struct _boardInfo { + char boardName[MV_BOARD_NAME_LEN]; + MV_BOOL enableModuleScan; + MV_U8 numBoardMppTypeValue; + MV_BOARD_MODULE_TYPE_INFO *pBoardModTypeValue; + MV_U8 numBoardMppConfigValue; + MV_BOARD_MPP_INFO *pBoardMppConfigValue; + MV_BOARD_PEX_INFO boardPexInfo; /* filled in runtime */ + MV_U32 intsGppMaskLow; + MV_U32 intsGppMaskMid; + MV_U32 intsGppMaskHigh; + MV_U8 numBoardDeviceIf; + MV_DEV_CS_INFO *pDevCsInfo; + MV_U8 numBoardTwsiDev; + MV_BOARD_TWSI_INFO *pBoardTwsiDev; + MV_U8 numBoardMacInfo; + MV_BOARD_MAC_INFO *pBoardMacInfo; + MV_U8 numBoardGppInfo; + MV_BOARD_GPP_INFO *pBoardGppInfo; + MV_U8 activeLedsNumber; + MV_U8 *pLedGppPin; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + + MV_U8 pmuPwrUpPolarity; + MV_U32 pmuPwrUpDelay; + /* GPP values */ + MV_U32 gppOutEnValLow; + MV_U32 gppOutEnValMid; + MV_U32 gppOutEnValHigh; + MV_U32 gppOutValLow; + MV_U32 gppOutValMid; + MV_U32 gppOutValHigh; + MV_U32 gppPolarityValLow; + MV_U32 gppPolarityValMid; + MV_U32 gppPolarityValHigh; + + /* External Switch Configuration */ + MV_BOARD_SWITCH_INFO *pSwitchInfo; + MV_U32 switchInfoNum; + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + MV_U8 numBoardTdmInfo[BOARD_TDM_SLIC_COUNT]; + MV_BOARD_TDM_INFO *pBoardTdmInt2CsInfo[BOARD_TDM_SLIC_COUNT]; + MV_16 boardTdmInfoIndex; + MV_BOARD_TDM_SPI_INFO *pBoardTdmSpiInfo; + + /* NAND init params */ + MV_U32 nandFlashReadParams; + MV_U32 nandFlashWriteParams; + MV_U32 nandFlashControl; + MV_U32 norFlashReadParams; + MV_U32 norFlashWriteParams; + +} MV_BOARD_INFO; + +/* Functions Decleraion */ + +/* Board General */ +MV_VOID mvBoardEnvInit(MV_VOID); +MV_VOID mvBoardReset(MV_VOID); +MV_U16 mvBoardModelGet(MV_VOID); +MV_U16 mvBoardRevGet(MV_VOID); +MV_STATUS mvBoardNameGet(char *pNameBuff); +MV_U32 mvBoardTclkGet(MV_VOID); +MV_U32 mvBoardSysClkGet(MV_VOID); +MV_BOOL mvBoardSpecInitGet(MV_U32 *regOff, MV_U32 *data); + +/* GPIO */ +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS gppClass, MV_U32 index); +MV_32 mvBoardResetGpioPinGet(MV_VOID); +MV_32 mvBoardSDIOGpioPinGet(MV_BOARD_GPP_CLASS type); +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId); +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId); +MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp); +MV_32 mvBoardMppGet(MV_U32 mppGroupNum); +MV_U32 mvBoardGppConfigGet(void); +MV_VOID mvBoardDebugLed(MV_U32 hexNum); +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); +MV_VOID mvBoardBitMaskConfigSet(MV_U32 config); + +/* Networking */ +MV_BOOL mvBoardIsSwitchConnected(void); +MV_BOOL mvBoardIsGMIIConnected(void); +MV_BOOL mvBoardIsGbEPortConnected(MV_U32 ethPortNum); +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); +MV_32 mvBoardQuadPhyAddr0Get(MV_U32 ethPortNum); +MV_32 mvBoardPhyLinkCryptPortAddrGet(MV_U32 ethPortNum); +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); +MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx); +MV_BOOL mvBoardIsPortInGmii(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInRgmii(MV_U32 ethPortNum); +MV_32 mvBoardSwitchPortGet(MV_U32 switchIdx, MV_U32 boardPortNum); +MV_32 mvBoardSwitchConnectedPortGet(MV_U32 ethPortNum); +MV_32 mvBoardSwitchPortMap(MV_U32 switchIdx, MV_U32 switchPortNum); +MV_32 mvBoardSwitchCpuPortGet(MV_U32 switchIdx); +MV_BOOL mvBoardIsQsgmiiModuleConnected(MV_VOID); +MV_32 mvBoardGePhySwitchPortGet(MV_VOID); +MV_32 mvBoardRgmiiASwitchPortGet(MV_VOID); +MV_32 mvBoardSwitchIrqGet(MV_VOID); +MV_32 mvBoardSwitchCpuPortGet(MV_U32 switchIdx); +MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx); + +/* TDM */ +MV_32 mvBoardTdmSpiModeGet(MV_VOID); +MV_U8 mvBoardTdmDevicesCountGet(void); +MV_U8 mvBoardTdmSpiCsGet(MV_U8 devId); +MV_U8 mvBoardTdmSpiIdGet(MV_VOID); + +/* Device Bus */ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardNandWidthGet(void); + +/* Twsi */ +MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index); +MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index); +MV_U32 mvBoardIdGet(MV_VOID); +MV_VOID mvBoardIdSet(MV_VOID); +MV_U8 mvBoardTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); +MV_STATUS mvBoardTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); +MV_U8 mvBoardFabFreqGet(MV_VOID); +MV_STATUS mvBoardFabFreqSet(MV_U8 freqVal); +MV_U8 mvBoardCpuFreqGet(MV_VOID); +MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal); +MV_U8 mvBoardBootDevGet(MV_VOID); +MV_STATUS mvBoardBootDevSet(MV_U8 val); +MV_U8 mvBoardBootDevWidthGet(MV_VOID); +MV_STATUS mvBoardBootDevWidthSet(MV_U8 val); +MV_U8 mvBoardCpu0CoreModeGet(MV_VOID); +MV_STATUS mvBoardCpu0CoreModeSet(MV_U8 val); + +/* Modules and Serdeses */ +MV_STATUS mvBoardMppModulesScan(void); +MV_STATUS mvBoardUpdateMppAfterScan(void); +MV_BOOL mvBoardIsModScanEnabled(void); +MV_STATUS mvBoardUpdateEthAfterScan(void); +MV_U32 mvBoardMppModulesCfgGet(MV_U8 group); +MV_VOID mvBoardMppModuleTypePrint(MV_VOID); +MV_VOID mvBoardOtherModuleTypePrint(MV_VOID); +MV_U32 mvBoardSerdesModeGet(void); + +/* PEX */ +MV_BOOL mvBoardIsPciEConnected(MV_U32 pcieIdx); +MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void); +MV_U16 mvBoardPexCapabilityGet(MV_VOID); +MV_STATUS mvBoardPexCapabilitySet(MV_U16 conf); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* __INCmvBoardEnvLibh */ diff --git a/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvSpec.c b/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvSpec.c new file mode 100755 index 000000000..5b76529b9 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvSpec.c @@ -0,0 +1,935 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvCommon.h" +#include "mvBoardEnvLib.h" +#include "mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPexRegs.h" + +#define ARRSZ(x) (sizeof(x)/sizeof(x[0])) + +/***********************/ +/* ARMADA-370 DB BOARD */ +/***********************/ + +#define DB_88F6710_BOARD_NOR_READ_PARAMS 0x403E07CF +#define DB_88F6710_BOARD_NOR_WRITE_PARAMS 0x000F0F0F + +MV_U8 db88f6710InfoBoardDebugLedIf[] = {59, 60, 61}; + +MV_BOARD_TWSI_INFO db88f6710InfoBoardTwsiDev[] = { + /* {{MV_BOARD_TWSI_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, +}; + +MV_BOARD_MAC_INFO db88f6710InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x0,0,0}, + {BOARD_MAC_SPEED_AUTO, 0x1,0,0}, +}; + +MV_BOARD_SWITCH_INFO db88f6710InfoBoardSwitchValue[] = { + { + .switchIrq = (31 + 128), /* set to -1 for timer operation. 128 is the base IRQ number for GPP interrupts */ + .switchPort = {0, 1, 2, 3, 4}, + .cpuPort = 6, + .connectedPort = {-1, 6}, + .smiScanMode = 2, + .quadPhyAddr = 0, + .forceLinkMask = 0x0 + } +}; + +MV_BOARD_MODULE_TYPE_INFO db88f6710InfoBoardModTypeInfo[] = { + { + .boardMppGrp1Mod = MV_BOARD_AUTO, + .boardMppGrp2Mod = MV_BOARD_AUTO + } +}; + +MV_BOARD_GPP_INFO db88f6710InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 48} /* from MPP map */ +}; + +MV_DEV_CS_INFO db88f6710InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db88f6710InfoBoardMppConfigValue[] = { + { { + DB_88F6710_MPP0_7, + DB_88F6710_MPP8_15, + DB_88F6710_MPP16_23, + DB_88F6710_MPP24_31, + DB_88F6710_MPP32_39, + DB_88F6710_MPP40_47, + DB_88F6710_MPP48_55, + DB_88F6710_MPP56_63, + DB_88F6710_MPP64_67, + } } +}; + + +MV_BOARD_TDM_INFO db88f6710Tdm880[] = { {0} }; /* SPI Cs */ + +MV_BOARD_TDM_SPI_INFO db88f6710TdmSpiInfo[] = { {1} }; /* SPI controller ID */ + +MV_BOARD_INFO db88f6710Info = { + .boardName = "DB-88F6710-BP", + .enableModuleScan = MV_TRUE, + .numBoardMppTypeValue = ARRSZ(db88f6710InfoBoardModTypeInfo), + .pBoardModTypeValue = db88f6710InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(db88f6710InfoBoardMppConfigValue), + .pBoardMppConfigValue = db88f6710InfoBoardMppConfigValue, + .intsGppMaskLow = BIT31, /* for Switch link interrupt */ + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(db88f6710InfoBoardDeCsInfo), + .pDevCsInfo = db88f6710InfoBoardDeCsInfo, + .numBoardTwsiDev = ARRSZ(db88f6710InfoBoardTwsiDev), + .pBoardTwsiDev = db88f6710InfoBoardTwsiDev, + .numBoardMacInfo = ARRSZ(db88f6710InfoBoardMacInfo), + .pBoardMacInfo = db88f6710InfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(db88f6710InfoBoardGppInfo), + .pBoardGppInfo = db88f6710InfoBoardGppInfo, + .activeLedsNumber = ARRSZ(db88f6710InfoBoardDebugLedIf), + .pLedGppPin = db88f6710InfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 16000, + + /* GPP values */ + .gppOutEnValLow = DB_88F6710_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_88F6710_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_88F6710_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_88F6710_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_88F6710_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_88F6710_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_88F6710_GPP_POL_LOW, + .gppPolarityValMid = DB_88F6710_GPP_POL_MID, + .gppPolarityValHigh = DB_88F6710_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = db88f6710InfoBoardSwitchValue, + .switchInfoNum = ARRSZ(db88f6710InfoBoardSwitchValue), + + /* TDM configuration */ + .numBoardTdmInfo = {1}, + .pBoardTdmInt2CsInfo = {db88f6710Tdm880}, + .boardTdmInfoIndex = 0, + .pBoardTdmSpiInfo = db88f6710TdmSpiInfo, + + /* NOR init params */ + .norFlashReadParams = DB_88F6710_BOARD_NOR_READ_PARAMS, + .norFlashWriteParams = DB_88F6710_BOARD_NOR_WRITE_PARAMS +}; + +/*************************/ +/* ARMADA-370 PCAC BOARD */ +/*************************/ + +MV_U8 db88f6710pcacInfoBoardDebugLedIf[] = {58, 59, 61}; + +MV_BOARD_MAC_INFO db88f6710pcacInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x0, 0, 0}, + {BOARD_MAC_SPEED_AUTO, 0x1, 0, 0}, +}; + +MV_BOARD_MODULE_TYPE_INFO db88f6710pcacInfoBoardModTypeInfo[] = { + { + .boardMppGrp1Mod = MV_BOARD_AUTO, + .boardMppGrp2Mod = MV_BOARD_AUTO + } +}; + +MV_BOARD_GPP_INFO db88f6710pcacInfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ +}; + +MV_DEV_CS_INFO db88f6710pcacInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db88f6710pcacInfoBoardMppConfigValue[] = { + { { + DB_88F6710_PCAC_MPP0_7, + DB_88F6710_PCAC_MPP8_15, + DB_88F6710_PCAC_MPP16_23, + DB_88F6710_PCAC_MPP24_31, + DB_88F6710_PCAC_MPP32_39, + DB_88F6710_PCAC_MPP40_47, + DB_88F6710_PCAC_MPP48_55, + DB_88F6710_PCAC_MPP56_63, + DB_88F6710_PCAC_MPP64_67, + } } +}; + + +MV_BOARD_INFO db88f6710pcacInfo = { + .boardName = "DB-88F6710-PCAC", + .enableModuleScan = MV_FALSE, + .numBoardMppTypeValue = ARRSZ(db88f6710pcacInfoBoardModTypeInfo), + .pBoardModTypeValue = db88f6710pcacInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(db88f6710pcacInfoBoardMppConfigValue), + .pBoardMppConfigValue = db88f6710pcacInfoBoardMppConfigValue, + .intsGppMaskLow = BIT31, /* for Switch link interrupt */ + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(db88f6710pcacInfoBoardDeCsInfo), + .pDevCsInfo = db88f6710pcacInfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(db88f6710pcacInfoBoardMacInfo), + .pBoardMacInfo = db88f6710pcacInfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(db88f6710pcacInfoBoardGppInfo), + .pBoardGppInfo = db88f6710pcacInfoBoardGppInfo, + .activeLedsNumber = ARRSZ(db88f6710pcacInfoBoardDebugLedIf), + .pLedGppPin = db88f6710pcacInfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 80000, + + /* GPP values */ + .gppOutEnValLow = DB_88F6710_PCAC_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_88F6710_PCAC_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_88F6710_PCAC_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_88F6710_PCAC_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_88F6710_PCAC_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_88F6710_PCAC_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_88F6710_PCAC_GPP_POL_LOW, + .gppPolarityValMid = DB_88F6710_PCAC_GPP_POL_MID, + .gppPolarityValHigh = DB_88F6710_PCAC_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + .numBoardTdmInfo = { 0 }, + .pBoardTdmInt2CsInfo = { NULL }, + .boardTdmInfoIndex = -1, + + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0, +}; + +/*************************/ +/* ARMADA-370 RD BOARD */ +/*************************/ +#define RD_88F6710_BOARD_NOR_READ_PARAMS 0x403E07CF +#define RD_88F6710_BOARD_NOR_WRITE_PARAMS 0x000F0F0F + +MV_U8 rd88F6710InfoBoardDebugLedIf[] = {32}; + +MV_BOARD_TWSI_INFO rd88F6710InfoBoardTwsiDev[] = { + /* {{MV_BOARD_TWSI_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x50, ADDR7_BIT}, +}; + +MV_BOARD_MAC_INFO rd88F6710InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x0, 0, 0}, + {BOARD_MAC_SPEED_1000M, 0x10, 0, 0}, +}; + +MV_BOARD_SWITCH_INFO rd88F6710InfoBoardSwitchValue[] = { + { + .switchIrq = (31 + 128), /* set to -1 for timer operation. 128 is the base IRQ number for GPP interrupts */ + .switchPort = {0, 1, 2, 3, -1}, + .cpuPort = 5, + .connectedPort = {-1, 5}, + .smiScanMode = 2, + .quadPhyAddr = 0, + .forceLinkMask = 0x0 + } +}; + +MV_BOARD_MODULE_TYPE_INFO rd88F6710InfoBoardModTypeInfo[] = { + { + .boardMppGrp1Mod = MV_BOARD_SDIO | MV_BOARD_RGMII1, + .boardMppGrp2Mod = MV_BOARD_TDM + } +}; + +MV_BOARD_GPP_INFO rd88F6710InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ +}; + +MV_DEV_CS_INFO rd88F6710InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO rd88F6710InfoBoardMppConfigValue[] = { + { { + RD_88F6710_MPP0_7, + RD_88F6710_MPP8_15, + RD_88F6710_MPP16_23, + RD_88F6710_MPP24_31, + RD_88F6710_MPP32_39, + RD_88F6710_MPP40_47, + RD_88F6710_MPP48_55, + RD_88F6710_MPP56_63, + RD_88F6710_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO rd88F6710Tdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO rd88F6710Tdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO rd88F6710Tdm3215[] = { {1} }; + +MV_BOARD_INFO rd88F6710Info = { + .boardName = "RD-88F6710", + .enableModuleScan = MV_FALSE, + .numBoardMppTypeValue = ARRSZ(rd88F6710InfoBoardModTypeInfo), + .pBoardModTypeValue = rd88F6710InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(rd88F6710InfoBoardMppConfigValue), + .pBoardMppConfigValue = rd88F6710InfoBoardMppConfigValue, + .intsGppMaskLow = BIT31, /* for Switch link interrupt */ + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(rd88F6710InfoBoardDeCsInfo), + .pDevCsInfo = rd88F6710InfoBoardDeCsInfo, + .numBoardTwsiDev = ARRSZ(rd88F6710InfoBoardTwsiDev), + .pBoardTwsiDev = rd88F6710InfoBoardTwsiDev, + .numBoardMacInfo = ARRSZ(rd88F6710InfoBoardMacInfo), + .pBoardMacInfo = rd88F6710InfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(rd88F6710InfoBoardGppInfo), + .pBoardGppInfo = rd88F6710InfoBoardGppInfo, + .activeLedsNumber = ARRSZ(rd88F6710InfoBoardDebugLedIf), + .pLedGppPin = rd88F6710InfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 80000, + + /* GPP values */ + .gppOutEnValLow = RD_88F6710_GPP_OUT_ENA_LOW, + .gppOutEnValMid = RD_88F6710_GPP_OUT_ENA_MID, + .gppOutEnValHigh = RD_88F6710_GPP_OUT_ENA_HIGH, + .gppOutValLow = RD_88F6710_GPP_OUT_VAL_LOW, + .gppOutValMid = RD_88F6710_GPP_OUT_VAL_MID, + .gppOutValHigh = RD_88F6710_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = RD_88F6710_GPP_POL_LOW, + .gppPolarityValMid = RD_88F6710_GPP_POL_MID, + .gppPolarityValHigh = RD_88F6710_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = rd88F6710InfoBoardSwitchValue, + .switchInfoNum = ARRSZ(rd88F6710InfoBoardSwitchValue), + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {2, 6, 1}, + .pBoardTdmInt2CsInfo = {rd88F6710Tdm880, rd88F6710Tdm792, rd88F6710Tdm3215}, + .boardTdmInfoIndex = -1, + + /* NOR init params */ + .norFlashReadParams = RD_88F6710_BOARD_NOR_READ_PARAMS, + .norFlashWriteParams = RD_88F6710_BOARD_NOR_WRITE_PARAMS +}; + +#if defined(CONFIG_SYNO_ARMADA_ARCH) +/***********************/ +/* SYNO DS213j BOARD */ +/***********************/ + +MV_BOARD_MAC_INFO synods213jInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1, 0, 0}, +}; + +MV_BOARD_MODULE_TYPE_INFO synods213jInfoBoardModTypeInfo[] = { + { + .boardMppGrp1Mod = MV_BOARD_AUTO, + .boardMppGrp2Mod = MV_BOARD_AUTO + } +}; + +MV_DEV_CS_INFO synods213jInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO synods213jInfoBoardMppConfigValue[] = { + { { + SYNO_DS213j_MPP0_7, + SYNO_DS213j_MPP8_15, + SYNO_DS213j_MPP16_23, + SYNO_DS213j_MPP24_31, + SYNO_DS213j_MPP32_39, + SYNO_DS213j_MPP40_47, + SYNO_DS213j_MPP48_55, + SYNO_DS213j_MPP56_63, + SYNO_DS213j_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO synods213jTdm880[] = { {0} }; + +MV_BOARD_TDM_SPI_INFO synods213jTdmSpiInfo[] = { {1} }; + +MV_BOARD_INFO synods213jInfo = { + .boardName = "SYNO-DS213j-BP", + .enableModuleScan = MV_FALSE, + .numBoardMppTypeValue = ARRSZ(synods213jInfoBoardModTypeInfo), + .pBoardModTypeValue = synods213jInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(synods213jInfoBoardMppConfigValue), + .pBoardMppConfigValue = synods213jInfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(synods213jInfoBoardDeCsInfo), + .pDevCsInfo = synods213jInfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(synods213jInfoBoardMacInfo), + .pBoardMacInfo = synods213jInfoBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 16000, + + /* GPP values */ + .gppOutEnValLow = SYNO_DS213j_GPP_OUT_ENA_LOW, + .gppOutEnValMid = SYNO_DS213j_GPP_OUT_ENA_MID, + .gppOutEnValHigh = SYNO_DS213j_GPP_OUT_ENA_HIGH, + .gppOutValLow = SYNO_DS213j_GPP_OUT_VAL_LOW, + .gppOutValMid = SYNO_DS213j_GPP_OUT_VAL_MID, + .gppOutValHigh = SYNO_DS213j_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = SYNO_DS213j_GPP_POL_LOW, + .gppPolarityValMid = SYNO_DS213j_GPP_POL_MID, + .gppPolarityValHigh = SYNO_DS213j_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + .numBoardTdmInfo = {1}, + .pBoardTdmInt2CsInfo = {synods213jTdm880}, + .boardTdmInfoIndex = 0, + .pBoardTdmSpiInfo = synods213jTdmSpiInfo, + + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0 +}; + + +/***********************/ +/* SYNO DS214se BOARD */ +/***********************/ + +MV_BOARD_MAC_INFO synods214seInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1, 0, 0}, +}; + +MV_BOARD_MODULE_TYPE_INFO synods214seInfoBoardModTypeInfo[] = { + { + .boardMppGrp1Mod = MV_BOARD_RGMII0, + .boardMppGrp2Mod = MV_BOARD_AUTO + } +}; + +MV_DEV_CS_INFO synods214seInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO synods214seInfoBoardMppConfigValue[] = { + { { + SYNO_DS214se_MPP0_7, + SYNO_DS214se_MPP8_15, + SYNO_DS214se_MPP16_23, + SYNO_DS214se_MPP24_31, + SYNO_DS214se_MPP32_39, + SYNO_DS214se_MPP40_47, + SYNO_DS214se_MPP48_55, + SYNO_DS214se_MPP56_63, + SYNO_DS214se_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO synods214seTdm880[] = { {0} }; + +MV_BOARD_TDM_SPI_INFO synods214seTdmSpiInfo[] = { {1} }; + +MV_BOARD_INFO synods214seInfo = { + .boardName = "SYNO-DS214se-BP", + .enableModuleScan = MV_FALSE, + .numBoardMppTypeValue = ARRSZ(synods214seInfoBoardModTypeInfo), + .pBoardModTypeValue = synods214seInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(synods214seInfoBoardMppConfigValue), + .pBoardMppConfigValue = synods214seInfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(synods214seInfoBoardDeCsInfo), + .pDevCsInfo = synods214seInfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(synods214seInfoBoardMacInfo), + .pBoardMacInfo = synods214seInfoBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 16000, + + /* GPP values */ + .gppOutEnValLow = SYNO_DS214se_GPP_OUT_ENA_LOW, + .gppOutEnValMid = SYNO_DS214se_GPP_OUT_ENA_MID, + .gppOutEnValHigh = SYNO_DS214se_GPP_OUT_ENA_HIGH, + .gppOutValLow = SYNO_DS214se_GPP_OUT_VAL_LOW, + .gppOutValMid = SYNO_DS214se_GPP_OUT_VAL_MID, + .gppOutValHigh = SYNO_DS214se_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = SYNO_DS214se_GPP_POL_LOW, + .gppPolarityValMid = SYNO_DS214se_GPP_POL_MID, + .gppPolarityValHigh = SYNO_DS214se_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + .numBoardTdmInfo = {1}, + .pBoardTdmInt2CsInfo = {synods214seTdm880}, + .boardTdmInfoIndex = 0, + .pBoardTdmSpiInfo = synods214seTdmSpiInfo, + + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0 +}; + + +/***********************/ +/* SYNO US3 BOARD */ +/***********************/ +MV_BOARD_MAC_INFO synous3InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1, 0 ,0}, + {BOARD_MAC_SPEED_AUTO, 0x0, 0 ,0}, +}; + +MV_BOARD_MODULE_TYPE_INFO synous3InfoBoardModTypeInfo[] = { + { + .boardMppGrp1Mod = MV_BOARD_RGMII1 | MV_BOARD_RGMII0, + .boardMppGrp2Mod = MV_BOARD_AUTO + } +}; + + +MV_DEV_CS_INFO synous3InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO synous3InfoBoardMppConfigValue[] = { + { { + SYNO_US3_MPP0_7, + SYNO_US3_MPP8_15, + SYNO_US3_MPP16_23, + SYNO_US3_MPP24_31, + SYNO_US3_MPP32_39, + SYNO_US3_MPP40_47, + SYNO_US3_MPP48_55, + SYNO_US3_MPP56_63, + SYNO_US3_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO synous3Tdm880[] = { {0} }; + +MV_BOARD_TDM_SPI_INFO synous3TdmSpiInfo[] = { {1} }; + +MV_BOARD_INFO synous3Info = { + .boardName = "SYNO-US3-BP", + .enableModuleScan = MV_FALSE, + .numBoardMppTypeValue = ARRSZ(synous3InfoBoardModTypeInfo), + .pBoardModTypeValue = synous3InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(synous3InfoBoardMppConfigValue), + .pBoardMppConfigValue = synous3InfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(synous3InfoBoardDeCsInfo), + .pDevCsInfo = synous3InfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(synous3InfoBoardMacInfo), + .pBoardMacInfo = synous3InfoBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 16000, + + /* GPP values */ + .gppOutEnValLow = SYNO_US3_GPP_OUT_ENA_LOW, + .gppOutEnValMid = SYNO_US3_GPP_OUT_ENA_MID, + .gppOutEnValHigh = SYNO_US3_GPP_OUT_ENA_HIGH, + .gppOutValLow = SYNO_US3_GPP_OUT_VAL_LOW, + .gppOutValMid = SYNO_US3_GPP_OUT_VAL_MID, + .gppOutValHigh = SYNO_US3_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = SYNO_US3_GPP_POL_LOW, + .gppPolarityValMid = SYNO_US3_GPP_POL_MID, + .gppPolarityValHigh = SYNO_US3_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + .numBoardTdmInfo = {1}, + .pBoardTdmInt2CsInfo = {synous3Tdm880}, + .boardTdmInfoIndex = 0, + .pBoardTdmSpiInfo = synous3TdmSpiInfo, + + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0 +}; + +/**********************/ +/* SYNO RS214 BOARD */ +/**********************/ +MV_BOARD_MAC_INFO synors214InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1, 0, 0}, + {BOARD_MAC_SPEED_AUTO, 0x0, 0, 0}, +}; + +MV_BOARD_MODULE_TYPE_INFO synors214InfoBoardModTypeInfo[] = { + { + .boardMppGrp1Mod = MV_BOARD_RGMII1 | MV_BOARD_RGMII0, + .boardMppGrp2Mod = MV_BOARD_AUTO + } +}; + +MV_DEV_CS_INFO synors214InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO synors214InfoBoardMppConfigValue[] = { + { { + SYNO_RS214_MPP0_7, + SYNO_RS214_MPP8_15, + SYNO_RS214_MPP16_23, + SYNO_RS214_MPP24_31, + SYNO_RS214_MPP32_39, + SYNO_RS214_MPP40_47, + SYNO_RS214_MPP48_55, + SYNO_RS214_MPP56_63, + SYNO_RS214_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO synors214Tdm880[] = { {0} }; + +MV_BOARD_TDM_SPI_INFO synors214TdmSpiInfo[] = { {1} }; + +MV_BOARD_INFO synors214Info = { + .boardName = "SYNO-RS214-BP", + .enableModuleScan = MV_FALSE, + .numBoardMppTypeValue = ARRSZ(synors214InfoBoardModTypeInfo), + .pBoardModTypeValue = synors214InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(synors214InfoBoardMppConfigValue), + .pBoardMppConfigValue = synors214InfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(synors214InfoBoardDeCsInfo), + .pDevCsInfo = synors214InfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(synors214InfoBoardMacInfo), + .pBoardMacInfo = synors214InfoBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 16000, + + /* GPP values */ + .gppOutEnValLow = SYNO_RS214_GPP_OUT_ENA_LOW, + .gppOutEnValMid = SYNO_RS214_GPP_OUT_ENA_MID, + .gppOutEnValHigh = SYNO_RS214_GPP_OUT_ENA_HIGH, + .gppOutValLow = SYNO_RS214_GPP_OUT_VAL_LOW, + .gppOutValMid = SYNO_RS214_GPP_OUT_VAL_MID, + .gppOutValHigh = SYNO_RS214_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = SYNO_RS214_GPP_POL_LOW, + .gppPolarityValMid = SYNO_RS214_GPP_POL_MID, + .gppPolarityValHigh = SYNO_RS214_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + .numBoardTdmInfo = {1}, + .pBoardTdmInt2CsInfo = {synors214Tdm880}, + .boardTdmInfoIndex = 0, + .pBoardTdmSpiInfo = synors214TdmSpiInfo, + + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0 +}; + +/***********************/ +/* SYNO DS414slim BOARD */ +/***********************/ + +MV_BOARD_MAC_INFO synods414slimInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1, 0, 0}, + {BOARD_MAC_SPEED_AUTO, 0x0, 0, 0}, +}; + +MV_BOARD_MODULE_TYPE_INFO synods414slimInfoBoardModTypeInfo[] = { + { + .boardMppGrp1Mod = MV_BOARD_RGMII0|MV_BOARD_RGMII1, + .boardMppGrp2Mod = MV_BOARD_AUTO + } +}; + +MV_DEV_CS_INFO synods414slimInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO synods414slimInfoBoardMppConfigValue[] = { + { { + SYNO_DS414slim_MPP0_7, + SYNO_DS414slim_MPP8_15, + SYNO_DS414slim_MPP16_23, + SYNO_DS414slim_MPP24_31, + SYNO_DS414slim_MPP32_39, + SYNO_DS414slim_MPP40_47, + SYNO_DS414slim_MPP48_55, + SYNO_DS414slim_MPP56_63, + SYNO_DS414slim_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO synods414slimTdm880[] = { {0} }; + +MV_BOARD_TDM_SPI_INFO synods414slimTdmSpiInfo[] = { {1} }; + +MV_BOARD_INFO synods414slimInfo = { + .boardName = "SYNO-DS414slim", + .enableModuleScan = MV_FALSE, + .numBoardMppTypeValue = ARRSZ(synods414slimInfoBoardModTypeInfo), + .pBoardModTypeValue = synods414slimInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(synods414slimInfoBoardMppConfigValue), + .pBoardMppConfigValue = synods414slimInfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(synods414slimInfoBoardDeCsInfo), + .pDevCsInfo = synods414slimInfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(synods414slimInfoBoardMacInfo), + .pBoardMacInfo = synods414slimInfoBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 16000, + + /* GPP values */ + .gppOutEnValLow = SYNO_DS414slim_GPP_OUT_ENA_LOW, + .gppOutEnValMid = SYNO_DS414slim_GPP_OUT_ENA_MID, + .gppOutEnValHigh = SYNO_DS414slim_GPP_OUT_ENA_HIGH, + .gppOutValLow = SYNO_DS414slim_GPP_OUT_VAL_LOW, + .gppOutValMid = SYNO_DS414slim_GPP_OUT_VAL_MID, + .gppOutValHigh = SYNO_DS414slim_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = SYNO_DS414slim_GPP_POL_LOW, + .gppPolarityValMid = SYNO_DS414slim_GPP_POL_MID, + .gppPolarityValHigh = SYNO_DS414slim_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + .numBoardTdmInfo = {1}, + .pBoardTdmInt2CsInfo = {synods414slimTdm880}, + .boardTdmInfoIndex = 0, + .pBoardTdmSpiInfo = synods414slimTdmSpiInfo, + + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0 +}; + +#endif /* CONFIG_SYNO_ARMADA_ARCH */ + +MV_BOARD_INFO *boardInfoTbl[] = { + &db88f6710Info, + &db88f6710pcacInfo, + &rd88F6710Info +#if defined(CONFIG_SYNO_ARMADA_ARCH) + ,NULL /* Reserved begin: 0x3 */ + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL /* Reserved end: 0xF */ + ,&synods213jInfo + ,&synous3Info + ,&synors214Info + ,&synods214seInfo + ,&synods414slimInfo +#endif +}; diff --git a/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvSpec.h b/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvSpec.h new file mode 100755 index 000000000..a70fa2626 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/boardEnv/mvBoardEnvSpec.h @@ -0,0 +1,377 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoardEnvSpech +#define __INCmvBoardEnvSpech + +#include "mvSysHwConfig.h" + +/* For future use */ +#define BD_ID_DATA_START_OFFS 0x0 +#define BD_DETECT_SEQ_OFFS 0x0 +#define BD_SYS_NUM_OFFS 0x4 +#define BD_NAME_OFFS 0x8 + +#define MV_BOARD_DIMM0_I2C_ADDR 0x56 +#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 + + +/* Board specific configuration */ +/* ============================ */ + +/* boards ID numbers */ +#define BOARD_ID_BASE 0x0 +#if defined(CONFIG_SYNO_ARMADA_ARCH) +#define BOARD_ID_MAX_RESERVED 0xF +#endif + +/* New board ID numbers */ +#define DB_88F6710_BP_ID (BOARD_ID_BASE) +#define DB_88F6710_PCAC_ID (DB_88F6710_BP_ID + 1) +#define RD_88F6710_ID (DB_88F6710_PCAC_ID + 1) + +#if defined(CONFIG_SYNO_ARMADA_ARCH) + +#define LAST_MV_BOARD_ID RD_88F6710_ID +#if LAST_MV_BOARD_ID > BOARD_ID_MAX_RESERVED +#error "please check board id setting!" +#endif + +#define SYNO_DS213j_ID (BOARD_ID_MAX_RESERVED + 1) +#define SYNO_US3_ID (SYNO_DS213j_ID + 1) +#define SYNO_RS214_ID (SYNO_US3_ID + 1) +#define SYNO_DS214se_ID (SYNO_RS214_ID + 1) +#define SYNO_DS414slim_ID (SYNO_DS214se_ID + 1) +#define MV_MAX_BOARD_ID (SYNO_DS414slim_ID + 1) + +#else /* CONFIG_SYNO_ARMADA_ARCH */ +#define MV_MAX_BOARD_ID (RD_88F6710_ID + 1) +#endif /* CONFIG_SYNO_ARMADA_ARCH */ +#define INVALID_BAORD_ID 0xFFFFFFFF + +#ifdef CONFIG_SYNO_ARMADA_ARCH +/*******************/ +/* SYNO DS213j BP */ +/*******************/ + +#define SYNO_DS213j_MPP0_7 0x00011111 +#define SYNO_DS213j_MPP8_15 0x00000000 +#define SYNO_DS213j_MPP16_23 0x00000110 +#define SYNO_DS213j_MPP24_31 0x00000000 +#define SYNO_DS213j_MPP32_39 0x00022220 +#define SYNO_DS213j_MPP40_47 0x00000220 + +#ifdef MV_INCLUDE_NOR +#define SYNO_DS213j_MPP48_55 0x00000004 +#define SYNO_DS213j_MPP56_63 0x00030000 +#else +#define SYNO_DS213j_MPP48_55 0x00000004 +#define SYNO_DS213j_MPP56_63 0x00030000 +#endif + +#define SYNO_DS213j_MPP64_67 0x00000000 + + +#define SYNO_DS213j_GPP_OUT_ENA_LOW (~(BIT31)) +#define SYNO_DS213j_GPP_OUT_ENA_MID (~(BIT0|BIT5|BIT16|BIT28|BIT30|BIT31)) +#define SYNO_DS213j_GPP_OUT_ENA_HIGH (~(BIT0|BIT1)) + +#define SYNO_DS213j_GPP_OUT_VAL_LOW 0x0 +#define SYNO_DS213j_GPP_OUT_VAL_MID 0x0 +#define SYNO_DS213j_GPP_OUT_VAL_HIGH 0x0 + +#define SYNO_DS213j_GPP_POL_LOW 0x0 +#define SYNO_DS213j_GPP_POL_MID 0x0 +#define SYNO_DS213j_GPP_POL_HIGH 0x0 + + +/*********************/ +/* SYNO DS214se BP */ +/*********************/ +#define SYNO_DS214se_MPP0_7 0x11111111 +#define SYNO_DS214se_MPP8_15 0x11111111 +#define SYNO_DS214se_MPP16_23 0x00000111 +#define SYNO_DS214se_MPP24_31 0x00000000 +#define SYNO_DS214se_MPP32_39 0x00022220 +#define SYNO_DS214se_MPP40_47 0x00000220 +#define SYNO_DS214se_MPP48_55 0x00000004 +#define SYNO_DS214se_MPP56_63 0x00030000 +#define SYNO_DS214se_MPP64_67 0x00000000 + + +#define SYNO_DS214se_GPP_OUT_ENA_LOW (~(BIT31)) +#define SYNO_DS214se_GPP_OUT_ENA_MID (~(BIT0|BIT5|BIT16|BIT28|BIT30|BIT31)) +#define SYNO_DS214se_GPP_OUT_ENA_HIGH (~(BIT0|BIT1)) + +#define SYNO_DS214se_GPP_OUT_VAL_LOW 0x0 +#define SYNO_DS214se_GPP_OUT_VAL_MID BIT5 +#define SYNO_DS214se_GPP_OUT_VAL_HIGH 0x0 + +#define SYNO_DS214se_GPP_POL_LOW 0x0 +#define SYNO_DS214se_GPP_POL_MID 0x0 +#define SYNO_DS214se_GPP_POL_HIGH 0x0 + +/*******************/ +/* SYNO US3 BP */ +/*******************/ +#define SYNO_US3_MPP0_7 0x11110011 +#define SYNO_US3_MPP8_15 0x11111111 +#define SYNO_US3_MPP16_23 0x22222111 +#define SYNO_US3_MPP24_31 0x02222222 +#define SYNO_US3_MPP32_39 0x00000001 +#define SYNO_US3_MPP40_47 0x30000000 +#define SYNO_US3_MPP48_55 0x00033333 +#define SYNO_US3_MPP56_63 0x10000000 +#define SYNO_US3_MPP64_67 0x00000011 + + +#define SYNO_US3_GPP_OUT_ENA_LOW (~(0x0)) +#define SYNO_US3_GPP_OUT_ENA_MID (~(BIT8|BIT10|BIT11|BIT13|BIT28)) +#define SYNO_US3_GPP_OUT_ENA_HIGH (~(0x0)) + +#define SYNO_US3_GPP_OUT_VAL_LOW 0x0 +#define SYNO_US3_GPP_OUT_VAL_MID (BIT11|BIT28) +#define SYNO_US3_GPP_OUT_VAL_HIGH 0x0 + +#define SYNO_US3_GPP_POL_LOW 0x0 +#define SYNO_US3_GPP_POL_MID 0x0 +#define SYNO_US3_GPP_POL_HIGH 0x0 + +/***********************/ +/* SYNO RS214 BP */ +/***********************/ +#define SYNO_RS214_MPP0_7 0x11111111 +#define SYNO_RS214_MPP8_15 0x11111111 +#define SYNO_RS214_MPP16_23 0x22222111 +#define SYNO_RS214_MPP24_31 0x02222222 +#define SYNO_RS214_MPP32_39 0x00022220 +#define SYNO_RS214_MPP40_47 0x00000220 +#define SYNO_RS214_MPP48_55 0x00000004 +#define SYNO_RS214_MPP56_63 0x00030000 +#define SYNO_RS214_MPP64_67 0x00000000 + +#define SYNO_RS214_GPP_OUT_ENA_LOW 0x0 +#define SYNO_RS214_GPP_OUT_ENA_MID (~(BIT0|BIT16|BIT17|BIT28|BIT31)) +#define SYNO_RS214_GPP_OUT_ENA_HIGH (~(BIT0|BIT1)) + +#define SYNO_RS214_GPP_OUT_VAL_LOW 0x0 +#define SYNO_RS214_GPP_OUT_VAL_MID 0x0 +#define SYNO_RS214_GPP_OUT_VAL_HIGH 0x0 + +#define SYNO_RS214_GPP_POL_LOW 0x0 +#define SYNO_RS214_GPP_POL_MID 0x0 +#define SYNO_RS214_GPP_POL_HIGH 0x0 + +/*********************/ +/* SYNO DS414slim */ +/*********************/ +#define SYNO_DS414slim_MPP0_7 0x11111111 +#define SYNO_DS414slim_MPP8_15 0x11111111 +#define SYNO_DS414slim_MPP16_23 0x22222111 +#define SYNO_DS414slim_MPP24_31 0x02222222 +#define SYNO_DS414slim_MPP32_39 0x00022220 +#define SYNO_DS414slim_MPP40_47 0x00000220 +#define SYNO_DS414slim_MPP48_55 0x00000004 +#define SYNO_DS414slim_MPP56_63 0x00000000 +#define SYNO_DS414slim_MPP64_67 0x00000000 + + +#define SYNO_DS414slim_GPP_OUT_ENA_LOW (~(0x0)) +#define SYNO_DS414slim_GPP_OUT_ENA_MID (~(BIT31)) +#define SYNO_DS414slim_GPP_OUT_ENA_HIGH (~(BIT0|BIT1)) + +#define SYNO_DS414slim_GPP_OUT_VAL_LOW 0x0 +#define SYNO_DS414slim_GPP_OUT_VAL_MID 0x0 +#define SYNO_DS414slim_GPP_OUT_VAL_HIGH 0x0 + +#define SYNO_DS414slim_GPP_POL_LOW 0x0 +#define SYNO_DS414slim_GPP_POL_MID 0x0 +#define SYNO_DS414slim_GPP_POL_HIGH 0x0 + +#define GPIO_UNDEF 0xFF + +#endif /* CONFIG_SYNO_ARMADA_ARCH */ + +/******************/ +/* DB-88F6710-BP */ +/******************/ +#define DB_88F6710_MPP0_7 0x11111111 +#define DB_88F6710_MPP8_15 0x11111111 +#define DB_88F6710_MPP16_23 0x22222111 +#define DB_88F6710_MPP24_31 0x02222222 +#define DB_88F6710_MPP32_39 0x11111111 +#define DB_88F6710_MPP40_47 0x11111111 + +#ifdef MV_INCLUDE_NOR +#define DB_88F6710_MPP48_55 0x41111111 +#define DB_88F6710_MPP56_63 0x11111140 +#else +#define DB_88F6710_MPP48_55 0x41111110 +#define DB_88F6710_MPP56_63 0x11000140 +#endif + +#define DB_88F6710_MPP64_67 0x00000011 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +31 Giga_inN IN +48 USB_Dev_Detect IN +59 7seg bit0 OUT +60 7seg bit1 OUT +61 7seg bit2 OUT +*/ +#define DB_88F6710_GPP_OUT_ENA_LOW (~(0x0)) +#define DB_88F6710_GPP_OUT_ENA_MID (~(BIT27 | BIT28 | BIT29)) +#define DB_88F6710_GPP_OUT_ENA_HIGH (~(0x0)) + +#define DB_88F6710_GPP_OUT_VAL_LOW 0x0 +#define DB_88F6710_GPP_OUT_VAL_MID 0x0 +#define DB_88F6710_GPP_OUT_VAL_HIGH 0x0 + +#define DB_88F6710_GPP_POL_LOW 0x0 +#define DB_88F6710_GPP_POL_MID 0x0 +#define DB_88F6710_GPP_POL_HIGH 0x0 + +/*******************/ +/* DB-88F6710-PCAC */ +/*******************/ + +#define DB_88F6710_PCAC_MPP0_7 0x00001111 +#define DB_88F6710_PCAC_MPP8_15 0x00000000 +#define DB_88F6710_PCAC_MPP16_23 0x00000110 +#define DB_88F6710_PCAC_MPP24_31 0x10000000 +#define DB_88F6710_PCAC_MPP32_39 0x11111111 +#define DB_88F6710_PCAC_MPP40_47 0x01111111 +#define DB_88F6710_PCAC_MPP48_55 0x00000000 +#define DB_88F6710_PCAC_MPP56_63 0x14040000 +#define DB_88F6710_PCAC_MPP64_67 0x00000011 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +58 7seg bit0 OUT +59 7seg bit1 OUT +61 7seg bit2 OUT +*/ +#define DB_88F6710_PCAC_GPP_OUT_ENA_LOW (~(0x0)) +#define DB_88F6710_PCAC_GPP_OUT_ENA_MID (~(BIT26 | BIT27 | BIT29)) +#define DB_88F6710_PCAC_GPP_OUT_ENA_HIGH (~(0x0)) + +#define DB_88F6710_PCAC_GPP_OUT_VAL_LOW 0x0 +#define DB_88F6710_PCAC_GPP_OUT_VAL_MID 0x0 +#define DB_88F6710_PCAC_GPP_OUT_VAL_HIGH 0x0 + +#define DB_88F6710_PCAC_GPP_POL_LOW 0x0 +#define DB_88F6710_PCAC_GPP_POL_MID 0x0 +#define DB_88F6710_PCAC_GPP_POL_HIGH 0x0 + +/*******************/ +/* RD_88F6710 */ +/*******************/ +#define RD_88F6710_MPP0_7 0x00001111 +#define RD_88F6710_MPP8_15 0x33333030 +#define RD_88F6710_MPP16_23 0x22222110 +#define RD_88F6710_MPP24_31 0x02222222 +#define RD_88F6710_MPP32_39 0x11111110 +#define RD_88F6710_MPP40_47 0x01111111 +#define RD_88F6710_MPP48_55 0x33344444 +#define RD_88F6710_MPP56_63 0x03555556 +#define RD_88F6710_MPP64_67 0x00000000 + +/* GPPs ARMADA370 +MPP# NAME IN/OUT +---------------------------------------------- +5 PEX RST# OUT (1) +6 GPP_PB IN +8 Fan power control OUT (1) +10 SDIO Status IN +16 SDIO WP IN +31 Switch Interrupt IN +32 User LED OUT(?) +47 USB Power On OUT(0) +63 HDD Select OUT(0) +64 Int HDD Power OUT(1) +65 Ext HDD Power OUT(0) + +*/ +#define RD_88F6710_GPP_OUT_ENA_LOW (~(BIT5 | BIT8)) +#define RD_88F6710_GPP_OUT_ENA_MID (~(BIT0 | BIT15 | BIT31)) +#define RD_88F6710_GPP_OUT_ENA_HIGH (~(BIT0 | BIT1)) + +#define RD_88F6710_GPP_OUT_VAL_LOW (BIT5 | BIT8) +#define RD_88F6710_GPP_OUT_VAL_MID 0x0 +#define RD_88F6710_GPP_OUT_VAL_HIGH 0x0 + + +#define RD_88F6710_GPP_POL_LOW BIT31 +#define RD_88F6710_GPP_POL_MID 0x0 +#define RD_88F6710_GPP_POL_HIGH 0x0 + + + + +#endif /* __INCmvBoardEnvSpech */ diff --git a/arch/arm/mach-armada370/armada_370_family/cpu/mvCpu.c b/arch/arm/mach-armada370/armada_370_family/cpu/mvCpu.c new file mode 100755 index 000000000..a7f1ba3ce --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/cpu/mvCpu.c @@ -0,0 +1,306 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ + +/******************************************************************************* +* mvCpuPclkGet - Get the CPU pClk (pipe clock) +* +* DESCRIPTION: +* This routine extract the CPU core clock. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvCpuPclkGet(MV_VOID) +{ +#if defined(PCLCK_AUTO_DETECT) + MV_U32 idx; + MV_U32 cpuClk[] = MV_CPU_CLK_TBL; + + idx = MSAR_CPU_CLK_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET)); + + return cpuClk[idx] * 1000000; +#else + return MV_DEFAULT_PCLK; +#endif +} + +/******************************************************************************* +* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU L2 clock. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvCpuL2ClkGet(MV_VOID) +{ +#ifdef L2CLK_AUTO_DETECT + MV_U32 idx; + MV_U32 freqMhz, l2FreqMhz; + MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL; + + idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET)); + + if (clockRatioTbl[idx].vco2cpu != 0) { + freqMhz = mvCpuPclkGet() / 1000000; /* CPU freq */ + freqMhz *= clockRatioTbl[idx].vco2cpu; /* VCO freq */ + l2FreqMhz = freqMhz / clockRatioTbl[idx].vco2l2c; + /* round up to integer MHz */ + if (((freqMhz % clockRatioTbl[idx].vco2l2c) * 10 / clockRatioTbl[idx].vco2l2c) >= 5) + l2FreqMhz++; + + return l2FreqMhz * 1000000; + } else + return (MV_U32)-1; +#else + return MV_BOARD_DEFAULT_L2CLK; +#endif +} + +/******************************************************************************* +* mvCpuNameGet - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +MV_VOID mvCpuNameGet(char *pNameBuff) +{ + MV_U32 cpuModel; + MV_U32 archType; + + cpuModel = mvOsCpuPartGet(); + archType = mvOsCpuThumbEEGet(); + /* The CPU module is indicated in the Processor Version Register (PVR) */ + switch (cpuModel & 0xfff) { + case CPU_PART_ARM_V6UP: + case CPU_PART_ARM_V6MP: + case CPU_PART_MRVLPJ4B_MP: + case CPU_PART_ARM_V7UP: + case CPU_PART_MRVLPJ4B_UP: + if (archType == 0x1) + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v7 UP", mvOsCpuRevGet()); + else + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B v6 UP", mvOsCpuRevGet()); + break; + default: + mvOsSPrintf(pNameBuff, "??? (0x%04x) (Rev %d)", cpuModel, mvOsCpuRevGet()); + break; + } /* switch */ + + return; +} + +#define MV_PROC_STR_SIZE 50 + +static void mvCpuIfGetL2EccMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_ECC_MASK) == CL2ACR_ECC_EN) + mvOsSPrintf(buf, "L2 ECC Enabled"); + else + mvOsSPrintf(buf, "L2 ECC Disabled"); +} + +static void mvCpuIfGetL2ParityMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_PARITY_MASK) == CL2ACR_PARITY_EN) + mvOsSPrintf(buf, "L2 Parity Enabled"); + else + mvOsSPrintf(buf, "L2 Parity Disabled"); +} + +static void mvCpuIfGetL2Mode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_CTRL_REG); + if (regVal & CL2CR_L2_EN_MASK) + mvOsSPrintf(buf, "L2 Enabled"); + else + mvOsSPrintf(buf, "L2 Disabled"); +} + +static void mvCpuIfGetWriteAllocMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_FORCE_WA_MASK) == CL2ACR_FORCE_NO_WA) + mvOsSPrintf(buf, "L2 Write Allocate Disabled"); + else + mvOsSPrintf(buf, "L2 Write Allocate Enabled"); +} + +static void mvCpuIfGetCpuStreamMode(MV_8 *buf) +{ /* valid for PJ4B as well */ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT29) + mvOsSPrintf(buf, "CPU Streaming Enabled"); + else + mvOsSPrintf(buf, "CPU Streaming Disabled"); +} + +static void mvCpuIfPrintCpuRegs(void) +{ + MV_U32 regVal = 0; + + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register0 */ + mvOsPrintf("Extra Features Reg[0] = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 1, %0, c15, c1, 1" : "=r" (regVal)); /* Read Marvell extra features register1 */ + mvOsPrintf("Extra Features Reg[1] = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ + mvOsPrintf("Control Reg = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read Main ID register */ + mvOsPrintf("Main ID Reg = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ + mvOsPrintf("Cache Type Reg = 0x%x\n", regVal); + + regVal = MV_REG_READ(CPU_L2_CTRL_REG); + mvOsPrintf("L2 Control Reg = 0x%x\n", regVal); + + regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + mvOsPrintf("L2 Auxilary Control Reg = 0x%x\n", regVal); + +} + +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) +{ + MV_U32 count = 0; + + MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; + MV_8 L2_En_str[MV_PROC_STR_SIZE]; + MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; + MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; + MV_8 L2_Parity_str[MV_PROC_STR_SIZE]; + + mvCpuIfGetL2Mode(L2_En_str); + mvCpuIfGetL2EccMode(L2_ECC_str); + mvCpuIfGetL2ParityMode(L2_Parity_str); + mvCpuIfGetWriteAllocMode(Write_Alloc_str); + mvCpuIfGetCpuStreamMode(Cpu_Stream_str); + mvCpuIfPrintCpuRegs(); + + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Parity_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); + return count; +} + + +/******************************************************************************* +* whoAmI - Get the CPU ID +* +* DESCRIPTION: +* This function returns CPU ID in multiprocessor system +* Not relevant for Armada 370. +* +* INPUT: +* None. +* +* OUTPUT: +* none. +* +* RETURN: +* CPU ID. +*******************************************************************************/ +unsigned int whoAmI(void) +{ + return 0; +} diff --git a/arch/arm/mach-armada370/armada_370_family/cpu/mvCpu.h b/arch/arm/mach-armada370/armada_370_family/cpu/mvCpu.h new file mode 100755 index 000000000..c1d01edd4 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/cpu/mvCpu.h @@ -0,0 +1,115 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCpuh +#define __INCmvCpuh + +#include "mvCommon.h" +#ifndef MV_ASMLANGUAGE +#include "mvOs.h" +#endif +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#define MASTER_CPU 0 +/* defines */ +#define CPU_PART_MRVL131 0x131 +#define CPU_PART_ARM926 0x926 +#define CPU_PART_ARM946 0x946 +#define CPU_PART_MRVL_A8 0xC08 +#define CPU_PART_MRVL_A9 0xC09 + +#define CPU_PART_MRVL571 0x571 +#define CPU_PART_MRVL521 0x521 + +#define CPU_PART_ARM_V6UP 0xb76 +#define CPU_PART_ARM_V7UP 0xc08 +#define CPU_PART_ARM_V6MP 0xb02 + +#define CPU_PART_MRVLPJ4B_UP 0x581 +#define CPU_PART_MRVLPJ4B_MP 0x584 + +#if 0 +#define MV_CPU_ARM_CLK_ELM_SIZE 12 +#define MV_CPU_ARM_CLK_RATIO_OFF 8 +#define MV_CPU_ARM_CLK_DDR_OFF 4 +#endif + +#ifndef MV_ASMLANGUAGE +typedef struct _mvCpuArmClkRatio { + MV_U32 vco2cpu; /* VCO:PCLK0(CPU) clock ratio */ + MV_U32 vco2l2c; /* VCO:NB(L2 cache) clock ratio */ + MV_U32 vco2hcl; /* VCO:HCLK(DDR controller) clock ratio */ + MV_U32 vco2ddr; /* VCO:DDR(DDR memory) clock ratio */ + +} MV_CPU_ARM_CLK_RATIO; + +MV_U32 mvCpuPclkGet(MV_VOID); +MV_VOID mvCpuNameGet(char *pNameBuff); +MV_U32 mvCpuL2ClkGet(MV_VOID); +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); +MV_U32 whoAmI(MV_VOID); + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvCpuh */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAddrDec.c b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAddrDec.c new file mode 100755 index 000000000..8449c1500 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAddrDec.c @@ -0,0 +1,271 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCtrlEnvAddrDec.h - Marvell controller address decode library +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "sys/mvCpuIf.h" + +#undef MV_DEBUG + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* Default Attributes array */ +MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; +extern MV_TARGET sampleAtResetTargetArray[]; + +/******************************************************************************* +* mvCtrlAttribGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib) +{ + targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; + targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlGetAttrib - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS; target++) { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) { + /* found it */ + break; + } + } + + return target; +} + +/******************************************************************************* +* mvCtrlTargetByWinInfoGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetByWinInfoGet(MV_UNIT_WIN_INFO *unitWinInfo) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS; target++) { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == unitWinInfo->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == unitWinInfo->targetId)) { + /* found it */ + break; + } + } + + return target; +} + +/******************************************************************************* +* mvCtrlAddrWinMapBuild +* +* DESCRIPTION: +* Build the windows address decoding table, to be used for initializing +* the unit's address decoding windows. +* +* INPUT: +* pAddrWinMap: An array to hold the address decoding windows parameters. +* len: Number of entries in pAddrWinMap. +* +* OUTPUT: +* pAddrWinMap: Address window information. +* +* RETURN: +* MV_BAD_PARAM: input array is smaller than needed to store all window +* addresses. +* MV_ERROR: Otherwise. +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrWinMapBuild(MV_UNIT_WIN_INFO *pAddrWinMap, MV_U32 len) +{ + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 i; + MV_TARGET_ATTRIB targetAttrib; + MV_STATUS status; + + /* Check size of CPU address win table */ + if (len <= MAX_TARGETS) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - Table size too small.\n"); + return MV_BAD_PARAM; + } + + /* Fill in the pAddrWinMap fields */ + for (i = 0; i < MAX_TARGETS; i++) { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) { + if (status == MV_NO_SUCH) { + pAddrWinMap[i].enable = MV_FALSE; + continue; + } else { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCpuIfTargetWinGet() failed.\n"); + return MV_ERROR; + } + } + + pAddrWinMap[i].addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + pAddrWinMap[i].addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + pAddrWinMap[i].addrWin.size = cpuAddrDecWin.addrWin.size; + pAddrWinMap[i].enable = cpuAddrDecWin.enable; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + pAddrWinMap[i].attrib = targetAttrib.attrib; + pAddrWinMap[i].targetId = targetAttrib.targetId; + } + pAddrWinMap[i].addrWin.baseLow = TBL_TERM; + pAddrWinMap[i].addrWin.baseHigh = TBL_TERM; + pAddrWinMap[i].addrWin.size = TBL_TERM; + pAddrWinMap[i].enable = TBL_TERM; + pAddrWinMap[i].attrib = TBL_TERM; + pAddrWinMap[i].targetId = TBL_TERM; + + return MV_OK; +} + +MV_STATUS mvCtrlAddrWinInfoGet(MV_UNIT_WIN_INFO *pAddrWinInfo, MV_ULONG physAddr) +{ + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 i; + MV_TARGET_ATTRIB targetAttrib; + MV_STATUS status; + + for (i = 0; i < MAX_TARGETS; i++) { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) + continue; + + if ((physAddr >= cpuAddrDecWin.addrWin.baseLow) && + (physAddr < cpuAddrDecWin.addrWin.baseLow + cpuAddrDecWin.addrWin.size)) { + /* Found */ + pAddrWinInfo->addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + pAddrWinInfo->addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + pAddrWinInfo->addrWin.size = cpuAddrDecWin.addrWin.size; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + pAddrWinInfo->attrib = targetAttrib.attrib; + pAddrWinInfo->targetId = targetAttrib.targetId; + return MV_OK; + } + } + /* not found */ + return MV_NOT_FOUND; +} diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAddrDec.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAddrDec.h new file mode 100755 index 000000000..4174b044c --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAddrDec.h @@ -0,0 +1,193 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAddrDech +#define __INCmvCtrlEnvAddrDech + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + + +/* defines */ +/* DUnit attributes */ +#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 +#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 +#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) + +#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 +#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 +#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) + +#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 +#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 +#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) + +#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 +#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 +#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) + +/* RUnit (Device) attributes */ +#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 +#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 +#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 +#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 +#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 +#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 +#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) + +#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 +#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 +#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) + +/* LMaster (PCI) attributes */ +#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) + + +#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 +#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 +#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) + +#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 + +#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 +#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 +#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) +#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) + +#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 +#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 +#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 +#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 +#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +/* PEX Attributes */ +#define ATMWCR_WIN_PEX_TYPE_OFFS 3 +#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 +#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) +#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) + +/* typedefs */ + +/* Unsupported attributes for address decode: */ +/* 2) PCI0/1_REQ64n control */ + +typedef struct _mvTargetAttrib { + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ +} MV_TARGET_ATTRIB; + + +/* This structure describes address decode window */ +typedef struct _mvDecWin { + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ +} MV_DEC_WIN; + +typedef struct _mvDecWinParams { + MV_TARGET_ID targetId; /* Target ID field */ + MV_U8 attrib; /* Attribute field */ + MV_U32 baseAddr; /* Base address in register format */ + MV_U32 size; /* Size in register format */ +} MV_DEC_WIN_PARAMS; + + +/* mvCtrlEnvAddrDec API list */ + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib); + +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); +MV_TARGET mvCtrlTargetByWinInfoGet(MV_UNIT_WIN_INFO *unitWinInfo); + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, MV_DEC_WIN_PARAMS *pWinParam); + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, MV_DEC_WIN *pAddrDecWin); + +MV_STATUS mvCtrlAddrWinMapBuild(MV_UNIT_WIN_INFO *pAddrWinMap, MV_U32 len); + +MV_STATUS mvCtrlAddrWinInfoGet(MV_UNIT_WIN_INFO *pAddrWinInfo, MV_ULONG physAddr); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* __INCmvCtrlEnvAddrDech */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAsm.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAsm.h new file mode 100755 index 000000000..1a14a79bb --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvAsm.h @@ -0,0 +1,97 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAsmh +#define __INCmvCtrlEnvAsmh +#include "pex/mvPexRegs.h" + +#define CHIP_BOND_REG 0x18238 +#define PCKG_OPT_MASK_AS #3 +#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK + +/* Read device ID into toReg bits 15:0 from 0xd0000000 */ +/* defines */ +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read device ID into toReg bits 15:0 from 0xf1000000*/ +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read Revision into toReg bits 7:0 0xd0000000*/ +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0, PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +/* Read Revision into toReg bits 7:0 0xf1000000*/ +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0, PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +#endif /* __INCmvCtrlEnvAsmh */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvLib.c b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvLib.c new file mode 100755 index 000000000..dbee75a2e --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvLib.c @@ -0,0 +1,1850 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "gpp/mvGpp.h" +#include "gpp/mvGppRegs.h" +#include "mvSysEthConfig.h" + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#include "pex/mvPexRegs.h" +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#if defined(MV_ETH_LEGACY) +#include "eth/mvEth.h" +#else +#include "neta/gbe/mvNeta.h" +#endif /* MV_ETH_LEGACY or MV_ETH_NETA */ +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +#endif + +#if defined(MV_INCLUDE_SATA) +#include "mvSysSataConfig.h" +#include "sata/CoreDriver/mvSata.h" +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#endif + +#if defined(MV_INCLUDE_TDM) +#include "mvSysTdmConfig.h" +static MV_VOID mvCtrlTdmClkCtrlSet(MV_VOID); +#endif + +/* defines */ +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/******************************************************************************* +* mvCtrlGetCpuNum - Get number of Processors +* +* DESCRIPTION: +* This function returns the number of Processors +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns always 0 for KW-40 +*******************************************************************************/ +MV_U32 mvCtrlGetCpuNum(MV_VOID) +{ + return 0; +} + + +/******************************************************************************* +* mvCtrlIsValidSatR - Verify if the SatR is Valid +* +* DESCRIPTION: +* This function determines if the SatR is Valid or customized +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns MV_TRUE for a valid SatR, or MV_FALSE for a customized SatR +*******************************************************************************/ +MV_BOOL mvCtrlIsValidSatR(MV_VOID) +{ + return MV_TRUE; +} + +/******************************************************************************* +* mvCtrlEnvInit - Initialize Marvell controller environment. +* +* DESCRIPTION: +* This function get environment information and initialize controller +* internal/external environment. For example +* 1) MPP settings according to board MPP macros. +* NOTE: It is the user responsibility to shut down all DMA channels +* in device and disable controller sub units interrupts during +* boot process. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCtrlEnvInit(MV_VOID) +{ + MV_U32 mppGroup; + MV_U32 mppVal; + + /* Disable MBus Error Propagation */ + MV_REG_BIT_RESET(SOC_COHERENCY_FABRIC_CTRL_REG, BIT8); + + /* Use Background sync barrier (polling) for I/O cache coherency */ + MV_REG_BIT_SET(SOC_CIB_CTRL_CFG_REG, BIT8); + + /* Write first MPP group. */ + /* This will enable module scanning using the I2C bus. */ + for (mppGroup = 0; mppGroup < 1; mppGroup++) { + mppVal = mvBoardMppGet(mppGroup); /* get pre-defined values */ + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + + /* MPP Init - scan attached modules. */ + mvBoardMppModulesScan(); + + /* Update MPP values after modules scan. */ + mvBoardUpdateMppAfterScan(); + + /* Read MPP config values from board level and write MPP options to HW */ + for (mppGroup = 0; mppGroup < MV_MPP_MAX_GROUP; mppGroup++) { + mppVal = mvBoardMppGet(mppGroup); /* get pre-defined values */ + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + + /* Update Board eth info after modules scan. */ + mvBoardUpdateEthAfterScan(); + + /* Update interfaces configuration based on above scan */ + if (MV_OK != mvCtrlSerdesPhyConfig()) + mvOsPrintf("mvCtrlEnvInit: Can't init some or all SERDES lanes\n"); + + mvOsDelay(10); + +#if defined(MV_INCLUDE_TDM) + mvCtrlTdmClkCtrlSet(); +#endif + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlMppRegGet - return reg address of mpp group +* +* DESCRIPTION: +* +* INPUT: +* mppGroup - MPP group. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - Register address. +* +*******************************************************************************/ +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) +{ + MV_U32 ret; + + if (mppGroup >= MV_MPP_MAX_GROUP) + mppGroup = 0; + + ret = MPP_CONTROL_REG(mppGroup); + + return ret; +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxIfGet(MV_VOID) +{ +#if defined(CONFIG_SYNO_ARMADA_ARCH) + MV_U32 boardId = mvBoardIdGet(); + + switch (boardId) { + case SYNO_DS213j_ID: + return 1; + case SYNO_US3_ID: + return 1; + case SYNO_RS214_ID: + return 2; + case SYNO_DS214se_ID: + return 1; + case SYNO_DS414slim_ID: + return 2; + default: + return MV_PEX_MAX_IF; + } +#else + return MV_PEX_MAX_IF; +#endif +} + + +/******************************************************************************* +* mvCtrlPexMaxUnitGet - Get Marvell controller number of PEX units. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX units. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxUnitGet(MV_VOID) +{ + return MV_PEX_MAX_UNIT; +} + +#endif + + +/******************************************************************************* +* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of etherent port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of etherent port. +* +*******************************************************************************/ +MV_U32 mvCtrlEthMaxPortGet(MV_VOID) +{ + return MV_ETH_MAX_PORTS; +} + + +/******************************************************************************* +* mvCtrlEthMaxCPUsGet - Get Marvell controller number of CPUs. +* +* DESCRIPTION: +* This function returns Marvell controller number of CPUs. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of CPUs. +* +*******************************************************************************/ +MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID) +{ + return 1; +} + + +#if defined(MV_INCLUDE_SATA) +/******************************************************************************* +* mvCtrlSataMaxPortGet - Get Marvell controller number of Sata ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of Sata ports. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of Sata ports. +* +*******************************************************************************/ +MV_U32 mvCtrlSataMaxPortGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + case MV_6W11_DEV_ID: + res = MV_SATA_MV6W11_CHAN; + break; + default: + res = MV_SATA_MAX_CHAN; + break; + } + return res; +} +#endif + +#if defined(MV_INCLUDE_XOR) +/******************************************************************************* +* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR channels. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxChanGet(MV_VOID) +{ + return MV_XOR_MAX_CHAN; +} + +/******************************************************************************* +* mvCtrlXorMaxUnitGet - Get Marvell controller number of XOR units. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR units. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxUnitGet(MV_VOID) +{ + return MV_XOR_MAX_UNIT; +} + +#endif + +#if defined(MV_INCLUDE_USB) +/******************************************************************************* +* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns number of Marvell USB controllers. +* +*******************************************************************************/ +MV_U32 mvCtrlUsbMaxGet(void) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + case MV_FPGA_DEV_ID: + res = 0; + break; + + default: + res = MV_MAX_USB_PORTS; + break; + } + + return res; +} +#endif + +#if defined(MV_INCLUDE_LEGACY_NAND) +/******************************************************************************* +* mvCtrlNandSupport - Return if this controller has integrated NAND flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if NAND is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlNandSupport(MV_VOID) +{ + return ARMADA_370_NAND; +} +#endif + +#if defined(MV_INCLUDE_SDIO) +/******************************************************************************* +* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if SDIO is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlSdioSupport(MV_VOID) +{ + return ARMADA_370_SDIO; +} +#endif + +/******************************************************************************* +* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if TDM is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlTdmSupport(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + case MV_6W11_DEV_ID: + case MV_6710_DEV_ID: + res = ARMADA_370_TDM; + break; + case MV_6707_DEV_ID: + default: + res = 0; + break; + } + return res; +} + +#if defined(MV_INCLUDE_TDM) +/******************************************************************************* +* mvCtrlTdmClkCtrlSet - Set TDM Clock Out Divider Control register +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvCtrlTdmClkCtrlSet(MV_VOID) +{ + MV_U32 pllCtrlReg, pcmClkFreq = TDM_FULL_DIV_8M; + +#if defined(MV_TDM_PCM_CLK_4MHZ) + pcmClkFreq = TDM_FULL_DIV_4M; +#elif defined(MV_TDM_PCM_CLK_2MHZ) + pcmClkFreq = TDM_FULL_DIV_2M; +#endif + pllCtrlReg = MV_REG_READ(TDM_PLL_CONTROL_REG); + pllCtrlReg = pllCtrlReg & ~(TDM_CLK_ENABLE_MASK | TDM_FULL_DIV_MASK); + pllCtrlReg |= (TDM_CLK_ENABLE_MASK | pcmClkFreq); + MV_REG_WRITE(TDM_PLL_CONTROL_REG, pllCtrlReg); +} + +/******************************************************************************* +* mvCtrlTdmMaxGet - Return the maximum number of TDM ports. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The number of TDM ports in device. +* +*******************************************************************************/ +MV_U32 mvCtrlTdmMaxGet(MV_VOID) +{ + return ARMADA_370_MAX_TDM_PORTS; +} + +/******************************************************************************* +* mvCtrlTdmTypeGet +* +* DESCRIPTION: +* Return the TDM unit type being compiled in. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The TDM unit type. +* +*******************************************************************************/ +MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID) +{ + return TDM_UNIT_2CH; +} + +/******************************************************************************* +* mvCtrlTdmUnitIrqGet +* +* DESCRIPTION: +* Return the TDM unit IRQ number depending on the TDM unit compilation +* options. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +******************************************************************************/ +MV_U32 mvCtrlTdmUnitIrqGet(MV_VOID) +{ + return MV_TDM_IRQ_NUM; +} + +#endif /* if defined(MV_INCLUDE_TDM) */ + +/******************************************************************************* +* mvCtrlAudioSupport - Return if this controller has integrated audio support. +* +* DESCRIPTION: +* None. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if Audio is supported and MV_FALSE otherwise. +* +*******************************************************************************/ +MV_U32 mvCtrlAudioSupport(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + case MV_6W11_DEV_ID: + res = MV_FALSE; + break; + default: + res = MV_TRUE; + break; + } + return res; +} + +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ + MV_U32 devId; + MV_U16 model = 0; + MV_U32 reg, reg2; + + /* if PEX0 clocks are disabled - enabled it to read */ + reg = MV_REG_READ(POWER_MNG_CTRL_REG); + if ((reg & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) { + reg2 = ((reg & ~PMC_PEXSTOPCLOCK_MASK(0)) | PMC_PEXSTOPCLOCK_EN(0)); + MV_REG_WRITE(POWER_MNG_CTRL_REG, reg2); + } + + devId = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_DEVICE_AND_VENDOR_ID)); + + /* Reset the original value of the PEX0 clock */ + if ((reg & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) + MV_REG_WRITE(POWER_MNG_CTRL_REG, reg); + + model = (MV_U16) ((devId >> 16) & 0xFFFF); + return model; +} + +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller device revision number +* +* DESCRIPTION: +* This function returns 8bit describing the device revision as defined +* in PCI Express Class Code and Revision ID Register. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 8bit desscribing Marvell controller revision number +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + MV_U8 revNum; +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID, 0); + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +#endif + revNum = (MV_U8) MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PCI_CLASS_CODE_AND_REVISION_ID)); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); +#endif + return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); +} + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlNameGet(char *pNameBuff) +{ + if (mvCtrlModelGet() == 0x6710) + mvOsSPrintf(pNameBuff, "%s6710", SOC_NAME_PREFIX); + else if (mvCtrlModelGet() == 0x6707) + mvOsSPrintf(pNameBuff, "%s6707", SOC_NAME_PREFIX); + else if (mvCtrlModelGet() == 0x6711) + mvOsSPrintf(pNameBuff, "%s6W11", SOC_NAME_PREFIX); + else + mvOsSPrintf(pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, mvCtrlModelGet(), mvCtrlRevGet()); + return MV_OK; +} + +/******************************************************************************* +* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision +* +* DESCRIPTION: +* This function returns 32bit value describing both Device ID and Revision +* as defined in PCI Express Device and Vendor ID Register and device revision +* as defined in PCI Express Class Code and Revision ID Register. + +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing both controller device ID and revision number +* +*******************************************************************************/ +MV_U32 mvCtrlModelRevGet(MV_VOID) +{ + return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); +} + +/******************************************************************************* +* mvCtrlModelRevNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) +{ + switch (mvCtrlModelRevGet()) { + case MV_6710_A1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6710_A1_NAME); + break; + + case MV_6710_A0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6710_A0_NAME); + break; + + case MV_6707_A1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6707_A1_NAME); + break; + + case MV_6707_A0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6707_A0_NAME); + break; + + case MV_6W11_A1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6W11_A1_NAME); + break; + + case MV_6W11_A0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6W11_A0_NAME); + break; + + default: + mvCtrlNameGet(pNameBuff); + break; + } + + return MV_OK; +} +MV_U32 gDevId = -1; +/******************************************************************************* +* mvCtrlDevFamilyIdGet - Get Device ID +* +* DESCRIPTION: +* This function returns Device ID. +* +* INPUT: +* ctrlModel. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board Device ID number, '-1' if Device ID is undefined. +* +*******************************************************************************/ +MV_U32 mvCtrlDevFamilyIdGet(MV_U16 ctrlModel) +{ + if (gDevId == -1) + { + switch (ctrlModel) { + case MV_6710_DEV_ID: + case MV_6W11_DEV_ID: + case MV_6707_DEV_ID: + gDevId=MV_67XX; + return gDevId; + break; + default: + return MV_ERROR; + } + } + else + return gDevId; +} + + +static const char *cntrlName[] = TARGETS_NAME_ARRAY; + +/******************************************************************************* +* mvCtrlTargetNameGet - Get Marvell controller target name +* +* DESCRIPTION: +* This function convert the trget enumeration to string. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Target name (const MV_8 *) +*******************************************************************************/ +const MV_8 *mvCtrlTargetNameGet(MV_TARGET target) +{ + if (target >= MAX_TARGETS) + return "target unknown"; + + return cntrlName[target]; +} + + +/******************************************************************************* +* mvCtrlPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvCtrlPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN win; + MV_U32 pexIf; + MV_U32 bar, winNum; + + for (pexIf = 0; pexIf < MV_PEX_MAX_IF; pexIf++) { + + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) + continue; + mvOsOutput("\n"); + mvOsOutput("PEX%d:\n", pexIf); + mvOsOutput("-----\n"); + + mvOsOutput("\nPex Bars \n\n"); + + for (bar = 0; bar < PEX_MAX_BARS; bar++) { + memset(&pexBar, 0, sizeof(MV_PEX_BAR)); + + mvOsOutput("%s ", pexBarNameGet(bar)); + + if (mvPexBarGet(pexIf, bar, &pexBar) == MV_OK) { + if (pexBar.enable) { + mvOsOutput("base %08x, ", pexBar.addrWin.baseLow); + if (pexBar.addrWin.size == 0) + mvOsOutput("size %3dGB ", 4); + else + mvSizePrint(pexBar.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + mvOsOutput("\nPex Decode Windows\n\n"); + + for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) { + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvPexTargetWinRead(pexIf, winNum, &win) == MV_OK) { + if (win.winInfo.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(mvCtrlTargetByWinInfoGet(&win.winInfo)), + win.winInfo.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.winInfo.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("default win - "); + + if (mvPexTargetWinRead(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("Expansion ROM - "); + + if (mvPexTargetWinRead(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + } +} + +/******************************************************************************* +* mvUnitAddrDecShow - Print the Unit's address decode map. +* +* DESCRIPTION: +* This is a generic function for printing the different unit's address +* decode map. +* +* INPUT: +* unit - The unit to print the address decode for. +* name - The unit's name. +* winGetFuncPtr - A pointer to the HAL's window get function. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void mvUnitAddrDecShow(MV_U8 numUnits, MV_UNIT_ID unitId, const char *name, MV_WIN_GET_FUNC_PTR winGetFuncPtr) +{ + MV_UNIT_WIN_INFO win; + MV_U32 unit, i; + + for (unit = 0; unit < numUnits; unit++) { + + if (MV_FALSE == mvCtrlPwrClckGet(unitId, unit)) + continue; + mvOsOutput("\n"); + mvOsOutput("%s %d:\n", name, unit); + mvOsOutput("----\n"); + + for (i = 0; i < 16; i++) { + memset(&win, 0, sizeof(MV_UNIT_WIN_INFO)); + + if (winGetFuncPtr(unit, i, &win) == MV_OK) { + mvOsOutput("win%d - ", i); + if (win.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(mvCtrlTargetByWinInfoGet(&win)), + win.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.addrWin.size); + } else + mvOsOutput("disable"); + + mvOsOutput("\n"); + } + } + } + return; +} + +/******************************************************************************* +* mvCtrlAddrDecShow - Print the Controller units address decode map. +* +* DESCRIPTION: +* This function the Controller units address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCtrlAddrDecShow(MV_VOID) +{ + mvCpuIfAddDecShow(); + mvAhbToMbusAddDecShow(); +#if defined(MV_INCLUDE_PEX) + mvCtrlPexAddrDecShow(); +#endif +#if defined(MV_INCLUDE_USB) + mvUnitAddrDecShow(mvCtrlUsbMaxGet(), USB_UNIT_ID, "USB", mvUsbWinRead); +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#if defined(MV_ETH_LEGACY) + mvUnitAddrDecShow(mvCtrlEthMaxPortGet(), ETH_GIG_UNIT_ID, "ETH", mvEthWinRead); +#else + mvUnitAddrDecShow(mvCtrlEthMaxPortGet(), ETH_GIG_UNIT_ID, "ETH", mvNetaWinRead); +#endif /* MV_ETH_LEGACY */ +#endif /* MV_INCLUDE_GIG_ETH */ + +#if defined(MV_INCLUDE_XOR) + mvUnitAddrDecShow(mvCtrlXorMaxUnitGet(), XOR_UNIT_ID, "XOR", mvXorTargetWinRead); +#endif +#if defined(MV_INCLUDE_SATA) + mvUnitAddrDecShow(mvCtrlSataMaxPortGet(), SATA_UNIT_ID, "Sata", mvSataWinRead); +#endif +} + +/******************************************************************************* +* ctrlSizeToReg - Extract size value for register assignment. +* +* DESCRIPTION: +* Address decode size parameter must be programed from LSB to MSB as +* sequence of 1's followed by sequence of 0's. The number of 1's +* specifies the size of the window in 64 KB granularity (e.g. a +* value of 0x00ff specifies 256x64k = 16 MB). +* This function extract the size value from the size parameter according +* to given aligment paramter. For example for size 0x1000000 (16MB) and +* aligment 0x10000 (64KB) the function will return 0x00FF. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size register value correspond to size parameter. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) +{ + MV_U32 retVal; + + /* Check size parameter alignment */ + if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); + return -1; + } + + /* Take out the "alignment" portion out of the size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + /* and size is 0x1000000 (16MB) for example */ + while (alignment & 1) { /* Check that alignmet LSB is set */ + size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ + alignment = (alignment >> 1); + } + + /* If after the alignment first '0' was met we still have '1' in */ + /* it then aligment is invalid (not power of 2) */ + if (alignment) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", (MV_U32) alignment)); + return -1; + } + + /* Now the size is shifted right according to aligment: 0x0100 */ + size--; /* Now the size is a sequance of '1': 0x00ff */ + retVal = size; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + while (size & 1) /* Check that LSB is set */ + size = (size >> 1); /* If LSB is set, move one bit to the right */ + + if (size) { /* Sequance of 1's is over. Check that we have no other 1's */ + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", size)); + return -1; + } + return retVal; +} + +/******************************************************************************* +* ctrlRegToSize - Extract size value from register value. +* +* DESCRIPTION: +* This function extract a size value from the register size parameter +* according to given aligment paramter. For example for register size +* value 0xff and aligment 0x10000 the function will return 0x01000000. +* +* INPUT: +* regSize - Size as in register format. See ctrlSizeToReg. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) +{ + MV_U32 temp; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ + + while (temp & 1) /* Check that LSB is set */ + temp = (temp >> 1); /* If LSB is set, move one bit to the right */ + + if (temp) { /* Sequance of 1's is over. Check that we have no other 1's */ + DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", regSize)); + return -1; + } + + /* Check that aligment is a power of two */ + temp = alignment - 1; /* Now the alignmet is a sequance of '1' (0xffff) */ + + while (temp & 1) /* Check that alignmet LSB is set */ + temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ + + /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ + /* then 'temp' is invalid (not power of 2) */ + if (temp) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", alignment)); + return -1; + } + + regSize++; /* Now the size is 0x0100 */ + + /* Add in the "alignment" portion to the register size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + + while (alignment & 1) { /* Check that alignmet LSB is set */ + regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ + alignment = (alignment >> 1); + } + + return regSize; +} + +/******************************************************************************* +* ctrlSizeRegRoundUp - Round up given size +* +* DESCRIPTION: +* This function round up a given size to a size that fits the +* restrictions of size format given an aligment parameter. +* to given aligment paramter. For example for size parameter 0xa1000 and +* aligment 0x1000 the function will return 0xFF000. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size value correspond to size in register. +*******************************************************************************/ +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) +{ + MV_U32 msbBit = 0; + MV_U32 retSize; + + /* Check if size parameter is already comply with restriction */ + if (!(-1 == ctrlSizeToReg(size, alignment))) + return size; + + while (size) { + size = (size >> 1); + msbBit++; + } + + retSize = (1 << msbBit); + + if (retSize < alignment) + return alignment; + else + return retSize; +} + +/******************************************************************************* +* mvCtrlIsBootFromNOR +* +* DESCRIPTION: +* Check if device is configured to boot from NOR flash according to the +* SAR registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NAND_NOR_BOOT_16BIT If boot device is 16-bit wide. +* MV_NAND_NOR_BOOT_8BIT If boot device is 8-bit wide. +* 0 otherwise. +*******************************************************************************/ +MV_U32 mvCtrlIsBootFromNOR(MV_VOID) +{ + MV_U32 satr; + MV_U32 satrList[] = MSAR_BOOT_NOR_LIST; + MV_U32 i = 0; + + satr = (MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS; + + while (satrList[i] != 0xFFFFFFFF) { + if (satrList[i] == satr) { + if (satr & 0x1) + return MV_NAND_NOR_BOOT_16BIT; + else + return MV_NAND_NOR_BOOT_8BIT; + } + i++; + } + + return 0; +} + +/******************************************************************************* +* mvCtrlIsBootFromSPI +* +* DESCRIPTION: +* Check if device is configured to boot from SPI flash according to the +* SAR registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 0 if device is not configured to boot from SPI. +* MV_SPI_LOW_MPPS if configured to boot from low MPPs [36:33]. +* MV_SPI_HIGH_MPPS if configured to boot from high MPPs [65:63, 32]. +*******************************************************************************/ +MV_U32 mvCtrlIsBootFromSPI(MV_VOID) +{ + MV_U32 satr; + MV_U32 satrLowList[] = MSAR_BOOT_SPI_LOW_LIST; + MV_U32 satrHighList[] = MSAR_BOOT_SPI_HIGH_LIST; + MV_U32 i; + + satr = (MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS; + + i = 0; + while (satrLowList[i] != 0xFFFFFFFF) { + if (satrLowList[i] == satr) + return MV_SPI_LOW_MPPS; + i++; + } + + i = 0; + while (satrHighList[i] != 0xFFFFFFFF) { + if (satrHighList[i] == satr) + return MV_SPI_HIGH_MPPS; + i++; + } + + return 0; +} + + +/******************************************************************************* +* mvCtrlIsBootFromNAND +* +* DESCRIPTION: +* Check if device is confiogured to boot from NAND flash according to the SAR +* registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NAND_NOR_BOOT_16BIT If boot device is 16-bit wide. +* MV_NAND_NOR_BOOT_8BIT If boot device is 8-bit wide. +* 0 otherwise. +*******************************************************************************/ +MV_U32 mvCtrlIsBootFromNAND(MV_VOID) +{ + MV_U32 satr; + MV_U32 satrList[] = MSAR_BOOT_NAND_LIST; + MV_U32 i = 0; + + satr = (MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS; + + while (satrList[i] != 0xFFFFFFFF) { + if (satrList[i] == satr) { + if (satr < 0x20) + return MV_NAND_NOR_BOOT_8BIT; + else + return MV_NAND_NOR_BOOT_16BIT; + } + i++; + } + + return 0; +} + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +/******************************************************************************* +* mvCtrlPwrClckSet - Set Power State for specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_CESASTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_CESASTOPCLOCK_MASK); + + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUSTOPCLOCK_MASK); + + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_2CH_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + + break; +#endif + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrClckGet - Get Power State of specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); + MV_BOOL state = MV_TRUE; + + /* Clock gating is not supported on FPGA */ + if (mvCtrlModelGet() == MV_FPGA_DEV_ID) + return MV_TRUE; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if ((reg & PMC_PEXSTOPCLOCK_MASK(index)) == PMC_PEXSTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if ((reg & PMC_CESASTOPCLOCK_MASK) == PMC_CESASTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if ((reg & PMC_USBSTOPCLOCK_MASK(index)) == PMC_USBSTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if ((reg & PMC_SDIOSTOPCLOCK_MASK) == PMC_SDIOSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_2CH_UNIT_ID: + if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if ((reg & PMC_AUSTOPCLOCK_MASK) == PMC_AUSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + + return state; +} + +/******************************************************************************* +* mvCtrlPwrMemSet - Set Power State for memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX), PMC_PEXSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX), PMC_PEXSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE), PMC_GESTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE), PMC_GESTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA), PMC_SATASTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA), PMC_SATASTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA), PMC_CESASTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA), PMC_CESASTOPMEM_MASK); + + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB), PMC_USBSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB), PMC_USBSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR), PMC_XORSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR), PMC_XORSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_AUDIO), PMC_AUSTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_AUDIO), PMC_AUSTOPMEM_MASK); + break; +#endif + + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrMemGet - Get Power State of memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg; + MV_BOOL state = MV_TRUE; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX)); + if ((reg & PMC_PEXSTOPMEM_MASK(index)) == PMC_PEXSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE)); + if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA)); + if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA)); + if ((reg & PMC_CESASTOPMEM_MASK) == PMC_CESASTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB)); + if ((reg & PMC_USBSTOPMEM_MASK(index)) == PMC_USBSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR)); + if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR)); + if ((reg & PMC_AUSTOPMEM_MASK) == PMC_AUSTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif + + default: + state = MV_TRUE; + break; + } + + return state; +} +#else +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + return; +} + +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + return MV_TRUE; +} +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +/******************************************************************************* +* mvCtrlSerdesMaxLinesGet - Get Marvell controller number of SERDES lines. +* +* DESCRIPTION: +* This function returns Marvell controller number of SERDES lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX units. +* +*******************************************************************************/ +MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID) +{ + + switch (mvCtrlModelGet()) { + case MV_FPGA_DEV_ID: + return 0; + default: + return MV_SERDES_MAX_LANES; + } +} + + +MV_U32 mvCtrlDDRBudWidth(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(0x1400); + + return (reg & 0x8000) ? 32 : 16; +} +MV_BOOL mvCtrlDDRThruXbar(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(0x20184); + + return (reg & 0x1) ? MV_FALSE : MV_TRUE; +} + + +static const MV_U8 serdesCfg[][5] = SERDES_CFG; + +/******************************************************************************* +* mvCtrlSerdesPhyConfig +* +* DESCRIPTION: +* Configure Serdes MUX and init PHYs connected to SERDES lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Status +* +*******************************************************************************/ +/* #define DB(x) x */ +MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID) +{ + MV_U32 socCtrlReg; + MV_U8 pexUnit; + MV_U32 pexIfNum = mvCtrlPexMaxIfGet(); + MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet(); + + memset(boardPexInfo, 0, sizeof(MV_BOARD_PEX_INFO)); + + socCtrlReg = MV_REG_READ(SOC_CTRL_REG); + + + for (pexUnit = 0; pexUnit < pexIfNum; pexUnit++) { + if ((socCtrlReg & (1<< pexUnit)) == 0) + boardPexInfo->pexUnitCfg[pexUnit] = PEX_BUS_DISABLED; + else + boardPexInfo->pexUnitCfg[pexUnit] = PEX_BUS_MODE_X1; + } + boardPexInfo->boardPexIfNum = pexIfNum; + return MV_OK; +} + diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvLib.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvLib.h new file mode 100755 index 000000000..09436df47 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvLib.h @@ -0,0 +1,245 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvLibh +#define __INCmvCtrlEnvLibh + +/* includes */ +#include "mvSysHwConfig.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* 0 for Auto scan mode, 1 for manual. */ +#define MV_INTERNAL_SWITCH_SMI_SCAN_MODE 0 + +#define MV_SPI_LOW_MPPS 2 +#define MV_SPI_HIGH_MPPS 3 + +#define MV_NAND_NOR_BOOT_8BIT 2 +#define MV_NAND_NOR_BOOT_16BIT 3 + +#define SRDS_MOD_NUM 9 +#define SRDS_MOD_SHIFT 4 +#define SRDS_AUTO_CFG 0 + +/* typedefs */ +typedef MV_STATUS (*MV_WIN_GET_FUNC_PTR)(MV_U32, MV_U32, MV_UNIT_WIN_INFO*); + +/* This enumerator describes the possible HW cache coherency policies the */ +/* controllers supports. */ +typedef enum _mvCachePolicy { + NO_COHERENCY, /* No HW cache coherency support */ + WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ + WB_COHERENCY /* HW cache coherency supported in Write Back policy */ +} MV_CACHE_POLICY; + +/* The swapping is referred to a 64-bit words (as this is the controller */ +/* internal data path width). This enumerator describes the possible */ +/* data swap types. Below is an example of the data 0x0011223344556677 */ +typedef enum _mvSwapType { + MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ + MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ + MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ + MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ + SWAP_TYPE_MAX /* Delimiter for this enumerator */ +} MV_SWAP_TYPE; + +typedef enum { + LANE0 = 0x1, + LANE1 = 0x2, + LANE2 = 0x4, + LANE3 = 0x8 +} MV_SERDES_LANES; + +typedef enum { + SRDS_MOD_AUTO = 0x0, + SRDS_MOD_PCIE0_LANE0 = 0x001, + SRDS_MOD_PCIE1_LANE1 = 0x002, + SRDS_MOD_SATA0_LANE0 = 0x004, + SRDS_MOD_SATA0_LANE2 = 0x008, + SRDS_MOD_SATA1_LANE3 = 0x010, + SRDS_MOD_SGMII0_LANE1 = 0x020, + SRDS_MOD_SGMII0_LANE2 = 0x040, + SRDS_MOD_SGMII1_LANE0 = 0x080, + SRDS_MOD_SGMII1_LANE3 = 0x100, + SRDS_MOD_ALL = 0x1FF, + SRDS_MOD_ILLEGAL = 0xFFFFFFFF +} MV_SERDES_MODE; + +typedef enum { + SRDS_SPEED_AUTO = 0x0, + SRDS_SPEED_PCIE0_LANE0 = 0x001, + SRDS_SPEED_PCIE1_LANE1 = 0x002, + SRDS_SPEED_SATA0_LANE0 = 0x004, + SRDS_SPEED_SATA0_LANE2 = 0x008, + SRDS_SPEED_SATA1_LANE3 = 0x010, + SRDS_SPEED_SGMII0_LANE1 = 0x020, + SRDS_SPEED_SGMII0_LANE2 = 0x040, + SRDS_SPEED_SGMII1_LANE0 = 0x080, + SRDS_SPEED_SGMII1_LANE3 = 0x100, + SRDS_SPEED_ALL = 0x1FF, + SRDS_SPEED_ILLEGAL = 0xFFFFFFFF +} MV_SERDES_LANE_SPEED; + +typedef enum { + SRDS_SPEED_LOW = 0, + SRDS_SPEED_HIGH = 1 +} MV_SERDES_SPEED; + +typedef enum { + SERDES_UNIT_UNCONNECTED = 0x0, + SERDES_UNIT_PEX = 0x1, + SERDES_UNIT_SATA = 0x2, + SERDES_UNIT_SGMII = 0x3, + SERDES_UNIT_LAST +} MV_SERDES_UNIT_INDX; + +typedef enum { + PEX_BUS_DISABLED = 0, + PEX_BUS_MODE_X1 = 1 +} MV_PEX_UNIT_CFG; + +typedef struct { + MV_U32 serdesMode; /* Bitmap of MV_SERDES_MODE - one bit per SERDES line */ + MV_U32 serdesSpeed; /* Bitmap of SRDS_LANE_SPEED - one bit per SERDES line */ +} MV_SERDES_CFG; + +typedef struct { + MV_U32 serdesMode; + /* register setup for MV_SERDES_MODE - one nibble per SERDES line (serdes register format) */ + MV_U32 serdesSpeed; /* Bitmap of SRDS_LANE_SPEED - one bit per SERDES line */ +} MV_SERDES_REG_CFG; + + + +MV_U32 mvCtrlGetCpuNum(MV_VOID); +MV_BOOL mvCtrlIsValidSatR(MV_VOID); +void mvCtrlSetSkipSerdesPhyConfig(MV_VOID); +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCtrlPexMaxIfGet(MV_VOID); +MV_U32 mvCtrlPexMaxUnitGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCtrlPciMaxIfGet(MV_VOID); +#else +#define mvCtrlPciIfMaxIfGet() (mvCtrlPexMaxIfGet()) +#endif +MV_U32 mvCtrlEthMaxPortGet(MV_VOID); +MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID); +#if defined(MV_INCLUDE_SATA) +MV_U32 mvCtrlSataMaxPortGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_XOR) +MV_U32 mvCtrlXorMaxChanGet(MV_VOID); +MV_U32 mvCtrlXorMaxUnitGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_USB) +MV_U32 mvCtrlUsbMaxGet(void); +#endif +#if defined(MV_INCLUDE_LEGACY_NAND) +MV_U32 mvCtrlNandSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_SDIO) +MV_U32 mvCtrlSdioSupport(MV_VOID); +#endif +MV_U32 mvCtrlTdmSupport(MV_VOID); +#if defined(MV_INCLUDE_TDM) +MV_U32 mvCtrlTdmMaxGet(MV_VOID); +MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID); +MV_U32 mvCtrlTdmUnitIrqGet(MV_VOID); +#endif /* if defined(MV_INCLUDE_TDM) */ +MV_U32 mvCtrlDevFamilyIdGet(MV_U16 ctrlModel); +MV_U16 mvCtrlModelGet(MV_VOID); +MV_U8 mvCtrlRevGet(MV_VOID); +MV_STATUS mvCtrlNameGet(char *pNameBuff); +MV_U32 mvCtrlModelRevGet(MV_VOID); +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); +const MV_8 *mvCtrlTargetNameGet(MV_TARGET target); +MV_VOID mvCtrlAddrDecShow(MV_VOID); +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); +MV_U32 mvCtrlIsBootFromNOR(MV_VOID); +MV_U32 mvCtrlIsBootFromSPI(MV_VOID); +MV_U32 mvCtrlIsBootFromNAND(MV_VOID); +MV_U32 mvCtrlAudioSupport(MV_VOID); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ +MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID); +MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID); +MV_U32 mvCtrlDDRBudWidth(MV_VOID); +MV_BOOL mvCtrlDDRThruXbar(MV_VOID); + +#endif /* __INCmvCtrlEnvLibh */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvRegs.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvRegs.h new file mode 100755 index 000000000..6b49f38e0 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvRegs.h @@ -0,0 +1,504 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvRegsh +#define __INCmvCtrlEnvRegsh + +#include "mvCtrlEnvSpec.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PEX0_MEM + +/* Controller revision info */ +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +/* Controler environment registers offsets */ +#define MV_TDM_IRQ_NUM 56 + + +/* Coherent Fabric Control and Status */ +#define MV_COHERENCY_FABRIC_CTRL_REG (MV_COHERENCY_FABRIC_OFFSET + 0x0) +#define MV_COHERENCY_FABRIC_CFG_REG (MV_COHERENCY_FABRIC_OFFSET + 0x4) + +/* CIB registers offsets */ +#define MV_CIB_CTRL_CFG_REG (MV_COHERENCY_FABRIC_OFFSET + 0x80) + +/* PMU_NFABRIC PMU_NFABRIC PMU_UNIT_SERVICE Units */ +#define MV_L2C_NFABRIC_PM_CTRL_CFG_REG (MV_PMU_NFABRIC_UNIT_SERV_OFFSET + 0x4) +#define MV_L2C_NFABRIC_PM_CTRL_CFG_PWR_DOWN (1 << 20) + +#define MV_L2C_NFABRIC_PWR_DOWN_FLOW_CTRL_REG (MV_PMU_NFABRIC_UNIT_SERV_OFFSET + 0x8) + +#define PM_CONTROL_AND_CONFIG_REG(cpu) (MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) + 0x4) +#define PM_CONTROL_AND_CONFIG_PWDDN_REQ (1 << 16) +#define PM_CONTROL_AND_CONFIG_L2_PWDDN (1 << 20) + +#define PM_STATUS_AND_MASK_REG(cpu) (MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) + 0xc) +#define PM_STATUS_AND_MASK_CPU_IDLE_WAIT (1 << 16) +#define PM_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT (1 << 17) +#define PM_STATUS_AND_MASK_IRQ_WAKEUP (1 << 20) +#define PM_STATUS_AND_MASK_FIQ_WAKEUP (1 << 21) +#define PM_STATUS_AND_MASK_DBG_WAKEUP (1 << 22) +#define PM_STATUS_AND_MASK_IRQ_MASK (1 << 24) +#define PM_STATUS_AND_MASK_FIQ_MASK (1 << 25) + +#define PM_CPU_BOOT_ADDR_REDIRECT(cpu) (MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) + 0x24) + +/* Power Management Memory Power Down Registers 1 - 6 */ +#define POWER_MNG_MEM_CTRL_REG(num) (((num) < 6) ? (0x18210 + ((num) - 2) * 4) : 0x18228) + +#define PMC_MCR_NUM_PEX 2 +#define PMC_MCR_NUM_CFU 3 +#define PMC_MCR_NUM_L2 3 +#define PMC_MCR_NUM_CIB 3 +#define PMC_MCR_NUM_CPU 3 +#define PMC_MCR_NUM_NCS 3 +#define PMC_MCR_NUM_DUNIT 3 +#define PMC_MCR_NUM_NF 4 +#define PMC_MCR_NUM_XOR 4 +#define PMC_MCR_NUM_DEVB 4 +#define PMC_MCR_NUM_CESA 4 +#define PMC_MCR_NUM_USB 4 +#define PMC_MCR_NUM_SATA 5 +#define PMC_MCR_NUM_AUDIO 5 +#define PMC_MCR_NUM_GE 5 +#define PMC_MCR_NUM_COMM 6 +#define PMC_MCR_NUM_PMU 6 + + +/* #2 */ +#define PMC_PEXSTOPMEM_OFFS(port) (((port) == 0) ? 0 : 12) +#define PMC_PEXSTOPMEM_MASK(port) (7 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_EN(port) (0 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_STOP(port) (1 << PMC_PEXSTOPMEM_OFFS(port)) + +#define PMC_CPUSTOPMEM_OFFS(id) 21 +#define PMC_CPUSTOPMEM_MASK(id) (7 << PMC_CPUSTOPMEM_OFFS(id)) +#define PMC_CPUSTOPMEM_EN(id) (0 << PMC_CPUSTOPMEM_OFFS(id)) +#define PMC_CPUSTOPMEM_STOP(id) (1 << PMC_CPUSTOPMEM_OFFS(id)) + +/* #3 */ +#define PMC_NCSSTOPMEM_OFFS 24 +#define PMC_NCSSTOPMEM_MASK (7 << PMC_NCSSTOPMEM_OFFS) +#define PMC_NCSSTOPMEM_EN (0 << PMC_NCSSTOPMEM_OFFS) +#define PMC_NCSSTOPMEM_STOP (1 << PMC_NCSSTOPMEM_OFFS) + +#define PMC_CFUSTOPMEM_OFFS 21 +#define PMC_CFUSTOPMEM_MASK (7 << PMC_CFUSTOPMEM_OFFS) +#define PMC_CFUSTOPMEM_EN (0 << PMC_CFUSTOPMEM_OFFS) +#define PMC_CFUSTOPMEM_STOP (1 << PMC_CFUSTOPMEM_OFFS) + +#define PMC_L2STOPMEM_OFFS 18 +#define PMC_L2STOPMEM_MASK (7 << PMC_L2STOPMEM_OFFS) +#define PMC_L2STOPMEM_EN (0 << PMC_L2STOPMEM_OFFS) +#define PMC_L2STOPMEM_STOP (1 << PMC_L2STOPMEM_OFFS) + +#define PMC_CIBSTOPMEM_OFFS 15 +#define PMC_CIBSTOPMEM_MASK (7 << PMC_CIBSTOPMEM_OFFS) +#define PMC_CIBSTOPMEM_EN (0 << PMC_CIBSTOPMEM_OFFS) +#define PMC_CIBSTOPMEM_STOP (1 << PMC_CIBSTOPMEM_OFFS) + +#define PMC_DUNITSTOPMEM_OFFS 12 +#define PMC_DUNITSTOPMEM_MASK (7 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) + +/* #4 */ +#define PMC_NFSTOPMEM_OFFS 27 +#define PMC_NFSTOPMEM_MASK (7 << PMC_NFSTOPMEM_OFFS) +#define PMC_NFSTOPMEM_EN (0 << PMC_NFSTOPMEM_OFFS) +#define PMC_NFSTOPMEM_STOP (1 << PMC_NFSTOPMEM_OFFS) + +#define PMC_XORSTOPMEM_OFFS(port) (((port) == 0) ? 15 : 24) +#define PMC_XORSTOPMEM_MASK(port) (7 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) + +#define PMC_DEVBSTOPMEM_OFFS 21 +#define PMC_DEVBSTOPMEM_MASK (7 << PMC_DEVBSTOPMEM_OFFS) +#define PMC_DEVBSTOPMEM_EN (0 << PMC_DEVBSTOPMEM_OFFS) +#define PMC_DEVBSTOPMEM_STOP (1 << PMC_DEVBSTOPMEM_OFFS) + +#define PMC_CESASTOPMEM_OFFS 18 +#define PMC_CESASTOPMEM_MASK (7 << PMC_CESASTOPMEM_OFFS) +#define PMC_CESASTOPMEM_EN (0 << PMC_CESASTOPMEM_OFFS) +#define PMC_CESASTOPMEM_STOP (1 << PMC_CESASTOPMEM_OFFS) + +#define PMC_USBSTOPMEM_OFFS(port) (((port) == 0) ? 3 : 0) +#define PMC_USBSTOPMEM_MASK(port) (7 << PMC_USBSTOPMEM_OFFS(port)) +#define PMC_USBSTOPMEM_EN(port) (0 << PMC_USBSTOPMEM_OFFS(port)) +#define PMC_USBSTOPMEM_STOP(port) (1 << PMC_USBSTOPMEM_OFFS(port)) + +/* #5 */ +#define PMC_SATASTOPMEM_OFFS(port) ((port) == 0 ? 18 : 24) +#define PMC_SATASTOPMEM_MASK(port) (0x3F << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_STOP(port) (9 << PMC_SATASTOPMEM_OFFS(port)) + +#define PMC_AUSTOPMEM_OFFS 12 +#define PMC_AUSTOPMEM_MASK (7 << PMC_AUSTOPMEM_OFFS) +#define PMC_AUSTOPMEM_EN (0 << PMC_AUSTOPMEM_OFFS) +#define PMC_AUSTOPMEM_STOP (1 << PMC_AUSTOPMEM_OFFS) + +#define PMC_GESTOPMEM_OFFS(port) (((port) == 0) ? 9 : 6) +#define PMC_GESTOPMEM_MASK(port) (7 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) + +/* #6 */ +#define PMC_COMMSTOPMEM_OFFS 4 +#define PMC_COMMSTOPMEM_MASK (7 << PMC_COMMSTOPMEM_OFFS) +#define PMC_COMMSTOPMEM_EN (0 << PMC_COMMSTOPMEM_OFFS) +#define PMC_COMMSTOPMEM_STOP (1 << PMC_COMMSTOPMEM_OFFS) + +#define PMC_PMUSTOPMEM_OFFS 0 +#define PMC_PMUSTOPMEM_MASK (7 << PMC_PMUSTOPMEM_OFFS) +#define PMC_PMUSTOPMEM_EN (0 << PMC_PMUSTOPMEM_OFFS) +#define PMC_PMUSTOPMEM_STOP (1 << PMC_PMUSTOPMEM_OFFS) + + +/* Power Management Clock Gating Control Register */ +#define POWER_MNG_CTRL_REG 0x18220 + +#define PMC_SATASTOPCLOCK_OFFS(ch) (ch == 0 ? 14 : 29) +#define PMC_SATASTOPCLOCK_MASK(ch) (3 << PMC_SATASTOPCLOCK_OFFS(ch)) +#define PMC_SATASTOPCLOCK_EN(ch) (3 << PMC_SATASTOPCLOCK_OFFS(ch)) +#define PMC_SATASTOPCLOCK_STOP(ch) (0 << PMC_SATASTOPCLOCK_OFFS(ch)) + +#define PMC_DDRSTOPCLOCK_OFFS 28 +#define PMC_DDRSTOPCLOCK_MASK (1 << PMC_DDRSTOPCLOCK_OFFS) +#define PMC_DDRSTOPCLOCK_EN (1 << PMC_DDRSTOPCLOCK_OFFS) +#define PMC_DDRSTOPCLOCK_STOP (0 << PMC_DDRSTOPCLOCK_OFFS) + +#define PMC_TDMSTOPCLOCK_OFFS 25 +#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) + +#define PMC_RUNITSTOPCLOCK_OFFS 24 +#define PMC_RUNITSTOPCLOCK_MASK (1 << PMC_RUNITSTOPCLOCK_OFFS) +#define PMC_RUNITSTOPCLOCK_EN (1 << PMC_RUNITSTOPCLOCK_OFFS) +#define PMC_RUNITSTOPCLOCK_STOP (0 << PMC_RUNITSTOPCLOCK_OFFS) + +#define PMC_CESASTOPCLOCK_OFFS 23 +#define PMC_CESASTOPCLOCK_MASK (1 << PMC_CESASTOPCLOCK_OFFS) +#define PMC_CESASTOPCLOCK_EN (1 << PMC_CESASTOPCLOCK_OFFS) +#define PMC_CESASTOPCLOCK_STOP (0 << PMC_CESASTOPCLOCK_OFFS) + +#define PMC_XORSTOPCLOCK_OFFS 22 +#define PMC_XORSTOPCLOCK_MASK (1 << PMC_XORSTOPCLOCK_OFFS) +#define PMC_XORSTOPCLOCK_EN (1 << PMC_XORSTOPCLOCK_OFFS) +#define PMC_XORSTOPCLOCK_STOP (0 << PMC_XORSTOPCLOCK_OFFS) + +#define PMC_USBSTOPCLOCK_OFFS(port) (18 + (port)) +#define PMC_USBSTOPCLOCK_MASK(port) (1 << PMC_USBSTOPCLOCK_OFFS(port)) +#define PMC_USBSTOPCLOCK_EN(port) (1 << PMC_USBSTOPCLOCK_OFFS(port)) +#define PMC_USBSTOPCLOCK_STOP(port) (0 << PMC_USBSTOPCLOCK_OFFS(port)) + +#define PMC_SDIOSTOPCLOCK_OFFS 17 +#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) + +#define PMC_PEXSTOPCLOCK_OFFS(port) ((port == 0) ? 5 : 9) +#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port)) + +#define PMC_GESTOPCLOCK_OFFS(port) (4 - (port)) +#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) + +#define PMC_AUSTOPCLOCK_OFFS (0) +#define PMC_AUSTOPCLOCK_MASK (1 << PMC_AUSTOPCLOCK_OFFS) +#define PMC_AUSTOPCLOCK_EN (1 << PMC_AUSTOPCLOCK_OFFS) +#define PMC_AUSTOPCLOCK_STOP (0 << PMC_AUSTOPCLOCK_OFFS) + + +#define SATA_IMP_TX_SSC_CTRL_REG(port) (MV_SATA_REGS_BASE + 0x2810 + (port)*0x2000) +#define SATA_GEN_1_SET_0_REG(port) (MV_SATA_REGS_BASE + 0x2834 + (port)*0x2000) +#define SATA_GEN_1_SET_1_REG(port) (MV_SATA_REGS_BASE + 0x2838 + (port)*0x2000) +#define SATA_GEN_2_SET_0_REG(port) (MV_SATA_REGS_BASE + 0x283C + (port)*0x2000) +#define SATA_GEN_2_SET_1_REG(port) (MV_SATA_REGS_BASE + 0x2840 + (port)*0x2000) + +#define SATA_PWR_PLL_CTRL_REG(port) (MV_SATA_REGS_BASE + 0x2804 + (port)*0x2000) +#define SATA_DIG_LP_ENA_REG(port) (MV_SATA_REGS_BASE + 0x288C + (port)*0x2000) +#define SATA_REF_CLK_SEL_REG(port) (MV_SATA_REGS_BASE + 0x2918 + (port)*0x2000) +#define SATA_PHY_CONTROL_REGISTER(port) (MV_SATA_REGS_BASE + 0x2920 + (port)*0x2000) +#define SATA_LP_PHY_EXT_CTRL_REG(port) (MV_SATA_REGS_BASE + 0x2058 + (port)*0x2000) +#define SATA_LP_PHY_EXT_STAT_REG(port) (MV_SATA_REGS_BASE + 0x205C + (port)*0x2000) + +#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_SGMII_PHY_REGS_BASE(port) + 0xE04) +#define SGMII_GEN_1_SET_REG(port) (MV_ETH_SGMII_PHY_REGS_BASE(port) + 0xE34) +#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_SGMII_PHY_REGS_BASE(port) + 0xE8C) +#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_SGMII_PHY_REGS_BASE(port) + 0xF18) +#define SGMII_PHY_CTRL_REG(port) (MV_ETH_SGMII_PHY_REGS_BASE(port) + 0xF20) +#define SGMII_SERDES_CFG_REG(port) (MV_ETH_SGMII_PHY_REGS_BASE(port) + 0x4A0) +#define SGMII_SERDES_STAT_REG(port) (MV_ETH_SGMII_PHY_REGS_BASE(port) + 0x4A4) + +#define SERDES_LINE_MUX_REG_0_3 0x18270 + +/* TDM PLL Control Register */ +#define TDM_PLL_CONTROL_REG 0x18770 +#define TDM_CLK_ENABLE_OFFS 16 +#define TDM_CLK_ENABLE_MASK (1 << TDM_CLK_ENABLE_OFFS) +#define TDM_FULL_DIV_OFFS 0 +#define TDM_FULL_DIV_MASK (0x1fff << TDM_FULL_DIV_OFFS) +#define TDM_FULL_DIV_8M (0xB1 << TDM_FULL_DIV_OFFS) +#define TDM_FULL_DIV_4M (0x162 << TDM_FULL_DIV_OFFS) +#define TDM_FULL_DIV_2M (0x2C4 << TDM_FULL_DIV_OFFS) + +/* Thermal Sensor Registers */ +#define TSEN_STATUS_REG 0x18300 +#define TSEN_STATUS_TEMP_OUT_OFFSET 10 +#define TSEN_STATUS_TEMP_OUT_MASK (0x1FF << TSEN_STATUS_TEMP_OUT_OFFSET) + +#define TSEN_CONF_REG 0x18304 +#define TSEN_CONF_START_CAL_MASK (0x1 << 25) +#define TSEN_CONF_OTF_CALIB_MASK (0x1 << 30) +#define TSEN_CONF_REF_CAL_MASK (0x1FF << 11) +#define TSEN_CONF_SOFT_RESET_MASK (0x1 << 1) +#define TSEN_CONF_START_CALIB_MASK (0x1 << 25) + + +/* Controler environment registers offsets */ +#define GEN_PURP_RES_1_REG 0x182F4 +#define GEN_PURP_RES_2_REG 0x182F8 + +#define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) + +/* Sample at Reset */ +#define MPP_SAMPLE_AT_RESET (0x18230) + +/* SYSRSTn Length Counter */ +#define SYSRST_LENGTH_COUNTER_REG 0x18250 +#define SLCR_COUNT_OFFS 0 +#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) +#define SLCR_CLR_OFFS 31 +#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) + +/* Device ID */ +#define CHIP_BOND_REG 0x18238 +#define PCKG_OPT_MASK 0x3 + +#define MPP_OUTPUT_DRIVE_REG 0x184E4 +#define MPP_GE_A_OUTPUT_DRIVE_OFFS 6 +#define MPP_GE_A_1_8_OUTPUT_DRIVE (0x1 << MPP_GE_A_OUTPUT_DRIVE_OFFS) +#define MPP_GE_A_2_5_OUTPUT_DRIVE (0x2 << MPP_GE_A_OUTPUT_DRIVE_OFFS) +#define MPP_GE_B_OUTPUT_DRIVE_OFFS 14 +#define MPP_GE_B_1_8_OUTPUT_DRIVE (0x1 << MPP_GE_B_OUTPUT_DRIVE_OFFS) +#define MPP_GE_B_2_5_OUTPUT_DRIVE (0x2 << MPP_GE_B_OUTPUT_DRIVE_OFFS) + +#define MSAR_BOOT_MODE_OFFS 1 +#define MSAR_BOOT_MODE_MASK (0x3F << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_NOR_LIST {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, \ + 0x3A, 0x3B, 0xFFFFFFFF} +#define MSAR_BOOT_SPI_LOW_LIST {0x0, 0x1, 0xFFFFFFFF} +#define MSAR_BOOT_SPI_HIGH_LIST {0x10, 0x14, 0xFFFFFFFF} +#define MSAR_BOOT_NAND_LIST {0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF, 0x1A, 0x1B, 0x1C, \ + 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, \ + 0x27, 0x29, 0x2A, 0x2B, 0x2D, 0x2E, 0x2F, 0xFFFFFFFF} + + +#define MSAR_TCLK_OFFS 20 +#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS) + +/* Extract CPU, L2, DDR clocks SAR value from +** SAR bits 24-27 +*/ +#define MSAR_CPU_CLK_IDX(sar0) (((sar0) >> 11) & 0xF) +#define MSAR_CPU_CLK_TWSI(sar0) ((((sar0) >> 2) & 0x7) + (((sar1) & 1) << 3)) +#define MSAR_DDR_L2_CLK_RATIO_IDX(sar0) (((sar0) >> 15) & 0x1F) +#define MSAR_DDR_L2_CLK_RATIO_TWSI(sar0) (((sar0) >> 1) & 0xF) + +#ifndef MV_ASMLANGUAGE + +#define MV_CPU_CLK_TBL { 400, 533, 667, 800, 1000, 1067, 1200, 1333, 1500, 1600, 1667,\ + 1800, 2000, 333, 600, 900, 0 } + +#define MV_DEFAULT_PCLK 1200000000 +#define MV_BOARD_DEFAULT_SYSCLK MV_DEFAULT_PCLK +#define MV_BOARD_DEFAULT_L2CLK 600000000 + +/* cpu l2c hclk ddr */ +#define MV_DDR_L2_CLK_RATIO_TBL { \ +/*00*/ { 1, 1, 4, 2 },\ +/*01*/ { 1, 2, 2, 2 },\ +/*02*/ { 2, 2, 6, 3 },\ +/*03*/ { 2, 2, 3, 3 },\ +/*04*/ { 1, 2, 3, 3 },\ +/*05*/ { 1, 2, 4, 2 },\ +/*06*/ { 1, 1, 2, 2 },\ +/*07*/ { 2, 3, 6, 6 },\ +/*08*/ { 2, 3, 5, 5 },\ +/*09*/ { 1, 2, 6, 3 },\ +/*10*/ { 2, 4, 10, 5 },\ +/*11*/ { 1, 3, 6, 6 },\ +/*12*/ { 1, 2, 4, 4 },\ +/*13*/ { 1, 3, 6, 3 },\ +/*14*/ { 1, 2, 5, 5 },\ +/*15*/ { 2, 2, 5, 5 },\ +/*16*/ { 1, 1, 3, 3 },\ +/*17*/ { 2, 5, 10, 10 },\ +/*18*/ { 1, 3, 8, 4 },\ +/*19*/ { 1, 1, 2, 1 },\ +/*20*/ { 2, 3, 6, 3 },\ +/*21*/ { 1, 2, 8, 4 },\ +/*22*/ { 0, 0, 0, 0 },\ +/*23*/ { 0, 0, 0, 0 },\ +/*24*/ { 0, 0, 0, 0 },\ +/*25*/ { 0, 0, 0, 0 },\ +/*26*/ { 0, 0, 0, 0 },\ +/*27*/ { 1, 1, 1, 1 },\ +/*EOT*/ { 0, 0, 0, 0 } \ +} + +/* These macros help units to identify a target Mport Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) +#define MV_TARGET_IS_PEX1(target) \ + ((target >= PEX1_MEM) && (target <= PEX1_IO)) + +#define MV_TARGET_IS_PEX(target) ((target >= PEX0_MEM) && (target <= PEX1_IO)) + +#define MV_TARGET_IS_DEVICE(target) ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_CHANGE_BOOT_CS(target) target + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ + + +#define BOOT_TARGETS_NAME_ARRAY { \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + BOOT_ROM_CS \ +} + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + START_DEV_CS) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +/* This enumerator defines the Marvell controller target ID (see Address map) */ +typedef enum _mvTargetId { + DRAM_TARGET_ID = 0, /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> Device port, BootROM, SPI */ + PEX0_TARGET_ID = 4, /* Port 4 -> PCI Express 0 and 2 */ + PEX1_TARGET_ID = 8, /* Port 4 -> PCI Express 1 and 3 */ + CRYPT_TARGET_ID = 9, /* Port 9 --> Crypto Engine SRAM */ + MAX_TARGETS_ID +} MV_TARGET_ID; + +/* + This structure reflect registers: + Serdes 0-3 selectors 0x18270 + + Columns: + SERDES_UNIT_UNCONNECTED = 0x0, + SERDES_UNIT_PEX = 0x1, + SERDES_UNIT_SATA = 0x2, + SERDES_UNIT_SGMII = 0x3, +*/ + +#define SERDES_CFG { \ + {0, 1, 2, 3}, /* Lane 0 */ \ + {0, 1, -1, 2}, /* Lane 1 */ \ + {0, -1, 1, 2}, /* Lane 2 */ \ + {0, -1, 1, 2} /* Lane 3 */ \ +} + + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvSpec.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvSpec.h new file mode 100755 index 000000000..4bd380d54 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvCtrlEnvSpec.h @@ -0,0 +1,432 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvSpech +#define __INCmvCtrlEnvSpech + +#include "mvDeviceId.h" +#include "mvSysHwConfig.h" + +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +/* + * Armada-370 Units Address decoding + */ +#define MV_DRAM_REGS_OFFSET (0x0) +#define MV_AURORA_L2_REGS_OFFSET (0x8000) +#define MV_RTC_REGS_OFFSET (0x10300) +#ifdef CONFIG_SYNO_ARMADA +#define MV_RTC_EXTERNAL_ALARM_OFFSET (0x10320) +#endif +#define MV_DEV_BUS_REGS_OFFSET (0x10400) +#define MV_SPI_REGS_OFFSET(unit) (0x10600 + (unit * 0x80)) +#define MV_TWSI_SLAVE_REGS_OFFSET(chanNum) (0x11000 + (chanNum * 0x100)) +#define MV_UART_REGS_OFFSET(chanNum) (0x12000 + (chanNum * 0x100)) +#define MV_MPP_REGS_OFFSET (0x18000) +#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40)) +#define MV_MISC_REGS_OFFSET (0x18200) +#define MV_RUNIT_PMU_REGS_OFFSET (0x1C000) +#define MV_MBUS_REGS_OFFSET (0x20000) +#define MV_COHERENCY_FABRIC_OFFSET (0x20200) +#define MV_CIB_CTRL_STATUS_OFFSET (0x20280) +#define MV_CNTMR_REGS_OFFSET (0x20300) +#define MV_CPUIF_LOCAL_REGS_OFFSET (0x21800) +#define MV_AVS_REGS_OFFSET (0x20860) +#define MV_CPUIF_REGS_OFFSET(x) (0x21000) +#define MV_PMU_NFABRIC_UNIT_SERV_OFFSET (0x22000) +#define MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) (0x22100 + (cpu) * 0x100) +#define MV_AUDIO_REGS_OFFSET(unit) (0x30000) +#define MV_CPU_HW_SEM_OFFSET (0x20500) + +#if defined(MV_ETH_LEGACY) + #define MV_ETH_BASE_ADDR (0x72000) +#else + #define MV_ETH_BASE_ADDR (0x70000) +#endif +#define MV_ETH_SGMII_PHY_REGS_OFFSET(port) (0x72000 + (port) * 0x4000) +#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR + (port) * 0x4000) +#define MV_PEX_IF_REGS_OFFSET(pexIf) (0x40000 + (pexIf * 0x40000)) +#define MV_USB_REGS_OFFSET(dev) (0x50000 + (dev * 0x1000)) +#define MV_XOR_REGS_OFFSET(unit) (0x60800 + (unit * 0x100)) +#define MV_CESA_TDMA_REGS_OFFSET(chanNum) (0x90000 + (chanNum * 0x2000)) +#define MV_CESA_REGS_OFFSET(chanNum) (0x9D000 + (chanNum * 0x2000)) +#define MV_SATA_REGS_OFFSET (0xA0000) +#define MV_TDM_REGS_OFFSET (0xB0000) +#define MV_NFC_REGS_OFFSET (0xD0000) +#define MV_SDMMC_REGS_OFFSET (0xD4000) + +#define MV_ETH_SMI_PORT 0 + +#define MV_SERDES_NUM_TO_PEX_NUM(sernum) (sernum) +/* + * Miscellanuous Controller Configurations + */ +#define INTER_REGS_SIZE _1M + +/* TWSI bus speed. */ +#define TWSI_CPU_MAIN_INT_CAUSE_REG(cpu) CPU_MAIN_INT_CAUSE_REG(1) +#define TWSI_SPEED 100000 + +#define MV_GPP_MAX_PINS 65 +#define MV_GPP_MAX_GROUP 3 /* group == configuration register? */ +#define MV_CNTMR_MAX_COUNTER 8 +/* Global Counters 0-3 : 0-3 + Global WD : 4 + CPU Counter 0-1 : 5-6 + CPU WD : 7 +*/ + +#define MV_UART_MAX_CHAN 2 + +#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ +#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ +#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ + +#define MV_SATA_MAX_CHAN 2 +#define MV_SATA_MV6W11_CHAN 0 + +#define MV_AUDIO_MAX_UNITS 1 + +#define MV_MPP_MAX_GROUP 9 +#define MV_SERDES_MAX_LANES 4 + +#define MV_DRAM_MAX_CS 4 +#define MV_SPI_MAX_CS 8 +/* This define describes the maximum number of supported PCI\PCIX Interfaces */ +#ifdef MV_INCLUDE_PCI + #define MV_PCI_MAX_IF 1 + #define MV_PCI_START_IF 0 + #define PCI_HOST_BUS_NUM(pciIf) (pciIf) + #define PCI_HOST_DEV_NUM(pciIf) 0 +#else + #define MV_PCI_MAX_IF 0 + #define MV_PCI_START_IF 0 +#endif + +/* This define describes the maximum number of supported PEX Interfaces */ +#ifdef MV_INCLUDE_PEX +#define MV_INCLUDE_PEX0 +#define MV_DISABLE_PEX_DEVICE_BAR + +#define MV_PEX_MAX_IF 2 +#define MV_PEX_START_IF MV_PCI_MAX_IF +#define MV_PEX_MAX_UNIT 2 + #define PEX_HOST_BUS_NUM(pciIf) (pciIf) + #define PEX_HOST_DEV_NUM(pciIf) 0 +#else + #undef MV_INCLUDE_PEX0 +#endif + +#define PCI_IO(pciIf) (PEX0_IO + 2 * (pciIf)) +#define PCI_MEM(pciIf, memNum) (PEX0_MEM0 + 2 * (pciIf)) +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_IDMA_MAX_CHAN 4 +#define MV_MAX_USB_PORTS 2 +#define ARMADA_370_NAND 1 +#define ARMADA_370_SDIO 1 +#define ARMADA_370_MAX_TDM_PORTS 2 +#define MV_DEVICE_MAX_CS 4 +#define ARMADA_370_TDM 1 + +#ifndef MV_USB_MAX_PORTS +#define MV_USB_MAX_PORTS MV_MAX_USB_PORTS +#endif + + +/* CESA version #3: One channel, 2KB SRAM, TDMA, CHAIN Mode support */ +#define MV_CESA_VERSION 3 /*TODO verify */ +#define MV_CESA_SRAM_SIZE (2 * 1024) + +/* This define describes the support of Ethernet */ +#define MV_ETH_VERSION 4 /* for Legacy mode */ +#define MV_NETA_VERSION 1 /* for NETA mode */ +#define MV_ETH_MAX_PORTS 2 +#define MV_ETH_MAX_RXQ 8 +#define MV_ETH_MAX_TXQ 8 +#define MV_ETH_TX_CSUM_MAX_SIZE 2048 + +/* IPv6 parsing support for Legacy parser */ +#define MV_ETH_LEGACY_PARSER_IPV6 + +/* New GMAC module is used */ +#define MV_ETH_GMAC_NEW +/* New WRR/EJP module is used */ +#define MV_ETH_WRR_NEW + +/* This define describes the support of USB */ +#define MV_USB_VERSION 1 + +#define MV_SPI_VERSION 2 + +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 + +#ifndef MV_ASMLANGUAGE + +#define TBL_UNUSED 0 /* Used to mark unused entry */ + +/* Giga Site */ +#define MPP_GROUP_1_TYPE {\ + /* 0, 8, 16, 24*/ \ + {{0x00000000, 0x00000000}, {0x00000000, 0x00000000}, /* Reserved for AUTO */ \ + {0x00000000, 0x00000000}, {0x00000000, 0x00000000} }, \ + {{0xFFF00000, 0x44400000}, {0xFFFFFF0F, 0x44446404}, /* TDM */ \ + {0x0000000F, 0x00000004}, {0x00000000, 0x00000000} }, \ + {{0xFFF00000, 0x55500000}, {0x00FF0FFF, 0x00550555}, /* I2S-SPDIF */ \ + {0x00000000, 0x00000000}, {0x00000000, 0x00000000} }, \ + {{0xFFF00000, 0x11100000}, {0xFFFFFFFF, 0x11111111}, /* GMII0 */ \ + {0xFFFFF00F, 0x11111001}, {0xFFFFFFFF, 0x41111111} }, \ + {{0x00000000, 0x00000000}, {0xFFFFF0F0, 0x33333030}, /* SDIO */ \ + {0x00000000, 0x00000000}, {0x00000000, 0x00000000} }, \ + {{0xFFF00000, 0x11100000}, {0xFFFFFFFF, 0x11111111}, /* RGMII0 */ \ + {0x0000000F, 0x00000001}, {0x00000000, 0x00000000} }, \ + {{0x00000000, 0x00000000}, {0x00000000, 0x00000000}, /* RGMII1 */ \ + {0xFFFFF000, 0x22222000}, {0x0FFFFFFF, 0x02222222} }, \ +} + +/* Device Site */ +#define MPP_GROUP_2_TYPE {\ + /* 32, 40, 48, 56*/ \ + {{0x00000000, 0x00000000}, {0x00000000, 0x00000000}, /* Reserved for AUTO */ \ + {0x00000000, 0x00000000}, {0x00000000, 0x00000000} }, \ + {{0xFFFFFFF0, 0x11111110}, {0x0FFFFFFF, 0x01111111}, /* TDM + onBoard NAND */ \ + {0xFFFFFFF0, 0x33344440}, {0x0F000FFF, 0x03000336} }, \ + {{0x00000000, 0x00000000}, {0xF0000000, 0x50000000}, /* I2S-SPDIF */ \ + {0x00000FF0, 0x00000550}, {0x0FFFFFF0, 0x05555550} }, \ + {{0x00000000, 0x00000000}, {0x00000000, 0x00000000}, /* SDIO */ \ + {0x00FFFFFF, 0x00233333}, {0x00000000, 0x00000000} }, \ + {{0x00000000, 0x00000000}, {0x00000000, 0x00000000}, \ + {0x00000000, 0x00000000}, {0x00000000, 0x00000000} }, \ + {{0x00000000, 0x00000000}, {0x00000000, 0x00000000}, \ + {0x00000000, 0x00000000}, {0x00000000, 0x00000000} }, \ + {{0x00000000, 0x00000000}, {0x00000000, 0x00000000}, \ + {0x00000000, 0x00000000}, {0x00000000, 0x00000000} }, \ +} + +typedef enum { + TDM_UNIT_2CH +} MV_TDM_UNIT_TYPE; + +/* This enumerator defines the Marvell Units ID */ +typedef enum _mvUnitId { + DRAM_UNIT_ID, + PEX_UNIT_ID, + ETH_GIG_UNIT_ID, + USB_UNIT_ID, + XOR_UNIT_ID, + SATA_UNIT_ID, + TDM_2CH_UNIT_ID, + UART_UNIT_ID, + CESA_UNIT_ID, + SPI_UNIT_ID, + SDIO_UNIT_ID, + AUDIO_UNIT_ID, + MAX_UNITS_ID +} MV_UNIT_ID; + + +/* This enumerator describes the Marvell controller possible devices that */ +/* can be connected to its device interface. */ +typedef enum _mvDevice { +#if defined(MV_INCLUDE_DEVICE_CS0) + DEV_CS0 = 0, /* Device connected to dev CS[0] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEV_CS1 = 1, /* Device connected to dev CS[1] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEV_CS2 = 2, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEV_CS3 = 3, /* Device connected to dev CS[2] */ +#endif + BOOT_CS, /* Device connected to BOOT dev */ + MV_DEV_MAX_CS = MV_DEVICE_MAX_CS +} MV_DEVICE; + +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget { + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /*0 SDRAM chip select 0 */ + SDRAM_CS1, /*1 SDRAM chip select 1 */ + SDRAM_CS2, /*2 SDRAM chip select 2 */ + SDRAM_CS3, /*3 SDRAM chip select 3 */ + DEVICE_CS0, /*4 Device chip select 0 */ + DEVICE_CS1, /*5 Device chip select 1 */ + DEVICE_CS2, /*6 Device chip select 2 */ + DEVICE_CS3, /*7 Device chip select 3 */ + PEX0_MEM, /*8 PCI Express 0 Memory */ + PEX0_IO, /*9 PCI Express 0 IO */ + PEX1_MEM, /*10 PCI Express 1 Memory */ + PEX1_IO, /*11 PCI Express 1 IO */ + INTER_REGS, /*28 Internal registers */ + DMA_UART, /*29 DMA based UART request */ + SPI_CS0, /*30 SPI_CS0 */ + SPI_CS1, /*31 SPI_CS1 */ + SPI_CS2, /*32 SPI_CS2 */ + SPI_CS3, /*33 SPI_CS3 */ + SPI_CS4, /*34 SPI_CS4 */ + SPI_CS5, /*35 SPI_CS5 */ + SPI_CS6, /*36 SPI_CS6 */ + SPI_CS7, /*37 SPI_CS7 */ + BOOT_ROM_CS, /*38 BOOT_ROM_CS */ + DEV_BOOCS, /*39 DEV_BOOCS */ + PMU_SCRATCHPAD, /*40 PMU Scratchpad */ + CRYPT0_ENG, /*41 Crypto0 Engine */ + MAX_TARGETS +} MV_TARGET; + +#ifdef AURORA_IO_CACHE_COHERENCY +#define DRAM_CS0_ATTR 0x1E +#define DRAM_CS1_ATTR 0x1D +#define DRAM_CS2_ATTR 0x1B +#define DRAM_CS3_ATTR 0x17 +#else +#define DRAM_CS0_ATTR 0x0E +#define DRAM_CS1_ATTR 0x0D +#define DRAM_CS2_ATTR 0x0B +#define DRAM_CS3_ATTR 0x07 +#endif + +#define TARGETS_DEF_ARRAY { \ + {DRAM_CS0_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {DRAM_CS1_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {DRAM_CS2_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS2 */ \ + {DRAM_CS3_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS3 */ \ + {0x3E, DEV_TARGET_ID }, /* DEVICE_CS0 */ \ + {0x3D, DEV_TARGET_ID }, /* DEVICE_CS1 */ \ + {0x3B, DEV_TARGET_ID }, /* DEVICE_CS2 */ \ + {0x37, DEV_TARGET_ID }, /* DEVICE_CS3 */ \ + {0x18, PEX0_TARGET_ID }, /* PEX0_LANE0_MEM */ \ + {0x10, PEX0_TARGET_ID }, /* PEX0_LANE0_IO */ \ + {0x28, PEX1_TARGET_ID }, /* PEX1_LANE0_MEM */ \ + {0x20, PEX1_TARGET_ID }, /* PEX1_LANE0_IO */ \ + {0xFF, 0xFF }, /* INTER_REGS */ \ + {0x01, DEV_TARGET_ID }, /* DMA_UART */ \ + {0x1E, DEV_TARGET_ID }, /* SPI_CS0 */ \ + {0x5E, DEV_TARGET_ID }, /* SPI_CS1 */ \ + {0x9E, DEV_TARGET_ID }, /* SPI_CS2 */ \ + {0xDE, DEV_TARGET_ID }, /* SPI_CS3 */ \ + {0x1F, DEV_TARGET_ID }, /* SPI_CS4 */ \ + {0x5F, DEV_TARGET_ID }, /* SPI_CS5 */ \ + {0x9F, DEV_TARGET_ID }, /* SPI_CS6 */ \ + {0xDF, DEV_TARGET_ID }, /* SPI_CS7 */ \ + {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ + {0x2F, DEV_TARGET_ID }, /* DEV_BOOT_CS */ \ + {0x2D, DEV_TARGET_ID }, /* PMU_SCRATCHPAD */ \ + {0x01, CRYPT_TARGET_ID }, /* CRYPT_ENG0 */ \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEVICE_CS3", /* DEVICE_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PEX1_MEM", /* PEX1_MEM */ \ + "PEX1_IO", /* PEX1_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DMA_UART", /* DMA_UART */ \ + "SPI_CS0", /* SPI_CS0 */ \ + "SPI_CS1", /* SPI_CS1 */ \ + "SPI_CS2", /* SPI_CS2 */ \ + "SPI_CS3", /* SPI_CS3 */ \ + "SPI_CS4", /* SPI_CS4 */ \ + "SPI_CS5", /* SPI_CS5 */ \ + "SPI_CS6", /* SPI_CS6 */ \ + "SPI_CS7", /* SPI_CS7 */ \ + "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "PMU_SCRATCHPAD",/* PMU_SCRATCHPAD */ \ + "CRYPT0_ENG", /* CRYPT0_ENG */ \ +} + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCtrlEnvSpech */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvSemaphore.c b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvSemaphore.c new file mode 100755 index 000000000..d71df4e0c --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvSemaphore.c @@ -0,0 +1,124 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvSemaphore.h" + + +MV_BOOL mvSemaLock(MV_32 num) +{ + MV_U32 tmp; + MV_U32 cpuId; + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + cpuId = whoAmI(); + do + { + tmp = MV_REG_BYTE_READ(MV_SEMA_REG_BASE+num); + } while ((tmp & 0xFF) != cpuId); + return MV_TRUE; +} + +MV_BOOL mvSemaTryLock(MV_32 num) +{ + MV_U32 tmp; + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + tmp = MV_REG_BYTE_READ(MV_SEMA_REG_BASE+num); + if ((tmp & 0xFF) != whoAmI()) + { + return MV_FALSE; + } + else + return MV_TRUE; +} + +MV_BOOL mvSemaUnlock(MV_32 num) +{ + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + MV_REG_BYTE_WRITE(MV_SEMA_REG_BASE+(num), 0xFF); + return MV_TRUE; +} + +MV_32 mvReadAmpReg(int regId) +{ + return MV_REG_READ(MV_AMP_GLOBAL_REG(regId)); +} + +MV_32 mvWriteAmpReg(int regId, MV_32 value) +{ + return MV_REG_WRITE(MV_AMP_GLOBAL_REG(regId), value); +} diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvSemaphore.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvSemaphore.h new file mode 100755 index 000000000..c5bf5ca86 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvSemaphore.h @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef mvsemaphore_h +#define mvsemaphore_h + +#ifdef MV_VXWORKS +#include "common/mvTypes.h" +#include "config.h" +#endif + +#define MV_AMP_GLOBAL_REG(x) (0xC010 + (100*x)) +#define ADR_WIN_EN_REG 0 + +#define MV_SEMA_REG_BASE (0x20500) +#define MV_MAX_SEMA 128 +#define MV_SEMA_SMI 50 +#define MV_SEMA_RTC 51 +#define MV_SEMA_NOR_FLASH 0 +#define MV_SEMA_BOOT 1 +#define MV_SEMA_PEX0 2 +#define MV_SEMA_BRIDGE 3 +#define MV_SEMA_IRQ 4 +#define MV_SEMA_CLOCK 5 +#define MV_SEMA_L2 6 +#define MV_SEMA_TWSI 7 +#define MV_SEMA_ADR_WIN 8 + +#define MV_SEMA_BARRIER(cpu) (50 + cpu) + + +MV_BOOL mvSemaLock(MV_32 num); +MV_BOOL mvSemaTryLock(MV_32 num); +MV_BOOL mvSemaUnlock(MV_32 num); +MV_32 mvReadAmpReg(int regId); +MV_32 mvWriteAmpReg(int regId, MV_32 value); + +/* Turn on HW semapores only if AMP is enabled */ +#ifndef CONFIG_MV_AMP_ENABLE +#define mvSemaLock +#define mvSemaTryLock +#define mvSemaUnlock +#define mvHwBarrier +#endif /* CONFIG_MV_AMP_ENABLE */ + +#endif /* mvsemaphore_h */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvUnitMap.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvUnitMap.h new file mode 100755 index 000000000..0321d7b59 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/mvUnitMap.h @@ -0,0 +1,158 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef mvUnitMap_h +#define mvUnitMap_h + +#ifdef MV_VXWORKS +#include "common/mvTypes.h" +#include "config.h" +#endif + +typedef enum +{ + UART0=0, + UART1, + PEX0, + PEX1, + PEX2, + PEX3, + ETH0, + ETH1, + ETH2, + ETH3, + XOR0, + XOR1, + USB0, + USB1, + USB2, + I2C0, + I2C1, + SATA, + CESA, + NOR, + NAND, + SPI, + TDM, + SDIO, + LCD, + HWMON, + RTC, + GPIO, + MSTR, + MAX_UNITS +} MV_SOC_UNIT; + +/* binary flags for mvSocUnitMapFillTableFormBitMap */ +/*#define UART0_T0_CPU1 0x0001 +#define UART1_TO_CPU1 0x0002 +#define PEX0_TO_CPU1 0x0004 +#define PEX1_TO_CPU1 0x0008 +#define GIGA0_TO_CPU1 0x0010 +#define GIGA1_TO_CPU1 0x0020 +#define GIGA2_TO_CPU1 0x0040 +#define GIGA3_TO_CPU1 0x0080 +#define SATA_TO_CPU1 0x0100 +#define XOR_TO_CPU1 0x0200 +#define IDMA_TO_CPU1 0x0400 +#define USB0_TO_CPU1 0x0800 +#define USB1_TO_CPU1 0x1000 +#define USB2_TO_CPU1 0x2000 +#define CESA_TO_CPU1 0x4000 +#define NOR_TO_CPU1 0x8000 +#define NAND_TO_CPU1 0x10000 +#define SPI_TO_CPU1 0x20000 +#define TDM_TO_CPU1 0x40000 + +#define CPU1_DEFAULT_INTERFACE (UART1_TO_CPU1 | PEX1_TO_CPU1 | GIGA2_TO_CPU1 | GIGA3_TO_CPU1 | IDMA_TO_CPU1 | USB1_TO_CPU1)*/ + +typedef struct __MV_RES_MAP +{ + int isMine; + char* unitName; +} MV_RES_MAP; + +typedef char *(*STRSTR_FUNCPTR)(const char *s1, const char *s2); + +#ifdef CONFIG_MV_AMP_ENABLE + +MV_BOOL mvUnitMapIsMine(MV_SOC_UNIT unitIdx); +MV_BOOL mvUnitMapIsPexMine(int pciIf); +MV_VOID mvUnitMapSetMine(MV_SOC_UNIT unitIdx); +MV_BOOL mvUnitMapSetup(char* p, STRSTR_FUNCPTR strstr_func); +MV_VOID mvUnitMapSetAllMine(void); +MV_VOID mvUnitMapPrint(void); +MV_BOOL mvUnitMapIsRsrcLimited(void); +MV_VOID mvUnitMapSetRsrcLimited(MV_BOOL isLimited); +#else /* CONFIG_MV_AMP_ENABLE */ +#define mvUnitMapIsMine(rsrc) MV_TRUE +#define mvUnitMapIsPexMine(pciIf) MV_TRUE +#define mvUnitMapIsRsrcLimited MV_TRUE +#define mvUnitMapSetRsrcLimited(limit) +#define mvUnitMapSetMine(rsrc) +#define mvUnitMapSetAllMine +#define mvUnitMapPrint +#define mvUnitMapSetup(str, strstr_func) MV_TRUE +#endif /* CONFIG_MV_AMP_ENABLE */ + +#endif /* mvUnitMap_h */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbus.c b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbus.c new file mode 100755 index 000000000..b61f5e6a0 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbus.c @@ -0,0 +1,739 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "mvCpuIfRegs.h" + +#undef MV_DEBUG +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* typedefs */ + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _ahbToMbusRemapRegOffs { + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +} AHB_TO_MBUS_REMAP_REG_OFFS; + +/* locals */ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); + +/******************************************************************************* +* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK laways. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusInit(void) +{ + return MV_OK; + +} + +/******************************************************************************* +* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* This function sets +* address window, also known as address decode window. +* A new address decode window is set for specified winNum address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the winNum window, allowing CPU to access +* the winNum window. +* +* INPUT: +* winNum - Windows number. +* pAddrDecWin - CPU winNum window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU winNum window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + MV_U32 sizeToReg; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) { + mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to " + "target %s.\nAddress 0x%08x is unaligned to size 0x%llx.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* Size parameter validity check. */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.size, ATMWCR_WIN_SIZE_ALIGNMENT)) { + mvOsPrintf("mvAhbToMbusWinSet: Failed, size not aligned to 0x%x.\n", ATMWCR_WIN_SIZE_ALIGNMENT); + return MV_BAD_PARAM; + } + + /* Write to address decode Base Address Register */ + decRegs.baseReg = (pAddrDecWin->addrWin.baseLow & ATMWBR_BASE_MASK); + + /* Get size register value according to window size */ + sizeToReg = (pAddrDecWin->addrWin.size / ATMWCR_WIN_SIZE_ALIGNMENT) - 1; + + /* set size */ + decRegs.ctrlReg = (sizeToReg << ATMWCR_WIN_SIZE_OFFS); + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + decRegs.ctrlReg |= ATMWCR_WIN_ENABLE; + else + decRegs.ctrlReg &= ~ATMWCR_WIN_ENABLE; + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.ctrlReg &= ~ATMWCR_WIN_ATTR_MASK; + decRegs.ctrlReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.ctrlReg &= ~ATMWCR_WIN_TARGET_MASK; + decRegs.ctrlReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; + +#if !defined(MV_RUN_FROM_FLASH) + /* To be on the safe side we disable the window before writing the */ + /* new values. */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + mvAhbToMbusWinEnable(winNum, MV_FALSE); +#endif + + /* 3) Write to address decode Base Address Register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); + else + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); + + /* Internal register space have no size */ + /* register. Do not perform size register assigment for those targets */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) { + /* Write to address decode Size Register */ + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.ctrlReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* Get the CPU peripheral winNum address window. +* +* INPUT: +* winNum - Peripheral winNum enumerator +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_OK if winNum exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 sizeRegVal; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal register space size have no size register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + decRegs.ctrlReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + else + decRegs.ctrlReg = 0; + + /* Read base and size */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + else + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + + pAddrDecWin->addrWin.baseHigh = 0; + pAddrDecWin->addrWin.baseLow = decRegs.baseReg & ATMWBR_BASE_MASK; + sizeRegVal = (decRegs.ctrlReg & ATMWCR_WIN_SIZE_MASK) >> ATMWCR_WIN_SIZE_OFFS; + pAddrDecWin->addrWin.size = (sizeRegVal + 1) * ATMWCR_WIN_SIZE_ALIGNMENT; + + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) { + pAddrDecWin->addrWin.size = INTER_REGS_SIZE; + pAddrDecWin->target = INTER_REGS; + pAddrDecWin->enable = MV_TRUE; + + return MV_OK; + } + + if (decRegs.ctrlReg & ATMWCR_WIN_ENABLE) + pAddrDecWin->enable = MV_TRUE; + else + pAddrDecWin->enable = MV_FALSE; + + if (-1 == pAddrDecWin->addrWin.size) + return MV_ERROR; + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.ctrlReg & ATMWCR_WIN_ATTR_MASK) >> ATMWCR_WIN_ATTR_OFFS; + targetAttrib.targetId = (decRegs.ctrlReg & ATMWCR_WIN_TARGET_MASK) >> ATMWCR_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is illegal\n", target); + return 0xffffffff; + } + + if (INTER_REGS == target) + return MV_AHB_TO_MBUS_INTREG_WIN; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_TRUE) { + if (decWin.target == target) + return winNum; + } + } + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvAhbToMbusWinAvailGet - Get First Available window number. +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_FALSE) + return winNum; + } + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Peripheral winNum enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other winNum window. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) +{ + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal registers bar can't be disable or enabled */ + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + return (enable ? MV_OK : MV_ERROR); + + + if (enable == MV_TRUE) { + /* enable the window */ + MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } else { + /* Disable address decode winNum window */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* After a CPU address hits one of PCI address decode windows there is an +* option to remap the address to a different one. For example, CPU +* executes a read from PCI winNum window address 0x1200.0000. This +* can be modified so the address on the PCI bus would be 0x1400.0000 +* Using the PCI address remap mechanism. +* +* INPUT: +* winNum - Peripheral winNum enumerator. Must be a PCI winNum. +* pAddrDecWin - CPU winNum window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddr; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + MV_U32 effectiveBaseAddress = 0, baseAddrValue = 0, windowSizeValue = 0; + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) + return 0xffffffff; + + /* 1) Set address remap low */ + baseAddr = pAddrWin->baseLow; + + /* Check base address aligment */ + /* + if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) + { + mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", + baseAddr); + return MV_ERROR; + } + */ + + /* BaseLow[31:16] => base register [31:16] */ + baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; + + MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); + MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); + + baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + + baseAddrValue &= ATMWBR_BASE_MASK; + windowSizeValue &= ATMWCR_WIN_SIZE_MASK; + + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue; + + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + + if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) { + mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); + return 0xffffffff; + } + + return effectiveBaseAddress; +} + + +/******************************************************************************* +* mvAhbToMbusWinRemapGet - Get CPU remap register for address windows. +* +* DESCRIPTION: +* Get CPU address decode windows remap window configuration for a given +* windows index. +* +* INPUT: +* winNum - Peripheral winNum enumerator. +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_ERROR if windows is not a valid remap window, +* MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemapGet(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) + return 0xffffffff; + + pAddrWin->baseLow = MV_REG_READ(remapRegOffs.lowRegOffs) & ATMWRLR_REMAP_LOW_MASK; + pAddrWin->baseHigh = MV_REG_READ(remapRegOffs.highRegOffs); + + return MV_OK; +} + + +/******************************************************************************* +* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets +* +* DESCRIPTION: +* +* INPUT: +* target1 - CPU Interface target 1 +* target2 - CPU Interface target 2 +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if targets are illigal, or if one of the targets is not +* associated to a valid window . +* MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1, MV_TARGET target2) +{ + MV_U32 winNum1, winNum2; + MV_AHB_TO_MBUS_DEC_WIN winDec1, winDec2, winDecTemp; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1, remapRegs2; + MV_U32 remapBaseLow1 = 0, remapBaseLow2 = 0; + MV_U32 remapBaseHigh1 = 0, remapBaseHigh2 = 0; + + /* Check parameters */ + if (target1 >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is illegal\n", target1); + return MV_ERROR; + } + + if (target2 >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is illegal\n", target1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum1 = mvAhbToMbusWinTargetGet(target1); + + if (winNum1 == 0xffffffff) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", target1, winNum1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum2 = mvAhbToMbusWinTargetGet(target2); + if (winNum2 == 0xffffffff) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", target2, winNum2); + return MV_ERROR; + } + + /* now Get original values of both Windows */ + if (MV_OK != mvAhbToMbusWinGet(winNum1, &winDec1)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinGet(winNum2, &winDec2)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", winNum2); + return MV_ERROR; + } + + /* disable both windows */ + if (MV_OK != mvAhbToMbusWinEnable(winNum1, MV_FALSE)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinEnable(winNum2, MV_FALSE)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", winNum2); + return MV_ERROR; + } + + /* now swap targets */ + + /* first save winDec2 values */ + winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; + winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; + winDecTemp.addrWin.size = winDec2.addrWin.size; + winDecTemp.enable = winDec2.enable; + winDecTemp.target = winDec2.target; + + /* winDec2 = winDec1 */ + winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; + winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; + winDec2.addrWin.size = winDec1.addrWin.size; + winDec2.enable = winDec1.enable; + winDec2.target = winDec1.target; + + /* winDec1 = winDecTemp */ + winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; + winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; + winDec1.addrWin.size = winDecTemp.addrWin.size; + winDec1.enable = winDecTemp.enable; + winDec1.target = winDecTemp.target; + + /* now set the new values */ + mvAhbToMbusWinSet(winNum1, &winDec1); + mvAhbToMbusWinSet(winNum2, &winDec2); + + /* now we will treat the remap windows if exist */ + + /* now check if one or both windows has a remap window + as well after the swap ! */ + + /* if a window had a remap value differnt than the base value + before the swap , then after the swap the remap value will be + equal to the base value unless both windows has a remap windows */ + + /* first get old values */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1, &remapRegs1)) { + remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); + remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); + } + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); + remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); + } + + /* now do the swap */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1, &remapRegs1)) { + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + /* Two windows has a remap !!! so swap */ + + MV_REG_WRITE(remapRegs2.highRegOffs, remapBaseHigh1); + MV_REG_WRITE(remapRegs2.lowRegOffs, remapBaseLow1); + + MV_REG_WRITE(remapRegs1.highRegOffs, remapBaseHigh2); + MV_REG_WRITE(remapRegs1.lowRegOffs, remapBaseLow2); + } else { + /* remap == base */ + MV_REG_WRITE(remapRegs1.highRegOffs, winDec1.addrWin.baseHigh); + MV_REG_WRITE(remapRegs1.lowRegOffs, winDec1.addrWin.baseLow); + } + } else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + /* remap == base */ + MV_REG_WRITE(remapRegs2.highRegOffs, winDec2.addrWin.baseHigh); + MV_REG_WRITE(remapRegs2.lowRegOffs, winDec2.addrWin.baseLow); + } + + return MV_OK; +} + +/******************************************************************************* +* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets +* +* DESCRIPTION: +* CPU to PCI address remap registers offsets are inconsecutive. +* This function returns PCI address remap registers offsets. +* +* INPUT: +* winNum - Address decode window number. See MV_U32 enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one. +* +*******************************************************************************/ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) +{ + switch (winNum) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + default: + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAhbToMbusAddDecShow(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN win; + MV_U32 winNum; + mvOsOutput("\n"); + mvOsOutput("AHB To MBUS Bridge:\n"); + mvOsOutput("-------------------\n"); + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + memset(&win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvAhbToMbusWinGet(winNum, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("%s base %08x, ", mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } +} diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbus.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbus.h new file mode 100755 index 000000000..e444dc9e0 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbus.h @@ -0,0 +1,97 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbush +#define __INCmvAhbToMbush + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* defines */ + +typedef struct _mvAhbtoMbusDecWin { + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_AHB_TO_MBUS_DEC_WIN; + +/* mvAhbToMbus.h API list */ + +MV_STATUS mvAhbToMbusInit(MV_VOID); +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable); +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvAhbToMbusWinRemapGet(MV_U32 winNum, MV_ADDR_WIN *pAddrWin); +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1, MV_TARGET target2); + +MV_VOID mvAhbToMbusAddDecShow(MV_VOID); + +#endif /* __INCmvAhbToMbush */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbusRegs.h new file mode 100755 index 000000000..92b04b793 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvAhbToMbusRegs.h @@ -0,0 +1,141 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusRegsh +#define __INCmvAhbToMbusRegsh + +#define MAX_AHB_TO_MBUS_WINS 21 +#define MAX_AHB_TO_MBUS_REMAP_WINS 8 +#define MV_AHB_TO_MBUS_INTREG_WIN 20 + +/***********************/ +/* AHB TO MBUS WINDOWS */ +/***********************/ +/* Window-X Control Registers */ +#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS) ? \ + (MV_MBUS_REGS_OFFSET + winNum * 0x10) : \ + (MV_MBUS_REGS_OFFSET + 0x90 + (winNum-8)*0x08)) +#define ATMWCR_WIN_ENABLE BIT0 +#define ATMWCR_WIN_TARGET_OFFS 4 +#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) +#define ATMWCR_WIN_ATTR_OFFS 8 +#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) +#define ATMWCR_WIN_SIZE_OFFS 16 +#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) +#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 + +/* Window-X Base Register */ +#define AHB_TO_MBUS_WIN_BASE_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS) ? \ + (MV_MBUS_REGS_OFFSET + 0x4 + winNum * 0x10) : \ + (MV_MBUS_REGS_OFFSET + 0x94 + (winNum - 8) * 0x08)) +#define ATMWBR_BASE_OFFS 16 +#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) +#define ATMWBR_BASE_ALIGNMENT 0x10000 + +/* Window-X Remap Low Register */ +#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS) ? \ + (MV_MBUS_REGS_OFFSET + 0x8 + winNum * 0x10) : \ + (0)) +#define ATMWRLR_REMAP_LOW_OFFS 16 +#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) +#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 + +/* Window-X Remap Hi Register */ +#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS) ? \ + (MV_MBUS_REGS_OFFSET + 0xC + winNum * 0x10) : \ + (0)) +#define ATMWRHR_REMAP_HIGH_OFFS 0 +#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) + +/*****************************/ +/* INTERNAL REGISTERS WINDOW */ +/*****************************/ +/* Internal Registers Base Address in set to be window 20 */ +#define AHB_TO_MBUS_WIN_INTEREG_REG (MV_MBUS_REGS_OFFSET + 0x80) + +/************************/ +/* SDRAM DECODE WINDOWS */ +/************************/ +/* All DRAM Window definitions are declared under the ddr2_3 HAL */ + +/****************************/ +/* SRAM (L2) DECODE WINDOWS */ +/****************************/ +#define SRAM_WIN_CTRL_REG(winNum) (MV_MBUS_REGS_OFFSET + 0x240 + winNum * 0x4) +#define SRAMWCR_ENABLE BIT0 +#define SRAMWCR_SIZE_OFFS 8 +#define SRAMWCR_SIZE_MASK (0x7 << SRAMWCR_SIZE_OFFS) +#define SRAMWCR_BASE_OFFS 16 +#define SRAMWCR_BASE_MASK (0xFFFF << SRAMWCR_BASE_OFFS) + +/**********************/ +/* MBUS BRIDGE WINDOW */ +/**********************/ +#define MBUS_BRIDGE_WIN_CTRL_REG (MV_MBUS_REGS_OFFSET + 0x250) +#define BRIDGWCR_ENABLE BIT0 +#define BRIDGWCR_SIZE_OFFS 16 +#define BRIDGWCR_SIZE_MASK (0xFFFF << BRIDGWCR_SIZE_OFFS) + +#endif /* __INCmvAhbToMbusRegsh */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIf.c b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIf.c new file mode 100755 index 000000000..5498bf4c9 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIf.c @@ -0,0 +1,855 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "ddr2_3/mvDramIf.h" +#include "ddr2_3/mvDramIfRegs.h" +#include "pex/mvPexRegs.h" + +/*#define MV_DEBUG*/ +/* defines */ + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ +/* static functions */ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +MV_TARGET sampleAtResetTargetArray[] = BOOT_TARGETS_NAME_ARRAY; +/******************************************************************************* +* mvCpuIfInit - Initialize Controller CPU interface +* +* DESCRIPTION: +* This function initialize Controller CPU interface: +* 1. Set CPU interface configuration registers. +* 2. Set CPU master Pizza arbiter control according to static +* configuration described in configuration file. +* 3. Opens CPU address decode windows. DRAM windows are assumed to be +* already set (auto detection). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_U32 regVal, i; + MV_TARGET target; + MV_ADDR_WIN addrWin; + + if (cpuAddrWinMap == NULL) { + DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); + return MV_ERROR; + } + + /* Set CPU Configuration register */ + regVal = MV_REG_READ(CPU_CONFIG_REG); + regVal &= ~CPU_CONFIG_DEFAULT_MASK; + regVal |= CPU_CONFIG_DEFAULT; + MV_REG_WRITE(CPU_CONFIG_REG, regVal); + + for (i = 0; i < MAX_AHB_TO_MBUS_WINS-1; i++) + mvAhbToMbusWinEnable(i, MV_FALSE); + + /* Disable all SRAM windows */ + mvCpuIfSramWinDisable(); + + /* First disable all CPU target windows */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + if ((MV_TARGET_IS_DRAM(target)) || (target == INTER_REGS)) + continue; + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + continue; +#endif +#if defined(MV_RUN_FROM_FLASH) + /* Don't disable the boot device. */ + if (target == DEV_BOOCS) + continue; +#endif /* MV_RUN_FROM_FLASH */ + mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target), MV_FALSE); + } + +#if defined(MV_RUN_FROM_FLASH) + /* Resize the bootcs windows before other windows, because this */ + /* window is enabled and will cause an overlap if not resized. */ + target = DEV_BOOCS; + + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum, &addrWin)) { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } +#endif /* MV_RUN_FROM_FLASH */ + + /* Go through all targets in user table until table terminator */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + +#if defined(MV_RUN_FROM_FLASH) + if (target == DEV_BOOCS) + continue; +#endif /* MV_RUN_FROM_FLASH */ + + /* if DRAM auto sizing is used do not initialized DRAM target windows, */ + /* assuming this already has been done earlier. */ +#ifdef MV_DRAM_AUTO_SIZE + if (MV_TARGET_IS_DRAM(target)) + continue; +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + continue; +#endif + if ((0 == cpuAddrWinMap[target].addrWin.size) || (DIS == cpuAddrWinMap[target].enable)) { + if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); + return MV_ERROR; + } + } else { + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum, &addrWin)) { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfDramInit - Initialize Controller DRAM Fastpath windows +* +* DESCRIPTION: +* This function initialize Controller DRAM Fastpath windows +* It takes the CS size information from the 0x1500 scratch registers +* and sets the correct windows sizes and base addresses accordingly +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfDramInit() +{ + MV_U32 base = 0; + MV_U32 size, cs, temp; + + for (cs = 0; cs < SDRAM_MAX_CS; cs++) { + size = MV_REG_READ(SDRAM_SIZE_REG(cs)) & SDRAM_ADDR_MASK; + if ((size > 0) && (base < SDRAM_MAX_ADDR)) { + size |= ~(SDRAM_ADDR_MASK); + + /* Set Base Address */ + MV_REG_WRITE(SDRAM_WIN_BASE_REG(cs), (base & SDRAM_ADDR_MASK)); + + /* Check if out of max window size and resize the window */ + if (base+size > SDRAM_MAX_ADDR) { + size = SDRAM_MAX_ADDR - base - 1; +/* MV_REG_WRITE(SDRAM_SIZE_REG(cs), 0); */ + } + + temp = (MV_REG_READ(SDRAM_WIN_CTRL_REG(cs)) & ~(SDRAM_ADDR_MASK)) | (1<= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinSet: target %d is illegal\n", target); + return MV_ERROR; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); + return MV_BAD_PARAM; + } + + if (MV_TARGET_IS_DRAM(target)) { + /* copy relevant data to MV_DRAM_DEC_WIN structure */ + addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; + addrDecWin.enable = pAddrDecWin->enable; + + if (mvDramIfWinSet(target, &addrDecWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); + return MV_ERROR; + } + } else { + /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ + decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + decWin.addrWin.size = pAddrDecWin->addrWin.size; + decWin.enable = pAddrDecWin->enable; + decWin.target = target; + + existingWinNum = mvAhbToMbusWinTargetGet(target); + + /* check if there is already another Window configured + for this target */ + if ((existingWinNum < MAX_AHB_TO_MBUS_WINS) && (existingWinNum != pAddrDecWin->winNum)) { + /* if we want to enable the new window number + passed by the user , then the old one should + be disabled */ + if (MV_TRUE == pAddrDecWin->enable) { + /* be sure it is disabled */ + mvAhbToMbusWinEnable(existingWinNum, MV_FALSE); + } + } + + if (mvAhbToMbusWinSet(pAddrDecWin->winNum, &decWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_U32 winNum = 0xffffffff; + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinGet: target %d is illegal\n", target); + return MV_ERROR; + } + + if (MV_TARGET_IS_DRAM(target)) { + if (mvDramIfWinGet(target, &addrDecWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", target); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; + pAddrDecWin->enable = addrDecWin.enable; + pAddrDecWin->winNum = target; + } else { + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(target); + if (winNum >= MAX_AHB_TO_MBUS_WINS) + return MV_NO_SUCH; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", __func__, winNum); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = decWin.addrWin.size; + pAddrDecWin->enable = decWin.enable; + pAddrDecWin->winNum = winNum; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* target - Peripheral target enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other target window. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_U32 winNum, temp; + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinEnable: target %d is illegal\n", target); + return MV_ERROR; + } + + /* get the window and check if it exist */ + temp = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == temp) { + return (enable ? MV_ERROR : MV_OK); + } else if (MV_OK != temp) { + mvOsPrintf("%s: ERR. Getting target %d failed.\n", __func__, target); + return MV_ERROR; + } + + /* check overlap */ + if (MV_TRUE == enable) { + if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) { + DB(mvOsPrintf("%s: ERR. Target %d overlap\n", __func__, target)); + return MV_ERROR; + } + } + + if (MV_TARGET_IS_DRAM(target)) { + if (mvDramIfWinEnable(target, enable) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); + return MV_ERROR; + } + } else { + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(target); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + return (enable ? MV_ERROR : MV_OK); + + if (mvAhbToMbusWinEnable(winNum, enable) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", winNum); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinSizeGet - Get CPU target address window size +* +* DESCRIPTION: +* Get the size of CPU-to-peripheral target window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit size. Function also returns '0' if window is closed. +* Function returns 0xFFFFFFFF in case of an error. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is illegal\n", target); + return 0; + } + + /* Get the winNum window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", target); + return 0; + } + + /* Check if window is enabled */ + if (addrDecWin.enable == MV_TRUE) + return (addrDecWin.addrWin.size); + else + return 0; /* Window disabled. return 0 */ +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target low base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit low base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is illegal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + return 0xffffffff; + + return (addrDecWin.addrWin.baseLow); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target high base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit high base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is illegal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + return 0; + + return (addrDecWin.addrWin.baseHigh); +} + + +/******************************************************************************* +* mvCpuIfSramWinDisable +* +* DESCRIPTION: +* Disable the SRAM windows. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success. +* +*******************************************************************************/ +MV_STATUS mvCpuIfSramWinDisable(MV_VOID) +{ + MV_U32 i; + + for (i = 0; i < 4; i++) + MV_REG_WRITE(SRAM_WIN_CTRL_REG(i), SRAM_WIN_CTRL_DEFAULT_VAL); + + return MV_OK; +} + + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfPexRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pexTarget - Peripheral target enumerator. Must be a PEX target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PEX one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + if (mvCtrlPexMaxIfGet() > 1) { + if ((!MV_TARGET_IS_PEX0(pexTarget)) && + (!MV_TARGET_IS_PEX1(pexTarget))) { + mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget); + return 0xffffffff; + } + } else { + if (!MV_TARGET_IS_PEX0(pexTarget)) { + mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget); + return 0xffffffff; + } + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pexTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + } + + return mvAhbToMbusWinRemap(winNum, pAddrDecWin); +} +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCpuIfPciRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pciIfTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + } + + return mvAhbToMbusWinRemap(winNum, pAddrDecWin); +} +#endif + +/******************************************************************************* +* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address +* +* DESCRIPTION: +* +* INPUT: +* baseAddress - base address to be checked +* +* OUTPUT: +* None. +* +* RETURN: +* the target number that baseAddress belongs to or MAX_TARGETS is not +* found +* +*******************************************************************************/ +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + for (target = 0; target < MAX_TARGETS; target++) { + if (mvCpuIfTargetWinGet(target, &win) == MV_OK) { + if (win.enable) { + if ((baseAddress >= win.addrWin.baseLow) && + (baseAddress < win.addrWin.baseLow + win.addrWin.size)) + break; + } + } else + return MAX_TARGETS; + } + + return target; +} + +/******************************************************************************* +* cpuTargetWinOverlap - Detect CPU address decode windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case CPU address decode +* windows overlapps. +* This function detects CPU address decode windows overlapping of a +* specified target. The function does not check the target itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 targetNum; + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS status; + + for (targetNum = 0; targetNum < MAX_TARGETS; targetNum++) { + /* don't check our target or illegal targets */ + if (targetNum == target) + continue; + + /* Get window parameters */ + status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); + if (MV_NO_SUCH == status) + continue; + + if (MV_OK != status) { + DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); + return MV_TRUE; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) { + DB(mvOsPrintf("cpuTargetWinOverlap: Required target %d overlap current %d\n", + target, targetNum)); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvCpuIfAddDecShow - Print the CPU address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfAddDecShow(MV_VOID) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + mvOsOutput("\n"); + mvOsOutput("CPU Interface\n"); + mvOsOutput("-------------\n"); + + for (target = 0; target < MAX_TARGETS; target++) { + memset(&win, 0, sizeof(MV_CPU_DEC_WIN)); + + mvOsOutput("%s ", mvCtrlTargetNameGet(target)); + mvOsOutput("...."); + + if (mvCpuIfTargetWinGet(target, &win) == MV_OK) { + if (win.enable == MV_TRUE) { + mvOsOutput("base %08x, ", win.addrWin.baseLow); + mvSizePrint(win.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } else if (mvCpuIfTargetWinGet(target, &win) == MV_NO_SUCH) { + mvOsOutput("no such\n"); + } + } +} + diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIf.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIf.h new file mode 100755 index 000000000..d8b8d63d7 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIf.h @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfh +#define __INCmvCpuIfh + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/sys/mvAhbToMbus.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ + +/* typedefs */ +/* This structure describes CPU interface address decode window */ +typedef struct _mvCpuIfDecWin { + MV_ADDR_WIN addrWin; /* An address window */ + MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +} MV_CPU_DEC_WIN; + + +/* mvCpuIfLib.h API list */ + +/* mvCpuIfLib.h API list */ + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); +MV_STATUS mvCpuIfDramInit(MV_VOID); +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target, MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); +MV_STATUS mvCpuIfSramWinDisable(MV_VOID); +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +MV_VOID mvCpuIfAddDecShow(MV_VOID); + +MV_STATUS mvCpuIfLvdsPadsEnable(MV_BOOL enable); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCpuIfh */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIfInit.S b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIfInit.S new file mode 100755 index 000000000..4b7ad20b4 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIfInit.S @@ -0,0 +1,166 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvCommon.h" +#include "mvOsAsm.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvDeviceId.h" +#include "mvCtrlEnvRegs.h" +#include "mvCpuIfRegs.h" +#include "mvCtrlEnvAsm.h" + + +/******************************************************************************* +* mvCpuIfPreInit - Make early initialization of CPU interface. +* +* DESCRIPTION: +* The function will initialize the CPU interface parameters that must +* be initialize before any BUS activity towards the DDR interface, +* which means it must be executed from ROM. Because of that, the function +* is implemented in assembly code. +* The function configure the following CPU config register parameters: +* 1) CPU2MbusLTickDrv +* 2) CPU2MbusLTickSample. +* NOTE: This function must be called AFTER the internal register +* base is modified to INTER_REGS_BASE. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* r11 holds return function address. +*******************************************************************************/ +#define MV88F6281_PCKG_OPT 2 +#define MV88F6192_PCKG_OPT 1 +#define MV88F6180_PCKG_OPT 0 + + .globl _mvCpuIfPreInit +_mvCpuIfPreInit: + + mov r11, LR /* Save link register */ + b done +#if 0 + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* goto calcConfigReg if device is 6281/6282 */ + ldr r5, =MV88F6281_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* goto calcConfigReg if device is 6192/6190 */ + ldr r5, =MV88F6192_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* Else 6180 */ + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_CPUCLCK_MASK_6180 + and r5, r4, r5 + mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3_1 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4_1 + beq setConfigReg + b setConfigReg + +calcConfigReg: + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_DDRCLCK_RTIO_MASK + and r5, r4, r5 + mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4 + beq setConfigReg + + /* Else */ + ldr r4, =0 +setConfigReg: + /* Read CPU Config register */ + MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) + ldr r5, = ~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) + and r7, r7, r5 /* Clear register fields */ + orr r7, r7, r4 /* Set the values according to the findings */ + MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) +#endif + +done: + mov PC, r11 /* r11 is saved link register */ diff --git a/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIfRegs.h b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIfRegs.h new file mode 100755 index 000000000..eeb9c0f50 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/ctrlEnv/sys/mvCpuIfRegs.h @@ -0,0 +1,265 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfRegsh +#define __INCmvCpuIfRegsh + +/****************************************/ +/* ARM Control and Status Registers Map */ +/****************************************/ +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + +#define MV_CPUIF_REGS_BASE (MV_CPUIF_REGS_OFFSET(0)) +#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET) +#define MV_L2C_REGS_BASE (MV_AURORA_L2_REGS_OFFSET) +#define MV_CPUIF_SHARED_REGS_BASE (MV_MBUS_REGS_OFFSET) +#define MV_COHERENCY_FABRIC_REGS_BASE (MV_COHERENCY_FABRIC_OFFSET) + +#define CPU_CONFIG_REG (MV_CPUIF_REGS_BASE + 0x800) +#define CPU_CTRL_STAT_REG (MV_CPUIF_REGS_BASE + 0x808) +#define CPU_RSTOUTN_MASK_REG (MV_MISC_REGS_BASE + 0x60) +#define CPU_SYS_SOFT_RST_REG (MV_MISC_REGS_BASE + 0x64) +#define CPU_L2_CTRL_REG (MV_L2C_REGS_BASE + 0x100) +#define CPU_L2_AUX_CTRL_REG (MV_L2C_REGS_BASE + 0x104) +#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) +#define SOC_DEVICE_MUX_REG (MV_MISC_REGS_BASE + 0x8) +#define CPU_PEX_IO_CONF_5_REG (MV_MISC_REGS_OFFSET + 0x2F0) +#define SOC_DEVICE_MUX_NAND_SEL_OFFS 0 +#define SOC_COHERENCY_FABRIC_CTRL_REG (MV_COHERENCY_FABRIC_REGS_BASE) +#define SOC_COHERENCY_FABRIC_CFG_REG (MV_COHERENCY_FABRIC_REGS_BASE + 0x4) +#define SOC_CIB_CTRL_CFG_REG (MV_COHERENCY_FABRIC_REGS_BASE + 0x80) + +/* ARM Configuration register */ +/* CPU_CONFIG_REG (CCR) */ + +/* Reset vector location */ +#define CCR_VEC_INIT_LOC_OFFS 1 +#define CCR_VEC_INIT_LOC_MASK (1 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0x00000000 */ +#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0xFFFF0000 */ +#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) + +#define CCR_ENDIAN_INIT_OFFS 3 +#define CCR_ENDIAN_INIT_MASK (1 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) + +#define CCR_ARM_ID_SEL_OFFS 4 +#define CCR_CPU_ID_SEL_MASK (1 << CCR_ARM_ID_SEL_OFFS) +#define CCR_CPU_ID_SEL_ARM (0 << CCR_ARM_ID_SEL_OFFS) +#define CCR_CPU_ID_SEL_MRVL (1 << CCR_ARM_ID_SEL_OFFS) + +#define CCR_TE_INIT_OFFS 5 +#define CCR_TE_INIT_MASK (1 << CCR_TE_INIT_OFFS) +#define CCR_TE_INIT_ARM (0 << CCR_TE_INIT_OFFS) +#define CCR_TE_INIT_THUMB (1 << CCR_TE_INIT_OFFS) + +#define CCR_NFMI_EN_OFFS 6 +#define CCR_NFMI_EN_MASK (1 << CCR_NFMI_EN_OFFS) +#define CCR_NFMI_EN_DIS (0 << CCR_NFMI_EN_OFFS) +#define CCR_NFMI_EN_EN (1 << CCR_NFMI_EN_OFFS) + +#define CCR_CORE_MODE_OFFS 9 +#define CCR_CORE_MODE_MASK (3 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_ARM1176 (0 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_CORTEX_A8 (1 << CCR_CORE_MODE_OFFS) + +#define CCR_UBIT_INIT_OFFS 11 +#define CCR_UBIT_INIT_MASK (1 << CCR_UBIT_INIT_OFFS) +#define CCR_UBIT_INIT_DIS (0 << CCR_UBIT_INIT_OFFS) +#define CCR_UBIT_INIT_EN (1 << CCR_UBIT_INIT_OFFS) + +#define CCR_PCLK_WFI_OFFS 15 +#define CCR_PCLK_WFI_MASK (1 << CCR_PCLK_WFI_OFFS) +#define CCR_PCLK_WFI_DIS (0 << CCR_PCLK_WFI_OFFS) +#define CCR_PCLK_WFI_EN (1 << CCR_PCLK_WFI_OFFS) + +#define CCR_SRAM_LOW_LEAK_OFFS 19 +#define CCR_SRAM_LOW_LEAK_MASK (1 << CCR_SRAM_LOW_LEAK_OFFS) +#define CCR_SRAM_LOW_LEAK_EN (0 << CCR_SRAM_LOW_LEAK_OFFS) +#define CCR_SRAM_LOW_LEAK_DIS (1 << CCR_SRAM_LOW_LEAK_OFFS) + +#define CCR_CLUSTER_ID_OFFS 24 +#define CCR_CLUSTER_ID_MASK (0xF << CCR_SRAM_LOW_LEAK_OFFS) + + +/* ARM Control and Status register */ +/* CPU_CTRL_STAT_REG (CCSR) */ +#define CCSR_SMP_N_AMP_OFFS 0 +#define CCSR_SMP_N_AMP_MASK (1 << CCSR_SMP_N_AMP_OFFS) + +#define CCSR_ENDIAN_STATUS_OFFS 0 +#define CCSR_ENDIAN_STATUS_MASK (1 << CCSR_ENDIAN_STATUS_OFFS) +#define CCSR_ENDIAN_STATUS_LITTLE (0 << CCSR_ENDIAN_STATUS_OFFS) +#define CCSR_ENDIAN_STATUS_BIG (1 << CCSR_ENDIAN_STATUS_OFFS) + + +/* RSTOUTn Mask Register */ +/* CPU_RSTOUTN_MASK_REG (CRMR) */ + +#define CRMR_SOFT_RST_OUT_OFFS 0 +#define CRMR_SOFT_RST_OUT_MASK (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_DISABLE (0 << CRMR_SOFT_RST_OUT_OFFS) + +#define CRMR_PEX_SYSRST_OUT_OFFS(bus) (1 + ((bus) & 0x3)) +#define CRMR_PEX_SYSRST_OUT_MASK(bus) (1 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) +#define CRMR_PEX_SYSRST_OUT_ENABLE(bus) (1 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) +#define CRMR_PEX_SYSRST_OUT_DISABLE(bus) (0 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) + +#define CRMR_PEX_TRST_OUT_OFFS(bus) (5 + ((bus) & 0x3)) +#define CRMR_PEX_TRST_OUT_MASK(bus) (1 << CRMR_PEX_TRST_OUT_OFFS(bus)) +#define CRMR_PEX_TRST_OUT_ENABLE(bus) (1 << CRMR_PEX_TRST_OUT_OFFS(bus)) +#define CRMR_PEX_TRST_OUT_DISABLE(bus) (0 << CRMR_PEX_TRST_OUT_OFFS(bus)) + + +/* System Software Reset Register */ +/* CPU_SYS_SOFT_RST_REG (CSSRR) */ + +#define CSSRR_SYSTEM_SOFT_RST BIT0 + + +/* CPU_L2_CTRL_REG fields */ + +#define CL2CR_L2_EN_OFFS 0 +#define CL2CR_L2_EN_MASK (1 << CL2CR_L2_EN_OFFS) + +/* CPU_L2_AUX_CTRL_REG fields */ +#define CL2ACR_WB_WT_ATTR_OFFS 0 +#define CL2ACR_WB_WT_ATTR_MASK (3 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_PAGE (0 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_WB (1 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_WT (2 << CL2ACR_WB_WT_ATTR_OFFS) + +#define CL2ACR_ECC_OFFS 20 +#define CL2ACR_ECC_MASK (1 << CL2ACR_ECC_OFFS) +#define CL2ACR_ECC_EN (1 << CL2ACR_ECC_OFFS) +#define CL2ACR_ECC_DIS (0 << CL2ACR_ECC_OFFS) + +#define CL2ACR_PARITY_OFFS 21 +#define CL2ACR_PARITY_MASK (1 << CL2ACR_PARITY_OFFS) +#define CL2ACR_PARITY_EN (1 << CL2ACR_PARITY_OFFS) +#define CL2ACR_PARITY_DIS (0 << CL2ACR_PARITY_OFFS) + +#define CL2ACR_INVAL_UCE_OFFS 22 +#define CL2ACR_INVAL_UCE_MASK (1 << CL2ACR_INVAL_UCE_OFFS) +#define CL2ACR_INVAL_UCE_EN (1 << CL2ACR_INVAL_UCE_OFFS) +#define CL2ACR_INVAL_UCE_DIS (0 << CL2ACR_INVAL_UCE_OFFS) + +#define CL2ACR_FORCE_WA_OFFS 23 +#define CL2ACR_FORCE_WA_MASK (3 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_WA_DISABLE (0 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_NO_WA (1 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_WA (2 << CL2ACR_FORCE_WA_OFFS) + +#define CL2ACR_REP_STRGY_OFFS 27 +#define CL2ACR_REP_STRGY_MASK (3 << CL2ACR_REP_STRGY_OFFS) +#define CL2ACR_REP_STRGY_PLRU_MASK (1 << 28) + +/* SOC_CTRL_REG fields */ +#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3) +#define SCR_PEX_ENA_MASK(pex) (1 << pex) + + +/*******************************************/ +/* Main Interrupt Controller Registers Map */ +/*******************************************/ + +#define CPU_MAIN_INT_CAUSE_REG(vec) (MV_CPUIF_REGS_BASE + 0x880 + (vec * 0x4)) + +/* Special defines for TWSI HAL. */ +#define CPU_MAIN_INT_TWSI_OFFS(i) (2 + i) +#define CPU_MAIN_INT_CAUSE_TWSI(i) (31 + i) + +#define CPU_CF_LOCAL_MASK_REG (MV_CPUIF_REGS_BASE + 0x8c4) +#define CPU_INT_SOURCE_CONTROL_REG(i) (MV_CPUIF_SHARED_REGS_BASE + 0xB00 + (i * 0x4)) + +#define CPU_INT_SOURCE_CONTROL_ENA_OFFS 28 +#define CPU_INT_SOURCE_CONTROL_ENA_MASK (1 << CPU_INT_SOURCE_CONTROL_ENA_OFFS) + +#define CPU_INT_SOURCE_CONTROL_IRQ_OFFS 0 +#define CPU_INT_SOURCE_CONTROL_IRQ_MASK (1 << CPU_INT_SOURCE_CONTROL_IRQ_OFFS) + +#define MV_IRQ_NR 116 + + +/*******************************************/ +/* ARM Doorbell Registers Map */ +/*******************************************/ + +#define CPU_HOST_TO_ARM_DRBL_REG (MV_CPUIF_REGS_BASE + 0x878) +#define CPU_HOST_TO_ARM_MASK_REG (MV_CPUIF_REGS_BASE + 0x87C) +#define CPU_ARM_TO_HOST_DRBL_REG (MV_CPUIF_REGS_BASE + 0x870) +#define CPU_ARM_TO_HOST_MASK_REG (MV_CPUIF_REGS_BASE + 0x874) + + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK) +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) + +#endif /* __INCmvCpuIfRegsh */ diff --git a/arch/arm/mach-armada370/armada_370_family/device/mvDevice.c b/arch/arm/mach-armada370/armada_370_family/device/mvDevice.c new file mode 100755 index 000000000..74c7f27dd --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/device/mvDevice.c @@ -0,0 +1,291 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "device/mvDevice.h" + +/* defines */ +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/******************************************************************************* +* mvDevPramSet - Set device interface bank parameters +* +* DESCRIPTION: +* This function sets a device bank parameters to a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* *pDevParams - Device bank parameter struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + } + if (pDevParams->turnOff > MAX_DBP_TURNOFF) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->turnOff out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2First > MAX_DBP_ACC2FIRST) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2First out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2Next > MAX_DBP_ACC2NEXT) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2Next out of range\n")); + return MV_ERROR; + } + if (pDevParams->ale2Wr > MAX_DBP_ALE2WR) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrLow > MAX_DBP_WRLOW) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrHigh > MAX_DBP_WRHIGH) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if ((pDevParams->badrSkew << DBP_BADRSKEW_OFFS) > DBP_BADRSKEW_2CYCLE) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->badrSkew out of range\n")); + return MV_ERROR; + } + if ((pDevParams->deviceWidth != 8) && (pDevParams->deviceWidth != 16) && (pDevParams->deviceWidth != 32)) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth out of range\n")); + return MV_ERROR; + } + + /* devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); */ + /* setting values */ + devParam |= DBP_TURNOFF_SET(pDevParams->turnOff); + devParam |= DBP_ACC2FIRST_SET(pDevParams->acc2First); + devParam |= DBP_ACC2NEXT_SET(pDevParams->acc2Next); + devParam |= ((pDevParams->badrSkew & DBP_BADRSKEW_MASK) << DBP_BADRSKEW_OFFS); + + switch (pDevParams->deviceWidth) { + case 8: + devParam |= DBP_DEVWIDTH_8BIT; + break; + case 16: + devParam |= DBP_DEVWIDTH_16BIT; + break; + case 32: + devParam |= DBP_DEVWIDTH_32BIT; + break; + default: + return MV_ERROR; + } + + MV_REG_WRITE(DEV_BANK_PARAM_REG(device), devParam); + + devParam = 0; + devParam |= DBP_ALE2WR_SET(pDevParams->ale2Wr); + devParam |= DBP_WRLOW_SET(pDevParams->wrLow); + devParam |= DBP_WRHIGH_SET(pDevParams->wrHigh); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(device), devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevPramget - Get device interface bank parameters +* +* DESCRIPTION: +* This function retrieves a device bank parameter settings. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* *pDevParams - Device bank parameter struct. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + pDevParams->turnOff = DBP_TURNOFF_GET(devParam); + pDevParams->acc2First = DBP_ACC2FIRST_GET(devParam); + pDevParams->acc2Next = DBP_ACC2NEXT_GET(devParam); + pDevParams->badrSkew = (devParam & DBP_BADRSKEW_MASK) >> DBP_BADRSKEW_OFFS; + + switch (devParam & DBP_DEVWIDTH_MASK) { + case DBP_DEVWIDTH_8BIT: + pDevParams->deviceWidth = 8; + break; + case DBP_DEVWIDTH_16BIT: + pDevParams->deviceWidth = 16; + break; + case DBP_DEVWIDTH_32BIT: + pDevParams->deviceWidth = 32; + break; + default: + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth non valid value\n")); + return MV_ERROR; + break; + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG_WR(device)); + pDevParams->ale2Wr = DBP_ALE2WR_GET(devParam); + pDevParams->wrLow = DBP_WRLOW_GET(devParam); + pDevParams->wrHigh = DBP_WRHIGH_GET(devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevWidthGet - Get device width parameter +* +* DESCRIPTION: +* This function gets width parameter of a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* Device width in bits (8,16,32...). +* +*******************************************************************************/ +MV_U32 mvDevWidthGet(MV_DEVICE device) +{ + MV_U32 devParam; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + devParam = (devParam & DBP_DEVWIDTH_MASK) >> DBP_DEVWIDTH_OFFS; + + return (MV_U32) (0x8 << devParam); + +} + +/******************************************************************************* +* mvDevNandDevCsSet - Set NAND chip-select, care mode and init sequence +* +* DESCRIPTION: +* This function set the NAND flash controller registers with NAND +* device chip-select. +* +* INPUT: +* devNum - Device number. See MV_DEVICE enumerator. +* careMode - NAND device care mode (0 = Don't care, '1' = care). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode) +{ + MV_U32 nfCtrlReg; /* NAND Flash Control Register */ + + /* Set chip select */ + nfCtrlReg = MV_REG_READ(DEV_NAND_CTRL_REG); + + nfCtrlReg |= (DINFCR_NF_CS_MASK(device)); + + if (careMode) + nfCtrlReg |= (DINFCR_NF_ACT_CE_MASK(device)); + else + nfCtrlReg &= ~(DINFCR_NF_ACT_CE_MASK(device)); + + MV_REG_WRITE(DEV_NAND_CTRL_REG, nfCtrlReg); +} diff --git a/arch/arm/mach-armada370/armada_370_family/device/mvDevice.h b/arch/arm/mach-armada370/armada_370_family/device/mvDevice.h new file mode 100755 index 000000000..2f7d33f12 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/device/mvDevice.h @@ -0,0 +1,99 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceH +#define __INCmvDeviceH + +#include "device/mvDeviceRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* This structure describes device interface parameters to be assigned to */ +/* device bank parameter */ +typedef struct _mvDeviceParam { + /* boundary values */ + MV_U32 turnOff; /* 0x0 - 0xf */ + MV_U32 acc2First; /* 0x0 - 0x1f */ + MV_U32 acc2Next; /* 0x0 - 0x1f */ + MV_U32 ale2Wr; /* 0x0 - 0xf */ + MV_U32 wrLow; /* 0x0 - 0xf */ + MV_U32 wrHigh; /* 0x0 - 0xf */ + MV_U32 badrSkew; /* 0x0 - 0x2 */ + MV_U32 deviceWidth; /* in Bytes */ +} MV_DEVICE_PARAM; + + +/* mvDevPramSet - Set device interface bank parameters */ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevPramget - Get device interface bank parameters */ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevWidthGet - Get device width parameter*/ +MV_U32 mvDevWidthGet(MV_DEVICE device); + +/* mvDevNandDevCsSet - Set the NAND flash control registers with NAND device- */ +/* select and care mode */ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode); + +#endif /* #ifndef __INCmvDeviceH */ diff --git a/arch/arm/mach-armada370/armada_370_family/device/mvDeviceRegs.h b/arch/arm/mach-armada370/armada_370_family/device/mvDeviceRegs.h new file mode 100755 index 000000000..413abd8c1 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/device/mvDeviceRegs.h @@ -0,0 +1,268 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceRegsH +#define __INCmvDeviceRegsH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_DEVICE_MAX_XBAR_TIMEOUT 0x0FFF +/* registers offsets */ + +static INLINE MV_U32 DEV_BANK_PARAM_REG(int num) +{ + switch (num) { + case (DEV_BOOCS): + return MV_DEV_BUS_REGS_OFFSET + 0x00; + case (DEVICE_CS0): + return MV_DEV_BUS_REGS_OFFSET + 0x08; + case (DEVICE_CS1): + return MV_DEV_BUS_REGS_OFFSET + 0x10; +#ifdef MV_INCLUDE_DEVICE_CS2 + case (DEVICE_CS2): + return MV_DEV_BUS_REGS_OFFSET + 0x18; +#endif +#ifdef MV_INCLUDE_DEVICE_CS3 + case (DEVICE_CS3): + return MV_DEV_BUS_REGS_OFFSET + 0x20; +#endif + default: + return 0xFFFFFFFF; + } +} + +#define DEV_BANK_PARAM_REG_WR(num) (DEV_BANK_PARAM_REG(num)+0x4) +#define DEV_NAND_CTRL_REG (MV_DEV_BUS_REGS_OFFSET + 0x0470) +#define DEV_BUS_SYNC_CTRL (MV_DEV_BUS_REGS_OFFSET + 0xC8) + +/* Device Bank Parameters register fields (DBP_REG)*/ +/* Boot Device Bank Parameters (DBP) register fields (DEV_BOOT_BANK_PARAM_REG)*/ +/* DBP_XXX_MASK_HIGH is the offset of the extend bit from the msb of the input value */ + +#define DBP_TURNOFF_OFFS_LOW 0 +#define DBP_TURNOFF_MASK_LOW 0x3F +#define MAX_DBP_TURNOFF 0xf + + +#define DBP_TURNOFF_SET(value) \ +((value & DBP_TURNOFF_MASK_LOW) << DBP_TURNOFF_OFFS_LOW) + +#define DBP_TURNOFF_GET(value) \ +((value >> DBP_TURNOFF_OFFS_LOW) & DBP_TURNOFF_MASK_LOW) + +#define DBP_ACC2FIRST_OFFS_LOW 6 +#define DBP_ACC2FIRST_MASK_LOW 0x3f +#define MAX_DBP_ACC2FIRST 0x3f + +#define DBP_ACC2FIRST_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2FIRST_GET(value) \ +((value >> DBP_ACC2FIRST_OFFS_LOW) & DBP_ACC2FIRST_MASK_LOW) + +#define DBP_ACC2NEXT_OFFS_LOW 17 +#define DBP_ACC2NEXT_MASK_LOW 0x3f +#define MAX_DBP_ACC2NEXT 0x3f + +#define DBP_ACC2NEXT_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2NEXT_GET(value) \ +((value >> DBP_ACC2NEXT_OFFS_LOW) & DBP_ACC2NEXT_MASK_LOW) + +#define DBP_DEVWIDTH_OFFS 30 /* Device Width */ +#define DBP_DEVWIDTH_MASK (0x3 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_8BIT (0x0 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_16BIT (0x1 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_32BIT (0x2 << DBP_DEVWIDTH_OFFS) + +#define DBP_BADRSKEW_OFFS 28 +#define DBP_BADRSKEW_MASK (0x3 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_NOGAP (0x0 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_1CYCLE (0x1 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_2CYCLE (0x2 << DBP_BADRSKEW_OFFS) + + +#define DBP_ALE2WR_OFFS_LOW 0 +#define DBP_ALE2WR_MASK_LOW 0x3f +#define MAX_DBP_ALE2WR 0x3F + +#define DBP_ALE2WR_SET(value) \ +((value & DBP_ALE2WR_MASK_LOW) << DBP_ALE2WR_OFFS_LOW) + +#define DBP_ALE2WR_GET(value) \ +((value >> DBP_ALE2WR_OFFS_LOW) & DBP_ALE2WR_MASK_LOW) + +#define DBP_WRLOW_OFFS_LOW 8 +#define DBP_WRLOW_MASK_LOW 0x3F +#define MAX_DBP_WRLOW 0x3F + +#define DBP_WRLOW_SET(value) \ +((value & DBP_WRLOW_MASK_LOW) << DBP_WRLOW_OFFS_LOW) + +#define DBP_WRLOW_GET(value) \ +((value >> DBP_WRLOW_OFFS_LOW) & DBP_WRLOW_MASK_LOW) + +#define DBP_WRHIGH_OFFS_LOW 16 +#define DBP_WRHIGH_MASK_LOW 0x3F +#define MAX_DBP_WRHIGH 0x3F + +#define DBP_WRHIGH_SET(value) \ +((value & DBP_WRHIGH_MASK_LOW) << DBP_WRHIGH_OFFS_LOW) + +#define DBP_WRHIGH_GET(value) \ +((value >> DBP_WRHIGH_OFFS_LOW) & DBP_WRHIGH_MASK_LOW) + + +/* Device Interface Control register fields (DIC) (DIC_REG)*/ +#define DIC_TIMEOUT_OFFS 0 /* Timeout Timer Preset Value. */ +#define DIC_TIMEOUT_MASK (0xffff << DIC_TIMEOUT_OFFS) +#define MAX_DIC_TIMEOUT 0xffff + +/* NAND Flash Control register fields (NF) (NF_REG)*/ +#define NF_BOOTCS_OFFS 0 /* Define if BOOTCS is connected to NAND Flash */ +#define NF_BOOT_MASK (1 << NF_BOOTCS_OFFS) +#define NF_BOOT_NC (0 << NF_BOOTCS_OFFS) +#define NF_BOOT_C (1 << NF_BOOTCS_OFFS) + +#define NF_BOOTCS_CE_ACT_OFFS 1 /* Define if NAND Flash on BOOTCS is CE care or CE don't care */ +#define NF_BOOTCS_CE_ACT_MASK (1 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_NCARE (0 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_CARE (1 << NF_BOOTCS_CE_ACT_OFFS) + +#define NF_CS0_OFFS 2 /* Define if CS0 is connected to NAND Flash */ +#define NF_CS0_MASK (1 << NF_CS0_OFFS) +#define NF_CS0_NC (0 << NF_CS0_OFFS) +#define NF_CS0_C (1 << NF_CS0_OFFS) + +#define NF_CS0_CE_ACT_OFFS 3 /* Define if NAND Flash on CS0 is CE care or CE don't care */ +#define NF_CS0_CE_ACT_MASK (1 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_NCARE (0 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_CARE (1 << NF_CS0_CE_ACT_OFFS) + +#define NF_CS1_OFFS 4 /* Define if CS1 is connected to NAND Flash */ +#define NF_CS1_MASK (1 << NF_CS1_OFFS) +#define NF_CS1_NC (0 << NF_CS1_OFFS) +#define NF_CS1_C (1 << NF_CS1_OFFS) + +#define NF_CS1_CE_ACT_OFFS 5 /* Define if NAND Flash on CS1 is CE care or CE don't care */ +#define NF_CS1_CE_ACT_MASK (1 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_NCARE (0 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_CARE (1 << NF_CS1_CE_ACT_OFFS) + +#define NF_CS2_OFFS 6 /* Define if CS2 is connected to NAND Flash */ +#define NF_CS2_MASK (1 << NF_CS2_OFFS) +#define NF_CS2_NC (0 << NF_CS2_OFFS) +#define NF_CS2_C (1 << NF_CS2_OFFS) + +#define NF_CS2_CE_ACT_OFFS 7 /* Define if NAND Flash on CS2 is CE care or CE don't care */ +#define NF_CS2_CE_ACT_MASK (1 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_NCARE (0 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_CARE (1 << NF_CS2_CE_ACT_OFFS) + +#define NF_INIT_SEQ_OFFS 8 /* NAND Flash initialization sequence */ +#define NF_INIT_SEQ_MASK (1 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_EN (0 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_DIS (1 << NF_INIT_SEQ_OFFS) + +#define NF_OE_HIGHW_OFFS 9 /* NAND Flash OE high width in core clocks units (value + 1) */ +#define NF_OE_HIGHW_MASK (0x1f << NF_OE_HIGHW_OFFS) +#define MAX_OE_HIGHW (0x1f << NF_OE_HIGHW_OFFS) + +#define NF_TREADY_OFFS 14 /* NAND Flash time ready in core clocks units (value + 1) */ +#define NF_TREADY_MASK (0x1f << NF_TREADY_OFFS) +#define MAX_TREADY (0x1f << NF_TREADY_OFFS) + +#define NF_OE_TCTRL_OFFS 19 /* NAND Flash OE toggle control */ +#define NF_OE_TCTRL_MASK (1 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_1_CYC_AFT (0 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_SAME_CYC (1 << NF_OE_TCTRL_OFFS) + +#define NF_CS3_OFFS 20 /* Define if CS3 is connected to NAND Flash */ +#define NF_CS3_MASK (1 << NF_CS3_OFFS) +#define NF_CS3_NC (0 << NF_CS3_OFFS) +#define NF_CS3_C (1 << NF_CS3_OFFS) + +#define NF_CS3_CE_ACT_OFFS 21 /* Define if NAND Flash on CS3 is CE care or CE don't care */ +#define NF_CS3_CE_ACT_MASK (1 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_NCARE (0 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_CARE (1 << NF_CS3_CE_ACT_OFFS) + + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) \ +(csNum == BOOT_CS) ? 0x1 : ((csNum == DEV_CS3) ? (0x1 << 20) : (0x1 << (((csNum+1) % MV_DEV_MAX_CS) * 2))) + + +#define DINFCR_NF_ACT_CE_MASK(csNum) \ +(csNum == DEV_CS3) ? (0x2 << 20) : (0x2 << (((csNum+1) % MV_DEV_MAX_CS) * 2)) + +#define NAND_ACTCEBOOT_BIT BIT1 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #ifndef __INCmvDeviceRegsH */ diff --git a/arch/arm/mach-armada370/armada_370_family/version.txt b/arch/arm/mach-armada370/armada_370_family/version.txt new file mode 100755 index 000000000..0a33871d1 --- /dev/null +++ b/arch/arm/mach-armada370/armada_370_family/version.txt @@ -0,0 +1 @@ +2013_Q1.0 diff --git a/arch/arm/mach-armada370/clock.c b/arch/arm/mach-armada370/clock.c new file mode 100755 index 000000000..15b04ae98 --- /dev/null +++ b/arch/arm/mach-armada370/clock.c @@ -0,0 +1,50 @@ +/* + * linux/arch/arm/mach-dove/clock.c + */ + +/* TODO: Implement the functions below... */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clock.h" + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_get_rate); + + +void clks_register(struct clk *clks, size_t num) +{ +} + +static int __init clk_init(void) +{ + /* TODO: Call clks_register with appropriate params. */ + clks_register(NULL, 0); + return 0; +} +arch_initcall(clk_init); diff --git a/arch/arm/mach-armada370/clock.h b/arch/arm/mach-armada370/clock.h new file mode 100755 index 000000000..3fd3a3bcc --- /dev/null +++ b/arch/arm/mach-armada370/clock.h @@ -0,0 +1,5 @@ +struct clk { + unsigned int dummy; +}; + +void clks_register(struct clk *clks, size_t num); diff --git a/arch/arm/mach-armada370/config/mvRules.mk b/arch/arm/mach-armada370/config/mvRules.mk new file mode 100755 index 000000000..9e129fe9f --- /dev/null +++ b/arch/arm/mach-armada370/config/mvRules.mk @@ -0,0 +1,175 @@ +# This flags will be used only by the Marvell arch files compilation. + +################################################################################################### +# General definitions +################################################################################################### +CPU_ARCH = ARM +CHIP = 88F78xx0 +VENDOR = Marvell +ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) +ENDIAN = BE +else +ENDIAN = LE +endif + +################################################################################################### +# directory structure +################################################################################################### +# Main directory structure +PLAT_PATH = ../plat-armada +PLAT_DRIVERS = $(PLAT_PATH)/mv_drivers_lsp +HAL_DIR = $(PLAT_PATH)/mv_hal +COMMON_DIR = $(PLAT_PATH)/common +OSSERV_DIR = $(PLAT_PATH)/linux_oss +CONFIG_DIR = config +HAL_IF = mv_hal_if + +# HALs +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/flash +HAL_RTC_DIR = $(HAL_DIR)/rtc/integ_rtc +HAL_VOICEBAND = $(HAL_DIR)/voiceband +HAL_SLIC_DIR = $(HAL_VOICEBAND)/slic +HAL_DAA_DIR = $(HAL_VOICEBAND)/daa +HAL_SATA_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_QD_DIR = $(HAL_DIR)/qd-dsdt +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_DRAM_DIR = $(HAL_DIR)/ddr2_3 +HAL_DRAM_SPD_DIR = $(HAL_DIR)/ddr2_3/spd +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(SOC_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_UART_DIR = $(HAL_DIR)/uart + +ifeq ($(CONFIG_MV_ETH_NETA),y) +HAL_ETH_DIR = $(HAL_DIR)/neta +HAL_ETH_GBE_DIR = $(HAL_DIR)/neta/gbe +HAL_ETH_NFP_DIR = $(HAL_DIR)/neta/nfp +HAL_ETH_PNC_DIR = $(HAL_DIR)/neta/pnc +HAL_ETH_BM_DIR = $(HAL_DIR)/neta/bm +HAL_ETH_PMT_DIR = $(HAL_DIR)/neta/pmt +LSP_NETWORK_DIR = $(PLAT_DRIVERS)/mv_neta +LSP_NET_DEV_DIR = $(LSP_NETWORK_DIR)/net_dev +LSP_NFP_MGR_DIR = $(LSP_NETWORK_DIR)/nfp_mgr +LSP_PNC_DIR = $(LSP_NETWORK_DIR)/pnc +LSP_PMT_DIR = $(LSP_NETWORK_DIR)/pmt +LSP_HWF_DIR = $(LSP_NETWORK_DIR)/hwf +LSP_L2FW_DIR = $(LSP_NETWORK_DIR)/l2fw +LSP_SWITCH_DIR = $(PLAT_DRIVERS)/mv_switch +endif + +ifeq ($(CONFIG_MV_ETH_LEGACY),y) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_DIR)/eth/gbe +HAL_ETH_NFP_DIR = $(HAL_DIR)/eth/nfp +LSP_NETWORK_DIR = $(PLAT_DRIVERS)/mv_network +LSP_NET_DEV_DIR = $(LSP_NETWORK_DIR)/mv_etherent +LSP_NFP_MGR_DIR = $(LSP_NETWORK_DIR)/nfp_mgr +endif + +HAL_CPU_DIR = $(HAL_DIR)/cpu +HAL_SDMMC_DIR = $(HAL_DIR)/sdmmc +ifeq ($(CONFIG_MV_INCLUDE_PEX),y) +HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PEX_DIR = $(HAL_DIR)/pex +endif +ifeq ($(CONFIG_MV_INCLUDE_TDM),y) +HAL_TDM_DIR = $(HAL_DIR)/voiceband/tdm +endif +ifeq ($(CONFIG_MV_INCLUDE_USB),y) +HAL_USB_DIR = $(HAL_DIR)/usb +endif +ifeq ($(CONFIG_MV_INCLUDE_CESA),y) +HAL_CESA_DIR = $(HAL_DIR)/cesa +HAL_CESA_AES_DIR = $(HAL_DIR)/cesa/AES +endif +ifeq ($(CONFIG_MV_INCLUDE_XOR),y) +HAL_XOR_DIR = $(HAL_DIR)/xor +endif +ifeq ($(CONFIG_MV_INCLUDE_SPI),y) +HAL_SPI_DIR = $(HAL_DIR)/spi +endif +ifeq ($(CONFIG_MV_INCLUDE_AUDIO),y) +HAL_AUDIO_DIR = $(HAL_DIR)/audio +endif +ifeq ($(CONFIG_MV_INCLUDE_NFC),y) +HAL_NFC_DIR = $(HAL_DIR)/nfc +endif + +# Environment components +ARMADA370_FAM_DIR = armada_370_family +SOC_DEVICE_DIR = $(ARMADA370_FAM_DIR)/device +SOC_CPU_DIR = $(ARMADA370_FAM_DIR)/cpu +BOARD_ENV_DIR = $(ARMADA370_FAM_DIR)/boardEnv +SOC_ENV_DIR = $(ARMADA370_FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(ARMADA370_FAM_DIR)/ctrlEnv/sys +HAL_IF_DIR = mv_hal_if + +##################################################################################################### +# Include path +################################################################################################### + +LSP_PATH_I = $(srctree)/arch/arm/mach-armada370 +PLAT_PATH_I = $(srctree)/arch/arm/plat-armada + +HAL_PATH = -I$(PLAT_PATH_I)/$(HAL_DIR) -I$(PLAT_PATH_I)/$(HAL_SATA_DIR) -I$(PLAT_PATH_I)/$(HAL_ETH_DIR) +ARMADA370_FAM_PATH = -I$(LSP_PATH_I)/$(ARMADA370_FAM_DIR) +QD_PATH = -I$(PLAT_PATH_I)/$(HAL_QD_DIR)/Include -I$(PLAT_PATH_I)/$(HAL_QD_DIR)/Include/h/msApi \ + -I$(PLAT_PATH_I)/$(HAL_QD_DIR)/Include/h/driver -I$(PLAT_PATH_I)/$(HAL_QD_DIR)/Include/h/platform + +COMMON_PATH = -I$(PLAT_PATH_I)/$(COMMON_DIR) -I$(srctree) + +OSSERV_PATH = -I$(PLAT_PATH_I)/$(OSSERV_DIR) +LSP_PATH = -I$(LSP_PATH_I) +CONFIG_PATH = -I$(LSP_PATH_I)/$(CONFIG_DIR) +HAL_IF_PATH = -I$(LSP_PATH_I)/$(HAL_IF) +DRIVERS_LSP_PATH = -I$(PLAT_PATH_I)/$(PLAT_DRIVERS) -I$(PLAT_PATH_I)/$(LSP_NETWORK_DIR) \ + -I$(PLAT_PATH_I)/$(LSP_SWITCH_DIR) + +EXTRA_INCLUDE = $(OSSERV_PATH) $(COMMON_PATH) $(HAL_PATH) $(ARMADA370_FAM_PATH) \ + $(LSP_PATH) $(CONFIG_PATH) $(DRIVERS_LSP_PATH) $(HAL_IF_PATH) + +################################################################################################### +# defines +################################################################################################### +MV_DEFINE = -DMV_LINUX -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + + +ifeq ($(CONFIG_MV_GATEWAY),y) +EXTRA_INCLUDE += $(QD_PATH) +EXTRA_CFLAGS += -DLINUX +endif + +ifeq ($(CONFIG_MV_INCLUDE_SWITCH),y) +EXTRA_INCLUDE += $(QD_PATH) +EXTRA_CFLAGS += -DLINUX +endif + +ifeq ($(CONFIG_MV_CESA_TEST),y) +EXTRA_CFLAGS += -DCONFIG_MV_CESA_TEST +endif + +ifeq ($(CONFIG_SATA_DEBUG_ON_ERROR),y) +EXTRA_CFLAGS += -DMV_LOG_ERROR +endif + +ifeq ($(CONFIG_SATA_FULL_DEBUG),y) +EXTRA_CFLAGS += -DMV_LOG_DEBUG +endif + +ifeq ($(CONFIG_MV_SATA_SUPPORT_ATAPI),y) +EXTRA_CFLAGS += -DMV_SUPPORT_ATAPI +endif + +ifeq ($(CONFIG_MV_SATA_ENABLE_1MB_IOS),y) +EXTRA_CFLAGS += -DMV_SUPPORT_1MBYTE_IOS +endif + +ifeq ($(CONFIG_MV_CESA_CHAIN_MODE_SUPPORT),y) +EXTRA_CFLAGS += -DMV_CESA_CHAIN_MODE_SUPPORT +endif + +EXTRA_CFLAGS += $(EXTRA_INCLUDE) $(MV_DEFINE) + +EXTRA_AFLAGS += $(EXTRA_CFLAGS) diff --git a/arch/arm/mach-armada370/config/mvSysAudioConfig.h b/arch/arm/mach-armada370/config/mvSysAudioConfig.h new file mode 100755 index 000000000..ef45d19fb --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysAudioConfig.h @@ -0,0 +1,42 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysAudioConfig.h - Marvell Audio unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for audio registers. +*/ +#define MV_AUDIO_REGS_BASE(unit) (MV_AUDIO_REGS_OFFSET(unit)) + +/* +** Don't perform decoding / playback address decoding fix in the HAL, as it +** will be done in the Audio driver. +*/ +#define MV_AUDIO_SKIP_WIN_DECODING diff --git a/arch/arm/mach-armada370/config/mvSysCesaConfig.h b/arch/arm/mach-armada370/config/mvSysCesaConfig.h new file mode 100755 index 000000000..1991be280 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysCesaConfig.h @@ -0,0 +1,53 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysCesaConfig.h - Marvell Cesa unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +//#include "mvSysHwConfig.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* +** Base address for cesa registers. +*/ +#define MV_CESA_REGS_BASE(chan) (MV_CESA_REGS_OFFSET(chan)) + +#define MV_CESA_TDMA_REGS_BASE(chan) (MV_CESA_TDMA_REGS_OFFSET(chan)) + +#define MV_CESA_CHANNELS (CONFIG_MV_CESA_CHANNELS) + +#ifdef CONFIG_MV_CESA_TEST + #define MV_CESA_TEST +#endif + +#ifdef CONFIG_MV_CESA_CHAIN_MODE + #define MV_CESA_CHAIN_MODE +#endif + +#ifdef CONFIG_MV_CESA_INT_PER_PACKET + #define MV_CESA_INT_PER_PACKET +#endif diff --git a/arch/arm/mach-armada370/config/mvSysCntmrConfig.h b/arch/arm/mach-armada370/config/mvSysCntmrConfig.h new file mode 100755 index 000000000..b6646ae4e --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysCntmrConfig.h @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysCntmrConfig.h - Marvell Counter Manager unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for counter manager registers. +*/ +#define MV_CNTMR_REGS_BASE (MV_CNTMR_REGS_OFFSET) diff --git a/arch/arm/mach-armada370/config/mvSysDdrConfig.h b/arch/arm/mach-armada370/config/mvSysDdrConfig.h new file mode 100755 index 000000000..6dfd4461c --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysDdrConfig.h @@ -0,0 +1,44 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysDdrConfig.h - Marvell DRAM controller unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for DDR registers. +*/ +#define MV_DDR_WIN_REGS_BASE (MV_MBUS_REGS_OFFSET) +#define MV_DDR_CTRL_REGS_BASE (MV_DRAM_REGS_OFFSET) + +/* used for ddr2 "bak" files */ +#define MV_DDR_REGS_BASE (MV_DRAM_REGS_OFFSET) + +#ifndef MV_BOOTROM +#define MV_STATIC_DRAM_ON_BOARD +#endif diff --git a/arch/arm/mach-armada370/config/mvSysEthConfig.h b/arch/arm/mach-armada370/config/mvSysEthConfig.h new file mode 100755 index 000000000..23df325ae --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysEthConfig.h @@ -0,0 +1,151 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysEthConfig.h - Marvell Ethernet unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvSysEthConfig_h__ +#define __mvSysEthConfig_h__ + +#include "mvSysHwConfig.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* +** Base address for ethernet registers. +*/ +#ifdef CONFIG_MV_PON +#define MV_PON_PORT(p) ((p) == MV_PON_PORT_ID) +#define MV_PON_REG_BASE MV_PON_REGS_OFFSET +#define MV_ETH_REGS_BASE(p) (MV_PON_PORT(p) ? MV_PON_REGS_OFFSET : MV_ETH_REGS_OFFSET(p)) +#else +#define MV_PON_PORT(p) MV_FALSE +#define MV_ETH_REGS_BASE(p) MV_ETH_REGS_OFFSET(p) +#endif /* CONFIG_MV_PON */ + +#define MV_BM_REG_BASE MV_BM_REGS_OFFSET +#define MV_PNC_REG_BASE MV_PNC_REGS_OFFSET +#define MV_ETH_SGMII_PHY_REGS_BASE(p) MV_ETH_SGMII_PHY_REGS_OFFSET(p) + +#if defined(CONFIG_MV_INCLUDE_GIG_ETH) + +/* put descriptors in uncached memory */ +/* #define ETH_DESCR_UNCACHED */ + +/* port's default queueus */ +#define ETH_DEF_RXQ 0 + +#ifdef CONFIG_MV_ETH_LEGACY + +#ifdef CONFIG_MV_NFP_STATS +#define MV_FP_STATISTICS +#else +#undef MV_FP_STATISTICS +#endif + +/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ +#define MV_ETH_TX_EN_DEFAULT 0 + +/* un-comment if you want to perform tx_done from within the poll function */ +/* #define ETH_TX_DONE_ISR */ + +/* Descriptors location: DRAM/internal-SRAM */ +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ + +#if defined(ETH_DESCR_IN_SRAM) +#if defined(ETH_DESCR_UNCACHED) + #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" +#else + #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" +#endif +#elif defined(ETH_DESCR_IN_SDRAM) +#if defined(ETH_DESCR_UNCACHED) + #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" +#else + #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" +#endif +#else + #error "Ethernet descriptors location undefined" +#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ + +/* SW Sync-Barrier: not relevant for 88fxx81*/ +/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ +/* In RX the CPU theoretically might see himself as the descriptor owner, */ +/* although the buffer hadn't been written to DRAM yet. Performance cost. */ +/* #define INCLUDE_SYNC_BARR */ + +/* Buffers cache coherency method (buffers in DRAM) */ +#ifndef MV_CACHE_COHER_SW +/* Taken from mvCommon.h */ +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + +#endif + +#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) + #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) + #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) + #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "DRAM uncached" +#else + #error "Ethernet-DRAM undefined" +#endif /* ETHER_DRAM_COHER */ + + +/****************************************************************/ +/************* Ethernet driver configuration ********************/ +/****************************************************************/ + +/* port's default queueus */ +#define ETH_DEF_TXQ 0 + +#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RXQ +#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TXQ + +/* interrupt coalescing setting */ +#define ETH_TX_COAL 200 +#define ETH_RX_COAL 200 + +/* Checksum offloading */ +#define TX_CSUM_OFFLOAD +#define RX_CSUM_OFFLOAD +#endif /* CONFIG_MV_ETH_LEGACY */ + +#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ + +#endif /* __mvSysEthConfig_h__ */ diff --git a/arch/arm/mach-armada370/config/mvSysEthPhyConfig.h b/arch/arm/mach-armada370/config/mvSysEthPhyConfig.h new file mode 100755 index 000000000..ce9ff4a72 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysEthPhyConfig.h @@ -0,0 +1,31 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysEthPhyConfig.h - Marvell Ethernet-PHY specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" diff --git a/arch/arm/mach-armada370/config/mvSysGppConfig.h b/arch/arm/mach-armada370/config/mvSysGppConfig.h new file mode 100755 index 000000000..7e37a905a --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysGppConfig.h @@ -0,0 +1,37 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysGppConfig.h - Marvell GPP unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for GPP registers. +*/ +#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit)) +#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET(0)) diff --git a/arch/arm/mach-armada370/config/mvSysHwConfig.h b/arch/arm/mach-armada370/config/mvSysHwConfig.h new file mode 100755 index 000000000..ffc706e30 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysHwConfig.h @@ -0,0 +1,226 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvSysHwConfigh +#define __INCmvSysHwConfigh + +#define CONFIG_MARVELL 1 + +/* includes */ +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +/****************************************/ +/* Soc supporeted Units definitions */ +/****************************************/ + +#ifdef CONFIG_MV_INCLUDE_PEX +#define MV_INCLUDE_PEX +#endif + +#ifdef CONFIG_MV_INCLUDE_PCI +#define MV_INCLUDE_PCI +#endif + +#ifdef CONFIG_MV_INCLUDE_TWSI +#define MV_INCLUDE_TWSI +#endif +#ifdef CONFIG_MV_INCLUDE_CESA +#define MV_INCLUDE_CESA +#endif +#ifdef CONFIG_MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_GIG_ETH +#endif +#ifdef CONFIG_MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_SATA +#endif +#ifdef CONFIG_MV_INCLUDE_USB +#define MV_INCLUDE_USB +#define MV_USB_VOLTAGE_FIX +#endif +#ifdef CONFIG_MV_INCLUDE_LEGACY_NAND +#define MV_INCLUDE_LEGACY_NAND +#endif +#ifdef CONFIG_MV_INCLUDE_TDM +#define MV_INCLUDE_TDM +#endif +#ifdef CONFIG_MV_INCLUDE_XOR +#define MV_INCLUDE_XOR +#endif +#ifdef CONFIG_MV_INCLUDE_TWSI +#define MV_INCLUDE_TWSI +#endif +#ifdef CONFIG_MV_INCLUDE_UART +#define MV_INCLUDE_UART +#endif +#ifdef CONFIG_MV_INCLUDE_SPI +#define MV_INCLUDE_SPI +#endif +#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD +#define MV_INCLUDE_SFLASH_MTD +#endif +#ifdef CONFIG_MV_INCLUDE_NOR +#define MV_INCLUDE_NOR +#endif +#ifdef CONFIG_MV_INCLUDE_AUDIO +#define MV_INCLUDE_AUDIO +#endif +#ifdef CONFIG_MV_INCLUDE_TS +#define MV_INCLUDE_TS +#endif +#ifdef CONFIG_MV_INCLUDE_SDIO +#define MV_INCLUDE_SDIO +#endif +#ifdef CONFIG_MTD_NAND_LNC_BOOT +#define MTD_NAND_LNC_BOOT +#endif +#ifdef CONFIG_MTD_NAND_LNC +#define MTD_NAND_LNC +#endif +#ifdef CONFIG_MTD_NAND_NFC +#define MTD_NAND_NFC +#endif +#ifdef CONFIG_MV_INCLUDE_PDMA +#define MV_INCLUDE_PDMA +#endif +#ifdef CONFIG_MV_SPI_BOOT +#define MV_SPI_BOOT +#endif +#ifdef CONFIG_AURORA_IO_CACHE_COHERENCY +#define AURORA_IO_CACHE_COHERENCY +#endif + +/* convert Definitions for Errata used in the HAL */ +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_4413 +#define SHEEVA_ERRATA_ARM_CPU_4413 +#endif +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_BTS61 +#define SHEEVA_ERRATA_ARM_CPU_BTS61 +#endif +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_4611 +#define SHEEVA_ERRATA_ARM_CPU_4611 +#endif + + +/****************************************************************/ +/************* General configuration ********************/ +/****************************************************************/ + +/* Enable Clock Power Control */ +#define MV_INCLUDE_CLK_PWR_CNTRL + +/* Disable the DEVICE BAR in the PEX */ +#define MV_DISABLE_PEX_DEVICE_BAR + +/* Allow the usage of early printings during initialization */ +#define MV_INCLUDE_EARLY_PRINTK + +/****************************************************************/ +/************* NFP configuration ********************************/ +/****************************************************************/ +#define MV_NFP_SEC_Q_SIZE 64 +#define MV_NFP_SEC_REQ_Q_SIZE 1000 + + + +/****************************************************************/ +/************* CESA configuration ********************/ +/****************************************************************/ + +#ifdef MV_INCLUDE_CESA + +#define MV_CESA_MAX_CHAN 4 + +/* Use 2K of SRAM */ +#define MV_CESA_MAX_BUF_SIZE 1600 + +#endif /* MV_INCLUDE_CESA */ + +/* DRAM cache coherency configuration */ +#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW + + +/* We use the following registers to store DRAM interface pre configuration */ +/* auto-detection results */ +/* IMPORTANT: We are using mask register for that purpose. Before writing */ +/* to units mask register, make sure main maks register is set to disable */ +/* all interrupts. */ +#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ +#define DRAM_BUF_REG1 0x30820 /* sdram config */ +#define DRAM_BUF_REG2 0x30830 /* sdram mode */ +#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ +#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ +#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ +#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ +#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ +#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ +#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ +#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ + +/* Following the pre-configuration registers default values restored after */ +/* auto-detection is done */ +#define DRAM_BUF_REG_DV 0 + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ +#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ + +#endif /* __INCmvSysHwConfigh */ diff --git a/arch/arm/mach-armada370/config/mvSysNfcConfig.h b/arch/arm/mach-armada370/config/mvSysNfcConfig.h new file mode 100755 index 000000000..72a9d7d85 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysNfcConfig.h @@ -0,0 +1,44 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSpiConfig.h - Marvell SPI unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for SPI registers. +*/ +#define MV_NFC_REGS_BASE (MV_NFC_REGS_OFFSET) + +#ifdef CONFIG_MV_INCLUDE_PDMA +#define MV_INCLUDE_PDMA +#endif + +#ifdef CONFIG_MTD_NAND_NFC_INIT_RESET +#define MTD_NAND_NFC_INIT_RESET +#endif diff --git a/arch/arm/mach-armada370/config/mvSysPciConfig.h b/arch/arm/mach-armada370/config/mvSysPciConfig.h new file mode 100755 index 000000000..925af1958 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysPciConfig.h @@ -0,0 +1,25 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +#include "mvSysHwConfig.h" + +/* +** Base address for Pex registers. +*/ +#define MV_PCI_IF_REGS_BASE(pciIf) (MV_PEX_IF_REGS_OFFSET(pciIf)) diff --git a/arch/arm/mach-armada370/config/mvSysPexConfig.h b/arch/arm/mach-armada370/config/mvSysPexConfig.h new file mode 100755 index 000000000..a8e33678d --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysPexConfig.h @@ -0,0 +1,53 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysPciIfConfig.h - Marvell PCI / Pex units specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for Pex registers. +*/ +#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) + +/* PEX Bridge*/ +#define PEX0_PTP 0 /* no Bridge on pciIf0*/ +#define PEX1_PTP 0 /* no Bridge on pciIf1*/ + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0xF3000000 +#define PEX_CONFIG_RW_WA_SIZE _16M diff --git a/arch/arm/mach-armada370/config/mvSysPonConfig.h b/arch/arm/mach-armada370/config/mvSysPonConfig.h new file mode 100755 index 000000000..a29f56f88 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysPonConfig.h @@ -0,0 +1,37 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysDdrConfig.h - Marvell DRAM controller unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for PON registers. +*/ +#define MV_EPON_MAC_REGS_BASE (MV_GPON_MAC_REGS_OFFSET) +#define MV_GPON_MAC_REGS_BASE (MV_GPON_MAC_REGS_OFFSET) diff --git a/arch/arm/mach-armada370/config/mvSysRtcConfig.h b/arch/arm/mach-armada370/config/mvSysRtcConfig.h new file mode 100755 index 000000000..d1be3083a --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysRtcConfig.h @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysRtcConfig.h - Marvell Real-Time clock unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for RTC registers. +*/ +#define MV_RTC_REGS_BASE (MV_RTC_REGS_OFFSET) diff --git a/arch/arm/mach-armada370/config/mvSysSataConfig.h b/arch/arm/mach-armada370/config/mvSysSataConfig.h new file mode 100755 index 000000000..b9df3145a --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysSataConfig.h @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSataConfig.h - Marvell Sata unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for SPI registers. +*/ +#define MV_SATA_REGS_BASE (MV_SATA_REGS_OFFSET) diff --git a/arch/arm/mach-armada370/config/mvSysSdmmcConfig.h b/arch/arm/mach-armada370/config/mvSysSdmmcConfig.h new file mode 100755 index 000000000..7e39c3bc6 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysSdmmcConfig.h @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSdmmcConfig.h - Marvell SDMMC unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for audio registers. +*/ +#define MV_SDMMC_REGS_BASE (MV_SDMMC_REGS_OFFSET) diff --git a/arch/arm/mach-armada370/config/mvSysSpiConfig.h b/arch/arm/mach-armada370/config/mvSysSpiConfig.h new file mode 100755 index 000000000..990119375 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysSpiConfig.h @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysSpiConfig.h - Marvell SPI unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for SPI registers. +*/ +#define MV_SPI_REGS_BASE(unit) (MV_SPI_REGS_OFFSET(unit)) diff --git a/arch/arm/mach-armada370/config/mvSysTdmConfig.h b/arch/arm/mach-armada370/config/mvSysTdmConfig.h new file mode 100755 index 000000000..28d71b0ae --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysTdmConfig.h @@ -0,0 +1,119 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvSysTdmConfig.h - Marvell TDM unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvOs.h" + +/****************************************************************/ +/*************** Telephony configuration ************************/ +/****************************************************************/ +#if defined(CONFIG_MV_TDM_SUPPORT) + #define MV_TDM_SUPPORT + #define MV_TDM_REGS_BASE MV_TDM_REGS_OFFSET +#elif defined(CONFIG_MV_COMM_UNIT_SUPPORT) + #define MV_COMM_UNIT_SUPPORT + #define MV_COMM_UNIT_REGS_BASE MV_COMM_UNIT_REGS_OFFSET +#endif + +/* SLIC vendor */ +#if defined(CONFIG_SILABS_SLIC_SUPPORT) + #define SILABS_SLIC_SUPPORT + #if defined(CONFIG_SILABS_SLIC_3215) + #define SILABS_SLIC_3215 + #elif defined(CONFIG_SILABS_SLIC_3217) + #define SILABS_SLIC_3217 + #endif +#else /* CONFIG_ZARLINK_SLIC_SUPPORT) */ + #define ZARLINK_SLIC_SUPPORT + #define SLIC_TIMER_EVENT_SUPPORT + #if defined(CONFIG_ZARLINK_SLIC_VE880) + #define ZARLINK_SLIC_VE880 + #elif defined(CONFIG_ZARLINK_SLIC_VE792) + #define ZARLINK_SLIC_VE792 + #endif +#endif + +#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) + #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE +#endif + +#if defined(CONFIG_MV_TDM_PCM_CLK_8MHZ) + #define MV_TDM_PCM_CLK_8MHZ +#elif defined(CONFIG_MV_TDM_PCM_CLK_4MHZ) + #define MV_TDM_PCM_CLK_4MHZ +#elif defined(CONFIG_MV_TDM_PCM_CLK_2MHZ) + #define MV_TDM_PCM_CLK_2MHZ +#endif diff --git a/arch/arm/mach-armada370/config/mvSysTsConfig.h b/arch/arm/mach-armada370/config/mvSysTsConfig.h new file mode 100755 index 000000000..8fae50f74 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysTsConfig.h @@ -0,0 +1,37 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysTsConfig.h - Marvell TS unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for TS registers. +*/ +#define MV_TSU_GLOBAL_REGS_BASE (MV_TSU_GLOBAL_REGS_OFFSET) +#define MV_TSU_REGS_BASE(port) (MV_TSU_REGS_OFFSET(port)) diff --git a/arch/arm/mach-armada370/config/mvSysTwsiConfig.h b/arch/arm/mach-armada370/config/mvSysTwsiConfig.h new file mode 100755 index 000000000..7ba637af5 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysTwsiConfig.h @@ -0,0 +1,41 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysTwsiConfig.h - Marvell TWSI unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" +/* +** Base address for TWSI registers. +*/ +#define MV_TWSI_SLAVE_REGS_BASE(unit) (MV_TWSI_SLAVE_REGS_OFFSET(unit)) + +/* +** Specific definition for Main CPU interrupt cause register. +** Needed for TWSI operation completion monitoring. +*/ +#define MV_TWSI_CPU_MAIN_INT_CAUSE(chNum, cpu) TWSI_CPU_MAIN_INT_CAUSE_REG(cpu) diff --git a/arch/arm/mach-armada370/config/mvSysUsbConfig.h b/arch/arm/mach-armada370/config/mvSysUsbConfig.h new file mode 100755 index 000000000..de9bdedc5 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysUsbConfig.h @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysUsbConfig.h - Marvell USB unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for USB registers. +*/ +#define MV_USB_REGS_BASE(unit) (MV_USB_REGS_OFFSET(unit)) diff --git a/arch/arm/mach-armada370/config/mvSysXorConfig.h b/arch/arm/mach-armada370/config/mvSysXorConfig.h new file mode 100755 index 000000000..ae86fc642 --- /dev/null +++ b/arch/arm/mach-armada370/config/mvSysXorConfig.h @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysXorConfig.h - Marvell XOR unit specific configurations +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvSysHwConfig.h" + +/* +** Base address for XOR registers. +*/ +#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) diff --git a/arch/arm/mach-armada370/core.c b/arch/arm/mach-armada370/core.c new file mode 100755 index 000000000..49cea17ab --- /dev/null +++ b/arch/arm/mach-armada370/core.c @@ -0,0 +1,1380 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "mvDebug.h" +#include "mvSysHwConfig.h" +#include "pex/mvPexRegs.h" +#include "cntmr/mvCntmr.h" +#include "gpp/mvGpp.h" +#include "plat/gpio.h" +#include "cpu/mvCpu.h" + +#if defined(CONFIG_MV_INCLUDE_SDIO) +#include "sdmmc/mvSdmmc.h" +#include +#endif +#if defined(CONFIG_MV_INCLUDE_CESA) +#include "cesa/mvCesa.h" +#endif +#if defined(CONFIG_MV_INCLUDE_AUDIO) +#include +#endif + +#include + +/* I2C */ +#include +#include +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + +/* SPI */ +#include "mvSysSpiApi.h" + +/* Eth Phy */ +#include "mvSysEthPhyApi.h" + +/* NAND */ +#ifdef CONFIG_MTD_NAND_NFC +#include "mv_mtd/nand_nfc.h" +#endif + +/* DLB */ +#define MV_DLB_CTRL_REG (INTER_REGS_BASE + 0x1700) +#define MV_DLB_BUS_OPT_WEIGHTS_REG (INTER_REGS_BASE + 0x1704) +#define MV_DLB_CMD_PRIO_REG (INTER_REGS_BASE + 0x1708) +#define MV_MBUS_UNITS_PRIO_CTRL_REG (INTER_REGS_BASE + 0x20420) +#define MV_FABRIC_UNITS_PRIO_CTRL_REG (INTER_REGS_BASE + 0x20424) + +#define MV_COHERENCY_FABRIC_CTRL_REG (MV_COHERENCY_FABRIC_OFFSET + 0x0) +#define MV_COHERENCY_FABRIC_CFG_REG (MV_COHERENCY_FABRIC_OFFSET + 0x4) + +extern unsigned int irq_int_type[]; +extern void __init axp_map_io(void); +extern void __init mv_init_irq(void); +extern struct sys_timer axp_timer; +extern MV_CPU_DEC_WIN* mv_sys_map(void); +#if defined(CONFIG_MV_INCLUDE_CESA) +extern u32 mv_crypto_virt_base_get(u8 chan); +#endif +extern void axp_init_irq(void); +unsigned int support_wait_for_interrupt; +u32 bit_mask_config; + +/* for debug putstr */ +static char arr[256]; +MV_U32 mvTclk = 166666667; +MV_U32 mvSysclk = 200000000; + +#ifdef CONFIG_MV_INCLUDE_GIG_ETH +MV_U8 mvMacAddr[CONFIG_MV_ETH_PORTS_NUM][6]; +MV_U16 mvMtu[CONFIG_MV_ETH_PORTS_NUM] = {0}; +#endif + +/* + * Helpers to get DDR bank info + */ +#define DDR_BASE_CS_OFF(n) (0x0180 + ((n) << 2)) +#define DDR_SIZE_CS_OFF(n) (0x0184 + ((n) << 2)) +#define TARGET_DDR 0 +#define COHERENCY_STATUS_SHARED_NO_L2_ALLOC 0x1 + +struct mbus_dram_target_info armadaxp_mbus_dram_info; + +/*********************************************************************************/ +/************** Early Printk Support **************/ +/*********************************************************************************/ +#ifdef MV_INCLUDE_EARLY_PRINTK +#define MV_UART0_LSR (*(volatile unsigned char *)(INTER_REGS_BASE + 0x12000 + 0x14)) +#define MV_UART0_THR (*(volatile unsigned char *)(INTER_REGS_BASE + 0x12000 + 0x0 )) +#define MV_UART1_LSR (*(volatile unsigned char *)(INTER_REGS_BASE + 0x12100 + 0x14)) +#define MV_UART1_THR (*(volatile unsigned char *)(INTER_REGS_BASE + 0x12100 + 0x0 )) +#define MV_SERIAL_BASE ((unsigned char *)(INTER_REGS_BASE + 0x12000 + 0x0 )) +#define DEV_REG (*(volatile unsigned int *)(INTER_REGS_BASE + 0x40000)) +#define CLK_REG (*(volatile unsigned int *)(INTER_REGS_BASE + 0x2011c)) +/* + * This does not append a newline + */ +static void putstr(const char *s) +{ + unsigned int model; + + /* Get dev ID, make sure pex clk is on */ + if((CLK_REG & 0x4) == 0) + { + CLK_REG = CLK_REG | 0x4; + model = (DEV_REG >> 16) & 0xffff; + CLK_REG = CLK_REG & ~0x4; + } + else + model = (DEV_REG >> 16) & 0xffff; + + while (*s) { + while ((MV_UART0_LSR & UART_LSR_THRE) == 0); + MV_UART0_THR = *s; + + if (*s == '\n') { + while ((MV_UART0_LSR & UART_LSR_THRE) == 0); + MV_UART0_THR = '\r'; + } + s++; + } +} +extern void putstr(const char *ptr); +void mv_early_printk(char *fmt,...) +{ + va_list args; + va_start(args, fmt); + vsprintf(arr,fmt,args); + va_end(args); + putstr(arr); +} +#endif + +/*********************************************************************************/ +/************** UBoot Tagging Parameters **************/ +/*********************************************************************************/ +#ifdef CONFIG_BE8_ON_LE +#define read_tag(a) le32_to_cpu(a) +#define read_mtu(a) le16_to_cpu(a) +#else +#define read_tag(a) a +#define read_mtu(a) a +#endif + +extern MV_U32 gBoardId; +extern unsigned int elf_hwcap; +extern u32 mvIsUsbHost; + +static int __init parse_tag_mv_uboot(const struct tag *tag) +{ + unsigned int mvUbootVer = 0; + int i = 0; + + printk("Using UBoot passing parameters structure\n"); + mvUbootVer = read_tag(tag->u.mv_uboot.uboot_version); + mvIsUsbHost = read_tag(tag->u.mv_uboot.isUsbHost); + gBoardId = (mvUbootVer & 0xff); + bit_mask_config = read_tag(tag->u.mv_uboot.bit_mask_config); + +#ifdef CONFIG_MV_INCLUDE_GIG_ETH + for (i = 0; i < CONFIG_MV_ETH_PORTS_NUM; i++) { +#if defined (CONFIG_OVERRIDE_ETH_CMDLINE) + memset(mvMacAddr[i], 0, 6); + mvMtu[i] = 0; +#else +printk(">>>>>>>Tag MAC %02x:%02x:%02x:%02x:%02x:%02x\n", tag->u.mv_uboot.macAddr[i][5], tag->u.mv_uboot.macAddr[i][4], + tag->u.mv_uboot.macAddr[i][3], tag->u.mv_uboot.macAddr[i][2], tag->u.mv_uboot.macAddr[i][1], tag->u.mv_uboot.macAddr[i][0]); + memcpy(mvMacAddr[i], tag->u.mv_uboot.macAddr[i], 6); + mvMtu[i] = read_mtu(tag->u.mv_uboot.mtu[i]); +#endif + } +#endif + +#ifdef CONFIG_MV_NAND + /* get NAND ECC type(1-bit or 4-bit) */ + mv_nand_ecc = read_tag(tag->u.mv_uboot.nand_ecc); +#endif + return 0; +} + +__tagtable(ATAG_MV_UBOOT, parse_tag_mv_uboot); + +/*********************************************************************************/ +/************** Command Line Parameters **************/ +/*********************************************************************************/ +#ifdef CONFIG_MV_INCLUDE_USB +#include "mvSysUsbApi.h" +/* Required to get the configuration string from the Kernel Command Line */ +static char *usb0Mode = "host"; +static char *usb1Mode = "host"; +int mv_usb0_cmdline_config(char *s); +int mv_usb1_cmdline_config(char *s); +__setup("usb0Mode=", mv_usb0_cmdline_config); +__setup("usb1Mode=", mv_usb1_cmdline_config); + +int mv_usb0_cmdline_config(char *s) +{ + usb0Mode = s; + return 1; +} + +int mv_usb1_cmdline_config(char *s) +{ + usb1Mode = s; + return 1; +} +#endif + +#ifdef CONFIG_CACHE_AURORA_L2 +static int noL2 = 0; +static int __init noL2_setup(char *__unused) +{ + noL2 = 1; + return 1; +} + +__setup("noL2", noL2_setup); +#endif + +#ifndef CONFIG_SHEEVA_ERRATA_ARM_CPU_4948 +unsigned int l0_disable_flag = 0; /* L0 Enabled by Default */ +static int __init l0_disable_setup(char *__unused) +{ + l0_disable_flag = 1; + return 1; +} + +__setup("l0_disable", l0_disable_setup); +#endif + +#ifndef CONFIG_SHEEVA_ERRATA_ARM_CPU_5315 +unsigned int sp_enable_flag = 0; /* SP Disabled by Default */ +static int __init spec_prefesth_setup(char *__unused) +{ + sp_enable_flag = 1; + return 1; +} + +__setup("sp_enable", spec_prefesth_setup); +#endif + +char *nfcConfig = NULL; +static int __init nfcConfig_setup(char *s) +{ + nfcConfig = s; + return 1; +} +__setup("nfcConfig=", nfcConfig_setup); + +static int dlb_enable = 1; +static int __init dlb_setup(char *__unused) +{ + dlb_enable = 0; + return 1; +} + +__setup("noDLB", dlb_setup); + +void __init armadaxp_setup_cpu_mbus(void) +{ + void __iomem *addr; + int i; + int cs; + u8 coherency_status = 0; + +#if defined(CONFIG_AURORA_IO_CACHE_COHERENCY) + coherency_status = COHERENCY_STATUS_SHARED_NO_L2_ALLOC; +#endif + + /* + * Setup MBUS dram target info. + */ + armadaxp_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + addr = (void __iomem *)DDR_WINDOW_CPU_BASE; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(addr + DDR_BASE_CS_OFF(i)); + u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &armadaxp_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->mbus_attr |= coherency_status << 4; + w->base = base & 0xff000000; + w->size = (size | 0x00ffffff) + 1; + } + } + armadaxp_mbus_dram_info.num_cs = cs; +} + +/*********************************************************************************/ +/************** I/O Devices Platform Info **************/ +/*********************************************************************************/ +/************* + * I2C(TWSI) * + *************/ +static struct mv64xxx_i2c_pdata axp_i2c_pdata = { + .freq_m = 8, /* assumes 166 MHz TCLK */ + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource axp_i2c_0_resources[] = { + { + .name = "i2c base", + .start = INTER_REGS_PHYS_BASE + MV_TWSI_SLAVE_REGS_OFFSET(0), + .end = INTER_REGS_PHYS_BASE + MV_TWSI_SLAVE_REGS_OFFSET(0) + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "i2c irq", + .start = IRQ_AURORA_I2C0, + .end = IRQ_AURORA_I2C0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device axp_i2c = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(axp_i2c_0_resources), + .resource = axp_i2c_0_resources, + .dev = { + .platform_data = &axp_i2c_pdata, + }, +}; + +/********** + * UART-0 * + **********/ +static struct plat_serial8250_port aurora_uart0_data[] = { + { + .mapbase = (INTER_REGS_PHYS_BASE | MV_UART_REGS_OFFSET(0)), + .membase = (char *)(INTER_REGS_BASE | MV_UART_REGS_OFFSET(0)), + .irq = IRQ_AURORA_UART0, + .flags = UPF_FIXED_TYPE | UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_DWAPB, + .private_data = (void *) (INTER_REGS_BASE | MV_UART_REGS_OFFSET(0) | 0x7C), + .type = PORT_16550A, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource aurora_uart0_resources[] = { + { + .start = (INTER_REGS_PHYS_BASE | MV_UART_REGS_OFFSET(0)), + .end = (INTER_REGS_PHYS_BASE | MV_UART_REGS_OFFSET(0)) + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_AURORA_UART0, + .end = IRQ_AURORA_UART0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device aurora_uart0 = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = aurora_uart0_data, + }, + .resource = aurora_uart0_resources, + .num_resources = ARRAY_SIZE(aurora_uart0_resources), +}; + +#if defined(CONFIG_SYNO_ARMADA_ARCH) +/********** + * UART-1 * + **********/ +static struct plat_serial8250_port aurora_uart1_data[] = { + { + .mapbase = (INTER_REGS_PHYS_BASE | MV_UART_REGS_OFFSET(1)), + .membase = (char *)(INTER_REGS_BASE | MV_UART_REGS_OFFSET(1)), + .irq = IRQ_AURORA_UART1, + .flags = UPF_FIXED_TYPE | UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_DWAPB, + .private_data = (void *) (INTER_REGS_BASE | MV_UART_REGS_OFFSET(1) | 0x7C), + .type = PORT_16550A, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource aurora_uart1_resources[] = { + { + .start = (INTER_REGS_PHYS_BASE | MV_UART_REGS_OFFSET(1)), + .end = (INTER_REGS_PHYS_BASE | MV_UART_REGS_OFFSET(1)) + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_AURORA_UART1, + .end = IRQ_AURORA_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device aurora_uart1 = { + .name = "serial8250", + .id = 1, + .dev = { + .platform_data = aurora_uart1_data, + }, + .resource = aurora_uart1_resources, + .num_resources = ARRAY_SIZE(aurora_uart1_resources), +}; +#endif + + +void __init serial_initialize(void) +{ + aurora_uart0_data[0].uartclk = mvBoardTclkGet(); + platform_device_register(&aurora_uart0); +#if defined(CONFIG_SYNO_ARMADA_ARCH) + aurora_uart1_data[0].uartclk = mvBoardTclkGet(); + platform_device_register(&aurora_uart1); +#endif +} + +#ifdef CONFIG_MV_INCLUDE_AUDIO + +/***************************************************************************** + * I2S/SPDIF + ****************************************************************************/ +static struct resource mv_i2s_resources[] = { + [0] = { + .start = INTER_REGS_PHYS_BASE + MV_AUDIO_REGS_OFFSET(0), + .end = INTER_REGS_PHYS_BASE + MV_AUDIO_REGS_OFFSET(0) + SZ_16K -1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_AURORA_AUDIO, + .end = IRQ_AURORA_AUDIO, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 mv_i2s0_dmamask = 0xFFFFFFFFUL; + +static struct orion_i2s_platform_data mv_i2s_plat_data = { + .dram = NULL, + .spdif_rec = 1, + .spdif_play = 1, + .i2s_rec = 1, + .i2s_play = 1, +}; + + +static struct platform_device mv_i2s = { + .name = "mv88fx_snd", + .id = 0, + .dev = { + .dma_mask = &mv_i2s0_dmamask, + .coherent_dma_mask = 0xFFFFFFFF, + .platform_data = &mv_i2s_plat_data, + }, + .num_resources = ARRAY_SIZE(mv_i2s_resources), + .resource = mv_i2s_resources, +}; + +static struct platform_device mv_mv88fx_i2s = { + .name = "mv88fx-i2s", + .id = -1, +}; + +/***************************************************************************** + * A2D on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata i2c_a2d = { + I2C_BOARD_INFO("i2s_i2c", 0x4A), +}; + + +void __init mv_audio_init(void) +{ + if (MV_TRUE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) { + platform_device_register(&mv_mv88fx_i2s); + platform_device_register(&mv_i2s); + i2c_register_board_info(0, &i2c_a2d, 1); + } +} + +#endif /* #ifdef CONFIG_MV_INCLUDE_AUDIO */ + +/***************************************************************************** + * Audio + ****************************************************************************/ +static struct resource kirkwood_i2s_resources[] = { + [0] = { + .start = INTER_REGS_PHYS_BASE + MV_AUDIO_REGS_OFFSET(0), + .end = INTER_REGS_PHYS_BASE + MV_AUDIO_REGS_OFFSET(0) + SZ_16K -1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_AURORA_AUDIO, + .end = IRQ_AURORA_AUDIO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { + .dram = &armadaxp_mbus_dram_info, + .burst = 128, +}; + +static struct platform_device kirkwood_i2s_device = { + .name = "kirkwood-i2s", + .id = -1, + .num_resources = ARRAY_SIZE(kirkwood_i2s_resources), + .resource = kirkwood_i2s_resources, + .dev = { + .platform_data = &kirkwood_i2s_data, + }, +}; + +static struct platform_device kirkwood_pcm_device = { + .name = "kirkwood-pcm-audio", + .id = -1, +}; + +/***************************************************************************** + * A2D on I2C bus + ****************************************************************************/ +static struct i2c_board_info __initdata i2c_a2d = { + I2C_BOARD_INFO("cs42l51", 0x4A), +}; + + +void __init kirkwood_audio_init(void) +{ + if (MV_TRUE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) { + platform_device_register(&kirkwood_i2s_device); + platform_device_register(&kirkwood_pcm_device); + i2c_register_board_info(0, &i2c_a2d, 1); + } +} + + +/************ + * GPIO + ***********/ +static struct platform_device mv_gpio = { + .name = "mv_gpio", + .id = 0, + .num_resources = 0, +}; + +static void __init mv_gpio_init(void) +{ + platform_device_register(&mv_gpio); +} + +/******** + * SDIO * + ********/ +#if defined(CONFIG_MV_INCLUDE_SDIO) +static struct resource mvsdio_resources[] = { + [0] = { + .start = INTER_REGS_PHYS_BASE + MV_SDMMC_REGS_OFFSET, + .end = INTER_REGS_PHYS_BASE + MV_SDMMC_REGS_OFFSET + SZ_1K -1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_AURORA_SDIO, + .end = IRQ_AURORA_SDIO, + .flags = IORESOURCE_IRQ, + }, + +}; + +static u64 mvsdio_dmamask = 0xffffffffUL; + +static struct mvsdio_platform_data mvsdio_data = { + .gpio_write_protect = 0, + .gpio_card_detect = 0, + .dram = NULL, +}; + +static struct platform_device mv_sdio_plat = { + .name = "mvsdio", + .id = -1, + .dev = { + .dma_mask = &mvsdio_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mvsdio_data, + }, + .num_resources = ARRAY_SIZE(mvsdio_resources), + .resource = mvsdio_resources, +}; +#endif /* #if defined(CONFIG_MV_INCLUDE_SDIO) */ + +/******* + * GBE * + *******/ +#ifdef CONFIG_MV_ETHERNET +#if defined(CONFIG_MV_ETH_LEGACY) +static struct platform_device mv88fx_eth = { + .name = "mv88fx_eth", + .id = 0, + .num_resources = 0, +}; +#elif defined(CONFIG_MV_ETH_NETA) +static struct platform_device mv88fx_neta = { + .name = "mv88fx_neta", + .id = 0, + .num_resources = 0, +}; +#else +#error "Ethernet Mode is not defined (should be Legacy or NETA)" +#endif /* Ethernet mode: legacy or NETA */ + +static void __init eth_init(void) +{ +#if defined(CONFIG_MV_ETH_LEGACY) + platform_device_register(&mv88fx_eth); +#elif defined(CONFIG_MV_ETH_NETA) + platform_device_register(&mv88fx_neta); +#endif /* Ethernet mode: legacy or NETA */ +} +#endif /* CONFIG_MV_ETHERNET */ + + +/******* + * RTC * + *******/ +static struct resource axp_rtc_resource[] = { + { + .start = INTER_REGS_PHYS_BASE + MV_RTC_REGS_OFFSET, + .end = INTER_REGS_PHYS_BASE + MV_RTC_REGS_OFFSET + 32 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_AURORA_RTC, + .flags = IORESOURCE_IRQ, + } +}; + +static void __init rtc_init(void) +{ + platform_device_register_simple("rtc-mv", -1, axp_rtc_resource, 2); +} + +/******** + * SATA * + ********/ +#ifdef CONFIG_SATA_MV +#define SATA_PHYS_BASE (INTER_REGS_PHYS_BASE | MV_SATA_REGS_OFFSET) + +static struct mv_sata_platform_data dbdsmp_sata_data = { + .n_ports = 2, +}; + +static struct resource armadaxp_sata_resources[] = { + { + .name = "sata base", + .start = SATA_PHYS_BASE, + .end = SATA_PHYS_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "sata irq", + .start = IRQ_AURORA_SATA(0), + .end = IRQ_AURORA_SATA(0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device armadaxp_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(armadaxp_sata_resources), + .resource = armadaxp_sata_resources, +}; + +void __init armadaxp_sata_init(struct mv_sata_platform_data *sata_data) +{ + + /* If Port1 is disabled, then reduce the number of ports. */ + if (mvCtrlPwrClckGet(SATA_UNIT_ID, 1) == MV_FALSE) + sata_data->n_ports--; + + /* Cannot enable port1 if port 0 is disabled. */ + if (mvCtrlPwrClckGet(SATA_UNIT_ID, 0) == MV_FALSE) { + sata_data->n_ports = 0; + return; + } + + if (sata_data->n_ports != 0) { + armadaxp_sata.dev.platform_data = sata_data; + sata_data->dram = &armadaxp_mbus_dram_info; + platform_device_register(&armadaxp_sata); + } +} +#endif +/***************************************************************************** + * SoC hwmon Thermal Sensor + ****************************************************************************/ +void __init armadaxp_hwmon_init(void) +{ + platform_device_register_simple("axp-temp", 0, NULL, 0); +} + +/************* + * 7-Segment * + *************/ +static struct timer_list axp_db_timer; +static void axp_db_7seg_event(unsigned long data) +{ + static int count = 0; + + /* Update the 7 segment */ + mvBoardDebugLed(count); + + /* Incremnt count and arm the timer*/ + count = (count + 1) & 7; + mod_timer(&axp_db_timer, jiffies + 1 * HZ); +} + +static int __init axp_db_7seg_init(void) +{ + /* Create the 7segment timer */ + setup_timer(&axp_db_timer, axp_db_7seg_event, 0); + + /* Arm it expire in 1 second */ + mod_timer(&axp_db_timer, jiffies + 1 * HZ); + + return 0; +} +__initcall(axp_db_7seg_init); + +#ifdef CONFIG_MTD_NAND_NFC +/***************************************************************************** + * NAND controller + ****************************************************************************/ +static struct resource axp_nfc_resources[] = { + { + .start = INTER_REGS_BASE + MV_NFC_REGS_OFFSET, + .end = INTER_REGS_BASE + MV_NFC_REGS_OFFSET + 0x400 -1, + .flags = IORESOURCE_MEM, + } +}; + + +static struct mtd_partition nand_parts_info[] = { + { + .name = "UBoot", + .offset = 0, + .size = 1 * SZ_1M + }, + { + .name = "UImage", + .offset = MTDPART_OFS_APPEND, + .size = 4 * SZ_1M }, + { + .name = "Root", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + + +static struct nfc_platform_data axp_nfc_data = { + .nfc_width = 8, + .num_devs = 1, + .num_cs = 1, + .use_dma = 0, + .ecc_type = MV_NFC_ECC_BCH_2K, + .parts = nand_parts_info, + .nr_parts = ARRAY_SIZE(nand_parts_info), +}; + +static struct platform_device axp_nfc = { + .name = "armada-nand", + .id = 0, + .dev = { + .platform_data = &axp_nfc_data, + }, + .num_resources = ARRAY_SIZE(axp_nfc_resources), + .resource = axp_nfc_resources, + +}; + +static void __init axp_db_nfc_init(void) +{ + /* Check for ganaged mode */ + if (nfcConfig) { + if (strncmp(nfcConfig, "ganged", 6) == 0) { + axp_nfc_data.nfc_width = 16; + axp_nfc_data.num_devs = 2; + nfcConfig += 7; + } + + /* Check for ECC type directive */ + if (strcmp(nfcConfig, "8bitecc") == 0) { + axp_nfc_data.ecc_type = MV_NFC_ECC_BCH_1K; + } else if (strcmp(nfcConfig, "12bitecc") == 0) { + axp_nfc_data.ecc_type = MV_NFC_ECC_BCH_704B; + } else if (strcmp(nfcConfig, "16bitecc") == 0) { + axp_nfc_data.ecc_type = MV_NFC_ECC_BCH_512B; + } + } + + axp_nfc_data.tclk = mvBoardTclkGet(); + + platform_device_register(&axp_nfc); +} +#endif +/*********************************************************************************/ +/************** Helper Routines **************/ +/*********************************************************************************/ +#ifdef CONFIG_MV_INCLUDE_CESA +unsigned char* mv_sram_usage_get(int* sram_size_ptr) +{ + int used_size = 0; + +#if defined(CONFIG_MV_CESA) + used_size = sizeof(MV_CESA_SRAM_MAP); +#endif + + if(sram_size_ptr != NULL) + *sram_size_ptr = _8K - used_size; + + return (char *)(mv_crypto_virt_base_get(0) + used_size); +} +#endif + +void print_board_info(void) +{ + char name_buff[50]; + printk("\n Marvell Armada370 Board"); + + mvBoardNameGet(name_buff); + printk("-- %s ",name_buff); + + mvCtrlModelRevNameGet(name_buff); + printk(" Soc: %s", name_buff); +#if defined(MV_CPU_LE) + printk(" LE"); +#else + printk(" BE"); +#endif + printk("\n LSP version: %s\n", LSP_VERSION); + printk("\n\n"); + printk(" Detected Tclk %d, SysClk %d, FabricClk %d\n",mvTclk, mvSysclk, mvCpuL2ClkGet()); +} + +#ifdef CONFIG_AURORA_IO_CACHE_COHERENCY +static void io_coherency_init(void) +{ + MV_U32 reg; + + /* set CIB read snoop command to ReadUnique */ + reg = MV_REG_READ(MV_CIB_CTRL_CFG_REG); + reg &= ~(7 << 16); + reg |= (7 << 16); + MV_REG_WRITE(MV_CIB_CTRL_CFG_REG, reg); + + /* enable snoop CPU enable */ + MV_REG_BIT_SET(MV_COHERENCY_FABRIC_CTRL_REG, (1 << 24)); +} +#endif + +#ifdef CONFIG_DEBUG_LL +extern void printascii(const char *); +static void check_cpu_mode(void) +{ + u32 cpu_id_code_ext; + int cpu_mode = 0; + asm volatile("mrc p15, 1, %0, c15, c12, 0": "=r"(cpu_id_code_ext)); + + if (((cpu_id_code_ext >> 16) & 0xF) == 0x2) + cpu_mode = 6; + else if (((cpu_id_code_ext >> 16) & 0xF) == 0x3) + cpu_mode = 7; + else + pr_err("unknow cpu mode!!!\n"); +#ifdef CONFIG_DEBUGGER_MODE_V6 + if (cpu_mode != 6) { + printascii("cpu mode (ARMv7) doesn't mach kernel configuration\n"); + panic("cpu mode mismatch"); + } +#else +#ifdef CONFIG_CPU_V7 + if (cpu_mode != 7) { + printascii("cpu mode (ARMv6) doesn't mach kernel configuration\n"); + panic("cpu mode mismatch"); + } +#endif +#endif + printk("Armada370: Working in ARMv%d mode\n",cpu_mode); +} +#endif + +/***************************************************************************** + * XOR + ****************************************************************************/ +static struct mv_xor_platform_shared_data armadaxp_xor_shared_data = { + .dram = &armadaxp_mbus_dram_info, +}; + +static u64 armadaxp_xor_dmamask = DMA_BIT_MASK(32); + +/***************************************************************************** + * XOR0 + ****************************************************************************/ +static struct resource armadaxp_xor0_shared_resources[] = { + { + .name = "xor 0 low", + .start = XOR0_PHYS_BASE, + .end = XOR0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .name = "xor 0 high", + .start = XOR0_HIGH_PHYS_BASE, + .end = XOR0_HIGH_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device armadaxp_xor0_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &armadaxp_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(armadaxp_xor0_shared_resources), + .resource = armadaxp_xor0_shared_resources, +}; + +static struct resource armadaxp_xor00_resources[] = { + [0] = { + .start = IRQ_AURORA_XOR0_CH0, + .end = IRQ_AURORA_XOR0_CH0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data armadaxp_xor00_data = { + .shared = &armadaxp_xor0_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device armadaxp_xor00_channel = { + .name = MV_XOR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(armadaxp_xor00_resources), + .resource = armadaxp_xor00_resources, + .dev = { + .dma_mask = &armadaxp_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &armadaxp_xor00_data, + }, +}; + +static struct resource armadaxp_xor01_resources[] = { + [0] = { + .start = IRQ_AURORA_XOR0_CH1, + .end = IRQ_AURORA_XOR0_CH1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data armadaxp_xor01_data = { + .shared = &armadaxp_xor0_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device armadaxp_xor01_channel = { + .name = MV_XOR_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(armadaxp_xor01_resources), + .resource = armadaxp_xor01_resources, + .dev = { + .dma_mask = &armadaxp_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &armadaxp_xor01_data, + }, +}; + +static void __init armadaxp_xor0_init(void) +{ + platform_device_register(&armadaxp_xor0_shared); + + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + //dma_cap_set(DMA_MEMCPY, armadaxp_xor00_data.cap_mask); + dma_cap_set(DMA_XOR, armadaxp_xor00_data.cap_mask); + platform_device_register(&armadaxp_xor00_channel); + + //dma_cap_set(DMA_MEMCPY, armadaxp_xor01_data.cap_mask); + //dma_cap_set(DMA_MEMSET, armadaxp_xor01_data.cap_mask); + dma_cap_set(DMA_XOR, armadaxp_xor01_data.cap_mask); + platform_device_register(&armadaxp_xor01_channel); +} + +/***************************************************************************** + * XOR1 + ****************************************************************************/ +static struct resource armadaxp_xor1_shared_resources[] = { + { + .name = "xor 1 low", + .start = XOR1_PHYS_BASE, + .end = XOR1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .name = "xor 1 high", + .start = XOR1_HIGH_PHYS_BASE, + .end = XOR1_HIGH_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device armadaxp_xor1_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &armadaxp_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(armadaxp_xor1_shared_resources), + .resource = armadaxp_xor1_shared_resources, +}; + +static struct resource armadaxp_xor10_resources[] = { + [0] = { + .start = IRQ_AURORA_XOR1_CH0, + .end = IRQ_AURORA_XOR1_CH0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data armadaxp_xor10_data = { + .shared = &armadaxp_xor1_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device armadaxp_xor10_channel = { + .name = MV_XOR_NAME, + .id = 2, + .num_resources = ARRAY_SIZE(armadaxp_xor10_resources), + .resource = armadaxp_xor10_resources, + .dev = { + .dma_mask = &armadaxp_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &armadaxp_xor10_data, + }, +}; + +static struct resource armadaxp_xor11_resources[] = { + [0] = { + .start = IRQ_AURORA_XOR1_CH1, + .end = IRQ_AURORA_XOR1_CH1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data armadaxp_xor11_data = { + .shared = &armadaxp_xor1_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device armadaxp_xor11_channel = { + .name = MV_XOR_NAME, + .id = 3, + .num_resources = ARRAY_SIZE(armadaxp_xor11_resources), + .resource = armadaxp_xor11_resources, + .dev = { + .dma_mask = &armadaxp_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &armadaxp_xor11_data, + }, +}; + +static void __init armadaxp_xor1_init(void) +{ + platform_device_register(&armadaxp_xor1_shared); + + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, armadaxp_xor10_data.cap_mask); + //dma_cap_set(DMA_XOR, armadaxp_xor10_data.cap_mask); + platform_device_register(&armadaxp_xor10_channel); + + dma_cap_set(DMA_MEMCPY, armadaxp_xor11_data.cap_mask); + dma_cap_set(DMA_MEMSET, armadaxp_xor11_data.cap_mask); + //dma_cap_set(DMA_XOR, armadaxp_xor11_data.cap_mask); + platform_device_register(&armadaxp_xor11_channel); +} + +static void dram_dlb_setup(void) +{ + if (dlb_enable) { + printk("Enable DLB and DRAM write coalescing\n"); + writel(0x9083, MV_DLB_BUS_OPT_WEIGHTS_REG); + writel(0x250020, MV_DLB_CMD_PRIO_REG); + writel(0x55555555, MV_MBUS_UNITS_PRIO_CTRL_REG); + writel(0x2, MV_FABRIC_UNITS_PRIO_CTRL_REG); + writel(0x7, MV_DLB_CTRL_REG); + } +} + +static void cpu_fabric_common_init(void) +{ + MV_U32 reg; + +#ifdef CONFIG_DEBUG_LL + check_cpu_mode(); +#endif + +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_4948 + printk("L0 cache Disabled (by Errata #4948)\n"); +#else + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (reg)); + if (l0_disable_flag) { + printk("L0 cache Disabled\n"); + reg |= (1 << 0); + } else { + printk("L0 cache Enabled\n"); + reg &= ~(1 << 0); + } + __asm volatile ("mcr p15, 1, %0, c15, c1, 0" : : "r" (reg)); +#endif + +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_5315 + printk("Speculative Prefetch Disabled (by Errata #5315)\n"); +#else + __asm volatile ("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); + if (sp_enable_flag) { + printk("Speculative Prefetch Enabled\n"); + reg &= ~(1 << 7); + } else { + printk("Speculative Prefetch Disabled\n"); + reg |= (1 << 7); + } + __asm volatile ("mcr p15, 1, %0, c15, c2, 0" : : "r" (reg)); +#endif + +#ifdef CONFIG_CACHE_AURORA_L2 + if (!noL2) + aurora_l2_init((void __iomem *)(INTER_REGS_BASE + MV_AURORA_L2_REGS_OFFSET)); +#endif + +#ifdef CONFIG_AURORA_IO_CACHE_COHERENCY + printk("Support IO coherency.\n"); + io_coherency_init(); +#endif +} + +#ifdef CONFIG_SYNO_ARMADA_ARCH +#ifdef MY_ABC_HERE +extern void syno_mv_net_shutdown(); +#endif +#define UART1_REG(x) (PORT1_BASE + ((UART_##x) << 2)) +#define SET8N1 0x3 +#define SOFTWARE_SHUTDOWN 0x31 +#define SOFTWARE_REBOOT 0x43 +extern void synology_gpio_init(void); + +void (*syno_power_off_indicator)(void) = NULL; +static void synology_power_off(void) +{ +#ifdef MY_ABC_HERE + /* platform driver will not shutdown when poweroff */ + syno_mv_net_shutdown(); +#endif + + writel(SET8N1, UART1_REG(LCR)); + writel(SOFTWARE_SHUTDOWN, UART1_REG(TX)); + + if (syno_power_off_indicator) { + syno_power_off_indicator(); + } +} + +static void synology_restart(char mode, const char *cmd) +{ + writel(SET8N1, UART1_REG(LCR)); + writel(SOFTWARE_REBOOT, UART1_REG(TX)); + + /* Calls original reset function for models those do not use uP + * I.e. USB Station. */ + arm_machine_restart(mode, cmd); +} +#endif /* CONFIG_SYNO_ARMADA_ARCH */ + +/***************************************************************************** + * DB BOARD: Main Initialization + ****************************************************************************/ +static void __init axp_db_init(void) +{ + /* Call Aurora/cpu special configurations */ + cpu_fabric_common_init(); + + /* Enable DLB and DRAM write coalescing */ + dram_dlb_setup(); + + /* init the Board environment */ + mvBoardEnvInit(); + + /* init the controller environment */ + if( mvCtrlEnvInit() ) { + printk( "Controller env initialization failed.\n" ); + return; + } + + /* Set configuration according to bit mask passed from U-Boot */ + mvBoardBitMaskConfigSet(bit_mask_config); + + armadaxp_setup_cpu_mbus(); + + /* Init the CPU windows setting and the access protection windows. */ + if( mvCpuIfInit(mv_sys_map())) { + printk( "Cpu Interface initialization failed.\n" ); + return; + } + + /* Init Tclk & SysClk */ + mvTclk = mvBoardTclkGet(); + mvSysclk = mvBoardSysClkGet(); + + support_wait_for_interrupt = 1; + +#ifdef CONFIG_SHEEVA_ERRATA_ARM_CPU_BTS61 + support_wait_for_interrupt = 0; +#endif + + elf_hwcap &= ~HWCAP_JAVA; + + serial_initialize(); + + /* At this point, the CPU windows are configured according to default definitions in mvSysHwConfig.h */ + /* and cpuAddrWinMap table in mvCpuIf.c. Now it's time to change defaults for each platform. */ + mvCpuIfAddDecShow(); + + print_board_info(); + + mv_gpio_init(); + + /* RTC */ + rtc_init(); + + /* SPI */ + mvSysSpiInit(0, _16M); + mvSysSpiInit(1, _16M); + +#ifdef CONFIG_MV_INCLUDE_AUDIO + /* Audio */ + mv_audio_init(); +#endif + kirkwood_audio_init(); + + /* ETH-PHY */ + mvSysEthPhyInit(); + + /* Sata */ +#ifdef CONFIG_SATA_MV + armadaxp_sata_init(&dbdsmp_sata_data); +#endif +#ifdef CONFIG_MTD_NAND_NFC + /* NAND */ + axp_db_nfc_init(); +#endif + /* HWMON */ + armadaxp_hwmon_init(); + + /* XOR */ + armadaxp_xor0_init(); + armadaxp_xor1_init(); + + /* I2C */ + platform_device_register(&axp_i2c); + +#if defined(CONFIG_MV_INCLUDE_SDIO) + if (MV_TRUE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) { + int irq_detect = mvBoardSDIOGpioPinGet(BOARD_GPP_SDIO_DETECT); + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + + if (irq_detect != MV_ERROR) { + mvsdio_data.gpio_card_detect = mvBoardSDIOGpioPinGet(BOARD_GPP_SDIO_DETECT); + irq_int_type[mvBoardSDIOGpioPinGet(BOARD_GPP_SDIO_DETECT)+IRQ_AURORA_GPIO_START] = GPP_IRQ_TYPE_CHANGE_LEVEL; + } + + if(mvBoardSDIOGpioPinGet(BOARD_GPP_SDIO_WP) != MV_ERROR) + mvsdio_data.gpio_write_protect = mvBoardSDIOGpioPinGet(BOARD_GPP_SDIO_WP); + + if(MV_OK == mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1)) + if (MV_OK == mvSdmmcWinInit(addrWinMap)) + mvsdio_data.clock = mvBoardTclkGet(); + platform_device_register(&mv_sdio_plat); + } +#endif + +#ifdef CONFIG_MV_ETHERNET + /* Ethernet */ + eth_init(); +#endif + +#if defined(CONFIG_SYNO_ARMADA_ARCH) + pm_power_off = synology_power_off; + arm_pm_restart = synology_restart; + synology_gpio_init(); +#endif + + return; +} + +MACHINE_START(ARMADA_370, "Marvell Armada-370") + /* MAINTAINER("MARVELL") */ + .atag_offset = 0x00000100, + .map_io = axp_map_io, + .init_irq = axp_init_irq, + .timer = &axp_timer, + .init_machine = axp_db_init, +MACHINE_END diff --git a/arch/arm/mach-armada370/dbg-trace.c b/arch/arm/mach-armada370/dbg-trace.c new file mode 100755 index 000000000..0de3ca70a --- /dev/null +++ b/arch/arm/mach-armada370/dbg-trace.c @@ -0,0 +1,111 @@ +#include +#include +#include +#include "dbg-trace.h" + +#define TRACE_ARR_LEN 800 +#define STR_LEN 128 +struct trace { + struct timeval tv; + char str[STR_LEN]; + unsigned int callback_val1; + unsigned int callback_val2; + char valid; +}; + +static unsigned int (*trc_callback1) (unsigned char) = NULL; +static unsigned int (*trc_callback2) (unsigned char) = NULL; +static unsigned char trc_param1 = 0; +static unsigned char trc_param2 = 0; +struct trace *trc_arr; +static int trc_index; +static int trc_active = 0; + +void TRC_START() +{ + trc_active = 1; +} + +void TRC_STOP() +{ + trc_active = 0; +} + +void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) +{ + printk("Marvell debug tracing is on\n"); + trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); + if(trc_arr == NULL) + { + printk("Can't allocate Debug Trace buffer\n"); + return; + } + memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); + trc_index = 0; + trc_callback1 = callback1; + trc_callback2 = callback2; + trc_param1 = callback1_param; + trc_param2 = callback2_param; +} + +void TRC_REC(char *fmt,...) +{ + va_list args; + struct trace *trc = &trc_arr[trc_index]; + + if(trc_active == 0) + return; + + do_gettimeofday(&trc->tv); + if(trc_callback1) + trc->callback_val1 = trc_callback1(trc_param1); + if(trc_callback2) + trc->callback_val2 = trc_callback2(trc_param2); + va_start(args, fmt); + vsprintf(trc->str,fmt,args); + va_end(args); + trc->valid = 1; + if((++trc_index) == TRACE_ARR_LEN) + trc_index = 0; +} + +void TRC_OUTPUT(void) +{ + int i,j; + struct trace *p; + printk("\n\nTrace %d items\n",TRACE_ARR_LEN); + for(i=0,j=trc_index; ivalid) { + unsigned long uoffs; + struct trace *plast; + if(p == &trc_arr[0]) + plast = &trc_arr[TRACE_ARR_LEN-1]; + else + plast = p-1; + if(p->tv.tv_sec == ((plast)->tv.tv_sec)) + uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); + else + uoffs = (1000000 - ((plast)->tv.tv_usec)) + + ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + + p->tv.tv_usec; + printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); + if(trc_callback1) + printk("[%u]",p->callback_val1); + if(trc_callback2) + printk("[%u]",p->callback_val2); + printk(": %s",p->str); + } + p->valid = 0; + } + memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); + trc_index = 0; +} + +void TRC_RELEASE(void) +{ + kfree(trc_arr); + trc_index = 0; +} diff --git a/arch/arm/mach-armada370/dbg-trace.h b/arch/arm/mach-armada370/dbg-trace.h new file mode 100755 index 000000000..c1ad60b1e --- /dev/null +++ b/arch/arm/mach-armada370/dbg-trace.h @@ -0,0 +1,24 @@ + +#ifndef _MV_DBG_TRCE_H_ +#define _MV_DBG_TRCE_H_ + +#ifdef CONFIG_MV_DBG_TRACE +void TRC_INIT(void *callback1, void *callback2, + unsigned char callback1_param, unsigned char callback2_param); +void TRC_REC(char *fmt,...); +void TRC_OUTPUT(void); +void TRC_RELEASE(void); +void TRC_START(void); +void TRC_STOP(void); + +#else +#define TRC_INIT(x1,x2,x3,x4) +#define TRC_REC(X...) +#define TRC_OUTPUT() +#define TRC_RELEASE() +#define TRC_START() +#define TRC_STOP() +#endif + + +#endif diff --git a/arch/arm/mach-armada370/dump_cp15_regs.c b/arch/arm/mach-armada370/dump_cp15_regs.c new file mode 100755 index 000000000..5ec2a4846 --- /dev/null +++ b/arch/arm/mach-armada370/dump_cp15_regs.c @@ -0,0 +1,218 @@ +/* + * arch/arm/mach-dove/dump_cp15_regs.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include + +#include +#include +#include +#include + +static int +proc_dump_cp15_read(char *page, char **start, off_t off, int count, int *eof, + void *data) +{ + char *p = page; + int len; + unsigned int value; + + asm volatile("mrc p15, 0, %0, c0, c0, 0": "=r"(value)); + p += sprintf(p, "Main ID: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c0, 1": "=r"(value)); + p += sprintf(p, "Cache Type: 0x%08x\n", value); + +#ifdef CONFIG_CPU_V7 + asm volatile("mrc p15, 0, %0, c0, c0, 2": "=r"(value)); + p += sprintf(p, "TCM Type: 0x%08x\n", value); +#endif + + asm volatile("mrc p15, 0, %0, c0, c0, 3": "=r"(value)); + p += sprintf(p, "TLB Type: 0x%08x\n", value); + +#ifdef CONFIG_CPU_V7 + asm volatile("mrc p15, 0, %0, c0, c0, 5": "=r"(value)); + p += sprintf(p, "Microprocessor ID: 0x%08x\n", value); +#endif + + asm volatile("mrc p15, 0, %0, c0, c1, 0": "=r"(value)); + p += sprintf(p, "Processor Feature 0: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c1, 1": "=r"(value)); + p += sprintf(p, "Processor Feature 1: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c1, 2": "=r"(value)); + p += sprintf(p, "Debug Feature 0: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c1, 3": "=r"(value)); + p += sprintf(p, "Auxiliary Feature 0: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c1, 4": "=r"(value)); + p += sprintf(p, "Memory Model Feature 0: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c1, 5": "=r"(value)); + p += sprintf(p, "Memory Model Feature 1: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c1, 6": "=r"(value)); + p += sprintf(p, "Memory Model Feature 2: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c1, 7": "=r"(value)); + p += sprintf(p, "Memory Model Feature 3: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c2, 0": "=r"(value)); + p += sprintf(p, "Set Attribute 0: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c2, 1": "=r"(value)); + p += sprintf(p, "Set Attribute 1: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c2, 2": "=r"(value)); + p += sprintf(p, "Set Attribute 2: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c2, 3": "=r"(value)); + p += sprintf(p, "Set Attribute 3: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c2, 4": "=r"(value)); + p += sprintf(p, "Set Attribute 4: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c0, c2, 5": "=r"(value)); + p += sprintf(p, "Set Attribute 5: 0x%08x\n", value); +#ifdef CONFIG_CPU_V7 + asm volatile("mrc p15, 1, %0, c0, c0, 0": "=r"(value)); + p += sprintf(p, "Current Cache Size ID: 0x%08x\n", value); + + asm volatile("mrc p15, 1, %0, c0, c0, 1": "=r"(value)); + p += sprintf(p, "Current Cache Level ID: 0x%08x\n", value); + + asm volatile("mrc p15, 1, %0, c0, c0, 7": "=r"(value)); + p += sprintf(p, "Silicon ID: 0x%08x\n", value); + + asm volatile("mrc p15, 2, %0, c0, c0, 0": "=r"(value)); + p += sprintf(p, "Cache Size Selection: 0x%08x\n", value); + +#endif + asm volatile("mrc p15, 0, %0, c1, c0, 0": "=r"(value)); + p += sprintf(p, "Control : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c1, c0, 1": "=r"(value)); + p += sprintf(p, "Auxiliary Control : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c1, c0, 2": "=r"(value)); + p += sprintf(p, "Coprocessor Access Control : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c1, c1, 0": "=r"(value)); + p += sprintf(p, "Secure Configuration : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c2, c0, 0": "=r"(value)); + p += sprintf(p, "Translation Table Base 0 : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c2, c0, 1": "=r"(value)); + p += sprintf(p, "Translation Table Base 1 : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c2, c0, 2": "=r"(value)); + p += sprintf(p, "Translation Table Control : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c3, c0, 0": "=r"(value)); + p += sprintf(p, "Domain Access Control : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c5, c0, 0": "=r"(value)); + p += sprintf(p, "Data Fault Status : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c5, c0, 1": "=r"(value)); + p += sprintf(p, "Instruction Fault Status : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c6, c0, 0": "=r"(value)); + p += sprintf(p, "Data Fault Address : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c6, c0, 1": "=r"(value)); + p += sprintf(p, "Watchpoint Fault Address : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c6, c0, 2": "=r"(value)); + p += sprintf(p, "Instruction Fault Address : 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c7, c10, 6": "=r"(value)); + p += sprintf(p, "Cache Dirty Status: 0x%08x\n", value); + + asm volatile("mrc p15, 1, %0, c15, c1, 0": "=r"(value)); + p += sprintf(p, "Auxiliary Debug Modes Control 0: 0x%08x\n", value); + + asm volatile("mrc p15, 1, %0, c15, c1, 1": "=r"(value)); + p += sprintf(p, "Auxiliary Debug Modes Control 1: 0x%08x\n", value); + +#if 1 + asm volatile("mrc p15, 1, %0, c15, c1, 0": "=r"(value)); + p += sprintf(p, "Control Configuration: 0x%08x\n", value); + p += sprintf(p, " Write Buffer Coalescing\t: %s\n", (value & (1 << 8)) ? + "Enabled" : "Disabled"); + if (value & (1 << 8)) + p += sprintf(p, " WB WAIT CYC\t: 0x%x\n", (value >> 9) & 0x7); + + p += sprintf(p, " Coprocessor dual issue \t: %s\n", (value & (1 << 15)) ? + "Disabled" : "Enabled"); + + p += sprintf(p, " L2 write allocate\t: %s\n", (value & (1 << 28)) ? + "Enabled" : "Disabled"); + + p += sprintf(p, " Streaming\t: %s\n", (value & (1 << 29)) ? + "Enabled" : "Disabled"); +#endif + asm volatile("mrc p15, 1, %0, c15, c12, 0": "=r"(value)); + p += sprintf(p, "CPU ID Code Extension: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c9, c14, 0": "=r"(value)); + p += sprintf(p, "User mode access for PMC registers: %s\n", (value & 1) ? + "Enabled" : "Disabled"); + asm volatile("mrc p15, 0, %0, c10, c2, 0": "=r"(value)); + p += sprintf(p, "Memory Attribute PRRR: 0x%08x\n", value); + + asm volatile("mrc p15, 0, %0, c10, c2, 1": "=r"(value)); + p += sprintf(p, "Memory Attribute NMRR: 0x%08x\n", value); + + asm volatile("mrc p15, 1, %0, c15, c1, 2": "=r"(value)); + p += sprintf(p, "Auxiliary Debug Modes Control 2: 0x%08x\n", value); + + asm volatile("mrc p15, 1, %0, c15, c2, 0": "=r"(value)); + p += sprintf(p, "Auxiliary Functional Modes Control 0: 0x%08x\n", value); + + asm volatile("mrc p15, 1, %0, c15, c2, 1": "=r"(value)); + p += sprintf(p, "Auxiliary Functional Modes Control 1: 0x%08x\n", value); + + len = (p - page) - off; + if (len < 0) + len = 0; + + *eof = (len <= count) ? 1 : 0; + *start = page + off; + + return len; +} +int dump_init_module(void) +{ +#ifdef CONFIG_PROC_FS + struct proc_dir_entry *res; + res = create_proc_entry("mv_dump_cp15", S_IRUSR, NULL); + if (!res) + return -ENOMEM; + + res->read_proc = proc_dump_cp15_read; +#endif + + return 0; +} + +void dump_cleanup_module(void) +{ + remove_proc_entry("mv_dump_cp15", NULL); +} + +module_init(dump_init_module); +module_exit(dump_cleanup_module); + +MODULE_AUTHOR("Saeed Bishara"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-armada370/export.c b/arch/arm/mach-armada370/export.c new file mode 100755 index 000000000..23d301c3c --- /dev/null +++ b/arch/arm/mach-armada370/export.c @@ -0,0 +1,203 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "mvDebug.h" +#include "mvSysHwConfig.h" +#include "pex/mvPexRegs.h" +#include "cntmr/mvCntmr.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvOs.h" + + +/************************************************************************************************************* + * Environment + *************************************************************************************************************/ +extern u32 mvTclk; +extern u32 mvSysclk; + +EXPORT_SYMBOL(mv_early_printk); +EXPORT_SYMBOL(mvCtrlPwrClckGet); +EXPORT_SYMBOL(mvCtrlModelRevGet); +EXPORT_SYMBOL(mvTclk); +EXPORT_SYMBOL(mvSysclk); +EXPORT_SYMBOL(mvCtrlModelGet); +EXPORT_SYMBOL(mvOsIoUncachedMalloc); +EXPORT_SYMBOL(mvOsIoUncachedFree); +EXPORT_SYMBOL(mvOsIoCachedMalloc); +EXPORT_SYMBOL(mvOsIoCachedFree); +EXPORT_SYMBOL(mvDebugMemDump); +EXPORT_SYMBOL(mvHexToBin); +EXPORT_SYMBOL(mvBinToHex); +EXPORT_SYMBOL(mvSizePrint); +EXPORT_SYMBOL(mvDebugPrintMacAddr); +EXPORT_SYMBOL(mvCtrlEthMaxPortGet); +EXPORT_SYMBOL(mvCtrlTargetNameGet); +EXPORT_SYMBOL(mvBoardIdGet); +EXPORT_SYMBOL(mvBoardPhyAddrGet); +EXPORT_SYMBOL(mvCpuIfTargetWinGet); +EXPORT_SYMBOL(mvMacStrToHex); +EXPORT_SYMBOL(mvBoardTclkGet); +EXPORT_SYMBOL(mvBoardMacSpeedGet); +EXPORT_SYMBOL(mvWinOverlapTest); +EXPORT_SYMBOL(mvCtrlAddrWinMapBuild); +EXPORT_SYMBOL(mvBoardTdmSpiModeGet); +EXPORT_SYMBOL(mvBoardTdmSpiCsGet); +EXPORT_SYMBOL(mvBoardTdmDevicesCountGet); + +#include "spi/mvSpiCmnd.h" +EXPORT_SYMBOL(mvSpiWriteThenWrite); +EXPORT_SYMBOL(mvSpiWriteThenRead); +#include "spi/mvSpi.h" +EXPORT_SYMBOL(mvSpiParamsSet); +#include "gpp/mvGpp.h" +EXPORT_SYMBOL(mvGppValueSet); + +/************************************************************************************************************* + * TDM + *************************************************************************************************************/ +#if defined(MV_INCLUDE_TDM) +EXPORT_SYMBOL(mvCtrlTdmUnitIrqGet); +EXPORT_SYMBOL(mvCtrlTdmUnitTypeGet); +#endif + +/************************************************************************************************************* + * Audio + *************************************************************************************************************/ +#ifdef CONFIG_MV_INCLUDE_AUDIO +#include "audio/mvAudio.h" +#include "mvSysAudioApi.h" +EXPORT_SYMBOL(mvSPDIFRecordTclockSet); +EXPORT_SYMBOL(mvSPDIFPlaybackCtrlSet); +EXPORT_SYMBOL(mvI2SPlaybackCtrlSet); +EXPORT_SYMBOL(mvAudioPlaybackControlSet); +EXPORT_SYMBOL(mvAudioDCOCtrlSet); +EXPORT_SYMBOL(mvI2SRecordCntrlSet); +EXPORT_SYMBOL(mvAudioRecordControlSet); +EXPORT_SYMBOL(mvSysAudioInit); +#endif + +/************************************************************************************************************* + * USB + *************************************************************************************************************/ +#ifdef CONFIG_MV_INCLUDE_USB +extern u32 mvIsUsbHost; + +#include "usb/mvUsb.h" +EXPORT_SYMBOL(mvIsUsbHost); +EXPORT_SYMBOL(mvCtrlUsbMaxGet); +EXPORT_SYMBOL(mvUsbGetCapRegAddr); +#ifdef MV_USB_VOLTAGE_FIX +EXPORT_SYMBOL(mvUsbGppInit); +EXPORT_SYMBOL(mvUsbBackVoltageUpdate); +#endif +#endif /* CONFIG_MV_INCLUDE_USB */ + +/************************************************************************************************************* + * CESA + *************************************************************************************************************/ +#ifdef CONFIG_MV_INCLUDE_CESA +#include "mvSysCesaApi.h" +#include "cesa/mvCesa.h" +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" +extern unsigned char* mv_sram_usage_get(int* sram_size_ptr); + +EXPORT_SYMBOL(mvSysCesaInit); +EXPORT_SYMBOL(mvCesaSessionOpen); +EXPORT_SYMBOL(mvCesaSessionClose); +EXPORT_SYMBOL(mvCesaAction); +EXPORT_SYMBOL(mvCesaReadyGet); +EXPORT_SYMBOL(mvCesaCopyFromMbuf); +EXPORT_SYMBOL(mvCesaCopyToMbuf); +EXPORT_SYMBOL(mvCesaMbufCopy); +EXPORT_SYMBOL(mvCesaCryptoIvSet); +EXPORT_SYMBOL(mvMD5); +EXPORT_SYMBOL(mvSHA1); + +EXPORT_SYMBOL(mvCesaDebugQueue); +EXPORT_SYMBOL(mvCesaDebugSram); +EXPORT_SYMBOL(mvCesaDebugSAD); +EXPORT_SYMBOL(mvCesaDebugStatus); +EXPORT_SYMBOL(mvCesaDebugMbuf); +EXPORT_SYMBOL(mvCesaDebugSA); +EXPORT_SYMBOL(mv_sram_usage_get); + +extern u32 mv_crypto_virt_base_get(void); +extern u32 mv_crypto_phys_base_get(void); +EXPORT_SYMBOL(mv_crypto_virt_base_get); +EXPORT_SYMBOL(mv_crypto_phys_base_get); +EXPORT_SYMBOL(cesaReqResources); +EXPORT_SYMBOL(mvCesaFinish); + +#endif + +/************************************************************************************************************* + * Flashes + *************************************************************************************************************/ +#if defined (CONFIG_MV_INCLUDE_SPI) +#include +#include +EXPORT_SYMBOL(mvSFlashInit); +EXPORT_SYMBOL(mvSFlashSectorErase); +EXPORT_SYMBOL(mvSFlashChipErase); +EXPORT_SYMBOL(mvSFlashBlockRd); +EXPORT_SYMBOL(mvSFlashBlockWr); +EXPORT_SYMBOL(mvSFlashIdGet); +EXPORT_SYMBOL(mvSFlashWpRegionSet); +EXPORT_SYMBOL(mvSFlashWpRegionGet); +EXPORT_SYMBOL(mvSFlashStatRegLock); +EXPORT_SYMBOL(mvSFlashSizeGet); +EXPORT_SYMBOL(mvSFlashPowerSaveEnter); +EXPORT_SYMBOL(mvSFlashPowerSaveExit); +EXPORT_SYMBOL(mvSFlashModelGet); +#endif + + +/************************************************************************************************************* + * SATA + *************************************************************************************************************/ +#ifdef CONFIG_MV_INCLUDE_INTEG_SATA +#include +EXPORT_SYMBOL(mvSataWinInit); +#endif + +/************************************************************************************************************* + * DMA/XOR + *************************************************************************************************************/ +#if (defined (CONFIG_MV_XOR_MEMCOPY) || defined (CONFIG_MV_IDMA_MEMCOPY)) && !defined(CONFIG_SYNO_ARMADA_ARCH) +EXPORT_SYMBOL(asm_memcpy); +#endif + +#ifdef CONFIG_MV_SP_I_FTCH_DB_INV +EXPORT_SYMBOL(mv_l2_inv_range); +#endif + +/************************************************************************************************************* + * Marvell TRACE + *************************************************************************************************************/ +#ifdef CONFIG_MV_DBG_TRACE +#include "dbg-trace.h" +EXPORT_SYMBOL(TRC_INIT); +EXPORT_SYMBOL(TRC_REC); +EXPORT_SYMBOL(TRC_OUTPUT); +EXPORT_SYMBOL(TRC_START); +EXPORT_SYMBOL(TRC_RELEASE); +#endif diff --git a/arch/arm/mach-armada370/flashmap.c b/arch/arm/mach-armada370/flashmap.c new file mode 100755 index 000000000..75dd10d87 --- /dev/null +++ b/arch/arm/mach-armada370/flashmap.c @@ -0,0 +1,274 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +********************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +/*#define MTD_FLASH_MAP_DEBUG*/ + +#ifdef MTD_FLASH_MAP_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#define MTD_MAX_FLASH_NUMBER 4 +#define MTD_DUMMY_BANK_WIDTH 2 + +struct maps_init_info +{ + struct map_info mapInfo; + char ** mtdDrv; + struct mtd_info * mtdInfo; + char name[32]; +}; + +static struct maps_init_info maps[MTD_MAX_FLASH_NUMBER]; +static unsigned int mapsNum = 0; + +#if defined (CONFIG_MTD_CFI) || defined (CONFIG_MTD_JEDECPROBE) +static char * cfiDev = "cfi_flash"; +static char * cfiMtdList[] = { "cfi_probe", "jedec_probe", "map_rom", NULL }; +#endif + +#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD +static char * sflashDev = "spi_flash"; +static char * sflashMtdList[] = {"sflash", NULL}; +#endif + +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition *mtd_parts; +static int mtd_parts_nb; +static const char *part_probes[] __initdata = {"cmdlinepart", NULL}; +#endif /* CONFIG_MTD_PARTITIONS */ + +static int flashInfoFill(void) +{ + int expectedDevs = 0; + int devs, i; + + /* clear the whole array */ + memset((void*)maps, 0x0, sizeof(maps)); + +#if defined (CONFIG_MTD_CFI) || defined (CONFIG_MTD_JEDECPROBE) + /* gather the CFI and JEDEC NOR flash devices information */ + devs = mvBoardGetDevicesNumber(BOARD_DEV_NOR_FLASH); + + for(i=0; i= MTD_MAX_FLASH_NUMBER) + { + printk(KERN_NOTICE "\nERROR: %s - Exceeded MAX MTD flash devices number", __FUNCTION__); + break; + } + maps[expectedDevs].mtdDrv = cfiMtdList; + sprintf(maps[expectedDevs].name, "%s_%d", cfiDev, i); + maps[expectedDevs].mapInfo.name = maps[expectedDevs].name; + maps[expectedDevs].mapInfo.phys = mvBoardGetDeviceBaseAddr(i, BOARD_DEV_NOR_FLASH); + maps[expectedDevs].mapInfo.size = mvBoardGetDeviceWinSize(i, BOARD_DEV_NOR_FLASH); + maps[expectedDevs].mapInfo.bankwidth = (mvBoardGetDeviceBusWidth(i, BOARD_DEV_NOR_FLASH) / 8); + + if ((maps[expectedDevs].mapInfo.phys != 0xFFFFFFFF) && + (maps[expectedDevs].mapInfo.size != 0xFFFFFFFF)) + { + DB(printk("\nINFO: Found %s %d - base 0x%08x, size 0x%x", maps[expectedDevs].mapInfo.name, i, + (unsigned int)maps[expectedDevs].mapInfo.phys, (unsigned int)maps[expectedDevs].mapInfo.size)); + ++expectedDevs; + } + else + { + printk(KERN_NOTICE "\nERROR: %s - Failed to get Device Base address and Size (%s %d)", __FUNCTION__, maps[expectedDevs].mapInfo.name, i); + } + } +#endif + +#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD + /* gather the SPI flash devices information */ + devs = mvBoardGetDevicesNumber(BOARD_DEV_SPI_FLASH); + + for(i=0; i= MTD_MAX_FLASH_NUMBER) + { + printk(KERN_NOTICE "\nERROR: %s - Exceeded MAX MTD flash devices number", __FUNCTION__); + break; + } + maps[expectedDevs].mtdDrv = sflashMtdList; + maps[expectedDevs].mapInfo.name = sflashDev; + maps[expectedDevs].mapInfo.phys = mvBoardGetDeviceBaseAddr(i, BOARD_DEV_SPI_FLASH); + maps[expectedDevs].mapInfo.size = mvBoardGetDeviceWinSize(i, BOARD_DEV_SPI_FLASH); + maps[expectedDevs].mapInfo.bankwidth = MTD_DUMMY_BANK_WIDTH; + + if ((maps[expectedDevs].mapInfo.phys != 0xFFFFFFFF) && + (maps[expectedDevs].mapInfo.size != 0xFFFFFFFF)) + { + DB(printk("\nINFO: Found %s %d - base 0x%08x, size 0x%x", maps[expectedDevs].mapInfo.name, i, + (unsigned int)maps[expectedDevs].mapInfo.phys, + (unsigned int)maps[expectedDevs].mapInfo.size)); + ++expectedDevs; + } + else + { + printk(KERN_NOTICE "\nERROR: %s - Failed to get Device Base address and Size (%s %d)", + __FUNCTION__, maps[expectedDevs].mapInfo.name, i); + } + } +#endif + + DB(printk("\nINFO: %s - Found %d Flash Devices", __FUNCTION__, expectedDevs)); + return expectedDevs; +} + +static int flashProbe(char ** mtdDrv, struct map_info * map, struct mtd_info ** mtd) +{ + if ((mtdDrv == NULL) || (map == NULL) || (mtd == NULL)) + { + printk(KERN_NOTICE "\nERROR: NULL pointer parameter at %s entry", __FUNCTION__); + return -EINVAL; + } + + /* remap the physical address to a virtual address */ + map->virt = ioremap(map->phys, map->size); + if (!map->virt) + { + printk(KERN_NOTICE "\nERROR: Failed to ioremap Flash device at physical base 0x%x.", (unsigned int)map->phys); + return -EIO; + } + + DB(printk("\nINFO: Io remapped successfully - phy addr = 0x%08x, virt addr = 0x%08x", + (unsigned int)map->phys, (unsigned int)map->virt)); + + simple_map_init(map); + + *mtd = NULL; + for(; (!(*mtd) && *mtdDrv); mtdDrv++) + { + DB(printk("\nINFO: Using %s to probe %s at address 0x%08x, size 0x%x, width %dm", + *mtdDrv, map->name, (unsigned int)map->phys, + (unsigned int)map->size, map->bankwidth)); + if ((*mtd = do_map_probe(*mtdDrv, map))) + { + DB(printk(" - detected OK")); + /*map->size = (*mtd)->size;*/ + (*mtd)->owner = THIS_MODULE; + +#ifdef CONFIG_MTD_PARTITIONS + mtd_parts_nb = parse_mtd_partitions(*mtd, part_probes, &mtd_parts, 0); + + if (mtd_parts_nb > 0) + { + add_mtd_partitions (*mtd, mtd_parts, mtd_parts_nb); + return 0; + } +#endif + + if (mtd_device_register(*mtd, NULL,0)) + { + printk(KERN_NOTICE "\nERROR: %s - Failed to add the mtd device", __FUNCTION__); + iounmap((void *)map->virt); + map->virt = 0; + return -ENXIO; + } + + return 0; + } + else + { + DB(printk(" - Not detected")); + } + } + + iounmap((void *)map->virt); + map->virt = 0; + return -ENXIO; +} + +static int __init flash_map_init(void) +{ + int i; + + mapsNum = flashInfoFill(); + DB(printk("\nINFO: flash_map_init - detected %d devices", mapsNum)); + + for (i=0; i +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +//#include "pmu/mvPmuRegs.h" + +/* Termal Sensor Registers */ +#define TSEN_STATUS_REG 0x18300 +#define TSEN_STATUS_TEMP_OUT_OFFSET 19 +#define TSEN_STATUS_TEMP_OUT_MASK (0x1FF << TSEN_STATUS_TEMP_OUT_OFFSET) + +#define TSEN_CONF_REG 0x18304 +#define TSEN_CONF_OTF_CALIB_MASK (0x1 << 30) +#define TSEN_CONF_REF_CAL_MASK (0x1FF << 11) +#define TSEN_CONF_SOFT_RESET_MASK (0x1 << 1) + +#define ARMADAXP_OVERHEAT_TEMP 105 /* milidegree Celsius */ +#define ARMADAXP_OVERHEAT_DELAY 0x700 +#define ARMADAXP_OVERCOOL_TEMP 10 /* milidegree Celsius */ +#define ARMADAXP_OVERCOOL_DELAY 0x700 +#define ARMADAXP_OVERHEAT_MIN 0 +#define ARMADAXP_OVERHEAT_MAX 110 +#define ARMADAXP_OVERCOOL_MIN 0 +#define ARMADAXP_OVERCOOL_MAX 110 + +/* Junction Temperature */ +#define ARMADAXP_TSEN_TEMP2RAW(x) ((3153000 - (13825 * x)) / 10000) +#define ARMADAXP_TSEN_RAW2TEMP(x) ((3153000 - (10000 * x)) / 13825) +#if 0 +/* Dove */ +((2281638 - (10 * x)) / 7298) /* in millCelsius */ + ((2281638 - (7298 * x)) / 10) +#endif + +#define LABEL "T-junction" +static struct device *hwmon_dev; +unsigned int temp_min = ARMADAXP_OVERCOOL_TEMP; +unsigned int temp_max = ARMADAXP_OVERHEAT_TEMP; + +typedef enum { + SHOW_TEMP, + TEMP_MAX, + TEMP_MIN, + SHOW_NAME, + SHOW_TYPE, + SHOW_LABEL } SHOW; + +static void axptemp_set_thresholds(unsigned int max, unsigned int min) +{ +#if 0 + u32 temp, reg; + + /* Set the overheat threashold & delay */ + temp = ARMADAXP_TSEN_TEMP2RAW(max); + reg = readl(INTER_REGS_BASE | PMU_THERMAL_MNGR_REG); + reg &= ~PMU_TM_OVRHEAT_THRSH_MASK; + reg |= (temp << PMU_TM_OVRHEAT_THRSH_OFFS); + writel(reg, (INTER_REGS_BASE | PMU_THERMAL_MNGR_REG)); + + /* Set the overcool threshole & delay */ + temp = ARMADAXP_TSEN_TEMP2RAW(min); + reg = readl(INTER_REGS_BASE | PMU_THERMAL_MNGR_REG); + reg &= ~PMU_TM_COOL_THRSH_MASK; + reg |= (temp << PMU_TM_COOL_THRSH_OFFS); + writel(reg, (INTER_REGS_BASE | PMU_THERMAL_MNGR_REG)); +#endif +} + +static int axptemp_init_sensor(void) +{ + u32 reg; + + /* init the TSEN sensor once */ + reg = readl(INTER_REGS_BASE | TSEN_CONF_REG); + reg |= TSEN_CONF_OTF_CALIB_MASK; + writel(reg, (INTER_REGS_BASE | TSEN_CONF_REG)); + + reg = readl(INTER_REGS_BASE | TSEN_CONF_REG); + reg &= ~(TSEN_CONF_REF_CAL_MASK); + reg |= (0xf1 << 11); + writel(reg, (INTER_REGS_BASE | TSEN_CONF_REG)); + + reg = readl(INTER_REGS_BASE | TSEN_CONF_REG); + reg |= TSEN_CONF_SOFT_RESET_MASK; + writel(reg, (INTER_REGS_BASE | TSEN_CONF_REG)); + + //udelay(1000); + + reg = readl(INTER_REGS_BASE | TSEN_CONF_REG); + reg &= ~(TSEN_CONF_SOFT_RESET_MASK); + writel(reg, (INTER_REGS_BASE | TSEN_CONF_REG)); + + //udelay(10000); + +#if 0 + /* Set thresholds */ + axptemp_set_thresholds(temp_max, temp_min); + + /* Set delays */ + writel(ARMADAXP_OVERHEAT_DELAY, (INTER_REGS_BASE | PMU_TM_OVRHEAT_DLY_REG)); + writel(ARMADAXP_OVERCOOL_DELAY, (INTER_REGS_BASE | PMU_TM_COOLING_DLY_REG)); +#endif + + return 0; +} + +#ifdef CONFIG_SYNO_ARMADA_ARCH +static int axptemp_read_temp(void) +#else +int axptemp_read_temp(void) +#endif +{ + int reg; + + reg = readl(INTER_REGS_BASE | TSEN_STATUS_REG); + reg = (reg & TSEN_STATUS_TEMP_OUT_MASK) >> TSEN_STATUS_TEMP_OUT_OFFSET; +// value = ((3153000 - (10000 * reg)) / 13825); + + return ARMADAXP_TSEN_RAW2TEMP(reg); +} +#ifdef CONFIG_SYNO_ARMADA_ARCH +EXPORT_SYMBOL(axptemp_read_temp); +#endif + + +/* + * Sysfs stuff + */ + +static ssize_t show_name(struct device *dev, struct device_attribute + *devattr, char *buf) { + return sprintf(buf, "%s\n", "axp-hwmon"); +} + +static ssize_t show_alarm(struct device *dev, struct device_attribute + *devattr, char *buf) +{ +#if 0 + int alarm = 0; + u32 reg; + + reg = readl(INTER_REGS_BASE | PMU_INT_CAUSE_REG); + if (reg & PMU_INT_OVRHEAT_MASK) + { + alarm = 1; + writel ((reg & ~PMU_INT_OVRHEAT_MASK), (INTER_REGS_BASE | PMU_INT_CAUSE_REG)); + } + else if (reg & PMU_INT_COOLING_MASK) + { + alarm = 2; + writel ((reg & ~PMU_INT_COOLING_MASK), (INTER_REGS_BASE | PMU_INT_CAUSE_REG)); + } +#endif + return sprintf(buf, "%d\n", 0); +} + +static ssize_t show_info(struct device *dev, + struct device_attribute *devattr, char *buf) { + int ret; + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + + if (attr->index == SHOW_TYPE) + ret = sprintf(buf, "%d\n", 3); + else if (attr->index == SHOW_LABEL) + ret = sprintf(buf, "%s\n", LABEL); + else + ret = sprintf(buf, "%d\n", -1); + return ret; +} + +static ssize_t show_temp(struct device *dev, + struct device_attribute *devattr, char *buf) { + int ret; + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + + if (attr->index == SHOW_TEMP) + ret = sprintf(buf, "%d\n", axptemp_read_temp()); + else if (attr->index == TEMP_MAX) + ret = sprintf(buf, "%d\n", temp_max); + else if (attr->index == TEMP_MIN) + ret = sprintf(buf, "%d\n", temp_min); + else + ret = sprintf(buf, "%d\n", -1); + + return ret; +} + +static ssize_t set_temp(struct device *dev, struct device_attribute *devattr, + const char *buf, size_t count) { + + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + unsigned int temp; + + if (sscanf(buf, "%d", &temp) != 1) + printk(KERN_WARNING "Invalid input string for temperature!"); + + if (attr->index == TEMP_MAX) { + if((temp < ARMADAXP_OVERHEAT_MIN) || (temp > ARMADAXP_OVERHEAT_MAX)) + printk(KERN_WARNING "Invalid max temperature input (out of range: %d-%d)!", + ARMADAXP_OVERHEAT_MIN, ARMADAXP_OVERHEAT_MAX); + else { + temp_max = temp; + axptemp_set_thresholds(temp_max, temp_min); + } + } + else if (attr->index == TEMP_MIN) { + if((temp < ARMADAXP_OVERCOOL_MIN) || (temp > ARMADAXP_OVERCOOL_MAX)) + printk(KERN_WARNING "Invalid min temperature input (out of range: %d-%d)!", + ARMADAXP_OVERCOOL_MIN, ARMADAXP_OVERCOOL_MAX); + else { + temp_min = temp; + axptemp_set_thresholds(temp_max, temp_min); + } + } + else + printk(KERN_ERR "axp-temp: Invalid sensor attribute!"); + + printk(KERN_INFO "set_temp got string: %d\n", temp); + + return count; +} + +/* TODO - Add read/write support in order to support setting max/min */ +static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO, show_info, NULL, + SHOW_TYPE); +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_info, NULL, + SHOW_LABEL); +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, + SHOW_TEMP); +static SENSOR_DEVICE_ATTR(temp1_max, S_IRWXUGO, show_temp, set_temp, + TEMP_MAX); +static SENSOR_DEVICE_ATTR(temp1_min, S_IRWXUGO, show_temp, set_temp, + TEMP_MIN); +static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL); +static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME); + +static struct attribute *axptemp_attributes[] = { + &sensor_dev_attr_name.dev_attr.attr, + &dev_attr_temp1_crit_alarm.attr, + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp1_max.dev_attr.attr, + &sensor_dev_attr_temp1_min.dev_attr.attr, + &sensor_dev_attr_temp1_type.dev_attr.attr, + &sensor_dev_attr_temp1_label.dev_attr.attr, + NULL +}; + +static const struct attribute_group axptemp_group = { + .attrs = axptemp_attributes, +}; + +static int __devinit axptemp_probe(struct platform_device *pdev) +{ + int err; + + err = axptemp_init_sensor(); + if (err) + goto exit; + + err = sysfs_create_group(&pdev->dev.kobj, &axptemp_group); + if (err) + goto exit; + + hwmon_dev = hwmon_device_register(&pdev->dev); + if (IS_ERR(hwmon_dev)) { + dev_err(&pdev->dev, "Class registration failed (%d)\n", + err); + goto exit; + } + + printk(KERN_INFO "Armada XP hwmon thermal sensor initialized.\n"); + + return 0; + +exit: + sysfs_remove_group(&pdev->dev.kobj, &axptemp_group); + return err; +} + +static int __devexit axptemp_remove(struct platform_device *pdev) +{ + struct axptemp_data *data = platform_get_drvdata(pdev); + + hwmon_device_unregister(hwmon_dev); + sysfs_remove_group(&pdev->dev.kobj, &axptemp_group); + platform_set_drvdata(pdev, NULL); + kfree(data); + return 0; +} + +static int axptemp_resume(struct platform_device *dev) +{ + return axptemp_init_sensor(); +} + +static struct platform_driver axptemp_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "axp-temp", + }, + .probe = axptemp_probe, + .remove = __devexit_p(axptemp_remove), + .resume = axptemp_resume, +}; + +static int __init axptemp_init(void) +{ + return platform_driver_register(&axptemp_driver); +} + +static void __exit axptemp_exit(void) +{ + platform_driver_unregister(&axptemp_driver); +} + +MODULE_AUTHOR("Marvell Semiconductors"); +MODULE_DESCRIPTION("Marvell Armada XP SoC hwmon driver"); +MODULE_LICENSE("GPL"); + +module_init(axptemp_init) +module_exit(axptemp_exit) diff --git a/arch/arm/mach-armada370/include/mach/armada370.h b/arch/arm/mach-armada370/include/mach/armada370.h new file mode 100755 index 000000000..d4a19ae0b --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/armada370.h @@ -0,0 +1,150 @@ +/* + * Generic definitions for Marvell Armada MV88F6710 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_AURORA_H +#define __ASM_ARCH_AURORA_H + +#include + +/****************************************************************/ +/******************* System Address Mapping *********************/ +/****************************************************************/ + +/* + * Armada-XP address maps. + * + * phys virt size + * e0000000 @runtime 128M PCIe-0 Memory space + * e8000000 @runtime 128M PCIe-1 Memory space + * f0000000 fab00000 16M SPI-CS0 (Flash) + * d0000000 fbb00000 1M Internal Registers + * f1100000 fbc00000 1M PCIe-0 I/O space + * f1200000 fbd00000 1M PCIe-1 I/O space + * f1b00000 fc600000 1M DMA based UART + * f2000000 fc700000 32M Device-CS0 (NOR Flash) + * f4000000 fe700000 1M Boot-Device CS + * f4100000 fe800000 1M Device-CS1 (NOR Flash) + * f4200000 fe900000 1M Device-CS2 (NOR Flash) + * f4300000 fea00000 1M Device-CS3 (NOR Flash) + * f4400000 feb00000 1M CESA SRAM + * f4600000 fed00000 1M BootROM + * f4700000 fee00800 1M PMU Scratch pad + * f4800000 fef00000 1M Legacy Nand Flash + */ + +/* + * SDRAM Address decoding + * These values are dummy. Uboot configures these values. + */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* + * PEX Address Decoding + * Virtual address not specified - remapped @runtime + */ +#define PEX0_MEM_PHYS_BASE 0xE0000000 +#define PEX0_MEM_SIZE _32M +#define PEX1_MEM_PHYS_BASE 0xE2000000 +#define PEX1_MEM_SIZE _32M + +#define SPI_CS0_PHYS_BASE 0xF0000000 +#define SPI_CS0_VIRT_BASE 0xFAB00000 +#define SPI_CS0_SIZE _16M + +#define INTER_REGS_PHYS_BASE 0xF1000000 +#define INTER_REGS_BASE 0xFBB00000 + +#define PEX0_IO_PHYS_BASE 0xF1100000 +#define PEX0_IO_VIRT_BASE 0xFBC00000 +#define PEX0_IO_SIZE _1M +#define PEX1_IO_PHYS_BASE 0xF1200000 +#define PEX1_IO_VIRT_BASE 0xFBD00000 +#define PEX1_IO_SIZE _1M + +#define UART_REGS_BASE 0xF1B00000 +#define UART_VIRT_BASE 0xFC600000 +#define UART_SIZE _1M + +#define DEVICE_CS0_PHYS_BASE 0xF2000000 +#define DEVICE_CS0_VIRT_BASE 0xFC700000 +#define DEVICE_CS0_SIZE _32M +#define DEVICE_BOOTCS_PHYS_BASE 0xF5000000 +#define DEVICE_BOOTCS_VIRT_BASE 0xF5000000 +#define DEVICE_BOOTCS_SIZE _16M +#define DEVICE_CS1_PHYS_BASE 0xF4100000 +#define DEVICE_CS1_VIRT_BASE 0xFE800000 +#define DEVICE_CS1_SIZE _1M +#define DEVICE_CS2_PHYS_BASE 0xF4200000 +#define DEVICE_CS2_VIRT_BASE 0xFE900000 +#define DEVICE_CS2_SIZE _1M +#define DEVICE_CS3_PHYS_BASE 0xF4300000 +#define DEVICE_CS3_VIRT_BASE 0xFEA00000 +#define DEVICE_CS3_SIZE _1M + +#define CRYPT_ENG_PHYS_BASE(chan) 0xC8010000 +#define CRYPT_ENG_VIRT_BASE(chan) 0xFEB00000 +#define CRYPT_ENG_SIZE _64K + +#define XOR0_PHYS_BASE (INTER_REGS_PHYS_BASE | 0x60800) +#define XOR1_PHYS_BASE (INTER_REGS_PHYS_BASE | 0x60900) +#define XOR0_HIGH_PHYS_BASE (INTER_REGS_PHYS_BASE | 0x60A00) +#define XOR1_HIGH_PHYS_BASE (INTER_REGS_PHYS_BASE | 0x60B00) + +#define BOOTROM_PHYS_BASE 0xFFF00000 +#define BOOTROM_VIRT_BASE 0xFE700000 +#define BOOTROM_SIZE _1M + +#define PMU_SCRATCH_PHYS_BASE 0xF4700000 +#define PMU_SCRATCH_VIRT_BASE 0xFEE00000 +#define PMU_SCRATCH_SIZE _1M + +#define LEGACY_NAND_PHYS_BASE 0xF4800000 +#define LEGACY_NAND_VIRT_BASE 0xFEF00000 +#define LEGACY_NAND_SIZE _1M + +#define AXP_NFC_PHYS_BASE (INTER_REGS_PHYS_BASE | 0xD0000) + +/* + * Linux native definitiotns + */ +#define SDRAM_OPERATION_REG (INTER_REGS_BASE | 0x1418) +#define SDRAM_CONFIG_REG (INTER_REGS_BASE | 0x1400) +#define SDRAM_DLB_EVICT_REG (INTER_REGS_BASE | 0x170C) + +#define AXP_UART0_PHYS_BASE (INTER_REGS_PHYS_BASE | 0x12000) +#define DDR_VIRT_BASE (INTER_REGS_BASE | 0x00000) +#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x20000) +#define AXP_BRIDGE_VIRT_BASE (INTER_REGS_BASE | 0x20000) +#define AXP_SW_TRIG_IRQ (AXP_BRIDGE_VIRT_BASE | 0x0A04) +#define AXP_PER_CPU_BASE (AXP_BRIDGE_VIRT_BASE | 0x1000) +#define AXP_IRQ_VIRT_BASE (AXP_PER_CPU_BASE) +#define AXP_IRQ_SEL_CAUSE_OFF 0xA0 +#define AXP_IN_DOORBELL_CAUSE 0x78 +#define AXP_IN_DRBEL_MSK (AXP_PER_CPU_BASE | 0x7c) +#define AXP_CPU_RESUME_CTRL_REG (AXP_BRIDGE_VIRT_BASE | 0x988) +#define AXP_CPU_RESUME_ADDR_REG(cpu) (AXP_BRIDGE_VIRT_BASE | (0x2124+(cpu)*0x100)) +#define AXP_CPU_RESET_REG(cpu) (AXP_BRIDGE_VIRT_BASE | (0x800+(cpu)*8)) +#define AXP_L2_CLEAN_WAY_REG (INTER_REGS_BASE | 0x87BC) +#define AXP_L2_MNTNC_STAT_REG (INTER_REGS_BASE | 0x8704) +#define AXP_ASM_GPP_IRQ_CAUSE_REG (INTER_REGS_BASE + 0x18110) /* level interrupts for gpp cause */ +#define AXP_ASM_GPP_IRQ_MID_CAUSE_REG (INTER_REGS_BASE + 0x18150) /* level interrupts for gpp mid cause */ +#define AXP_ASM_GPP_IRQ_HIGH_CAUSE_REG (INTER_REGS_BASE + 0x18190) /* level interrupts for gpp high cause */ +#define AXP_ASM_GPP_IRQ_MASK_REG (INTER_REGS_BASE + 0x1811c) /* level low mask */ +#define AXP_ASM_GPP_IRQ_MID_MASK_REG (INTER_REGS_BASE + 0x1815c) /* level mid mask */ +#define AXP_ASM_GPP_IRQ_HIGH_MASK_REG (INTER_REGS_BASE + 0x1819c) /* level high mask */ +#define AXP_ASM_SOC_MAIN_ERR_CAUSE_REG (INTER_REGS_BASE + 0x20A20) /* SoC main error cause */ +#define AXP_ASM_SOC_MAIN_ERR_MASK_REG (INTER_REGS_BASE + 0x218C0) /* SoC main error mask */ + +#endif diff --git a/arch/arm/mach-armada370/include/mach/clkdev.h b/arch/arm/mach-armada370/include/mach/clkdev.h new file mode 100755 index 000000000..04b37a898 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-armada370/include/mach/debug-macro.S b/arch/arm/mach-armada370/include/mach/debug-macro.S new file mode 100755 index 000000000..51f9fb870 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/debug-macro.S @@ -0,0 +1,29 @@ +/* + * debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + + .macro addruart, rp, rv, tmp + ldr \rp, =INTER_REGS_PHYS_BASE + ldr \rv, =INTER_REGS_BASE + orr \rp, \rp, #0x00012000 + orr \rv, \rv, #0x00012000 + .endm + + +#if 0 + .macro addruart,rx, tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =INTER_REGS_PHYS_BASE + ldrne \rx, =INTER_REGS_BASE + orr \rx, \rx, #0x00012000 + .endm +#endif +#define UART_SHIFT 2 +#include diff --git a/arch/arm/mach-armada370/include/mach/dma.h b/arch/arm/mach-armada370/include/mach/dma.h new file mode 100755 index 000000000..8e2f2d0ba --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/dma.h @@ -0,0 +1,16 @@ +/* + * DaVinci DMA definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-armada370/include/mach/entry-macro.S b/arch/arm/mach-armada370/include/mach/entry-macro.S new file mode 100755 index 000000000..aab77b6a1 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/entry-macro.S @@ -0,0 +1,145 @@ +/* + * arch/arm/mach-armada370/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for Marvell Armada370 platform + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =AXP_IRQ_VIRT_BASE + .endm + +#if defined(CONFIG_CPU_BIG_ENDIAN) + .macro HTOLL sr, tt @ sr = A ,B ,C ,D + eor \tt, \sr, \sr, ror #16 ; @ temp = A^C,B^ + bic \tt, \tt, #0xff0000 ; @ temp = A^C,0 ,C^A,D^B + mov \sr, \sr, ror #8 ; @ sr = D ,A ,B ,C + eor \sr, \sr, \tt, lsr #8 @ sr = D ,C ,B ,A + .endm +#else + .macro HTOLL sr, tt + .endm +#endif + /* TBD - need to be optimized 29*(sel-1) + cls */ + /* r1 - we shouldnt use it here */ + /* in case of SMP we only handle bit 0,1 (doorbell) and 5,6 (timer) from cause Vec 0 */ + /* return value is: irqnr and the flag state!!!!!!!!!!!! */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ check low interrupts + ldr \irqstat, [\base, #AXP_IRQ_SEL_CAUSE_OFF] + HTOLL \irqstat, \tmp + ands \tmp, \irqstat, #0x80000000 @ did we get irq + beq 1004f + mov \tmp, \irqstat + mov \tmp, \tmp, lsr #29 @ determine the irq group, + bics \tmp, \tmp, #4 @ clear irq_stat bit + bic \irqstat, \irqstat, #(0xE0000000) @ leave irq bits, clear the rest + mov \irqnr, #0x1F + orrs \irqnr, \irqnr, \tmp, lsl #5 @ irqnr = 0x1F, 0x3F, 0x5F, 0x7f, make sure Z is off + clz \irqstat, \irqstat @ find first active interrupt source + sub \irqnr, \irqnr, \irqstat + mov r1, #3 + mul \tmp, r1, \tmp + sub \irqnr, \irqnr, \tmp @ irqnr = per cpu irq number + cmp \irqnr, #82 @ GPP LOW 0-7 + beq 1000f + cmp \irqnr, #83 @ GPP LOW 8-15 + beq 1000f + cmp \irqnr, #84 @ GPP LOW 16-23 + beq 1000f + cmp \irqnr, #85 @ GPP LOW 24-31 + beq 1000f + cmp \irqnr, #87 @ GPP LOW 32-39 + beq 1001f + cmp \irqnr, #88 @ GPP LOW 40-47 + beq 1001f + cmp \irqnr, #89 @ GPP LOW 48-55 + beq 1001f + cmp \irqnr, #90 @ GPP LOW 56-63 + beq 1001f + cmp \irqnr, #91 @ GPP LOW 64-66 + beq 1002f + cmp \irqnr, #4 @ SoC Main Error Summary + beq 1003f + b 1004f + +1000: + ldr \tmp, =AXP_ASM_GPP_IRQ_MASK_REG + ldr \tmp, [\tmp] @ get gpp mask + ldr \irqstat, =AXP_ASM_GPP_IRQ_CAUSE_REG + ldr \irqstat, [\irqstat] @ get gpp data in (cause) + ands \irqstat, \irqstat, \tmp @ and mask and cause + beq 1004f @ if eq to 0 jump to 1004 + HTOLL \irqstat, \tmp + clz \irqnr, \irqstat + mov \tmp, #31 + subs \irqnr, \tmp, \irqnr + add \irqnr,\irqnr, #128 @ set GPIO base irq + teq \irqnr, #160 @ if irq isn't 160 unset the flag + b 1004f + +1001: + ldr \tmp, =AXP_ASM_GPP_IRQ_MID_MASK_REG + ldr \tmp, [\tmp] @ get gpp mask + ldr \irqstat, =AXP_ASM_GPP_IRQ_MID_CAUSE_REG + ldr \irqstat, [\irqstat] @ get gpp data in (cause) + ands \irqstat, \irqstat, \tmp @ and mask and cause + beq 1004f @ if eq to 0 jump to 1004 + HTOLL \irqstat, \tmp + clz \irqnr, \irqstat + mov \tmp, #31 + subs \irqnr, \tmp, \irqnr + add \irqnr,\irqnr, #160 @ set GPIO base irq + teq \irqnr, #192 @ if irq isn't 192 unset the flag + b 1004f + +1002: + ldr \tmp, =AXP_ASM_GPP_IRQ_HIGH_MASK_REG + ldr \tmp, [\tmp] @ get gpp mask + ldr \irqstat, =AXP_ASM_GPP_IRQ_HIGH_CAUSE_REG + ldr \irqstat, [\irqstat] @ get gpp data in (cause) + ands \irqstat, \irqstat, \tmp @ and mask and cause + beq 1004f @ if eq to 0 jump to 1004 + HTOLL \irqstat, \tmp + clz \irqnr, \irqstat + mov \tmp, #31 + subs \irqnr, \tmp, \irqnr + add \irqnr,\irqnr, #192 @ set GPIO base irq + teq \irqnr, #224 @ if irq isn't 224 unset the flag + b 1004f + +1003: + ldr \tmp, =AXP_ASM_SOC_MAIN_ERR_MASK_REG + ldr \tmp, [\tmp] @ get SoC main error mask + ldr \irqstat, =AXP_ASM_SOC_MAIN_ERR_CAUSE_REG + ldr \irqstat, [\irqstat] @ get SoC main error cause + ands \irqstat, \irqstat, \tmp @ and mask and cause + beq 1004f @ if eq to 0 jump to 1004 + HTOLL \irqstat, \tmp + clz \irqnr, \irqstat + mov \tmp, #31 + subs \irqnr, \tmp, \irqnr + add \irqnr,\irqnr, #224 @ set GPIO base irq + teq \irqnr, #256 @ if irq isn't 256 unset the flag + b 1004f + +1004: + .endm + + .macro test_for_pmuirq, irqnr, irqstat, base, tmp + ands \tmp, \irqstat, #0x80000000 @ did we get irq + beq 1005f + ands \tmp, \irqstat, #0x00000008 @ was it mp +1005: + .endm diff --git a/arch/arm/mach-armada370/include/mach/gpio.h b/arch/arm/mach-armada370/include/mach/gpio.h new file mode 100755 index 000000000..7ca789dbe --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/gpio.h @@ -0,0 +1,55 @@ +/* + * include/asm-arm/arch-dove/gpio.h + * + * Author: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include +#include +#include +#include /* cansleep wrappers */ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep + +#define GPIO_MAX 64 + +#define GPIO_BASE_LO (AURORA_GPIO_VIRT_BASE + 0x00) +#define GPIO_BASE_HI (AURORA_GPIO_VIRT_BASE + 0x20) + +#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI) + +#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00) +#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08) +#define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c) + +static inline int gpio_to_irq(int pin) +{ + if (pin < NR_GPIO_IRQS) + return pin + IRQ_AURORA_GPIO_START; + + return -EINVAL; +} + +static inline int irq_to_gpio(int irq) +{ + if (IRQ_AURORA_GPIO_START < irq && irq < NR_IRQS) + return irq - IRQ_AURORA_GPIO_START; + + return -EINVAL; +} + +#endif diff --git a/arch/arm/mach-armada370/include/mach/hardware.h b/arch/arm/mach-armada370/include/mach/hardware.h new file mode 100755 index 000000000..e31d9aa26 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/hardware.h @@ -0,0 +1,14 @@ +/* + * include/asm-arm/arch-dove/hardware.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include "armada370.h" + +#endif diff --git a/arch/arm/mach-armada370/include/mach/ide.h b/arch/arm/mach-armada370/include/mach/ide.h new file mode 100755 index 000000000..04e0bca10 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/ide.h @@ -0,0 +1,15 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/arch/arm/mach-armada370/include/mach/io.h b/arch/arm/mach-armada370/include/mach/io.h new file mode 100755 index 000000000..f358ee009 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/io.h @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-dove/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "armada370.h" + +#define IO_SPACE_LIMIT 0xffffffff +#define IO_SPACE_REMAP PEX0_IO_PHYS_BASE + +#define __io(a) ((a) + PEX0_IO_VIRT_BASE) +#define __mem_pci(a) ((unsigned long)(a)) +#define __mem_isa(a) (a) + +/*#define aurora_setbits(r, mask) writel(readl(r) | (mask), (r)) +#define aurora_clrbits(r, mask) writel(readl(r) & ~(mask), (r))*/ + +#ifdef CONFIG_AURORA_IO_CACHE_COHERENCY +#define dma_io_sync() do { \ + writel(0x1, INTER_REGS_BASE + 0x21810); \ + while (readl(INTER_REGS_BASE + 0x21810) & 0x1); \ +} while (0) +#else +#define dma_io_sync() do { } while (0) +#endif +#endif diff --git a/arch/arm/mach-armada370/include/mach/irqs.h b/arch/arm/mach-armada370/include/mach/irqs.h new file mode 100755 index 000000000..8caadb9f4 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/irqs.h @@ -0,0 +1,153 @@ +/* + * include/asm-arm/arch-aurora/irqs.h + * + * IRQ definitions for Marvell Dove MV88F6781 SoC + * + * Author: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* + * Aurora Low Interrupt Controller + */ + +#define IRQ_AURORA_IN_DRBL_LOW 0 +#define IRQ_AURORA_IN_DRBL_HIGH 1 +#define IRQ_AURORA_OUT_DRBL 2 +#define IRQ_AURORA_MP 3 +#define IRQ_AURORA_SOC_ERROR 4 +#define IRQ_AURORA_TIMER0 5 +#define IRQ_LOCALTIMER IRQ_AURORA_TIMER0 +#define IRQ_AURORA_TIMER1 6 +#define IRQ_AURORA_WD 7 +#define IRQ_AURORA_GBE0_FIC 8 +#define IRQ_AURORA_GBE0_SIC 9 +#define IRQ_AURORA_GBE1_FIC 10 +#define IRQ_AURORA_GBE1_SIC 11 + +#define IRQ_AURORA_SPI 30 +#define IRQ_AURORA_I2C0 31 +#define IRQ_AURORA_I2C1 32 + +#define IRQ_AURORA_GLOB_TIMER0 37 +#define IRQ_AURORA_GLOB_TIMER1 38 +#define IRQ_AURORA_GLOB_TIMER2 39 +#define IRQ_AURORA_GLOB_TIMER3 40 + +#define IRQ_AURORA_UART0 41 +#define IRQ_AURORA_UART1 42 + +#define IRQ_AURORA_USB0 45 +#define IRQ_AURORA_USB1 46 +#define IRQ_AURORA_USB(x) (45 + x) + +#define IRQ_AURORA_CRYPTO(chan) 48 + +#define IRQ_AURORA_RTC 50 + +#define IRQ_AURORA_XOR0_CH0 51 +#define IRQ_AURORA_XOR0_CH1 52 + +#define IRQ_AURORA_SDIO 54 +#define IRQ_AURORA_SATA0 55 +#define IRQ_AURORA_TDM 56 +#define IRQ_AURORA_SATA1 57 +#define IRQ_AURORA_PCIE0 58 + +#define IRQ_AURORA_PCIE1 62 + +#define IRQ_AURORA_GBE0 66 +#define IRQ_AURORA_GBE0_RX 67 +#define IRQ_AURORA_GBE0_TX 68 +#define IRQ_AURORA_GBE0_MISC 69 +#define IRQ_AURORA_GBE1 70 +#define IRQ_AURORA_GBE1_RX 71 +#define IRQ_AURORA_GBE1_TX 72 +#define IRQ_AURORA_GBE1_MISC 73 + +#define IRQ_AURORA_GPIO_0_7 82 +#define IRQ_AURORA_GPIO_8_15 83 +#define IRQ_AURORA_GPIO_16_23 84 +#define IRQ_AURORA_GPIO_24_31 85 +#define IRQ_AURORA_GPIO_32_39 87 +#define IRQ_AURORA_GPIO_40_47 88 +#define IRQ_AURORA_GPIO_48_55 89 +#define IRQ_AURORA_GPIO_56_63 90 +#define IRQ_AURORA_GPIO_64_66 91 + +#define IRQ_AURORA_AUDIO 93 + +#define IRQ_AURORA_XOR1_CH0 94 +#define IRQ_AURORA_XOR1_CH1 95 + +#define IRQ_AURORA_OUTB_DB0 96 +#define IRQ_AURORA_OUTB_DB1 97 +#define IRQ_AURORA_OUTB_DB2 98 + +#define IRQ_AURORA_DRAM 108 +#define IRQ_AURORA_NET_WKUP0 109 +#define IRQ_AURORA_NET_WKUP1 110 + +#define IRQ_AURORA_NFC 113 +#define IRQ_AURORA_MTL_FIX 114 + +#define IRQ_MAIN_INTS_NUM 115 + +/* + * AURORA General Purpose Pins + */ +#define IRQ_AURORA_GPIO_START 128 +#define NR_GPIO_IRQS 96 /* only 67 irqs are valid ,but just to be aligned */ + +#define GPP_IRQ_TYPE_LEVEL 0 +#define GPP_IRQ_TYPE_CHANGE_LEVEL 1 + +/* + * Aurora Error interrupts + */ + +#define MV_SOC_MAIN_INT_ERR_MASK_REG 0x218C0 +#define MV_SOC_MAIN_INT_ERR_CAUSE_REG 0x20A20 + +#define IRQ_AURORA_ERR_START 224 +#define NR_SOC_MAIN_ERR_IRQS 32 + +#define INT_ERR_CESA0 0 +#define INT_ERR_DEVBUS 1 +#define INT_ERR_PCIE(unit) ((unit == 0) ? 4 : 5) + +/* + * IRQ HAL remapping + */ +#define NET_TH_RXTX_IRQ_NUM(x) (IRQ_AURORA_GBE0_FIC + ((x) * 2)) +#define SATA_IRQ_NUM (IRQ_AURORA_SATA0) +#define CESA_IRQ(chan) IRQ_AURORA_CRYPTO(chan) +#define IRQ_GPP_START IRQ_AURORA_GPIO_START +#define IRQ_AURORA_SATA(x) ((x == 0) ? IRQ_AURORA_SATA0 : IRQ_AURORA_SATA1) + +#define MV_PCI_MASK_REG(unit) ((unit == 0) ? 0x41910 : 0x81910) +#define MV_PCI_IRQ_CAUSE_REG(unit) ((unit == 0) ? 0x41900 : 0x81900) +#define MV_PCI_MASK_ABCD (BIT24 | BIT25 | BIT26 | BIT27 ) + +/* Description for bit from PCI Express Interrupt Mask Register +** BIT3 - Erroneous Write Attempt to Internal Register +** BIT4 - Hit Default Window Error +** BIT6 and BIT7 -Rx and Tx RAM Parity Error +** BIT9 and BIT10 - Non Fatal and Fatal Error Detected +** BIT14 - Flow Control Protocol Error +** BIT23 - Link Failure Indication +*/ +#define MV_PCI_MASK_ERR (BIT3 | BIT4 | BIT6 | BIT7 | BIT9 | BIT10 | BIT14 | BIT23) + +#define NR_IRQS (IRQ_AURORA_ERR_START + NR_SOC_MAIN_ERR_IRQS) + +/* Interrupt Macros for backward compatibility */ +#define IRQ_USB_CTRL(x) ((x == 0) ? IRQ_AURORA_USB0 : IRQ_AURORA_USB1) + +#endif diff --git a/arch/arm/mach-armada370/include/mach/kw_macro.h b/arch/arm/mach-armada370/include/mach/kw_macro.h new file mode 100755 index 000000000..120992236 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/kw_macro.h @@ -0,0 +1,39 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Assembler-only file + */ + + +support_wait_for_interrupt_address: + .word support_wait_for_interrupt + +/* rd, rs, rt, re - are temp registers that will b used (non are input/output) */ +.macro mv_flush_all, rd, rs, rt, re + mov \re, #0 + + mov \rd, #(4 - 1) << 30 @ 4 way cache + mov \rs, #(256 * CACHE_DLINESIZE) + +1: orr \rt, \re, \rd +2: mcr p15, 0, \rt, c7, c14, 2 @ clean & invalidate D index + subs \rt, \rt, #1 << 30 + bcs 2b @ entries 3 to 0 + add \re, \re, #32 + cmp \re, \rs + bne 1b + +/* exit */ + .endm diff --git a/arch/arm/mach-armada370/include/mach/memory.h b/arch/arm/mach-armada370/include/mach/memory.h new file mode 100755 index 000000000..aafcbb769 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/memory.h @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-mv78xx0/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +/* #define __virt_to_bus(x) __virt_to_phys(x) */ +/* #define __bus_to_virt(x) __phys_to_virt(x) */ + + +/* Override the ARM default */ +#ifdef CONFIG_FB_AURORA_CONSISTENT_DMA_SIZE + +#if (CONFIG_FB_AURORA_CONSISTENT_DMA_SIZE == 0) +#undef CONFIG_FB_AURORA_CONSISTENT_DMA_SIZE +#define CONFIG_FB_AURORA_CONSISTENT_DMA_SIZE 2 +#endif + +#define CONSISTENT_DMA_SIZE \ + (((CONFIG_FB_AURORA_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024) + +#endif + +#ifdef CONFIG_AURORA_IO_CACHE_COHERENCY +#define arch_is_coherent() 1 +#endif + + +#endif diff --git a/arch/arm/mach-armada370/include/mach/param.h b/arch/arm/mach-armada370/include/mach/param.h new file mode 100755 index 000000000..04e0bca10 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/param.h @@ -0,0 +1,15 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/arch/arm/mach-armada370/include/mach/serial.h b/arch/arm/mach-armada370/include/mach/serial.h new file mode 100755 index 000000000..7af1a8fbb --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/serial.h @@ -0,0 +1,40 @@ +/* + * linux/include/asm-arm/arch-integrator/serial.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#include + +#include "../arch/arm/mach-armada370/config/mvSysHwConfig.h" + +extern unsigned int mvTclk; + +#undef BASE_BAUD +#define BASE_BAUD (mvTclk / 16) + +#define PORT0_BASE (INTER_REGS_BASE + 0x12000) /* port 0 base */ +#define PORT1_BASE (INTER_REGS_BASE + 0x12100) /* port 1 base */ + +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST /* | ASYNC_SPD_VHI 115200 */ ) + +#define STD_SERIAL_PORT_DEFNS +#define EXTRA_SERIAL_PORT_DEFNS + +#endif diff --git a/arch/arm/mach-armada370/include/mach/smp.h b/arch/arm/mach-armada370/include/mach/smp.h new file mode 100755 index 000000000..1f6a67d49 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/smp.h @@ -0,0 +1,29 @@ +#ifndef ASMARM_ARCH_SMP_H +#define ASMARM_ARCH_SMP_H + +#include +#include + +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +/* + * We use IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask) +{ + unsigned long map = *cpus_addr(*mask); + void __iomem *addr = (void __iomem *)(AXP_SW_TRIG_IRQ); + + //printk("smp_cross_call %x \n",(unsigned int)( ((map & 0x3) << 8) | 0x0) ); + writel( ( ((map & 0xf) << 8) | 0x0), addr); + + return; +} + +#endif diff --git a/arch/arm/mach-armada370/include/mach/system.h b/arch/arm/mach-armada370/include/mach/system.h new file mode 100755 index 000000000..b02bfb0e6 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/system.h @@ -0,0 +1,37 @@ +/* + * include/mach/system.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_SYSTEM_H +#define __MACH_SYSTEM_H + +#include +#include + +#include "boardEnv/mvBoardEnvLib.h" + +#ifdef CONFIG_MV_SUPPORT_64KB_PAGE_SIZE +#define LSP_PG_SZ_VER " (Large Page)" +#else +#define LSP_PG_SZ_VER "" +#endif +#define LSP_VERSION "linux-3.2.y-2013_Q1.2p2" LSP_PG_SZ_VER + + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + printk("Reseting...\n"); + mvBoardReset(); + while (1);/* This should never be reached */ +} + +#endif diff --git a/arch/arm/mach-armada370/include/mach/timex.h b/arch/arm/mach-armada370/include/mach/timex.h new file mode 100755 index 000000000..c8cf294ee --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/timex.h @@ -0,0 +1,9 @@ +/* + * include/asm-arm/arch-dove/timex.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-armada370/include/mach/uncompress.h b/arch/arm/mach-armada370/include/mach/uncompress.h new file mode 100755 index 000000000..2927925e5 --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/uncompress.h @@ -0,0 +1,133 @@ +/* + * include/asm-arm/arch-aurora/uncompress.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + +#define UART_THR ((volatile unsigned char *)(AXP_UART0_PHYS_BASE + 0x0)) +#define UART_LSR ((volatile unsigned char *)(AXP_UART0_PHYS_BASE + 0x14)) + +#define LSR_THRE 0x20 + +static void putc(const char c) +{ + int i; + + for (i = 0; i < 0x1000; i++) { + /* Transmit fifo not full? */ + if (*UART_LSR & LSR_THRE) + break; + } + + *UART_THR = c; +} + +static void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#if 0 +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//#include +#include "../arch/arm/mach-armadaxp/config/mvSysHwConfig.h" +#include +#define MV_UART0_LSR (*(volatile unsigned char *)(INTER_REGS_BASE + 0x12000 + 0x14)) +#define MV_UART0_THR (*(volatile unsigned char *)(INTER_REGS_BASE + 0x12000 + 0x0 )) + +#define MV_UART1_LSR (*(volatile unsigned char *)(INTER_REGS_BASE + 0x12100 + 0x14)) +#define MV_UART1_THR (*(volatile unsigned char *)(INTER_REGS_BASE + 0x12100 + 0x0 )) +#define MV_SERIAL_BASE ((unsigned char *)(INTER_REGS_BASE + 0x12000 + 0x0 )) + +#define DEV_REG (*(volatile unsigned int *)(INTER_REGS_BASE + 0x40000)) +#define CLK_REG (*(volatile unsigned int *)(INTER_REGS_BASE + 0x2011c)) +/* + * This does not append a newline + */ +static void putstr(const char *s) +{ + unsigned int model; + + /* Get dev ID, make sure pex clk is on */ + if((CLK_REG & 0x4) == 0) + { + CLK_REG = CLK_REG | 0x4; + model = (DEV_REG >> 16) & 0xffff; + CLK_REG = CLK_REG & ~0x4; + } + else + model = (DEV_REG >> 16) & 0xffff; + + while (*s) { + while ((MV_UART0_LSR & UART_LSR_THRE) == 0); + MV_UART0_THR = *s; + + if (*s == '\n') { + while ((MV_UART0_LSR & UART_LSR_THRE) == 0); + MV_UART0_THR = '\r'; + } + s++; + } +} + +#if 0 +static void putc(const char c) +{ + unsigned char *base = MV_SERIAL_BASE; + int i; + + for (i = 0; i < 0x1000; i++) { + if (base[UART_LSR << 2] & UART_LSR_THRE) + break; + barrier(); + } + + base[UART_TX << 2] = c; +} +#endif +#if 0 +static void flush(void) +{ + unsigned char *base = MV_SERIAL_BASE; + unsigned char mask; + int i; + + mask = UART_LSR_TEMT | UART_LSR_THRE; + + for (i = 0; i < 0x1000; i++) { + if ((base[UART_LSR << 2] & mask) == mask) + break; + barrier(); + } +} +#endif +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() +#endif diff --git a/arch/arm/mach-armada370/include/mach/vmalloc.h b/arch/arm/mach-armada370/include/mach/vmalloc.h new file mode 100755 index 000000000..da4836cad --- /dev/null +++ b/arch/arm/mach-armada370/include/mach/vmalloc.h @@ -0,0 +1,10 @@ +/* + * include/asm-arm/arch-aurora/vmalloc.h + */ + +/* Dove LCD driver performs big allocations for FrameBuffer memory, we need to + * move CONSISTENT_BASE by 32MB + */ +/* Was 0x2000000 */ + +#define VMALLOC_END (0xfa800000) diff --git a/arch/arm/mach-armada370/irq.c b/arch/arm/mach-armada370/irq.c new file mode 100755 index 000000000..64b3e9f57 --- /dev/null +++ b/arch/arm/mach-armada370/irq.c @@ -0,0 +1,160 @@ +/* + * arch/arm/mach/irq.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "gpp/mvGpp.h" +#include "gpp/mvGppRegs.h" +#include "mvOs.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" + +unsigned int irq_int_type[NR_IRQS]; + +static void axp_unmask_fabric_interrupt(void) +{ + u32 val; + + val = MV_REG_READ(CPU_CF_LOCAL_MASK_REG); + val |= 1; + MV_REG_WRITE(CPU_CF_LOCAL_MASK_REG, val); +} + +static void axp_mask_fabric_interrupt(void) +{ + u32 val; + + val = MV_REG_READ(CPU_CF_LOCAL_MASK_REG); + val &= ~1; + MV_REG_WRITE(CPU_CF_LOCAL_MASK_REG, val); +} + +void axp_irq_mask(struct irq_data *d) +{ + + u32 irq=d->irq; + + if (irq < IRQ_MAIN_INTS_NUM) { + MV_REG_BIT_RESET(CPU_INT_SOURCE_CONTROL_REG(irq), BIT0); + + } + else if (irq < (IRQ_AURORA_GPIO_START + NR_GPIO_IRQS)) { + MV_U32 bitmask = 1 << (irq & 0x1F); + MV_U32 reg = (irq - IRQ_AURORA_GPIO_START) >> 5; + MV_REG_BIT_RESET(GPP_INT_LVL_REG(reg), bitmask); + } + else if (irq < (IRQ_AURORA_ERR_START + NR_SOC_MAIN_ERR_IRQS)) { + MV_U32 bitmask = (1 << (irq - IRQ_AURORA_ERR_START)); + MV_REG_BIT_RESET(MV_SOC_MAIN_INT_ERR_MASK_REG, bitmask); + } + else + printk("%s: Error, invalid irqnr(%u)\n", __func__, irq); +} + +void axp_irq_unmask(struct irq_data *d) +{ + u32 irq=d->irq; + if (irq < IRQ_MAIN_INTS_NUM) { + if(irq < 16) + MV_REG_BIT_SET(CPU_INT_SOURCE_CONTROL_REG(irq), BIT0); + else + MV_REG_BIT_SET(CPU_INT_SOURCE_CONTROL_REG(irq), (BIT0 | BIT28)); + } + else if (irq < (IRQ_AURORA_GPIO_START + NR_GPIO_IRQS)) { + MV_U32 bitmask = 1 << (irq & 0x1F); + MV_U32 reg = (irq - IRQ_AURORA_GPIO_START) >> 5; + MV_REG_BIT_SET(GPP_INT_LVL_REG(reg), bitmask); + } + else if (irq < (IRQ_AURORA_ERR_START + NR_SOC_MAIN_ERR_IRQS)) { + MV_U32 bitmask = (1 << (irq - IRQ_AURORA_ERR_START)); + MV_REG_BIT_SET(MV_SOC_MAIN_INT_ERR_MASK_REG, bitmask); + } + else + printk("%s: Error, invalid irqnr(%u)\n", __func__, irq); +} + + +static struct irq_chip axp_irq_chip = { + .name = "armada370_irq", + .irq_mask = axp_irq_mask, + .irq_mask_ack = axp_irq_mask, + .irq_unmask = axp_irq_unmask, + .irq_disable = axp_irq_mask, + .irq_enable = axp_irq_unmask, +}; + + +void __init axp_init_irq(void) +{ + u32 irq, i; + + /* MASK all interrupts */ + for (irq = 0; irq < IRQ_MAIN_INTS_NUM; irq++) { + axp_irq_mask(irq_get_irq_data(irq)); + } + + /* Clear SoC main error masks & cause registers */ + MV_REG_WRITE(MV_SOC_MAIN_INT_ERR_MASK_REG, 0); + MV_REG_WRITE(MV_SOC_MAIN_INT_ERR_CAUSE_REG, 0); + + /* Enable SoC main error summary bit */ + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_SOC_ERROR)); + + /* Disable and clear all GPIO interrupts */ + for(i = 0; i < MV_GPP_MAX_GROUP; i++) { + MV_REG_WRITE(GPP_INT_MASK_REG(i), 0x0); + MV_REG_WRITE(GPP_INT_LVL_REG(i), 0x0); + MV_REG_WRITE(GPP_INT_CAUSE_REG(i), 0x0); + } + + /* Init GPP IRQs in default level mode */ + for (i = 0; i < NR_IRQS; i++) + irq_int_type[i] = GPP_IRQ_TYPE_LEVEL; + + /* Enable GPIO interrupts */ + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_0_7)); + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_8_15)); + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_16_23)); + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_24_31)); + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_32_39)); + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_40_47)); + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_48_55)); + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_56_63)); + axp_irq_unmask(irq_get_irq_data(IRQ_AURORA_GPIO_64_66)); + + /* Register IRQ sources */ + for (irq = 0; irq < NR_IRQS; irq++) { + irq_set_chip(irq, &axp_irq_chip); + irq_set_chip_data(irq, 0); + irq_set_handler(irq, handle_level_irq); + irq_set_status_flags(irq,IRQ_LEVEL); + set_irq_flags(irq, IRQF_VALID); + } +} + +int pmu_request_irq(int irq, irq_handler_t handler) +{ + int ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_NOBALANCING, "armpmu", NULL); + if (!ret) + axp_unmask_fabric_interrupt(); + + return ret; +} + +void pmu_free_irq(int irq) +{ + axp_mask_fabric_interrupt(); + free_irq(irq, NULL); +} diff --git a/arch/arm/mach-armada370/leds.c b/arch/arm/mach-armada370/leds.c new file mode 100755 index 000000000..f611b5ae6 --- /dev/null +++ b/arch/arm/mach-armada370/leds.c @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include +#include +#include +#include "boardEnv/mvBoardEnvLib.h" + +static u32 last_jiffies = 0; +static u32 led_val = 0; + + +void mv_leds_hearbeat(void) +{ + u32 sec = jiffies_to_msecs(jiffies - last_jiffies) / 1000; + + if (!sec) + return; + + led_val = (led_val % (1 << mvBoardDebugLedNumGet(mvBoardIdGet()))); + mvBoardDebugLed(led_val); + led_val++; + last_jiffies = jiffies; +} + +static int __init leds_init(void) +{ + return 0; +} + +__initcall(leds_init); diff --git a/arch/arm/mach-armada370/mpp.h b/arch/arm/mach-armada370/mpp.h new file mode 100755 index 000000000..10654688b --- /dev/null +++ b/arch/arm/mach-armada370/mpp.h @@ -0,0 +1,34 @@ +#ifndef __ARCH_DOVE_MPP_H +#define __ARCH_DOVE_MPP_H + +enum aurora_mpp_type { + /* + * This MPP is unused. + */ + MPP_UNUSED, + + /* + * This MPP pin is used as a generic GPIO pin. + */ + MPP_GPIO, + + /* + * This MPP is used as a SATA activity LED. + */ + MPP_SATA_LED, + /* + * This MPP is used as a functional pad. + */ + MPP_FUNCTIONAL, + +}; + +struct aurora_mpp_mode { + int mpp; + enum aurora_mpp_type type; +}; + +void aurora_mpp_conf(struct aurora_mpp_mode *mode); + + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysAudio.c b/arch/arm/mach-armada370/mv_hal_if/mvSysAudio.c new file mode 100755 index 000000000..065f919f8 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysAudio.c @@ -0,0 +1,175 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "audio/mvAudio.h" +#include "audio/mvAudioRegs.h" + + +/******************************************************************************* +* mvSysAudioInit - Initialize the Audio subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysAudioInit(MV_U8 unit) +{ + MV_AUDIO_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status = MV_OK; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if(status == MV_OK) + status = mvAudioWinInit(unit, addrWinMap); + + if(status == MV_OK) { + halData.tclk = mvBoardTclkGet(); + mvAudioHalInit(unit,&halData); + } + + return status; +} + +#if 0 +/******************************************************************************* +* mvSysAudioCodecRegRead +* +* DESCRIPTION: +* System interface for reading an Audio codec register. +* +* INPUT: +* codecHandle: Handle passed by OS glue by which an audio codec is +* identified. +* regOffset: Offset of codec register to be read. +* +* OUTPUT: +* regData: Register data +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysAudioCodecRegRead(MV_VOID *codecHandle, MV_U32 regOffset, MV_U32 *regData) +{ + MV_TWSI_SLAVE slave; + + slave.slaveAddr.address = mvBoardA2DTwsiAddrGet(0); + slave.slaveAddr.type = mvBoardA2DTwsiAddrTypeGet(0); + slave.validOffset = MV_TRUE; + slave.offset = regOffset; + slave.moreThen256 = MV_FALSE; + + return mvTwsiRead(mvBoardA2DTwsiChanNumGet(0), &slave, (MV_U8*)regData, 1); +} + + +/******************************************************************************* +* mvSysAudioCodecRegWrite +* +* DESCRIPTION: +* System interface for writing an Audio codec register. +* +* INPUT: +* codecHandle: Handle passed by OS glue by which an audio codec is +* identified. +* regOffset: Offset of codec register to be written. +* regData: Register data to write. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysAudioCodecRegWrite(MV_VOID *codecHandle, MV_U32 regOffset, MV_U32 regData) +{ + MV_TWSI_SLAVE slave; + + slave.slaveAddr.address = mvBoardA2DTwsiAddrGet(0); + slave.slaveAddr.type = mvBoardA2DTwsiAddrTypeGet(0); + slave.validOffset = MV_TRUE; + slave.offset = regOffset; + slave.moreThen256 = MV_FALSE; + + return mvTwsiWrite(mvBoardA2DTwsiChanNumGet(0), &slave, (MV_U8*)®Data, 1); +} + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysAudioApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysAudioApi.h new file mode 100755 index 000000000..402b3f696 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysAudioApi.h @@ -0,0 +1,72 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_AUDIO_API_H__ +#define __MV_SYS_AUDIO_API_H__ + + +MV_STATUS mvSysAudioInit(MV_U8 unit); +MV_VOID mvAudioAddrDecShow(MV_VOID); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysCesa.c b/arch/arm/mach-armada370/mv_hal_if/mvSysCesa.c new file mode 100755 index 000000000..20b3a20b1 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysCesa.c @@ -0,0 +1,122 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "mv_cesa/cesa_if.h" + +extern u32 mv_crypto_phys_base_get(u8 chan); +extern u32 mv_crypto_virt_base_get(u8 chan); + +/******************************************************************************* +* mvSysCesaInit - Initialize the Cesa subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysCesaInit(int numOfSession, int queueDepth, void *osHandle) +{ + MV_CESA_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + MV_U8 chan; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + + if(status == MV_OK) { + for(chan = 0; chan < MV_CESA_CHANNELS; chan++) { + status = mvCesaIfTdmaWinInit(chan, addrWinMap); + + if(status != MV_OK) { + mvOsPrintf("Error, unable to initialize CESA windows for channel(%d)\n", chan); + break; + } + halData.sramPhysBase[chan] = (MV_ULONG)mv_crypto_phys_base_get(chan); + halData.sramVirtBase[chan] = (MV_U8*)mv_crypto_virt_base_get(chan); +#ifdef CONFIG_ARMADA_SUPPORT_DEEP_IDLE_CESA_USE + halData.sramOffset[chan] = 32; +#else + halData.sramOffset[chan] = 0; +#endif + } + + if(status == MV_OK) { + halData.ctrlModel = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); + status = mvCesaIfInit(numOfSession, queueDepth, + osHandle, &halData); + } + } + + return status; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysCesaApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysCesaApi.h new file mode 100755 index 000000000..ce8aa9bb2 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysCesaApi.h @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_CESA_API_H__ +#define __MV_SYS_CESA_API_H__ + + +MV_STATUS mvSysCesaInit (int numOfSession, int queueDepth, void *osHandle); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysCntmr.c b/arch/arm/mach-armada370/mv_hal_if/mvSysCntmr.c new file mode 100755 index 000000000..714366a73 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysCntmr.c @@ -0,0 +1,93 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cntmr/mvCntmr.h" + + +/******************************************************************************* +* mvSysCntmrInit - Initialize the Cntmr subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysCntmrInit(void) +{ + MV_CNTMR_HAL_DATA halData; + + halData.ctrlModel = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); + halData.ctrlFamily=mvCtrlDevFamilyIdGet(halData.ctrlModel); + return mvCntmrHalInit(&halData); +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysCntmrApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysCntmrApi.h new file mode 100755 index 000000000..1a10df68b --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysCntmrApi.h @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_CNTMR_API_H__ +#define __MV_SYS_CNTMR_API_H__ + +MV_STATUS mvSysCntmrInit(void); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysDdr.c b/arch/arm/mach-armada370/mv_hal_if/mvSysDdr.c new file mode 100755 index 000000000..b6e992d48 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysDdr.c @@ -0,0 +1,133 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + + +/******************************************************************************* +* mvSysDdrSpdRead +* +* DESCRIPTION: +* System interface for reading DDR SPD contents. +* +* INPUT: +* data: Buffer to read data into. +* size: Number of bytes to read. +* +* OUTPUT: +* data: SPD data. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysDdrSpdRead(MV_U8 *data, MV_U32 size) +{ + MV_TWSI_SLAVE slave; + + slave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + slave.slaveAddr.type = ADDR7_BIT; + slave.validOffset = MV_TRUE; + slave.offset = 0; + slave.moreThen256 = MV_FALSE; + + return mvTwsiRead(MV_BOARD_DIMM_I2C_CHANNEL, &slave, data, size); +} + + +/******************************************************************************* +* mvSysDdrSpdWrite +* +* DESCRIPTION: +* System interface for writing DDR SPD contents. +* +* INPUT: +* data: Buffer holding the data to be written. +* size: Number of bytes to write. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysDdrSpdWrite(MV_U8 *data, MV_U32 size) +{ + MV_TWSI_SLAVE slave; + + slave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + slave.slaveAddr.type = ADDR7_BIT; + slave.validOffset = MV_TRUE; + slave.offset = 0; + slave.moreThen256 = MV_FALSE; + + return mvTwsiWrite(MV_BOARD_DIMM_I2C_CHANNEL, &slave, data, size); +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysEth.c b/arch/arm/mach-armada370/mv_hal_if/mvSysEth.c new file mode 100755 index 000000000..f6f9acc0e --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysEth.c @@ -0,0 +1,131 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cpu/mvCpu.h" +#include "eth/mvEth.h" + + +/******************************************************************************* +* mvSysEthInit - Initialize the Eth subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysEthInit(MV_VOID) +{ + MV_ETH_HAL_DATA halData; + MV_U32 port; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if(status != MV_OK) + return; + + { + int i; + for(i = 0; i < MAX_TARGETS; i++) { + if(addrWinMap[i].enable == MV_FALSE) + continue; + printk("%d - Base 0x%08x , Size = 0x%08x.\n", i, + addrWinMap[i].addrWin.baseLow, + addrWinMap[i].addrWin.size); + } + } + halData.maxPortNum = mvCtrlEthMaxPortGet(); + halData.cpuPclk = mvCpuPclkGet(); + halData.tclk = mvBoardTclkGet(); +#ifdef ETH_DESCR_IN_SRAM + halData.sramSize = mvCtrlSramSizeGet(); +#endif + + for (port=0;port < halData.maxPortNum;port++) { + if(mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE) { + halData.portData[port].powerOn = MV_FALSE; + continue; + } + status = mvEthWinInit(port, addrWinMap); + if(status == MV_OK) { + halData.portData[port].powerOn = MV_TRUE; + halData.portData[port].phyAddr = mvBoardPhyAddrGet(port); + halData.portData[port].isSgmii = mvBoardIsPortInSgmii(port); + halData.portData[port].macSpeed = mvBoardMacSpeedGet(port); + } + } + + mvEthHalInit(&halData); + + return; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysEthApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysEthApi.h new file mode 100755 index 000000000..e1016e40e --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysEthApi.h @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_ETH_API_H__ +#define __MV_SYS_ETH_API_H__ + + +MV_VOID mvSysEthInit(void); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysEthPhy.c b/arch/arm/mach-armada370/mv_hal_if/mvSysEthPhy.c new file mode 100755 index 000000000..d817e712d --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysEthPhy.c @@ -0,0 +1,104 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "eth-phy/mvEthPhy.h" +#if defined(MV_ETH_LEGACY) +#include "eth/gbe/mvEthRegs.h" +#else +#include "neta/gbe/mvEthRegs.h" +#endif + + +/******************************************************************************* +* mvSysEthPhyInit - Initialize the EthPhy subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysEthPhyInit(void) +{ + MV_ETHPHY_HAL_DATA halData; + MV_U32 port; + + for (port=0; port < mvCtrlEthMaxPortGet(); port++) { + halData.phyAddr[port] = mvBoardPhyAddrGet(port); + halData.boardSpecInit = MV_FALSE; + } + + halData.ethPhySmiReg = ETH_SMI_REG(MV_ETH_SMI_PORT); + + return mvEthPhyHalInit(&halData); +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysEthPhyApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysEthPhyApi.h new file mode 100755 index 000000000..eab268abd --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysEthPhyApi.h @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_ETHPHY_API_H__ +#define __MV_SYS_ETHPHY_API_H__ + + +MV_STATUS mvSysEthPhyInit(void); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysNeta.c b/arch/arm/mach-armada370/mv_hal_if/mvSysNeta.c new file mode 100755 index 000000000..7697da9c5 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysNeta.c @@ -0,0 +1,146 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "cpu/mvCpu.h" +#include "neta/gbe/mvNeta.h" + + +/******************************************************************************* +* mvSysNetaInit - Initialize the Eth subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +void mvSysNetaInit(MV_U32 portMask, MV_U32 cpuMask) +{ + MV_NETA_HAL_DATA halData; + MV_U32 port; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + int i; + + memset(&halData, 0, sizeof(halData)); + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status != MV_OK) + return; + + for (i = 0; i < MAX_TARGETS; i++) { + if (addrWinMap[i].enable == MV_FALSE) + continue; + +#ifdef CONFIG_MV_SUPPORT_L2_DEPOSIT + /* Setting DRAM windows attribute to : + 0x3 - Shared transaction + L2 write allocate (L2 Deposit) */ + if (MV_TARGET_IS_DRAM(i)) { + addrWinMap[i].attrib &= ~(0x30); + addrWinMap[i].attrib |= 0x30; + } +#endif /* CONFIG_MV_SUPPORT_L2_DEPOSIT */ + } + halData.portMask = portMask; + halData.cpuMask = cpuMask; + + halData.maxPort = mvCtrlEthMaxPortGet(); + halData.pClk = mvCpuPclkGet(); + halData.tClk = mvBoardTclkGet(); + halData.maxCPUs = mvCtrlEthMaxCPUsGet(); + halData.iocc = arch_is_coherent(); + halData.ctrlModel = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); +#ifdef CONFIG_MV_ETH_BM + halData.bmPhysBase = PNC_BM_PHYS_BASE; + halData.bmVirtBase = (MV_U8 *)ioremap(PNC_BM_PHYS_BASE, PNC_BM_SIZE); +#endif /* CONFIG_MV_ETH_BM */ + +#ifdef CONFIG_MV_ETH_PNC + halData.pncPhysBase = PNC_BM_PHYS_BASE; + halData.pncVirtBase = (MV_U8 *)ioremap(PNC_BM_PHYS_BASE, PNC_BM_SIZE); +#endif /* CONFIG_MV_ETH_PNC */ + + for (port = 0; port < halData.maxPort; port++) { + if (!(MV_BIT_CHECK(portMask, port))) + continue; + if (mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE) + continue; + + mvNetaPortPowerUp(port, mvBoardIsPortInSgmii(port), mvBoardIsPortInRgmii(port)); + status = mvNetaWinInit(port, addrWinMap); + if (status != MV_OK) + continue; + } + mvNetaHalInit(&halData); + + return; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysNetaApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysNetaApi.h new file mode 100755 index 000000000..2c4a08d46 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysNetaApi.h @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_NETA_API_H__ +#define __MV_SYS_NETA_API_H__ + + +void mvSysNetaInit(MV_U32 portMask, MV_U32 cpuMask); + +#endif /* __MV_SYS_NETA_API_H__ */ diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysPci.c b/arch/arm/mach-armada370/mv_hal_if/mvSysPci.c new file mode 100755 index 000000000..435181b82 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysPci.c @@ -0,0 +1,1422 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvSysPci.h" +#include "ddr2_3/mvDramIf.h" + +/* PCI BARs registers offsets are inconsecutive. This struct describes BAR */ +/* register offsets and its function where its is located. */ +/* Also, PCI address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _pciBarRegInfo +{ + MV_U32 funcNum; + MV_U32 baseLowRegOffs; + MV_U32 baseHighRegOffs; + MV_U32 sizeRegOffs; + MV_U32 remapLowRegOffs; + MV_U32 remapHighRegOffs; +}PCI_BAR_REG_INFO; + +typedef struct _pciBarStatus +{ + MV_PCI_BAR bar; + int enable; +}PCI_BAR_STATUS; + +PCI_BAR_STATUS pciBarStatusMap[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + {CS0_BAR, EN}, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + {CS1_BAR, EN}, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + {CS2_BAR, EN}, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + {CS3_BAR, EN}, +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + {DEVCS0_BAR, EN}, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + {DEVCS1_BAR, EN}, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + {DEVCS2_BAR, EN}, +#endif + {BOOTCS_BAR, EN}, + {MEM_INTER_REGS_BAR, EN}, + {IO_INTER_REGS_BAR, EN}, + {P2P_MEM0, DIS}, + {P2P_IO, DIS}, + {TBL_TERM, TBL_TERM} +}; + +/* PCI BAR table. Note that table entry number must match its target */ +/* enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* target which is represent by DEVICE_CS0 enumerator (4). */ +#if 0 +MV_PCI_BAR_WIN pciBarMap[] = +{ +/* base low base high size enable/disable */ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, EN}, + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, EN}, + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, EN}, + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, EN}, + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE }, EN}, + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE }, EN}, + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE }, EN}, + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE }, EN}, + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE }, EN}, + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE }, EN}, + {{ 0xFFFFFFFF , 0, 0xFFFFFFFF }, DIS}, /* Ignore P2P */ + {{ 0xFFFFFFFF , 0, 0xFFFFFFFF }, DIS}, /* Ignore P2P */ + /* Table terminator */ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM} +}; +#endif + +/* Locals */ +static MV_U32 pciBurstBytes2Reg(MV_U32 size); +static MV_U32 pciBurstReg2Bytes(MV_U32 size); + +static MV_STATUS pciWinOverlapDetect(MV_U32 pciIf, MV_PCI_BAR bar, + MV_ADDR_WIN *pAddrWin); + +static MV_STATUS pciBarRegInfoGet(MV_U32 pciIf, MV_PCI_BAR bar, + PCI_BAR_REG_INFO *pBarRegInfo); + +static MV_STATUS pciWinIsValid(MV_U32 baseLow, MV_U32 size); + +/* Forward declarations */ +const MV_8* pciBarNameGet(MV_PCI_BAR bar); + +static MV_TARGET pciBarToTarget(MV_PCI_BAR bar) +{ + switch(bar) + { + #if defined(MV_INCLUDE_SDRAM_CS0) + case CS0_BAR: + return SDRAM_CS0; + #endif + #if defined(MV_INCLUDE_SDRAM_CS1) + case CS1_BAR: + return SDRAM_CS1; + #endif + #if defined(MV_INCLUDE_SDRAM_CS2) + case CS2_BAR: + return SDRAM_CS2; + #endif + #if defined(MV_INCLUDE_SDRAM_CS3) + case CS3_BAR: + return SDRAM_CS3; + #endif + #if defined(MV_INCLUDE_DEVICE_CS0) + case DEVCS0_BAR: + return DEVICE_CS0; + #endif + #if defined(MV_INCLUDE_DEVICE_CS1) + case DEVCS1_BAR: + return DEVICE_CS1; + #endif + #if defined(MV_INCLUDE_DEVICE_CS2) + case DEVCS2_BAR: + return DEVICE_CS2; + #endif + case BOOTCS_BAR: + return DEV_BOOCS; + case MEM_INTER_REGS_BAR: + case IO_INTER_REGS_BAR: + return INTER_REGS; + + default: + mvOsPrintf("pciBarToTarget: ERR. no such target\n"); + } + + return -1; + +} +/******************************************************************************* +* mvPciInit - Initialize PCI interfaces +* +* DESCRIPTION: +* This function initiate the PCI interface: +* 1) Set local bus number. In case of convential PCI it gets the bus +* number using mvPciLocalBusNumGet(). In case of PCI-X this +* information is read only. +* 2) Interface device number. In case of conventional PCI it gets the +* device number using mvPciLocalDevNumGet(). In case of PCI-X this +* information is read only. +* 3) PCI Arbiter if needed. +* 4) Enable Master and Slave on PCI interfaces. +* 5) Open PCI BARs according to default setting. +* Note that PCI bridge (P2P) is NOT initialized. +* 6) Enable CPU to PCI ordering. +* +* INPUT: +* +* pciIf - PCI interface number. +* localBus - Local Bus of the PCI interface to be set +* localDev - Local Dev of the PCI interface to be set +* bFirstCall - Indicates wether this is the first call of this +* function . +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPciInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) +{ + MV_PCI_BAR bar, barix=0; + MV_PCI_MODE pciMode; + MV_CPU_DEC_WIN addrDecWin; + MV_PCI_PROT_WIN pciProtWin; + MV_PCI_BAR_WIN pciBarMap[PCI_MAX_BARS]; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) { + mvOsPrintf("mvPciInit: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + + /* device and bus numbers */ + if (MV_OK != mvPciModeGet(pciIf, &pciMode)) { + mvOsPrintf("mvPciInit: ERR. mvPciModeGet failed\n"); + return MV_ERROR; + } + + /* First disable all PCI target windows */ + for (bar = 0; bar < PCI_MAX_BARS; bar++) + mvPciTargetWinEnable(pciIf, bar, MV_FALSE); + + /* WA CQ 4382*/ + MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf) ,BIT15); + + /* Loop over all BARs and copy enabled SDRAM windows only */ + for (bar = 0; bar < PCI_MAX_BARS; bar++) { + if ((bar >= CS0_BAR) && (bar <= CS3_BAR)) { + if (mvCpuIfTargetWinGet(pciBarToTarget(bar), &addrDecWin) == MV_OK) { + if (addrDecWin.enable) { + pciBarMap[barix].addrWin.baseLow = addrDecWin.addrWin.baseLow; + pciBarMap[barix].addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pciBarMap[barix].addrWin.size = addrDecWin.addrWin.size; + pciBarMap[barix].enable = EN; + barix++; + } + } + } + } + + /* Initialize all non used BARs */ + for (bar = barix; bar < PCI_MAX_BARS; bar++) { + pciBarMap[bar].addrWin.baseLow = 0xFFFFFFFF; + pciBarMap[bar].addrWin.baseHigh = 0; + pciBarMap[bar].addrWin.size = 0xFFFFFFFF; + pciBarMap[bar].enable = DIS; + } + + /* finally fill table with TBL_TERM entry */ + bar = PCI_MAX_BARS - 1; + pciBarMap[bar].addrWin.baseLow = TBL_TERM; + pciBarMap[bar].addrWin.baseHigh = TBL_TERM; + pciBarMap[bar].addrWin.size = TBL_TERM; + pciBarMap[bar].enable = TBL_TERM; + + + /* Memory Mapped Internal Registers BAR can not be disabled. */ + /* Relocate its BAR first to avoid colisions with other BARs (e.g DRAM) */ + if (MV_OK != mvPciTargetWinSet(pciIf, MEM_INTER_REGS_BAR, &pciBarMap[MEM_INTER_REGS_BAR])) { + mvOsPrintf("mvPciInit: ERR. mvPciTargetWinSet failed\n"); + return MV_ERROR; + } + + /* Now, go through all targets in default table until table terminator */ + for (bar = 0; pciBarMap[bar].enable != TBL_TERM; bar++) + { + /* Skip the P2P BARs. They should be configured seperately */ + if (0xFFFFFFFF == pciBarMap[bar].addrWin.baseLow) + continue; + + /* check if the size passed is zero ! */ + if (0 == pciBarMap[bar].addrWin.size) { + /* disable the bar */ + mvPciTargetWinEnable(pciIf,bar,MV_FALSE); + continue; + } + + if (MV_OK != mvPciTargetWinSet(pciIf, bar, &pciBarMap[bar])) { + mvOsPrintf("mvPciInit: ERR. mvPciTargetWinSet %d failed\n", bar); + return MV_ERROR; + } + } + + MV_REG_BIT_SET(PCI_ADDR_DECODE_CONTROL_REG(pciIf), PADCR_REMAP_REG_WR_DIS); + + /* configure access control unit 0 to DDR to enhance performance */ + pciProtWin.addrWin.baseLow = 0; + pciProtWin.addrWin.baseHigh = 0; + pciProtWin.addrWin.size = mvDramIfSizeGet(); +#ifdef AURORA_IO_CACHE_COHERENCY + pciProtWin.attributes.snoop = WT_CACHE_COHER; +#else + pciProtWin.attributes.snoop = NO_CACHE_COHER; +#endif + pciProtWin.attributes.access = ALLOWED; + pciProtWin.attributes.write = ALLOWED; + pciProtWin.attributes.swapType = MV_BYTE_SWAP; + pciProtWin.attributes.readMaxBurst = 128; + pciProtWin.attributes.readBurst = 256; + pciProtWin.attributes.writeMaxBurst = 128; + pciProtWin.attributes.pciOrder = MV_FALSE; + pciProtWin.enable = MV_TRUE; + if( mvPciProtWinSet(pciIf, 0, &pciProtWin) != MV_OK ) { + mvOsPrintf("mvPciInit: ERR. mvPciProtWinSet failed\n"); + return MV_ERROR; + } + + mvPciHalInit(pciIf, pciIfmod); + + return MV_OK; +} + + + +/******************************************************************************* +* mvPciTargetWinSet - Set PCI to peripheral target address window BAR +* +* DESCRIPTION: +* This function sets an address window from PCI to a peripheral +* target (e.g. SDRAM bank0, PCI_MEM0), also known as BARs. +* A new PCI BAR window is set for specified target address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the target window, allowing PCI to access +* the target window. +* +* INPUT: +* pciIf - PCI interface number. +* bar - BAR to be accessed by slave. +* pAddrBarWin - PCI target window information data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if PCI BAR target window was set correctly, MV_BAD_PARAM on bad params +* MV_ERROR otherwise +* (e.g. address window overlapps with other active PCI target window). +* +*******************************************************************************/ +MV_STATUS mvPciTargetWinSet(MV_U32 pciIf, + MV_PCI_BAR bar, + MV_PCI_BAR_WIN *pAddrBarWin) +{ + MV_U32 pciData; + MV_U32 sizeToReg; + MV_U32 size; + MV_U32 baseLow; + MV_U32 baseHigh; + MV_U32 localBus; + MV_U32 localDev; + PCI_BAR_REG_INFO barRegInfo; + + size = pAddrBarWin->addrWin.size; + baseLow = pAddrBarWin->addrWin.baseLow; + baseHigh = pAddrBarWin->addrWin.baseHigh; + + /* Parameter checking */ + if(pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + + if(bar >= PCI_MAX_BARS ) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Illigal PCI BAR %d\n", bar); + return MV_BAD_PARAM; + } + + + /* if the address windows is disabled , we only disable the appropriare + pci bar and ignore other settings */ + + if (MV_FALSE == pAddrBarWin->enable) + { + MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf), BARER_ENABLE(bar)); + return MV_OK; + } + + if (0 == pAddrBarWin->addrWin.size) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Target %d can't be zero!\n",bar); + return MV_BAD_PARAM; + } + + /* Check if the window complies with PCI spec */ + if (MV_TRUE != pciWinIsValid(baseLow, size)) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Target %d window invalid\n", bar); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested window overlaps with current windows */ + if(MV_TRUE == pciWinOverlapDetect(pciIf, bar, &pAddrBarWin->addrWin)) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Overlap detected for target %d\n", + bar); + return MV_BAD_PARAM; + } + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(size, PBBLR_BASE_ALIGNMET); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Target BAR %d size invalid.\n",bar); + return MV_BAD_PARAM; + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + /* Get BAR register information */ + pciBarRegInfoGet(pciIf, bar, &barRegInfo); + + /* Internal register space size have no size register. Do not perform */ + /* size register assigment for this slave target */ + if (0 != barRegInfo.sizeRegOffs) + { + /* Update size register */ + MV_REG_WRITE(barRegInfo.sizeRegOffs, (sizeToReg << BAR_SIZE_OFFS)); + } + + /* Read current address */ + pciData = mvPciConfigRead(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseLowRegOffs); + + /* Clear current address */ + pciData &= ~PBBLR_BASE_MASK; + pciData |= (baseLow & PBBLR_BASE_MASK); + + /* Write new address */ + mvPciConfigWrite(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseLowRegOffs, pciData); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != barRegInfo.baseHighRegOffs) + { + mvPciConfigWrite(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseHighRegOffs, baseHigh); + } + + /* Enable/disable the BAR */ + if (MV_TRUE == pAddrBarWin->enable) + { + MV_REG_BIT_RESET(PCI_BASE_ADDR_ENABLE_REG(pciIf), BARER_ENABLE(bar)); + } + else + { + MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf), BARER_ENABLE(bar)); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPciTargetWinGet - Get PCI to peripheral target address window +* +* DESCRIPTION: +* Get the PCI to peripheral target address window BAR. +* +* INPUT: +* pciIf - PCI interface number. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* pAddrBarWin - PCI target window information data structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciTargetWinGet(MV_U32 pciIf, MV_PCI_BAR bar, + MV_PCI_BAR_WIN *pAddrBarWin) +{ + MV_U32 size; + MV_U32 baseLow; + MV_U32 baseHigh; + MV_U32 localBus; + MV_U32 localDev; + MV_U32 barEnable; + PCI_BAR_REG_INFO barRegInfo; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciTargetWinGet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + + if (bar >= PCI_MAX_BARS ) + { + mvOsPrintf("mvPciTargetWinGet: ERR. Illigal PCI BAR %d.\n", bar); + return MV_BAD_PARAM; + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + /* Get BAR register information */ + pciBarRegInfoGet(pciIf, bar, &barRegInfo); + + /* Reading Base Low bar */ + baseLow = mvPciConfigRead(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseLowRegOffs); + + baseLow &= PBBLR_BASE_MASK; + + /* Skip base high if the BAR has only base low (32-bit) */ + if (0 != barRegInfo.baseHighRegOffs) + { + /* Reading Base High */ + baseHigh = mvPciConfigRead(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseHighRegOffs); + } + else + { + baseHigh = 0; + } + + /* Internal register space size have no size register. Do not perform */ + /* size register assigment for this slave target */ + if (0 != barRegInfo.sizeRegOffs) + { + /* Reading bar size*/ + size = ctrlRegToSize( + (MV_REG_READ(barRegInfo.sizeRegOffs) >> PBSR_SIZE_OFFS), + PBBLR_BASE_ALIGNMET); + } + else + { + size = INTER_REGS_SIZE; + } + + /* Assign value to user struct */ + pAddrBarWin->addrWin.baseLow = baseLow; + pAddrBarWin->addrWin.baseHigh = baseHigh; + pAddrBarWin->addrWin.size = size; + + /* Check if window is enabled */ + barEnable = MV_REG_READ(PCI_BASE_ADDR_ENABLE_REG(pciIf)); + + if (~barEnable & (BARER_ENABLE(bar))) + { + pAddrBarWin->enable = MV_TRUE; + } + else + { + pAddrBarWin->enable = MV_FALSE; + } + + return MV_OK; +} + + +/******************************************************************************* +* mvPciTargetWinEnable - Enable/disable a PCI BAR window +* +* DESCRIPTION: +* This function enable/disable a PCI BAR window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling PCI accesses for that BAR (before enabling the +* window it is tested for overlapping). Otherwise, the window will +* be disabled. +* +* INPUT: +* pciIf - PCI interface number. +* bar - BAR to be accessed by slave. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciTargetWinEnable(MV_U32 pciIf, MV_PCI_BAR bar, MV_BOOL enable) +{ + MV_PCI_BAR_WIN barWin; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciTargetWinEnable: ERR. Invalid PCI interface %d\n", + pciIf); + return MV_BAD_PARAM; + } + + if (bar >= PCI_MAX_BARS ) + { + mvOsPrintf("mvPciTargetWinEnable: ERR. Illigal PCI BAR %d\n", bar); + return MV_BAD_PARAM; + } + + if (MV_TRUE == enable) + { /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvPciTargetWinGet(pciIf, bar, &barWin)) + { + mvOsPrintf("mvPciTargetWinEnable: ERR. targetWinGet fail\n"); + return MV_ERROR; + } + + /* Check for overlapping */ + if (MV_TRUE == pciWinOverlapDetect(pciIf, bar, &barWin.addrWin)) + + { /* Overlap detected */ + mvOsPrintf("mvPciTargetWinEnable: ERR. Overlap detected\n"); + return MV_ERROR; + } + else + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_RESET(PCI_BASE_ADDR_ENABLE_REG(pciIf),BARER_ENABLE(bar)); + } + } + else + { + /* Disable address decode target window */ + MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf), BARER_ENABLE(bar)); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvPciProtWinSet - Set PCI protection access window +* +* DESCRIPTION: +* This function sets a specified address window with access protection +* attributes. If protection structure enables the window the routine will +* also enable the protection window. +* +* INPUT: +* pciIf - PCI interface number. +* winNum - Protecion window number. +* pProtWin - Protection window structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciProtWinSet(MV_U32 pciIf, + MV_U32 winNum, + MV_PCI_PROT_WIN *pProtWin) +{ + MV_U32 protBaseLow; + MV_U32 protBaseHigh; + MV_U32 protSize; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciProtWinSet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + if (winNum >= PCI_MAX_PROT_WIN) + { + mvOsPrintf("mvPciProtWinSet: ERR. Invalid window num %d\n", winNum); + return MV_BAD_PARAM; + } + + /* Check if the window complies with PCI spec */ + if (MV_TRUE != pciWinIsValid(pProtWin->addrWin.baseLow, + pProtWin->addrWin.size)) + { + mvOsPrintf("mvPciProtWinSet: ERR. Win base 0x%x unaligned to size 0x%x\n", + pProtWin->addrWin.baseLow, pProtWin->addrWin.size); + + return MV_BAD_PARAM; + } + + if (pProtWin->attributes.swapType >= SWAP_TYPE_MAX) + { + mvOsPrintf("mvPciProtWinSet: ERR. Swap parameter invalid %d\n", + pProtWin->attributes.swapType); + return MV_BAD_PARAM; + + } + + /* 1) Calculate protection window base low register value */ + protBaseLow = pProtWin->addrWin.baseLow; + + /* Setting the appropriate bits according to the passed values */ + if (MV_TRUE == pProtWin->enable) + { + protBaseLow |= PACBLR_EN; + } + else + { + protBaseLow &= ~PACBLR_EN; + } + + /* I/O Cache Coherency */ + protBaseLow |= ((MV_U32)pProtWin->attributes.snoop << PACBLR_SNOOP_OFFS); + + /* Access protect */ + if (ALLOWED == pProtWin->attributes.access) + { + protBaseLow &= ~PACBLR_ACCPROT; + } + else + { + protBaseLow |= PACBLR_ACCPROT; + } + + /* Write Protect */ + if (ALLOWED == pProtWin->attributes.write) + { + protBaseLow &= ~PACBLR_WRPROT; + } + else + { + protBaseLow |= PACBLR_WRPROT; + } + + /* PCI slave Data Swap Control */ + protBaseLow |= (pProtWin->attributes.swapType << PACBLR_PCISWAP_OFFS); + + + /* Read Max Burst */ + if (( pciBurstBytes2Reg(pProtWin->attributes.readMaxBurst) << PACBLR_RDMBURST_OFFS) > PACBLR_RDMBURST_128BYTE) + { + mvOsPrintf("mvPciProtWinSet: ERR illigal read max burst\n"); + return MV_ERROR; + } + protBaseLow |= (pciBurstBytes2Reg(pProtWin->attributes.readMaxBurst) << PACBLR_RDMBURST_OFFS); + + + /* Typical PCI read transaction Size. Only valid for PCI conventional */ + if ((pciBurstBytes2Reg(pProtWin->attributes.readBurst) << PACBLR_RDSIZE_OFFS) > PACBLR_RDSIZE_256BYTE ) + { + mvOsPrintf("mvPciProtWinSet: ERR. illigal read size\n"); + return MV_ERROR; + } + protBaseLow |= (pciBurstBytes2Reg(pProtWin->attributes.readBurst) << PACBLR_RDSIZE_OFFS); + + + /* 2) Calculate protection window base high register value */ + protBaseHigh = pProtWin->addrWin.baseHigh; + + /* 3) Calculate protection window size register value */ + protSize = ctrlSizeToReg(pProtWin->addrWin.size, PACSR_SIZE_ALIGNMENT) << PACSR_SIZE_OFFS; + + + /* Write Max Burst */ + if ((pciBurstBytes2Reg(pProtWin->attributes.writeMaxBurst) << PACSR_WRMBURST_OFFS) > PACSR_WRMBURST_128BYTE ) + { + mvOsPrintf("mvPciProtWinSet: ERR illigal write max burst\n"); + return MV_ERROR; + } + protSize |= (pciBurstBytes2Reg(pProtWin->attributes.writeMaxBurst) << PACSR_WRMBURST_OFFS); + + /* Pci Order */ + if (MV_TRUE == pProtWin->attributes.pciOrder) + { + protSize |= PACSR_PCI_ORDERING; + } + else + { + protSize &= ~PACSR_PCI_ORDERING; + } + + /* Writing protection window walues into registers */ + MV_REG_WRITE(PCI_ACCESS_CTRL_BASEL_REG(pciIf,winNum), protBaseLow); + MV_REG_WRITE(PCI_ACCESS_CTRL_BASEH_REG(pciIf,winNum), protBaseHigh); + MV_REG_WRITE(PCI_ACCESS_CTRL_SIZE_REG(pciIf,winNum), protSize); + + return MV_OK; +} +/******************************************************************************* +* mvPciProtWinGet - Get PCI protection access window +* +* DESCRIPTION: +* This function gets a specified address window and access protection +* attributes for a specific protection window . +* +* INPUT: +* pciIf - PCI interface number. +* winNum - Protecion window number. +* pProtWin - pointer to a Protection window structure. +* +* OUTPUT: +* pProtWin - Protection window structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciProtWinGet(MV_U32 pciIf, + MV_U32 winNum, + MV_PCI_PROT_WIN *pProtWin) +{ + MV_U32 protBaseLow; + MV_U32 protBaseHigh; + MV_U32 protSize; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciProtWinGet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + if (winNum >= PCI_MAX_PROT_WIN) + { + mvOsPrintf("mvPciProtWinGet: ERR. Invalid window num %d\n", winNum); + return MV_BAD_PARAM; + } + + /* Writing protection window walues into registers */ + protBaseLow = MV_REG_READ(PCI_ACCESS_CTRL_BASEL_REG(pciIf,winNum)); + protBaseHigh = MV_REG_READ(PCI_ACCESS_CTRL_BASEH_REG(pciIf,winNum)); + protSize = MV_REG_READ(PCI_ACCESS_CTRL_SIZE_REG(pciIf,winNum)); + + + /* 1) Get Protection Windows base low */ + pProtWin->addrWin.baseLow = protBaseLow & PACBLR_BASE_L_MASK; + + /* Get the appropriate protection attributes according to register bits*/ + + /* Is Windows enabled ? */ + if (protBaseLow & PACBLR_EN) + { + pProtWin->enable = MV_TRUE; + } + else + { + pProtWin->enable = MV_FALSE; + } + + + /* What is access protect ? */ + if (protBaseLow & PACBLR_ACCPROT) + { + pProtWin->attributes.access = FORBIDDEN; + } + else + { + pProtWin->attributes.access = ALLOWED; + } + + /* Is write protect ? */ + if (protBaseLow & PACBLR_WRPROT) + { + pProtWin->attributes.write = FORBIDDEN; + } + else + { + pProtWin->attributes.write = ALLOWED; + } + + + /* PCI slave Data Swap Control */ + pProtWin->attributes.swapType = (protBaseLow & PACBLR_PCISWAP_MASK) >> PACBLR_PCISWAP_OFFS; + + + /* Read Max Burst */ + pProtWin->attributes.readMaxBurst = pciBurstReg2Bytes((protBaseLow & PACBLR_RDMBURST_MASK) >> PACBLR_RDMBURST_OFFS); + + /* Typical PCI read transaction Size. */ + pProtWin->attributes.readBurst = pciBurstReg2Bytes((protBaseLow & PACBLR_RDSIZE_MASK) >> PACBLR_RDSIZE_OFFS); + + + /* window base high register value */ + pProtWin->addrWin.baseHigh = protBaseHigh; + + /*Calculate protection window size register value */ + pProtWin->addrWin.size = ctrlRegToSize(((protSize & PACSR_SIZE_MASK) >> PACSR_SIZE_OFFS),PACSR_SIZE_ALIGNMENT); + + + /* Write Max Burst */ + pProtWin->attributes.writeMaxBurst = pciBurstReg2Bytes((protSize & PACSR_WRMBURST_MASK) >> PACSR_WRMBURST_OFFS); + + /* Pci Order */ + if (protSize & PACSR_PCI_ORDERING) + { + pProtWin->attributes.pciOrder = MV_TRUE; + } + else + { + pProtWin->attributes.pciOrder = MV_FALSE; + } + + + return MV_OK; +} + + +/******************************************************************************* +* mvPciProtWinEnable - Enable/disable a PCI protection access window +* +* DESCRIPTION: +* This function enable/disable a PCI protection access window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* protection window, otherwise, the protection window will be disabled. +* +* INPUT: +* pciIf - PCI interface number. +* winNum - Protecion window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciProtWinEnable(MV_U32 pciIf, MV_U32 winNum, MV_BOOL enable) +{ + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciProtWinEnable: ERR. Invalid PCI interface %d\n", + pciIf); + return MV_BAD_PARAM; + } + + if (winNum >= PCI_MAX_PROT_WIN) + { + mvOsPrintf("mvPciProtWinEnable: ERR. Invalid window num %d\n", winNum); + return MV_BAD_PARAM; + } + + if (MV_TRUE == enable) + { + MV_REG_BIT_SET(PCI_ACCESS_CTRL_BASEL_REG(pciIf,winNum), PACBLR_EN); + } + else + { + MV_REG_BIT_RESET(PCI_ACCESS_CTRL_BASEL_REG(pciIf,winNum), PACBLR_EN); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvPciTargetRemap - Set PCI to target address window remap. +* +* DESCRIPTION: +* The PCI interface supports remap of the BAR original address window. +* For each BAR it is possible to define a remap address. For example +* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified +* according to remap register but will also be targeted to the +* SDRAM CS[0]. +* +* INPUT: +* pciIf - PCI interface number. +* bar - Peripheral target enumerator accessed by slave. +* pAddrWin - Address window to be checked. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciTargetRemap(MV_U32 pciIf, + MV_PCI_BAR bar, + MV_ADDR_WIN *pAddrWin) +{ + PCI_BAR_REG_INFO barRegInfo; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciTargetRemap: ERR. Invalid PCI interface num %d\n", + pciIf); + return MV_BAD_PARAM; + } + + if (MV_IS_NOT_ALIGN(pAddrWin->baseLow, PBARR_REMAP_ALIGNMENT)) + { + mvOsPrintf("mvPciTargetRemap: Error remapping PCI interface %d bar %s."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + pciIf, + pciBarNameGet(bar), + pAddrWin->baseLow, + pAddrWin->size); + return MV_ERROR; + } + + pciBarRegInfoGet(pciIf, bar, &barRegInfo); + + /* Set remap low register value */ + MV_REG_WRITE(barRegInfo.remapLowRegOffs, pAddrWin->baseLow); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != barRegInfo.remapHighRegOffs) + { + MV_REG_WRITE(barRegInfo.remapHighRegOffs, pAddrWin->baseHigh); + } + + return MV_OK; +} + +/******************************************************************************* +* pciWinOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PCI BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pciWinOverlapDetect(MV_U32 pciIf, MV_PCI_BAR bar, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 barEnableReg; + MV_U32 targetBar; + MV_PCI_BAR_WIN barAddrWin; + + /* Read base address enable register. Do not check disabled windows */ + barEnableReg = MV_REG_READ(PCI_BASE_ADDR_ENABLE_REG(pciIf)); + + for(targetBar = 0; targetBar < PCI_MAX_BARS; targetBar++) { + /* don't check our target or illegal targets */ + if (targetBar == bar) + continue; + + /* Do not check disabled windows */ + if (barEnableReg & (BARER_ENABLE(targetBar))) + continue; + + /* Get window parameters */ + if (MV_OK != mvPciTargetWinGet(pciIf, targetBar, &barAddrWin)) { + mvOsPrintf("pciWinOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* skip overlapp detect between MEM_INTER_REGS_BAR and IO_INTER_REGS_BAR*/ + if (((bar == MEM_INTER_REGS_BAR)&&(targetBar == IO_INTER_REGS_BAR)) || + ((bar == IO_INTER_REGS_BAR)&&(targetBar == MEM_INTER_REGS_BAR))) { + return MV_FALSE; + } else if(MV_TRUE == mvWinOverlapTest(pAddrWin, &barAddrWin.addrWin)) { + mvOsPrintf("pciWinOverlapDetect: BAR %d overlap current %d\n", bar, targetBar); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* cpuWinIsValid - Check if the given address window is valid +* +* DESCRIPTION: +* PCI spec restrict BAR base to be aligned to BAR size. +* This function checks if the given address window is valid. +* +* INPUT: +* baseLow - 32bit low base address. +* size - Window size. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the address window is valid, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_STATUS pciWinIsValid(MV_U32 baseLow, MV_U32 size) +{ + + /* PCI spec restrict BAR base to be aligned to BAR size */ + if(MV_IS_NOT_ALIGN(baseLow, size)) + { + return MV_ERROR; + } + else + { + return MV_TRUE; + } +} + +/******************************************************************************* +* pciBarRegInfoGet - Get BAR register information +* +* DESCRIPTION: +* PCI BARs registers offsets are inconsecutive. +* This function gets a PCI BAR register information like register offsets +* and function location of the BAR. +* +* INPUT: +* pciIf - PCI interface number. +* bar - The PCI BAR in question. +* +* OUTPUT: +* pBarRegInfo - BAR register info struct. +* +* RETURN: +* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK +* +*******************************************************************************/ +static MV_STATUS pciBarRegInfoGet(MV_U32 pciIf, + MV_PCI_BAR bar, + PCI_BAR_REG_INFO *pBarRegInfo) +{ + switch (bar) + { + /* Function 0 Bars */ + #if defined(MV_INCLUDE_SDRAM_CS0) + case CS0_BAR: /* SDRAM chip select 0 bar*/ + pBarRegInfo->funcNum = 0; + pBarRegInfo->baseLowRegOffs = PCI_SCS0_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_SCS0_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_CS0_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_CS0_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_SDRAM_CS1) + case CS1_BAR: /* SDRAM chip select 1 bar*/ + pBarRegInfo->funcNum = 0; + pBarRegInfo->baseLowRegOffs = PCI_SCS1_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_SCS1_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_CS1_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_CS1_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + case MEM_INTER_REGS_BAR: /* Memory Mapped Internal bar */ + pBarRegInfo->funcNum = 0; + pBarRegInfo->baseLowRegOffs = PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_L; + pBarRegInfo->baseHighRegOffs = PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_H; + pBarRegInfo->sizeRegOffs = 0; + pBarRegInfo->remapLowRegOffs = 0; + pBarRegInfo->remapHighRegOffs = 0; + break; + + /* Function 1 Bars */ + #if defined(MV_INCLUDE_SDRAM_CS2) + case CS2_BAR: /* SDRAM chip select 2 bar*/ + pBarRegInfo->funcNum = 1; + pBarRegInfo->baseLowRegOffs = PCI_SCS2_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_SCS2_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_CS2_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_CS2_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_SDRAM_CS3) + case CS3_BAR: /* SDRAM chip select 3 bar*/ + pBarRegInfo->funcNum = 1; + pBarRegInfo->baseLowRegOffs = PCI_SCS3_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_SCS3_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_CS3_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_CS3_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_DEVICE_CS0) + /* Function 2 Bars */ + case DEVCS0_BAR: /* Device chip select 0 bar*/ + pBarRegInfo->funcNum = 2; + pBarRegInfo->baseLowRegOffs = PCI_DEVCS0_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_DEVCS0_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_DEVCS0_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_DEVCS0_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_DEVICE_CS1) + case DEVCS1_BAR: /* Device chip select 0 bar*/ + pBarRegInfo->funcNum = 2; + pBarRegInfo->baseLowRegOffs = PCI_DEVCS1_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_DEVCS1_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_DEVCS1_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_DEVCS1_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_DEVICE_CS2) + case DEVCS2_BAR: /* Device chip select 0 bar*/ + pBarRegInfo->funcNum = 2; + pBarRegInfo->baseLowRegOffs = PCI_DEVCS2_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_DEVCS2_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_DEVCS2_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_DEVCS2_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + case BOOTCS_BAR: /* Boot device chip select bar*/ + pBarRegInfo->funcNum = 3; + pBarRegInfo->baseLowRegOffs = PCI_BOOTCS_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_BOOTCS_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_BOOTCS_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_BOOTCS_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + + /* Function 4 Bars */ + case P2P_MEM0: /* P2P memory 0 */ + pBarRegInfo->funcNum = 4; + pBarRegInfo->baseLowRegOffs = PCI_P2P_MEM0_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_P2P_MEM0_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_P2P_MEM0_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_P2P_MEM0_ADDR_REMAP_LOW_REG(pciIf); + pBarRegInfo->remapHighRegOffs = PCI_P2P_MEM0_ADDR_REMAP_HIGH_REG(pciIf); + break; + case P2P_IO: /* P2P IO */ + pBarRegInfo->funcNum = 4; + pBarRegInfo->baseLowRegOffs = PCI_P2P_IO_BASE_ADDR; + pBarRegInfo->baseHighRegOffs = 0; + pBarRegInfo->sizeRegOffs = PCI_P2P_IO_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_P2P_IO_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + case IO_INTER_REGS_BAR: /* IO Mapped Internal bar */ + pBarRegInfo->funcNum = 4; + pBarRegInfo->baseLowRegOffs = PCI_INTER_REGS_IO_MAPPED_BASE_ADDR; + pBarRegInfo->baseHighRegOffs = 0; + pBarRegInfo->sizeRegOffs = 0; + pBarRegInfo->remapLowRegOffs = 0; + pBarRegInfo->remapHighRegOffs = 0; + break; + + + default: + mvOsPrintf("mvPciTargetWinGet: ERR.non existing target\n"); + return MV_ERROR; + + } + + return MV_OK; +} + +/******************************************************************************* +* pciBarNameGet - Get the string name of PCI BAR. +* +* DESCRIPTION: +* This function get the string name of PCI BAR. +* +* INPUT: +* bar - PCI bar number. +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string name of PCI BAR. +* +*******************************************************************************/ +const MV_8* pciBarNameGet( MV_PCI_BAR bar ) +{ + switch( bar ) + { + #if defined(MV_INCLUDE_SDRAM_CS0) + case CS0_BAR: + return "CS0_BAR.............."; + #endif + #if defined(MV_INCLUDE_SDRAM_CS1) + case CS1_BAR: + return "CS1_BAR.............."; + #endif + #if defined(MV_INCLUDE_SDRAM_CS2) + case CS2_BAR: + return "CS2_BAR.............."; + #endif + #if defined(MV_INCLUDE_SDRAM_CS3) + case CS3_BAR: + return "CS3_BAR.............."; + #endif + #if defined(MV_INCLUDE_DEVICE_CS0) + case DEVCS0_BAR: + return "DEVCS0_BAR..........."; + #endif + #if defined(MV_INCLUDE_DEVICE_CS1) + case DEVCS1_BAR: + return "DEVCS1_BAR..........."; + #endif + #if defined(MV_INCLUDE_DEVICE_CS2) + case DEVCS2_BAR: + return "DEVCS2_BAR..........."; + #endif + case BOOTCS_BAR: + return "BOOTCS_BAR..........."; + case MEM_INTER_REGS_BAR: + return "MEM_INTER_REGS_BAR..."; + case IO_INTER_REGS_BAR: + return "IO_INTER_REGS_BAR...."; + case P2P_MEM0: + return "P2P_MEM0............."; + case P2P_IO: + return "P2P_IO..............."; + default: + return "target unknown"; + } +} + +/******************************************************************************* +* mvPciAddrDecShow - Print the PCI address decode map (BARs). +* +* DESCRIPTION: +* This function print the PCI address decode map (BARs). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvPciAddrDecShow(MV_VOID) +{ + MV_PCI_BAR_WIN win; + MV_PCI_BAR bar; + MV_U32 pciIf; + + for( pciIf = 0; pciIf < mvCtrlPciMaxIfGet(); pciIf++ ) + { + mvOsOutput( "\n" ); + mvOsOutput( "PCI%d:\n", pciIf ); + mvOsOutput( "-----\n" ); + + for( bar = 0; bar < PCI_MAX_BARS; bar++ ) + { + memset( &win, 0, sizeof(MV_PCI_BAR_WIN) ); + + mvOsOutput( "%s ", pciBarNameGet(bar) ); + + if( mvPciTargetWinGet( pciIf, bar, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "base %08x, ", win.addrWin.baseLow ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + } +} + +/* convert burst bytes to register value*/ +static MV_U32 pciBurstBytes2Reg(MV_U32 size) +{ + MV_U32 ret; + switch(size) + { + case 32: ret = 0; break; + case 64: ret = 1; break; + case 128: ret = 2; break; + case 256: ret = 3; break; + default: ret = 0xF; /* error */ + } + return ret; +} + +/* convert register value to burst bytes*/ +static MV_U32 pciBurstReg2Bytes(MV_U32 size) +{ + MV_U32 ret; + switch(size) + { + case 0: ret = 32; break; + case 1: ret = 64; break; + case 2: ret = 128; break; + case 3: ret = 256; break; + default: ret = 0x0; /* error */ + } + return ret; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysPci.h b/arch/arm/mach-armada370/mv_hal_if/mvSysPci.h new file mode 100755 index 000000000..ffa393f7d --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysPci.h @@ -0,0 +1,256 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCSysPCIH +#define __INCSysPCIH + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "pci/mvPci.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "mvSysPciConfig.h" + +#define PCI_MAX_PROT_WIN 6 + +/* 4KB granularity */ +#define MINIMUM_WINDOW_SIZE 0x1000 +#define MINIMUM_BAR_SIZE 0x1000 +#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 +#define BAR_SIZE_OFFS 12 +#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) + +#define PCI_IO_WIN_NUM 1 /* Number of PCI_IO windows */ +#define PCI_MEM_WIN_NUM 4 /* Number of PCI_MEM windows */ + +#ifndef MV_ASMLANGUAGE +#include "ctrlEnv/mvCtrlEnvLib.h" +typedef enum _mvPCIBars +{ + PCI_BAR_TBL_TERM = -1, /* none valid bar, used as bars list terminator */ +#if defined(MV_INCLUDE_SDRAM_CS0) + CS0_BAR, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + CS1_BAR, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + CS2_BAR, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + CS3_BAR, +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVCS0_BAR, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVCS1_BAR, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVCS2_BAR, +#endif + BOOTCS_BAR, /* Boot device chip select bar*/ + MEM_INTER_REGS_BAR, /* Memory Mapped Internal bar */ + IO_INTER_REGS_BAR, /* IO Mapped Internal bar */ + P2P_MEM0, /* P2P memory 0 */ + P2P_IO, /* P2P IO */ + PCI_MAX_BARS +}MV_PCI_BAR; +#endif /* MV_ASMLANGUAGE */ + +#if defined(MV_INCLUDE_SDRAM_CS3) +#define MV_PCI_BAR_IS_DRAM_BAR(bar) ((bar >= CS0_BAR) && (bar <= CS3_BAR)) +#elif defined(MV_INCLUDE_SDRAM_CS2) +#define MV_PCI_BAR_IS_DRAM_BAR(bar) ((bar >= CS0_BAR) && (bar <= CS2_BAR)) +#elif defined(MV_INCLUDE_SDRAM_CS1) +#define MV_PCI_BAR_IS_DRAM_BAR(bar) ((bar >= CS0_BAR) && (bar <= CS1_BAR)) +#elif defined(MV_INCLUDE_SDRAM_CS0) +#define MV_PCI_BAR_IS_DRAM_BAR(bar) ((bar == CS0_BAR)) +#endif + + +/****************************************/ +/* PCI Slave Address Decoding registers */ +/****************************************/ +#define PCI_CS0_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0c08 + ((pciIf) * 0x80)) +#define PCI_CS1_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d08 + ((pciIf) * 0x80)) +#define PCI_CS2_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0c0c + ((pciIf) * 0x80)) +#define PCI_CS3_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d0c + ((pciIf) * 0x80)) +#define PCI_DEVCS0_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0c10 + ((pciIf) * 0x80)) +#define PCI_DEVCS1_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d10 + ((pciIf) * 0x80)) +#define PCI_DEVCS2_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d18 + ((pciIf) * 0x80)) +#define PCI_BOOTCS_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d14 + ((pciIf) * 0x80)) +#define PCI_P2P_MEM0_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d1c + ((pciIf) * 0x80)) +#define PCI_P2P_IO_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d24 + ((pciIf) * 0x80)) +#define PCI_EXPAN_ROM_BAR_SIZE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d2c + ((pciIf) * 0x80)) +#define PCI_BASE_ADDR_ENABLE_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0c3c + ((pciIf) * 0x80)) +#define PCI_CS0_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0c48 + ((pciIf) * 0x80)) +#define PCI_CS1_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d48 + ((pciIf) * 0x80)) +#define PCI_CS2_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0c4c + ((pciIf) * 0x80)) +#define PCI_CS3_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d4c + ((pciIf) * 0x80)) +#define PCI_DEVCS0_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0c50 + ((pciIf) * 0x80)) +#define PCI_DEVCS1_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d50 + ((pciIf) * 0x80)) +#define PCI_DEVCS2_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d58 + ((pciIf) * 0x80)) +#define PCI_BOOTCS_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d54 + ((pciIf) * 0x80)) +#define PCI_P2P_MEM0_ADDR_REMAP_LOW_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d5c + ((pciIf) * 0x80)) +#define PCI_P2P_MEM0_ADDR_REMAP_HIGH_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d60 + ((pciIf) * 0x80)) +#define PCI_P2P_IO_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d6c + ((pciIf) * 0x80)) +#define PCI_EXPAN_ROM_ADDR_REMAP_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0f38 + ((pciIf) * 0x80)) +#define PCI_DRAM_BAR_BANK_SELECT_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0c1c + ((pciIf) * 0x80)) +#define PCI_ADDR_DECODE_CONTROL_REG(pciIf) (MV_PCI_IF_REGS_BASE(pciIf) + 0x0d3c + ((pciIf) * 0x80)) + +/* PCI Bars Size Registers (PBSR) */ +#define PBSR_SIZE_OFFS 12 +#define PBSR_SIZE_MASK (0xfffff << PBSR_SIZE_OFFS) + +/* Base Address Registers Enable Register (BARER) */ +#define BARER_ENABLE(target) (1 << (target)) + +/* PCI Base Address Remap Registers (PBARR) */ +#define PBARR_REMAP_OFFS 12 +#define PBARR_REMAP_MASK (0xfffff << PBARR_REMAP_OFFS) +#define PBARR_REMAP_ALIGNMENT (1 << PBARR_REMAP_OFFS) + +/* PCI DRAM Bar Bank Select Register (PDBBSR) */ +#define PDBBSR_DRAM_BANK_OFFS(bank) ((bank) * 2) +#define PDBBSR_DRAM_BANK_MASK(bank) (0x3 << PDBBSR_DRAM_BANK_OFFS(bank)) + +/* PCI Address Decode Control Register (PADCR)*/ +#define PADCR_REMAP_REG_WR_DIS BIT0 +#define PADCR_MSG_REG_ACC BIT3 + +#define PADCR_VPD_HIGH_ADDR_OFFS 8 /* Bits [31:15] of the VPD address */ +#define PADCR_VPD_HIGH_ADDR_MASK (0x1ffff << PADCR_VPD_HIGH_ADDR_OFFS) + +/* PCI Headers Retarget Control Register (PHRCR) */ +#define PHRCR_ENABLE BIT0 +#define PHRCR_BUFF_SIZE_OFFS 1 +#define PHRCR_BUFF_SIZE_MASK (0x7 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_258BYTE (0x0 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_512BYTE (0x1 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_1KB (0x2 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_2KB (0x3 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_4KB (0x4 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_8KB (0x5 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_MASK1_OFFS 16 +#define PHRCR_MASK1_MASK (0xffff << PHRCR_MASK1_OFFS) + +/* PCI Headers Retarget Base Register (PHRBR) */ +#define PHRBR_BASE_OFFS 16 +#define PHRBR_BASE_MASK (0xffff << PHRBR_BASE_OFFS) + +/* PCI Headers Retarget Base High Register (PHRBHR) */ +#define PHRBHR_BASE_OFFS 0 +#define PHRBHR_BASE_MASK (0xffffffff << PHRBHR_BASE_OFFS) + +/* This structure describes a PCI BAR. It is also refered as PCI target */ +/* window to keep consistency with other address decode units in the system */ +typedef struct _mvPciBarWin +{ + MV_ADDR_WIN addrWin; /* Address window */ + MV_BOOL enable; /* BAR enable/disable */ +}MV_PCI_BAR_WIN; + +typedef enum +{ + NO_CACHE_COHER = 0, + WT_CACHE_COHER, + WB_CACHE_COHER +}MV_PCI_SNOOP; + +/* This structure describes PCI region attributes */ +typedef struct _mvPciRegionAttr +{ + MV_PCI_SNOOP snoop; /* Cache Coherenc */ + MV_PROT_RIGHT access; /* Access protection */ + MV_PROT_RIGHT write; /* Write protection */ + MV_SWAP_TYPE swapType; /* Data swap mode for that region */ + MV_U32 readMaxBurst; /* Read max burst */ + MV_U32 readBurst; /* Read burst. Conventional PCI only */ + MV_U32 writeMaxBurst; /* Write max burst */ + MV_BOOL pciOrder; /* Hardware support for PCI ordering */ +}MV_PCI_REGION_ATTR; + +/* The PCI slave interface supports configurable access control. */ +/* It is possible to define up to six address ranges to different */ +/* configurations. This structure describes the PCI access region */ +typedef struct _mvPciProtWin +{ + MV_ADDR_WIN addrWin; /* An address window */ + MV_PCI_REGION_ATTR attributes; /* Window attributes */ + MV_BOOL enable; /* Window enabled/disabled */ +}MV_PCI_PROT_WIN; + +/* Global Functions prototypes */ +MV_STATUS mvPciInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); +MV_STATUS mvPciTargetWinSet(MV_U32 pciIf, MV_PCI_BAR slaveTarget, MV_PCI_BAR_WIN *pAddrBarWin); +MV_STATUS mvPciTargetWinGet(MV_U32 pciIf, MV_PCI_BAR slaveTarget, MV_PCI_BAR_WIN *pAddrBarWin); +MV_STATUS mvPciTargetWinEnable(MV_U32 pciIf,MV_PCI_BAR slaveTarget, MV_BOOL enable); +MV_STATUS mvPciProtWinSet(MV_U32 pciIf, MV_U32 winNum, MV_PCI_PROT_WIN *pProtWin); +MV_STATUS mvPciProtWinGet(MV_U32 pciIf, MV_U32 winNum, MV_PCI_PROT_WIN *pProtWin); +MV_STATUS mvPciProtWinEnable(MV_U32 pciIf, MV_U32 winNum, MV_BOOL enable); +MV_STATUS mvPciTargetRemap(MV_U32 pciIf, MV_PCI_BAR slaveTarget, MV_ADDR_WIN *pAddrWin); +MV_VOID mvPciAddrDecShow(MV_VOID); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysPex.c b/arch/arm/mach-armada370/mv_hal_if/mvSysPex.c new file mode 100755 index 000000000..8917830fa --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysPex.c @@ -0,0 +1,107 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "pex/mvPex.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pAddrDecWin); + + +/******************************************************************************* +* mvSysPexInit - Initialize the Pex subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + MV_PEX_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if(status == MV_OK) + status = mvPexWinInit(pexIf, pexType, addrWinMap); + + if(status == MV_OK) { + halData.ctrlModel = mvCtrlModelGet(); + halData.maxPexIf = mvCtrlPexMaxIfGet(); + halData.ctrlFamily=mvCtrlDevFamilyIdGet(halData.ctrlModel); + status = mvPexInit(pexIf, pexType, &halData); + } + + return status; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysPexApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysPexApi.h new file mode 100755 index 000000000..7ae7e26f3 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysPexApi.h @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_PEX_API_H__ +#define __MV_SYS_PEX_API_H__ + +MV_STATUS mvSysPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); +MV_VOID mvSysPexCpuIfEnable(MV_U32 pexIf); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysSFlash.c b/arch/arm/mach-armada370/mv_hal_if/mvSysSFlash.c new file mode 100755 index 000000000..e4b594477 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysSFlash.c @@ -0,0 +1,225 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "spi/mvSpi.h" +#include "spi/mvSpiCmnd.h" +#include "sflash/mvSysSFlash.h" + +#define MV_SYS_SFLASH_MAX_CMD_LEN 8 + +static struct { + MV_U8 buf[MV_SYS_SFLASH_MAX_CMD_LEN]; + MV_U32 bufLen; + MV_U8 transType; +} mvSysSflashCmd; + +/******************************************************************************* +* mvSysSflashCommandSet +* +* DESCRIPTION: +* System interface for sending a command to the SPI flash. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* cmdBuff: Command data to be written. +* cmdLen: Command length in bytes. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashCommandSet(MV_VOID *flashHandle, MV_U8* cmdBuff, MV_U32 cmdLen, + MV_U8 transType) +{ + if (cmdLen > MV_SYS_SFLASH_MAX_CMD_LEN) + return MV_ERROR; + + if (!(transType & SYS_SFLASH_TRANS_START) || (mvSysSflashCmd.transType != 0)) + return MV_ERROR; + + mvSpiParamsSet(0, 0, SPI_TYPE_FLASH); + + memcpy(mvSysSflashCmd.buf,cmdBuff,cmdLen); + mvSysSflashCmd.bufLen = cmdLen; + mvSysSflashCmd.transType = transType; + + if (transType & SYS_SFLASH_TRANS_END) + return mvSysSflashDataWrite(flashHandle, NULL, 0, transType); + + return MV_OK; +} + + +/******************************************************************************* +* mvSysSflashDataRead +* +* DESCRIPTION: +* System interface for reading SPI flash data. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* dataBuff: Buffer to read the data into. +* dataLen: Number of bytes to read. +* dummyBytes: Number of dummy bytes to read before reading the real +* data. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* dataBuff: The data as read from flash. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashDataRead(MV_VOID *flashHandle, MV_U8* dataBuff, MV_U32 dataLen, + MV_U32 dummyBytes, MV_U8 transType) +{ + MV_STATUS ret; + + if (!(mvSysSflashCmd.transType & SYS_SFLASH_TRANS_START)) + return MV_ERROR; + + + ret = mvSpiWriteThenRead (0, mvSysSflashCmd.buf, mvSysSflashCmd.bufLen, + dataBuff, dataLen, dummyBytes); + if (transType & SYS_SFLASH_TRANS_END) + memset(&mvSysSflashCmd,0,sizeof(mvSysSflashCmd)); + return ret; +} + + +/******************************************************************************* +* mvSysSflashDataWrite +* +* DESCRIPTION: +* System interface for writing SPI flash data. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* dataBuff: Buffer holding the data to be written. +* dataLen: Number of bytes to write. +* transType: Bitmask describing the transaction type, see +* SYS_SFLASH_TRANS_XX for details. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashDataWrite(MV_VOID *flashHandle, MV_U8* dataBuff, MV_U32 dataLen, + MV_U8 transType) +{ + MV_STATUS ret; + + if (!(mvSysSflashCmd.transType & SYS_SFLASH_TRANS_START)) + return MV_ERROR; + + ret = mvSpiWriteThenWrite (0, mvSysSflashCmd.buf, mvSysSflashCmd.bufLen, dataBuff, dataLen); + if (transType & SYS_SFLASH_TRANS_END) + memset(&mvSysSflashCmd,0,sizeof(mvSysSflashCmd)); + return ret; +} + + +/******************************************************************************* +* mvSysSflashFreqSet +* +* DESCRIPTION: +* System interface for controlling the SPI interface frequency. +* +* INPUT: +* flashHandle: Handle passed by OS glue by which an SPI flash is +* identified. +* freq: The new frequency to be configured for the SPI IF. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSflashFreqSet(MV_VOID *flashHandle, MV_U32 freq) +{ + + return mvSpiBaudRateSet(0, freq); +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysSata.c b/arch/arm/mach-armada370/mv_hal_if/mvSysSata.c new file mode 100755 index 000000000..8086760f2 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysSata.c @@ -0,0 +1,81 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "sata/CoreDriver/mvSata.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +MV_STATUS mvSysSataWinInit(MV_VOID) +{ + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if(status == MV_OK) + status = mvSataWinInit(addrWinMap); + + return status; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysSataApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysSataApi.h new file mode 100755 index 000000000..8cca7d08e --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysSataApi.h @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_SATA_API_H__ +#define __MV_SYS_SATA_API_H__ + +MV_STATUS mvSysSataWinInit(MV_VOID); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysSpi.c b/arch/arm/mach-armada370/mv_hal_if/mvSysSpi.c new file mode 100755 index 000000000..05e44f2e9 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysSpi.c @@ -0,0 +1,125 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "spi/mvSpi.h" +#include "spi/mvSysSpi.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + + +/******************************************************************************* +* mvSysSpiInit - Initialize the SPI subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysSpiInit(MV_U8 spiId, MV_U32 serialBaudRate) +{ + MV_SPI_HAL_DATA halData; + + halData.ctrlModel = mvCtrlModelGet(); + halData.tclk = mvBoardTclkGet(); + + return mvSpiInit(spiId, serialBaudRate, &halData); +} + + +/******************************************************************************* +* mvSysSpiMppConfig +* +* DESCRIPTION: +* System interface for configuring the MPP's configuration to enable / +* disable SPI mode. +* +* INPUT: +* mode: The mode to be set into MPP unit. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysSpiMppConfig(MV_U8 mode) +{ +#if 0 + if(mode == SYS_SPI_MPP_ENABLE) + mvMPPConfigToSPI(); + else + mvMPPConfigToDefault(); +#endif + return MV_OK; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysSpiApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysSpiApi.h new file mode 100755 index 000000000..80888c08c --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysSpiApi.h @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_SPI_API_H__ +#define __MV_SYS_SPI_API_H__ + +MV_STATUS mvSysSpiInit(MV_U8 spi_id, MV_U32 serialBaudRate); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysTdm.c b/arch/arm/mach-armada370/mv_hal_if/mvSysTdm.c new file mode 100755 index 000000000..db94038c9 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysTdm.c @@ -0,0 +1,245 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#ifdef CONFIG_MV_TDM_SUPPORT +#include "voiceband/tdm/mvTdm.h" +#else + #include "voiceband/commUnit/mvCommUnit.h" + #include "gpp/mvGpp.h" +#endif +#include "voiceband/mvSysTdmSpi.h" +#include "spi/mvSpiCmnd.h" +#include "spi/mvSpi.h" + +#define MAX_DATA_LENGTH 255 + +/******************************************************************************* +* mvSysTdmInit - Initialize the TDM subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysTdmInit(MV_TDM_PARAMS* tdmParams) +{ + MV_TDM_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if(status == MV_OK) +#ifdef MV_TDM_SUPPORT + status = mvTdmWinInit(addrWinMap); +#else + status = mvCommUnitWinInit(addrWinMap); +#endif + + if(status == MV_OK) { + halData.spiMode = mvBoardTdmSpiModeGet(); + halData.model = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); +#if defined(MV_TDM_PCM_CLK_8MHZ) + halData.frameTs = MV_FRAME_128TS; +#elif defined(MV_TDM_PCM_CLK_4MHZ) + halData.frameTs = MV_FRAME_64TS; +#else /* MV_TDM_PCM_CLK_2MHZ */ + halData.frameTs = MV_FRAME_32TS; +#endif + +#ifdef MV_TDM_SUPPORT + status = mvTdmHalInit (tdmParams, &halData); +#else + halData.maxCs = mvBoardTdmDevicesCountGet(); + status = mvCommUnitHalInit (tdmParams, &halData); + + /* Issue SLIC reset */ + mvGppValueSet(0, BIT25, 0); + mvOsUDelay(60); + mvGppValueSet(0, BIT25, BIT25); +#endif + } + + return status; +} + +MV_VOID mvSysTdmSpiRead(MV_U16 lineId, MV_U8* cmdBuff, MV_U8 cmdSize, MV_U8* dataBuff, MV_U8 dataSize) +{ +#if defined(MV_TDM_SUPPORT) && !defined(ZARLINK_SLIC_SUPPORT) + + if((cmdSize > 4) || (dataSize > MAX_DATA_LENGTH)) + { + mvOsPrintf("Error, exceeded max size of command(%d) or data(%d)\n", cmdSize, dataSize); + return; + } + + mvTdmSpiRead(cmdBuff, cmdSize, dataBuff, dataSize, lineId); + +#else /* MV_COMM_UNIT_SUPPORT || ZARLINK_SLIC_SUPPORT */ + + /* Set SPI parameters(lineId = devId) */ + mvSpiParamsSet(mvBoardTdmSpiIdGet(), mvBoardTdmSpiCsGet(lineId), SPI_TYPE_SLIC); + + if(MV_OK != mvSpiWriteThenRead (mvBoardTdmSpiIdGet(), cmdBuff, cmdSize, dataBuff, dataSize, 0)) + printk("SPI read failed !!!\n"); + +#endif /* MV_TDM_SUPPORT */ +} + +/******************************************************************************* +* mvSysTdmSpiWrite - telephony register write via SPI interface +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmSpiWrite(MV_U16 lineId, MV_U8* cmdBuff, MV_U8 cmdSize, MV_U8* dataBuff, MV_U8 dataSize) +{ +#if defined(MV_TDM_SUPPORT) && !defined(ZARLINK_SLIC_SUPPORT) + + if((cmdSize > 3) || (dataSize > MAX_DATA_LENGTH)) + { + mvOsPrintf("Error, exceeded max size of command(%d) or data(%d)\n", cmdSize, dataSize); + return; + } + + mvTdmSpiWrite(cmdBuff, cmdSize, dataBuff, dataSize, lineId); + +#else /* MV_COMM_UNIT_SUPPORT || ZARLINK_SLIC_SUPPORT */ + + /* Set SPI parameters(lineId = devId) */ + mvSpiParamsSet(mvBoardTdmSpiIdGet(), mvBoardTdmSpiCsGet(lineId), SPI_TYPE_SLIC); + + if(MV_OK != mvSpiWriteThenWrite (mvBoardTdmSpiIdGet(), cmdBuff, cmdSize, dataBuff, dataSize)) + printk("SPI write failed !!!\n"); + +#endif /* MV_TDM_SUPPORT */ +} + +/******************************************************************************* +* mvSysTdmIntEnable - Enable CSLAC device interrupts. +* +* DESCRIPTION: +* +* INPUT: +* Device ID +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmIntEnable(MV_U8 deviceId) +{ +#if defined(MV_TDM_SUPPORT) + + mvTdmIntEnable(); + +#else /* MV_COMM_UNIT_SUPPORT */ + + mvCommUnitIntEnable(deviceId); + +#endif +} + +/******************************************************************************* +* mvSysTdmIntDisable - Disable CSLAC device interrupts. +* +* DESCRIPTION: +* +* INPUT: +* Device ID +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSysTdmIntDisable(MV_U8 deviceId) +{ +#if defined(MV_TDM_SUPPORT) + + mvTdmIntDisable(); + +#else /* MV_COMM_UNIT_SUPPORT */ + + mvCommUnitIntDisable(deviceId); + +#endif +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysTdmApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysTdmApi.h new file mode 100755 index 000000000..74ca02318 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysTdmApi.h @@ -0,0 +1,78 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_TDM_API_H__ +#define __MV_SYS_TDM_API_H__ + +#include "mvSysTdmConfig.h" + +#ifdef MV_TDM_SUPPORT +#include "voiceband/tdm/mvTdm.h" +#else + #include "voiceband/commUnit/mvCommUnit.h" +#endif + +MV_STATUS mvSysTdmInit (MV_TDM_PARAMS* tdmParams); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysTs.c b/arch/arm/mach-armada370/mv_hal_if/mvSysTs.c new file mode 100755 index 000000000..c68d75d37 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysTs.c @@ -0,0 +1,86 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ts/mvTsu.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ts/mvTsuRegs.h" + +MV_STATUS mvSysTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, + void *osHandle) +{ + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if(status == MV_OK) + status = mvTsuWinInit(addrWinMap); + + if(status == MV_OK) + status = mvTsuHalInit(coreClock, mode, osHandle); + return status; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysTsApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysTsApi.h new file mode 100755 index 000000000..837782d0c --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysTsApi.h @@ -0,0 +1,73 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_TS_API_H__ +#define __MV_SYS_TS_API_H__ + +#include "ts/mvTsu.h" + +MV_STATUS mvSysTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, + void *osHandle); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysTwsi.c b/arch/arm/mach-armada370/mv_hal_if/mvSysTwsi.c new file mode 100755 index 000000000..5c51c03d7 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysTwsi.c @@ -0,0 +1,136 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "twsi/mvTwsi.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" + + +/******************************************************************************* +* mvSysTwsiInterruptEnable +* +* DESCRIPTION: +* Mask or unmask TWSI main interrupt cause bit. +* +* INPUT: +* chanNum - TWSI channel number. +* mask - MV_TRUE to enable the interrupt, +* MV_FALSE to disable the interrupt. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success, +* MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvSysTwsiInterruptEnable(MV_U32 chanNum, MV_BOOL enable) +{ + MV_U32 val; + + val = MV_REG_READ(CPU_INT_SOURCE_CONTROL_REG(CPU_MAIN_INT_CAUSE_TWSI(chanNum))); + + if (enable == MV_TRUE) + val |= (1 << CPU_INT_SOURCE_CONTROL_IRQ_OFFS); + else + val &= ~(1 << CPU_INT_SOURCE_CONTROL_IRQ_OFFS); + + MV_REG_WRITE(CPU_INT_SOURCE_CONTROL_REG(CPU_MAIN_INT_CAUSE_TWSI(chanNum)), val); + return MV_OK; +} + + +/******************************************************************************* +* mvSysTwsiMainCauseIsSet +* +* DESCRIPTION: +* Check if the TWSI interrupt was triggered in the main interrupt cause +* register. +* +* INPUT: +* chanNum - TWSI channel number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if interrupt was triggered. +* MV_FALSE otherwise. +* +*******************************************************************************/ +MV_BOOL mvSysTwsiMainCauseIsSet(MV_U32 chanNum) +{ + MV_U32 val; + + /* Pass dummy 0 to keep compatibility with HAL */ + val = MV_REG_READ(MV_TWSI_CPU_MAIN_INT_CAUSE(chanNum, 0)); + + if (val & (1 << CPU_MAIN_INT_TWSI_OFFS(chanNum))) + return MV_TRUE; + + return MV_FALSE; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysUsb.c b/arch/arm/mach-armada370/mv_hal_if/mvSysUsb.c new file mode 100755 index 000000000..d1caba9a7 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysUsb.c @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "usb/mvUsb.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "usb/mvUsbRegs.h" + +/******************************************************************************* +* mvSysUsbHalInit - Initialize the USB subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_STATUS mvSysUsbInit(MV_U32 dev, MV_BOOL isHost) +{ + MV_USB_HAL_DATA halData; + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if(status == MV_OK) + status = mvUsbWinInit(dev, addrWinMap); + + if (dev == 0) + mvUsbPllInit(); + + if(status == MV_OK) { + halData.ctrlModel = mvCtrlModelGet(); + halData.ctrlRev = mvCtrlRevGet(); + halData.ctrlFamily=mvCtrlDevFamilyIdGet(halData.ctrlModel); + status = mvUsbHalInit(dev, isHost, &halData); + } + + return status; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysUsbApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysUsbApi.h new file mode 100755 index 000000000..675b6086b --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysUsbApi.h @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_USB_API_H__ +#define __MV_SYS_USB_API_H__ + +MV_STATUS mvSysUsbInit(MV_U32 dev, MV_BOOL isHost); + +#endif diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysXor.c b/arch/arm/mach-armada370/mv_hal_if/mvSysXor.c new file mode 100755 index 000000000..7857fba34 --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysXor.c @@ -0,0 +1,88 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "xor/mvXor.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "xor/mvXorRegs.h" + +MV_VOID mvSysXorInit (void) +{ + MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; + MV_STATUS status, unit; + + status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); + if (status == MV_OK) + status = mvXorWinInit(addrWinMap); + + if (status == MV_OK) { + for (unit = 0; unit < MV_XOR_MAX_UNIT; unit++) + mvXorHalInit(unit); + + } + return; +} diff --git a/arch/arm/mach-armada370/mv_hal_if/mvSysXorApi.h b/arch/arm/mach-armada370/mv_hal_if/mvSysXorApi.h new file mode 100755 index 000000000..fb2b06d6e --- /dev/null +++ b/arch/arm/mach-armada370/mv_hal_if/mvSysXorApi.h @@ -0,0 +1,70 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_SYS_XOR_API_H__ +#define __MV_SYS_XOR_API_H__ + +MV_VOID mvSysXorInit (void); + +#endif diff --git a/arch/arm/mach-armada370/pci.c b/arch/arm/mach-armada370/pci.c new file mode 100755 index 000000000..64b011dcd --- /dev/null +++ b/arch/arm/mach-armada370/pci.c @@ -0,0 +1,242 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvSysPci.h" +#include "pci/mvPci.h" + +#undef DEBUG +#ifdef DEBUG +# define DB(x) x +#else +# define DB(x) +#endif + +static int __init mv_map_irq(struct pci_dev *dev, u8 slot, u8 pin); + +extern u32 mv_pci_mem_size_get(int ifNum); +extern u32 mv_pci_io_base_get(int ifNum); +extern u32 mv_pci_io_size_get(int ifNum); +extern u32 mv_pci_mem_base_get(int ifNum); + +void __init mv_pci_preinit(void) +{ + MV_ADDR_WIN win; + + if (mvCtrlPciMaxIfGet() > 1) + panic("Single PCI is supported ONLY!"); + + mvPciInit(0, MV_PCI_MOD_HOST); + + /* I/O remmap */ + win.baseLow = 0x0; + win.baseHigh = 0x0; + mvCpuIfPciRemap(PCI_IF0_IO, &win); +} + + +/* Currentlly the PCI config read/write are implemented as read modify write + to 32 bit. + TBD: adjust it to realy use 1/2/4 byte(partial) read/write, after the pex + read config WA will be removed. +*/ +static int mv_pci0_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *val) +{ + + MV_U32 bus_num,func,regOff,dev_no,temp; + MV_U32 localBus; + + *val = 0xffffffff; + + bus_num = bus->number; + dev_no = PCI_SLOT(devfn); + + /* don't return for our device */ + localBus = mvPciLocalBusNumGet(0); + if((dev_no == 0) && ( bus_num == localBus)) { + DB(printk("PCI 0 read from our own dev return 0xffffffff \n")); + return 0xffffffff; + } + + func = PCI_FUNC(devfn); + regOff = (MV_U32)where & PCAR_REG_NUM_MASK; + + if ((func == 0)&&(dev_no < 2)) + DB(printk("PCI 0 read: bus = %x dev = %x func = %x regOff = %x ",bus_num,dev_no,func,regOff)); + + + temp = (u32) mvPciConfigRead(0, bus_num, dev_no, func, regOff); + + switch (size) { + case 1: + temp = (temp >> (8*(where & 0x3))) & 0xff; + break; + + case 2: + temp = (temp >> (8*(where & 0x2))) & 0xffff; + break; + + default: + break; + } + + *val = temp; + + if ((func == 0)&&(dev_no < 2)) { + DB(printk(" got %x \n",temp)); + } + + return 0; +} + +static int mv_pci0_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + MV_U32 bus_num,func,regOff,dev_no,temp, mask , shift; + + bus_num = bus->number; + dev_no = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + regOff = (MV_U32)where & PCAR_REG_NUM_MASK; + + DB(printk("PCI 0: writing data %x size %x to bus %x dev %x func %x offs %x \n",val,size,bus_num,dev_no,func,regOff)); + if( size != 4) + temp = (u32) mvPciConfigRead(0, bus_num, dev_no, func, regOff); + else + temp = val; + + switch (size) { + case 1: + shift = (8*(where & 0x3)); + mask = 0xff; + break; + + case 2: + shift = (8*(where & 0x2)); + mask = 0xffff; + break; + + default: + shift = 0; + mask = 0xffffffff; + break; + } + + temp = (temp & (~(mask<map_irq = mv_map_irq; + + res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + memset(res, 0, sizeof(struct resource) * 2); + + res[0].start = mv_pci_io_base_get(0) - IO_SPACE_REMAP; + res[0].end = mv_pci_io_base_get(0) - IO_SPACE_REMAP + mv_pci_io_size_get(0) - 1; + res[0].name = "PCI0 IO Primary"; + res[0].flags = IORESOURCE_IO; + + res[1].start = mv_pci_mem_base_get(0); + res[1].end = mv_pci_mem_base_get(0) + mv_pci_mem_size_get(0) - 1; + res[1].name = "PCI0 Memory Primary"; + res[1].flags = IORESOURCE_MEM; + + if (request_resource(&ioport_resource, &res[0])) + printk ("IO Request resource failed - Pci If %x\n",nr); + + if (request_resource(&iomem_resource, &res[1])) + printk ("Memory Request resource failed - Pci If %x\n",nr); + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + sys->io_offset = 0x0; + + return 1; + +} + +struct pci_bus *mv_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_ops *ops; + struct pci_bus *bus; + + if (nr) + panic("Single PCI is supported ONLY!"); + + ops = &mv_pci_ops; + bus = pci_scan_bus(sys->busnr, ops, sys); + return bus; +} + +static int __init mv_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return IRQ_AURORA_PCI0; +} + +static struct hw_pci mv_pci __initdata = { + .swizzle = pci_std_swizzle, + .map_irq = mv_map_irq, + .setup = mv_pci_setup, + .scan = mv_pci_scan_bus, + .preinit = mv_pci_preinit, +}; + +static int __init mv_pci_init(void) +{ + MV_U32 ifnum = mvCtrlPciMaxIfGet(); + if (ifnum) { + mv_pci.nr_controllers = ifnum; + pci_common_init(&mv_pci); + } + + return 0; +} + +subsys_initcall(mv_pci_init); diff --git a/arch/arm/mach-armada370/pex.c b/arch/arm/mach-armada370/pex.c new file mode 100755 index 000000000..6d9516354 --- /dev/null +++ b/arch/arm/mach-armada370/pex.c @@ -0,0 +1,455 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +//#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "pex/mvPex.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysPexApi.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +#undef DEBUG +#ifdef DEBUG +# define DB(x) x +#else +# define DB(x) +#endif + +#define PCI_ERR_NAME_LEN 12 +#define MV_MAX_PEX_IF_NUMBER 2 + +static int __init mv_map_irq_0(const struct pci_dev *dev, u8 slot, u8 pin); +static int __init mv_map_irq_1(const struct pci_dev *dev, u8 slot, u8 pin); + +void mv_pci_error_init(u32 pciIf); + +static irqreturn_t pex_error_interrupt(int irq, void *dev_id); + +static struct pex_if_error { + MV_8 irq_name[PCI_ERR_NAME_LEN]; + MV_U32 ifNumber; +} pex_err[MV_MAX_PEX_IF_NUMBER]; + +void __init mv_pci_preinit(void) +{ + MV_ADDR_WIN win; + MV_STATUS retval; + u32 pciIf; + u32 maxif = mvCtrlPexMaxIfGet(); + + /* Check Power State */ + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, 0)) + return; + + for (pciIf = 0; pciIf < maxif; pciIf++) { + + retval = mvSysPexInit(pciIf, MV_PEX_ROOT_COMPLEX); + + if (pciIf == 0) { + mvPexLocalBusNumSet(pciIf, 0); + mvPexLocalDevNumSet(pciIf, 1); + } + + /* Clear the secondary bus number */ + MV_REG_WRITE(PEX_SECONDARY_BUS_REG(pciIf), 0); + + if (retval == MV_NO_SUCH) { + //printk("pci_init:no such calling mvPexInit for PEX-%x\n",pciIf); + continue; + } + + if (retval != MV_OK) { + printk("pci_init:Error calling mvPexInit for PEX-%x\n",pciIf); + continue; + } + + /* unmask inter A/B/C/D */ + //printk("writing %x tp %x \n",MV_PCI_MASK_ABCD, MV_PCI_MASK_REG(pciIf) ); + MV_REG_WRITE(MV_PCI_MASK_REG(pciIf), MV_PCI_MASK_ABCD ); + + /* init PCI express error handling */ + mv_pci_error_init(pciIf); + + /* remmap IO !! */ + win.baseLow = (pciIf? PEX1_IO_PHYS_BASE : PEX0_IO_PHYS_BASE) - IO_SPACE_REMAP; + win.baseHigh = 0x0; + win.size = pciIf? PEX1_IO_SIZE : PEX0_IO_SIZE; + mvCpuIfPexRemap((pciIf? PEX1_IO : PEX0_IO), &win); + } +} + +/** +* mv_pci_error_init +* DESCRIPTION: init PCI express error handling +* INPUTS: pciIf - number of pex device +* OUTPUTS: N/A +* RETURNS: N/A +**/ +void mv_pci_error_init(u32 pciIf) +{ + MV_U32 reg_val; + + /* init pex_err structure per each pex */ + pex_err[pciIf].ifNumber = pciIf; + snprintf(pex_err[pciIf].irq_name, PCI_ERR_NAME_LEN, "error_pex%d", pciIf); + + /* register interrupt for PCI express error */ + if (request_irq((IRQ_AURORA_ERR_START + INT_ERR_PCIE(pciIf)), pex_error_interrupt, IRQF_DISABLED, + (const char*)pex_err[pciIf].irq_name, &pex_err[pciIf].ifNumber) < 0) { + panic("Could not allocate IRQ for PCI express error!"); + } + + /* get current value of Interrupt Mask Register */ + reg_val = MV_REG_READ(MV_PCI_MASK_REG(pciIf)); + + /* set relevant mask to Interrupt Mask Register */ + MV_REG_WRITE(MV_PCI_MASK_REG(pciIf), (reg_val | MV_PCI_MASK_ERR)); +} + +/* Currentlly the PCI config read/write are implemented as read modify write + to 32 bit. + TBD: adjust it to realy use 1/2/4 byte(partial) read/write, after the pex + read config WA will be removed. +*/ + +static int pci_read_cfg(u32 pciIf, u32 bus_num, u32 dev_no, + u32 func, u32 where) +{ + u32 cfgCmd; + u32 regOff = (MV_U32)where & (PXCAR_REG_NUM_MASK + | PXCAR_REAL_EXT_REG_NUM_MASK); + + /* Creating PEX address to be passed */ + cfgCmd = (bus_num << PXCAR_BUS_NUM_OFFS); + cfgCmd |= (dev_no << PXCAR_DEVICE_NUM_OFFS); + cfgCmd |= (func << PXCAR_FUNC_NUM_OFFS); + /* lgacy register space */ + cfgCmd |= (regOff & PXCAR_REG_NUM_MASK); + /* extended register space */ + cfgCmd |= (((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> + PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); + cfgCmd |= PXCAR_CONFIG_EN; + + /* Write the address to the PEX configuration address register */ + MV_REG_WRITE(PEX_CFG_ADDR_REG(pciIf), cfgCmd); + + /* + * In order to let the PEX controller absorbed the address of the + * read transaction we perform a validity check that the address + * was written + * */ + if (cfgCmd != MV_REG_READ(PEX_CFG_ADDR_REG(pciIf))) + return 0xFFFFFFFF; + + /* cleaning Master Abort */ + MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pciIf, PEX_STATUS_AND_COMMAND), + PXSAC_MABORT); + + /* Read the Data returned in the PEX Data register */ + return MV_REG_READ(PEX_CFG_DATA_REG(pciIf)); + +} + +/* Currentlly the PCI config read/write are implemented as read modify write + to 32 bit. + TBD: adjust it to realy use 1/2/4 byte(partial) read/write, after the pex + read config WA will be removed. +*/ +static int mv_pci_read_config(struct pci_bus *bus, + unsigned int devfn, int where, + int size, u32 *val) +{ + u32 bus_num, func, dev_no, temp, localBus; + struct pci_sys_data *sysdata = (struct pci_sys_data *)bus->sysdata; + u32 pciIf = sysdata->mv_controller_num; + + *val = 0xffffffff; + + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pciIf)) + return 0; + + bus_num = bus->number; + dev_no = PCI_SLOT(devfn); + + /* Our local bus is PEX so enable reading only device 0 */ + localBus = mvPexLocalBusNumGet(pciIf); + if ((dev_no != 0) && (bus_num == localBus)) { + DB(pr_info("PCI %d device %d illegal on local bus\n", pciIf, + dev_no)); + return 0xffffffff; + } + + func = PCI_FUNC(devfn); + temp = pci_read_cfg(pciIf, bus_num, dev_no, func, where); + + switch (size) { + case 1: + temp = (temp >> (8*(where & 0x3))) & 0xff; + break; + + case 2: + temp = (temp >> (8*(where & 0x2))) & 0xffff; + break; + + default: + break; + } + + *val = temp; + + DB(pr_info("PCI %d read: bus = %x dev = %x func = %x regOff = %x" + "val = 0x%08x\n", pciIf, bus_num, dev_no, func, + where, temp)); + + return 0; +} + +static int mv_pci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 bus_num, func, regOff, dev_no, temp, mask, shift; + struct pci_sys_data *sysdata = (struct pci_sys_data *)bus->sysdata; + u32 pciIf = sysdata->mv_controller_num; + u32 cfgCmd; + + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pciIf)) + return 0xFFFFFFFF; + + bus_num = bus->number; + dev_no = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + /* total of 12 bits: 8 legacy + 4 extended */ + regOff = (MV_U32)where & (PXCAR_REG_NUM_MASK | + PXCAR_REAL_EXT_REG_NUM_MASK); + + if (size != 4) + temp = pci_read_cfg(pciIf, bus_num, dev_no, func, where); + else + temp = val; + + switch (size) { + case 1: + shift = (8 * (where & 0x3)); + mask = 0xff; + break; + case 2: + shift = (8 * (where & 0x2)); + mask = 0xffff; + break; + + default: + shift = 0; + mask = 0xffffffff; + break; + } + + temp = (temp & (~(mask << shift))) | ((val & mask) << shift); + + /* Creating PEX address to be passed */ + cfgCmd = (bus_num << PXCAR_BUS_NUM_OFFS); + cfgCmd |= (dev_no << PXCAR_DEVICE_NUM_OFFS); + cfgCmd |= (func << PXCAR_FUNC_NUM_OFFS); + /* lgacy register space */ + cfgCmd |= (regOff & PXCAR_REG_NUM_MASK); + /* extended register space */ + cfgCmd |= (((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> + PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); + cfgCmd |= PXCAR_CONFIG_EN; + + DB(pr_info("PCI %d: write data 0x%08x size %x to bus %x dev %x func %x" + "offs %x\n", pciIf, temp, size, bus_num, dev_no, + func, regOff)); + + /* Write the address to the PEX configuration address register */ + MV_REG_WRITE(PEX_CFG_ADDR_REG(pciIf), cfgCmd); + + /* + * In order to let the PEX controller absorbed the address of the read + * transaction we perform a validity check that the address was written + */ + if (cfgCmd != MV_REG_READ(PEX_CFG_ADDR_REG(pciIf))) { + pr_info("Error: mv_pci_write_config failed to write\n"); + return 1; + } + + /* Write the Data passed to the PEX Data register */ + MV_REG_WRITE(PEX_CFG_DATA_REG(pciIf), temp); + + return 0; +} + +static struct pci_ops mv_pci_ops = { + .read = mv_pci_read_config, + .write = mv_pci_write_config, +}; + + +int __init mv_pci_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + switch (nr) { + case 0: + sys->map_irq = mv_map_irq_0; + break; + case 1: + sys->map_irq = mv_map_irq_1; + break; + default: + printk("mv_pci_setup: nr(%d) out of scope\n",nr); + return 0; + } + + res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + memset(res, 0, sizeof(struct resource) * 2); + + if(!nr) { + res[0].start = PEX0_IO_PHYS_BASE - IO_SPACE_REMAP; + res[0].end = PEX0_IO_PHYS_BASE - IO_SPACE_REMAP + PEX0_IO_SIZE - 1; + res[0].name = "PEX0 IO"; + res[0].flags = IORESOURCE_IO; + + res[1].start = PEX0_MEM_PHYS_BASE; + res[1].end = PEX0_MEM_PHYS_BASE + PEX0_MEM_SIZE - 1; + res[1].name = "PEX0 Memory"; + res[1].flags = IORESOURCE_MEM; + } else { + res[0].start = PEX1_IO_PHYS_BASE - IO_SPACE_REMAP; + res[0].end = PEX1_IO_PHYS_BASE - IO_SPACE_REMAP + PEX1_IO_SIZE - 1; + res[0].name = "PEX1 IO"; + res[0].flags = IORESOURCE_IO; + + res[1].start = PEX1_MEM_PHYS_BASE; + res[1].end = PEX1_MEM_PHYS_BASE + PEX1_MEM_SIZE - 1; + res[1].name = "PEX1 Memory"; + res[1].flags = IORESOURCE_MEM; + } + + if (request_resource(&ioport_resource, &res[0])) + { + printk ("IO Request resource failed - Pci If %x\n",nr); + } + if (request_resource(&iomem_resource, &res[1])) + { + printk ("Memory Request resource failed - Pci If %x\n",nr); + } + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + sys->io_offset = 0x0; + sys->mv_controller_num = nr; + + return 1; + +} + +struct pci_bus *mv_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_ops *ops = &mv_pci_ops; + struct pci_bus *bus; + + bus = pci_scan_bus(sys->busnr, ops, sys); + + if (sys->mv_controller_num == 0) { + mvPexLocalBusNumSet(1, bus->subordinate + 1); + mvPexLocalDevNumSet(1, 1); + } + + return bus; +} + +/** +* pex_error_interrupt +* DESCRIPTION: PCI express error interrupt routine +* INPUTS: @irq: irq number + @dev_id: device id - ignored +* OUTPUTS: kernel error message +* RETURNS: IRQ_HANDLED +**/ +static irqreturn_t pex_error_interrupt(int irq, void *dev_id) +{ + MV_U32 reg_val; + MV_U32 ifPexNumber=*(MV_U32 *)dev_id; + + /* get current value of Interrupt Cause Register */ + reg_val = MV_REG_READ(MV_PCI_IRQ_CAUSE_REG(ifPexNumber)); + printk(KERN_ERR "PCI express error: irq - %d, Pex number: %d, " + "Interrupt Cause Register value: %x \n", irq, ifPexNumber, reg_val); + + return IRQ_HANDLED; +} + +static int __init mv_map_irq_0(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return IRQ_AURORA_PCIE0; +} + +static int __init mv_map_irq_1(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return IRQ_AURORA_PCIE1; +} + + +static struct hw_pci mv_pci __initdata = { + .swizzle = pci_std_swizzle, + .map_irq = mv_map_irq_0, + .setup = mv_pci_setup, + .scan = mv_pci_scan_bus, + .preinit = mv_pci_preinit, +}; + +static int __init mv_pci_init(void) +{ +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); + if (pexPower == MV_FALSE) + { + printk("\nWarning PCI-E is Powered Off\n"); + return 0; + } +#endif + + mv_pci.nr_controllers = mvCtrlPexMaxIfGet(); + pci_common_init(&mv_pci); + + return 0; +} + + +subsys_initcall(mv_pci_init); diff --git a/arch/arm/mach-armada370/proc_aurora_dbg.c b/arch/arm/mach-armada370/proc_aurora_dbg.c new file mode 100755 index 000000000..a46b0fe77 --- /dev/null +++ b/arch/arm/mach-armada370/proc_aurora_dbg.c @@ -0,0 +1,87 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct proc_dir_entry *aurora_dbg; + +unsigned int aurora_core_index(void) +{ + unsigned int value; + + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 5 @ read CPU ID reg\n" + : "=r" (value) :: "memory"); + return (value & 0xF); +} + +/********************************************************************/ +int aurora_dbg_read (char *buffer, char **buffer_location, off_t offset, + int buffer_length, int *zero, void *ptr) { + + char *p = buffer; + unsigned int val, len; + +#ifdef CONFIG_SMP + p += sprintf(p,"CPU %d:\n", aurora_core_index()); +#endif + __asm volatile ("mrc p15, 1, %0, c15, c1, 1" : "=r" (val)); + p += sprintf(p, "c1, 1 %x \n", val); + __asm volatile ("mrc p15, 1, %0, c15, c1, 2" : "=r" (val)); + p += sprintf(p, "c1, 2 %x \n", val); + __asm volatile ("mrc p15, 1, %0, c15, c2, 0" : "=r" (val)); + p += sprintf(p, "c2, 0 %x \n", val); + __asm volatile ("mrc p15, 1, %0, c15, c2, 1" : "=r" (val)); + p += sprintf(p, "c2, 1 %x \n", val); + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (val)); + p += sprintf(p, "c1, 0 %x \n", val); + +#ifdef CONFIG_PERF_EVENTS + __asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); + p += sprintf(p, "pmon ctrl %x \n", val); + __asm volatile ("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); + p += sprintf(p, "pmon cntrs en %x \n", val); + __asm volatile ("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); + p += sprintf(p, "pmon cntrs oflow %x \n", val); + __asm volatile ("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); + p += sprintf(p, "pmon cntr sel %x \n", val); + __asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); + p += sprintf(p, "pmon cycle cnt %x \n", val); + __asm volatile ("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); + p += sprintf(p, "pmon evt sel %x \n", val); + __asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); + p += sprintf(p, "pmon cntr val %x \n", val); + __asm volatile ("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); + p += sprintf(p, "pmon int en %x \n", val); +#endif + + len = (p - buffer); + return len; +} + +/********************************************************************/ +int __init start_aurora_dbg(void) +{ + aurora_dbg = create_proc_entry ("aurora_dbg" , 0666 , NULL); + aurora_dbg->read_proc = aurora_dbg_read; + aurora_dbg->write_proc = NULL; + aurora_dbg->nlink = 1; + return 0; +} +void __exit stop_aurora_dbg(void) +{ + remove_proc_entry("aurora_dbg", NULL); + return; +} +module_init(start_aurora_dbg); +module_exit(stop_aurora_dbg); diff --git a/arch/arm/mach-armada370/synology-gpio.c b/arch/arm/mach-armada370/synology-gpio.c new file mode 100755 index 000000000..8e045546d --- /dev/null +++ b/arch/arm/mach-armada370/synology-gpio.c @@ -0,0 +1,1073 @@ +/* + * Synology Armada NAS Board GPIO Setup + * + * Maintained by: KueiHuan Chen + * + * Copyright 2009-2012 Synology, Inc. All rights reserved. + * Copyright 2009-2012 KueiHuan.Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#if defined(CONFIG_SYNO_ARMADA_ARCH) + +#include +#include +#include + +#include "boardEnv/mvBoardEnvSpec.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "config/mvSysSataConfig.h" +#include "mvOs.h" + +#define GPIO_UNDEF 0xFF + +/* copied from synobios.h */ +#define DISK_LED_OFF 0 +#define DISK_LED_GREEN_SOLID 1 +#define DISK_LED_ORANGE_SOLID 2 +#define DISK_LED_ORANGE_BLINK 3 +#define DISK_LED_GREEN_BLINK 4 + +#define SYNO_LED_OFF 0 +#define SYNO_LED_ON 1 +#define SYNO_LED_BLINKING 2 + +typedef struct __tag_SYNO_ARMADA_HDD_PM_GPIO { + u8 hdd1_pm; + u8 hdd2_pm; + u8 hdd3_pm; + u8 hdd4_pm; +} SYNO_ARMADA_HDD_PM_GPIO; + +typedef struct __tag_SYNO_ARMADA_FAN_GPIO { + u8 fan_1; + u8 fan_2; + u8 fan_3; + u8 fan_fail; + u8 fan_fail_2; + u8 fan_fail_3; +} SYNO_ARMADA_FAN_GPIO; + +typedef struct __tag_SYNO_ARMADA_MODEL_GPIO { + u8 model_id_0; + u8 model_id_1; + u8 model_id_2; + u8 model_id_3; +} SYNO_ARMADA_MODEL_GPIO; + +typedef struct __tag_SYNO_ARMADA_EXT_HDD_LED_GPIO { + u8 hdd1_led_0; + u8 hdd1_led_1; + u8 hdd2_led_0; + u8 hdd2_led_1; + u8 hdd3_led_0; + u8 hdd3_led_1; + u8 hdd4_led_0; + u8 hdd4_led_1; + u8 hdd5_led_0; + u8 hdd5_led_1; + u8 hdd_led_mask; +} SYNO_ARMADA_EXT_HDD_LED_GPIO; + +typedef struct __tag_SYNO_ARMADA_MULTI_BAY_GPIO { + u8 inter_lock; +}SYNO_ARMADA_MULTI_BAY_GPIO; + +typedef struct __tag_SYNO_ARMADA_SOC_HDD_LED_GPIO { + u8 hdd2_fail_led; + u8 hdd1_fail_led; +}SYNO_ARMADA_SOC_HDD_LED_GPIO; + +typedef struct __tag_SYNO_ARMADA_RACK_GPIO { + u8 buzzer_mute_req; + u8 buzzer_mute_ack; + u8 rps1_on; + u8 rps2_on; +}SYNO_ARMADA_RACK_GPIO; + +typedef struct __tag_SYNO_ARMADA_STATUS_LED_GPIO { + u8 alarm_led; + u8 power_led; +} SYNO_ARMADA_STATUS_LED_GPIO; + +typedef struct __tag_SYNO_ARMADA_USB_GPIO { + u8 usb_power; +} SYNO_ARMADA_USB_GPIO; + +typedef struct __tag_SYNO_ARMADA_GENERIC_GPIO { + SYNO_ARMADA_EXT_HDD_LED_GPIO ext_sata_led; + SYNO_ARMADA_SOC_HDD_LED_GPIO soc_sata_led; + SYNO_ARMADA_MODEL_GPIO model; + SYNO_ARMADA_FAN_GPIO fan; + SYNO_ARMADA_HDD_PM_GPIO hdd_pm; + SYNO_ARMADA_RACK_GPIO rack; + SYNO_ARMADA_MULTI_BAY_GPIO multi_bay; + SYNO_ARMADA_STATUS_LED_GPIO status; + SYNO_ARMADA_USB_GPIO usb; +}SYNO_ARMADA_GENERIC_GPIO; + +static SYNO_ARMADA_GENERIC_GPIO generic_gpio; + +unsigned int Syno6282ModelIDGet(SYNO_ARMADA_GENERIC_GPIO *pGpio) +{ + return (((gpio_get_value(pGpio->model.model_id_0) ? 1 : 0) << 3) | + ((gpio_get_value(pGpio->model.model_id_1) ? 1 : 0) << 2) | + ((gpio_get_value(pGpio->model.model_id_2) ? 1 : 0) << 1) | + ((gpio_get_value(pGpio->model.model_id_3) ? 1 : 0) << 0)); +} + +int +SYNO_ARMADA_GPIO_PIN(int pin, int *pValue, int isWrite) +{ + int ret = -1; + + if (!pValue) + goto END; + + if (1 == isWrite) + gpio_set_value(pin, *pValue); + else + *pValue = gpio_get_value(pin); + + ret = 0; +END: + return 0; +} + +extern MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); + +int +SYNO_ARMADA_GPIO_BLINK(int pin, int blink) +{ + u32 grp = pin >> 5; + u32 mask = (1 << (pin & 0x1F)); + + if (blink) + mvGppBlinkEn(grp, mask, mask); + else + mvGppBlinkEn(grp, mask, 0); + return 0; +} + +MV_STATUS SYNOMppCtrlRegWrite(MV_U32 mppPin, MV_U32 mppVal) +{ + MV_U32 origVal; + MV_U32 mppGroup; + + /* there are 66 mpp pins only */ + if(66 < mppPin) + return -EINVAL; + + /* get the group the pin belongs to, for addressing */ + /* 32 bits per register, 4 bits per pin, 8 pins in a group */ + mppGroup = mppPin / 8; + mppVal &= 0x0F; + origVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + + /* get the corresponding bits */ + origVal &= ~(0xF << ((mppPin % 8)*4)); + origVal |= (mppVal << ((mppPin % 8)*4)); + + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), origVal); + + return MV_OK; +} + +void SYNO_ENABLE_HDD_LED(int blEnable) +{ + if (GPIO_UNDEF != generic_gpio.ext_sata_led.hdd_led_mask) + gpio_set_value(generic_gpio.ext_sata_led.hdd_led_mask, blEnable ? 0 : 1); +} + +int +SYNO_SOC_HDD_LED_SET(int index, int status) +{ + int ret = -1; + int mpp_pin; + int mode_sata_present; + int mode_gpio; + int fail_led; + int active = 0; //note: led is low active + +#ifdef MY_ABC_HERE + if (syno_is_hw_version(HW_RS214v10)) { + // RS214 led is high active + active = 1; + } +#endif + + WARN_ON(GPIO_UNDEF == generic_gpio.soc_sata_led.hdd1_fail_led); + WARN_ON(GPIO_UNDEF == generic_gpio.soc_sata_led.hdd2_fail_led); + + if (SYNO_RS214_ID == mvBoardIdGet()) { + /* RS214 disk LED is HIGH active, so we need invert the active indication */ + MV_REG_WRITE(MV_SATA_REGS_OFFSET + 0x2c, 0xc); + } else { + MV_REG_WRITE(MV_SATA_REGS_OFFSET + 0x2c, 0x4); + } + + /* assign pin info according to hdd */ + switch (index) { + case 1: + mpp_pin = 60; + mode_sata_present = 0x03; + mode_gpio = 0; + fail_led = generic_gpio.soc_sata_led.hdd1_fail_led; + break; + case 2: + mpp_pin = 48; + mode_sata_present = 0x04; + mode_gpio = 0; + fail_led = generic_gpio.soc_sata_led.hdd2_fail_led; + break; + default: + printk("Wrong HDD number [%d]\n", index); + goto END; + } + + /* Since faulty led and present led are combined, + we need to disable present led when light on faulty's */ + if ( DISK_LED_ORANGE_SOLID == status || + DISK_LED_ORANGE_BLINK == status ) + { + SYNOMppCtrlRegWrite(mpp_pin, mode_gpio); // change MPP to GPIO mode + gpio_set_value(mpp_pin, !active); + gpio_set_value(fail_led, active); + } + else if ( DISK_LED_GREEN_SOLID == status || + DISK_LED_GREEN_BLINK == status ) + { + SYNOMppCtrlRegWrite(mpp_pin, mode_sata_present); // change MPP to sata present mode + gpio_set_value(fail_led, !active); + } + else if (DISK_LED_OFF == status) + { + SYNOMppCtrlRegWrite(mpp_pin, mode_gpio); + gpio_set_value(mpp_pin, !active); + gpio_set_value(fail_led, !active); + } + else + { + printk("Wrong HDD led status [%d]\n", status); + goto END; + } + + ret = 0; +END: + return ret; +} + +int +SYNO_CTRL_EXT_CHIP_HDD_LED_SET(int index, int status) +{ + int ret = -1; + int pin1 = 0, pin2 = 0, bit1 = 0, bit2 = 0; + + bit1 = ( status >> 0 ) & 0x1; + bit2 = ( status >> 1 ) & 0x1; + + switch (index) { + case 1: + pin1 = generic_gpio.ext_sata_led.hdd1_led_0; + pin2 = generic_gpio.ext_sata_led.hdd1_led_1; + break; + case 2: + pin1 = generic_gpio.ext_sata_led.hdd2_led_0; + pin2 = generic_gpio.ext_sata_led.hdd2_led_1; + break; + case 3: + pin1 = generic_gpio.ext_sata_led.hdd3_led_0; + pin2 = generic_gpio.ext_sata_led.hdd3_led_1; + break; + case 4: + pin1 = generic_gpio.ext_sata_led.hdd4_led_0; + pin2 = generic_gpio.ext_sata_led.hdd4_led_1; + break; + case 5: + if (generic_gpio.ext_sata_led.hdd5_led_0 == GPIO_UNDEF || + generic_gpio.ext_sata_led.hdd5_led_1 == GPIO_UNDEF) { + //some 4 bay model don't contain such gpio. + ret = 0; + goto END; + } + pin1 = generic_gpio.ext_sata_led.hdd5_led_0; + pin2 = generic_gpio.ext_sata_led.hdd5_led_1; + break; + case 6: + //for esata + ret = 0; + goto END; + default: + printk("Wrong HDD number [%d]\n", index); + goto END; + } + + WARN_ON(pin1 == GPIO_UNDEF); + WARN_ON(pin2 == GPIO_UNDEF); + + gpio_set_value(pin1, bit1); + gpio_set_value(pin2, bit2); + + ret = 0; +END: + return ret; +} + +int +SYNO_CTRL_USB_HDD_LED_SET(int status) +{ + int pin1 = GPIO_UNDEF, pin2 = GPIO_UNDEF, + bit1 = 0, bit2 = 0, + blink1 = 0, blink2 = 0; + + pin1 = generic_gpio.ext_sata_led.hdd1_led_0; + pin2 = generic_gpio.ext_sata_led.hdd1_led_1; + + WARN_ON(pin1 == GPIO_UNDEF); + WARN_ON(pin2 == GPIO_UNDEF); + + switch (status) { + case DISK_LED_OFF: + bit1 = 0; + bit2 = 0; + blink1 = 0; + blink2 = 0; + break; + case DISK_LED_GREEN_SOLID: + bit1 = 0; + bit2 = 1; + blink1 = 0; + blink2 = 0; + break; + case DISK_LED_ORANGE_SOLID: + bit1 = 1; + bit2 = 0; + blink1 = 0; + blink2 = 0; + break; + case DISK_LED_ORANGE_BLINK: + bit1 = 1; + bit2 = 0; + blink1 = 1; + blink2 = 0; + break; + case DISK_LED_GREEN_BLINK: + bit1 = 0; + bit2 = 1; + blink1 = 0; + blink2 = 1; + break; + default: + printk("Wrong disk led set.\n"); + break; + } + + gpio_set_value(pin1, bit1); + gpio_set_value(pin2, bit2); + SYNO_ARMADA_GPIO_BLINK(pin1, blink1); + SYNO_ARMADA_GPIO_BLINK(pin2, blink2); + + return 0; +} + +int SYNO_CTRL_POWER_LED_SET(int status) +{ + int pin = GPIO_UNDEF, bit = 0, blink = 0; + + pin = generic_gpio.status.power_led; + + WARN_ON(pin == GPIO_UNDEF); + + switch (status) { + case SYNO_LED_OFF: + blink = 0; + bit = 1; + break; + case SYNO_LED_ON: + blink = 0; + bit = 0; + break; + case SYNO_LED_BLINKING: + blink = 1; + bit = 0; + break; + } + + gpio_set_value(pin, bit); + SYNO_ARMADA_GPIO_BLINK(pin, blink); + + return 0; +} + +int SYNO_CTRL_HDD_POWERON(int index, int value) +{ + int ret = -1; + + switch (index) { + case 1: + WARN_ON(GPIO_UNDEF == generic_gpio.hdd_pm.hdd1_pm); + gpio_set_value(generic_gpio.hdd_pm.hdd1_pm, value); + break; + case 2: + WARN_ON(GPIO_UNDEF == generic_gpio.hdd_pm.hdd2_pm); + gpio_set_value(generic_gpio.hdd_pm.hdd2_pm, value); + break; + case 3: + WARN_ON(GPIO_UNDEF == generic_gpio.hdd_pm.hdd3_pm); + gpio_set_value(generic_gpio.hdd_pm.hdd3_pm, value); + break; + case 4: + WARN_ON(GPIO_UNDEF == generic_gpio.hdd_pm.hdd4_pm); + gpio_set_value(generic_gpio.hdd_pm.hdd4_pm, value); + break; + default: + goto END; + } + + ret = 0; +END: + return ret; +} + +int SYNO_CTRL_FAN_PERSISTER(int index, int status, int isWrite) +{ + int ret = 0; + u8 pin = GPIO_UNDEF; + + switch (index) { + case 1: + pin = generic_gpio.fan.fan_1; + break; + case 2: + pin = generic_gpio.fan.fan_2; + break; + case 3: + pin = generic_gpio.fan.fan_3; + break; + default: + ret = -1; + printk("%s fan not match\n", __FUNCTION__); + goto END; + } + + WARN_ON(GPIO_UNDEF == pin); + gpio_set_value(pin, status); +END: + return ret; +} + +int SYNO_CTRL_FAN_STATUS_GET(int index, int *pValue) +{ + int ret = 0; + + switch (index) { + case 1: + WARN_ON(GPIO_UNDEF == generic_gpio.fan.fan_fail); + *pValue = gpio_get_value(generic_gpio.fan.fan_fail); + break; + case 2: + WARN_ON(GPIO_UNDEF == generic_gpio.fan.fan_fail_2); + *pValue = gpio_get_value(generic_gpio.fan.fan_fail_2); + break; + case 3: + WARN_ON(GPIO_UNDEF == generic_gpio.fan.fan_fail_3); + *pValue = gpio_get_value(generic_gpio.fan.fan_fail_3); + break; + default: + WARN_ON(1); + break; + } + + if(*pValue) + *pValue = 0; + else + *pValue = 1; + + return ret; +} + +int SYNO_CTRL_ALARM_LED_SET(int status) +{ + WARN_ON(GPIO_UNDEF == generic_gpio.status.alarm_led); + + gpio_set_value(generic_gpio.status.alarm_led, status); + return 0; +} + +int SYNO_CTRL_BACKPLANE_STATUS_GET(int *pStatus) +{ + WARN_ON(GPIO_UNDEF == generic_gpio.multi_bay.inter_lock); + + *pStatus = gpio_get_value(generic_gpio.multi_bay.inter_lock); + return 0; +} + +int SYNO_CTRL_BUZZER_CLEARED_GET(int *pValue) +{ + int tempVal = 0; + + WARN_ON(GPIO_UNDEF == generic_gpio.rack.buzzer_mute_req); + + tempVal = gpio_get_value(generic_gpio.rack.buzzer_mute_req); + if ( tempVal ) { + *pValue = 0; + } else { + *pValue = 1; + tempVal = 1; + } + + return 0; +} + +#define ARRAY_LEN(x) (sizeof(x)/sizeof(x[0])) +struct disk_info { + char *hw_version; + int max_disk_id; +}; +static struct disk_info ds213j_family[] = { + {HW_DS213jv10, 2}, + {HW_DS114v10, 1}, + {HW_DS214v10, 2} +}; + +MV_U8 SYNOArmadaIsBoardNeedPowerUpHDD(MV_U32 disk_id) { + u8 ret = 0; + MV_U32 boardId = mvBoardIdGet(); + struct disk_info *table = NULL; + int table_cnt = 0; + int def_max_disk = 0; + + switch(boardId) { + case SYNO_DS213j_ID: + table = ds213j_family; + table_cnt = ARRAY_LEN(ds213j_family); + def_max_disk = 2; + break; + case SYNO_US3_ID: + def_max_disk = 0; + break; + case SYNO_RS214_ID: + def_max_disk = 2; + break; + case SYNO_DS214se_ID: + def_max_disk = 2; + break; + case SYNO_DS414slim_ID: + def_max_disk = 0; + break; + + default: + break; + } + + /* lookup table for max disk + if not found, compare default */ + ret = (disk_id <= def_max_disk)? 1 : 0; + if (table) { + int i; + for (i = 0; i < table_cnt; i++) { + if (syno_is_hw_version(table[i].hw_version)) { + if (disk_id <= table[i].max_disk_id) { + ret = 1; + } + break; + } + } + } + + return ret; +} + +/* SYNO_CHECK_HDD_PRESENT + * Check HDD present for evansport + * input : index - disk index, 1-based. + * output: 0 - HDD not present, 1 - HDD present. + */ +int SYNO_CHECK_HDD_PRESENT(int index) +{ + return 1; +} + +void SYNO_ENABLE_USB_POWER(int blEnable) +{ + if (GPIO_UNDEF != generic_gpio.usb.usb_power) + gpio_set_value(generic_gpio.usb.usb_power, blEnable ? 0 : 1); +} + +EXPORT_SYMBOL(SYNOArmadaIsBoardNeedPowerUpHDD); +EXPORT_SYMBOL(SYNO_ARMADA_GPIO_PIN); +EXPORT_SYMBOL(SYNO_ARMADA_GPIO_BLINK); +EXPORT_SYMBOL(SYNO_ENABLE_HDD_LED); +EXPORT_SYMBOL(SYNO_SOC_HDD_LED_SET); +EXPORT_SYMBOL(SYNO_CTRL_EXT_CHIP_HDD_LED_SET); +EXPORT_SYMBOL(SYNO_CTRL_USB_HDD_LED_SET); +EXPORT_SYMBOL(SYNO_CTRL_POWER_LED_SET); +EXPORT_SYMBOL(SYNO_CTRL_HDD_POWERON); +EXPORT_SYMBOL(SYNO_CTRL_FAN_PERSISTER); +EXPORT_SYMBOL(SYNO_CTRL_FAN_STATUS_GET); +EXPORT_SYMBOL(SYNO_CTRL_ALARM_LED_SET); +EXPORT_SYMBOL(SYNO_CTRL_BACKPLANE_STATUS_GET); +EXPORT_SYMBOL(SYNO_CTRL_BUZZER_CLEARED_GET); +EXPORT_SYMBOL(SYNO_CHECK_HDD_PRESENT); +EXPORT_SYMBOL(SYNO_ENABLE_USB_POWER); + +/* + Pin Mode Signal select and definition Input/output Pull-up/pull-down + MPP[0:1] 0x1 UART0 + MPP[2:3] 0x1 TWSI + MPP[4] 0x1 CPU Power control Out + MPP[5:16] 0x0 Reserved + MPP[17:18] 0x1 Ethernet SMI + MPP[19:30] 0x0 Reserved + MPP[31] 0x0 HDD 0 fail LED Out + MPP[32] 0x0 HDD 1 fail LED Out + MPP[33:36] 0x2 SPI + MPP[37] 0x0 HDD 0 Power Out + MPP[38] 0x0 Fan Sense In + MPP[39:40] 0x0 Reserved + MPP[41:42] 0x1 UART1 + MPP[43:47] 0x0 Reserved + MPP[48] 0x4 HDD 1 Present Out + MPP[49:54] 0x0 Reserved + MPP[55:58] 0x0 Model ID In + MPP[59] 0x0 Reserved + MPP[60] 0x3 HDD 0 Present Out + MPP[61] 0x0 Reserved + MPP[62] 0x0 HDD 1 Power Out + MPP[63] 0x0 FAN Control Max Out + MPP[64] 0x0 FAN Control Middle Out + MPP[65] 0x0 FAN Control Min Out +*/ +static void +Armada_370_213j_GPIO_init(SYNO_ARMADA_GENERIC_GPIO *global_gpio) +{ + SYNO_ARMADA_GENERIC_GPIO gpio_213j = { + .ext_sata_led = { + .hdd1_led_0 = GPIO_UNDEF, + .hdd1_led_1 = GPIO_UNDEF, + .hdd2_led_0 = GPIO_UNDEF, + .hdd2_led_1 = GPIO_UNDEF, + .hdd3_led_0 = GPIO_UNDEF, + .hdd3_led_1 = GPIO_UNDEF, + .hdd4_led_0 = GPIO_UNDEF, + .hdd4_led_1 = GPIO_UNDEF, + .hdd5_led_0 = GPIO_UNDEF, + .hdd5_led_1 = GPIO_UNDEF, + .hdd_led_mask = GPIO_UNDEF, + }, + .soc_sata_led = { + .hdd2_fail_led = 32, + .hdd1_fail_led = 31, + }, + .model = { + .model_id_0 = 55, + .model_id_1 = 56, + .model_id_2 = 57, + .model_id_3 = 58, + }, + .fan = { + .fan_1 = 63, + .fan_2 = 64, + .fan_3 = 65, + .fan_fail = 38, + .fan_fail_2 = GPIO_UNDEF, + .fan_fail_3 = GPIO_UNDEF, + }, + .hdd_pm = { + .hdd1_pm = 37, + .hdd2_pm = 62, + .hdd3_pm = GPIO_UNDEF, + .hdd4_pm = GPIO_UNDEF, + }, + .rack = { + .buzzer_mute_req = GPIO_UNDEF, + .buzzer_mute_ack = GPIO_UNDEF, + .rps1_on = GPIO_UNDEF, + .rps2_on = GPIO_UNDEF, + }, + .multi_bay = { + .inter_lock = GPIO_UNDEF, + }, + .status = { + .power_led = GPIO_UNDEF, + .alarm_led = GPIO_UNDEF, + }, + .usb = { + .usb_power = GPIO_UNDEF, + }, + }; + + *global_gpio = gpio_213j; +} + +extern void (*syno_power_off_indicator)(void); +static void us3_power_off(void) +{ + /* since US3 has no microP to power off, + * we need an indicator for system halt */ + printk("Set US3 shutdown indicator\n"); + /* set power green off */ + gpio_set_value(42, 1); + SYNO_ARMADA_GPIO_BLINK(42, 0); + /* set power orange on */ + gpio_set_value(43, 0); + SYNO_ARMADA_GPIO_BLINK(43, 0); +} + +static void +Armada_370_us3_GPIO_init(SYNO_ARMADA_GENERIC_GPIO *global_gpio) +{ + SYNO_ARMADA_GENERIC_GPIO gpio_us3 = { + .ext_sata_led = { + .hdd1_led_0 = GPIO_UNDEF, + .hdd1_led_1 = GPIO_UNDEF, + .hdd2_led_0 = GPIO_UNDEF, + .hdd2_led_1 = GPIO_UNDEF, + .hdd3_led_0 = GPIO_UNDEF, + .hdd3_led_1 = GPIO_UNDEF, + .hdd4_led_0 = GPIO_UNDEF, + .hdd4_led_1 = GPIO_UNDEF, + .hdd5_led_0 = GPIO_UNDEF, + .hdd5_led_1 = GPIO_UNDEF, + .hdd_led_mask = GPIO_UNDEF, + }, + .soc_sata_led = { + .hdd2_fail_led = GPIO_UNDEF, + .hdd1_fail_led = GPIO_UNDEF, + }, + .model = { + .model_id_0 = 55, + .model_id_1 = 56, + .model_id_2 = 57, + .model_id_3 = 58, + }, + .fan = { + .fan_1 = GPIO_UNDEF, + .fan_2 = GPIO_UNDEF, + .fan_3 = GPIO_UNDEF, + .fan_fail = GPIO_UNDEF, + .fan_fail_2 = GPIO_UNDEF, + .fan_fail_3 = GPIO_UNDEF, + }, + .hdd_pm = { + .hdd1_pm = GPIO_UNDEF, + .hdd2_pm = GPIO_UNDEF, + .hdd3_pm = GPIO_UNDEF, + .hdd4_pm = GPIO_UNDEF, + }, + .rack = { + .buzzer_mute_req = GPIO_UNDEF, + .buzzer_mute_ack = GPIO_UNDEF, + .rps1_on = GPIO_UNDEF, + .rps2_on = GPIO_UNDEF, + }, + .multi_bay = { + .inter_lock = GPIO_UNDEF, + }, + .status = { + .power_led = GPIO_UNDEF, + .alarm_led = GPIO_UNDEF, + }, + .usb = { + .usb_power = GPIO_UNDEF, + }, + }; + + *global_gpio = gpio_us3; + + /* customize power off indicator */ + syno_power_off_indicator = us3_power_off; +} + +static void +Armada_370_rs214_GPIO_init(SYNO_ARMADA_GENERIC_GPIO *global_gpio) +{ + SYNO_ARMADA_GENERIC_GPIO gpio_rs214 = { + .ext_sata_led = { + .hdd1_led_0 = GPIO_UNDEF, + .hdd1_led_1 = GPIO_UNDEF, + .hdd2_led_0 = GPIO_UNDEF, + .hdd2_led_1 = GPIO_UNDEF, + .hdd3_led_0 = GPIO_UNDEF, + .hdd3_led_1 = GPIO_UNDEF, + .hdd4_led_0 = GPIO_UNDEF, + .hdd4_led_1 = GPIO_UNDEF, + .hdd5_led_0 = GPIO_UNDEF, + .hdd5_led_1 = GPIO_UNDEF, + .hdd_led_mask = GPIO_UNDEF, + }, + .soc_sata_led = { + .hdd2_fail_led = 32, + .hdd1_fail_led = 49, + }, + .model = { + .model_id_0 = 55, + .model_id_1 = 56, + .model_id_2 = 57, + .model_id_3 = 58, + }, + .fan = { + .fan_1 = 65, + .fan_2 = 64, + .fan_3 = 63, + .fan_fail = 38, + .fan_fail_2 = 50, + .fan_fail_3 = 51, + }, + .hdd_pm = { + .hdd1_pm = 60, + .hdd2_pm = 48, + .hdd3_pm = GPIO_UNDEF, + .hdd4_pm = GPIO_UNDEF, + }, + .rack = { + .buzzer_mute_req = 52, + .buzzer_mute_ack = GPIO_UNDEF, + .rps1_on = GPIO_UNDEF, + .rps2_on = GPIO_UNDEF, + }, + .multi_bay = { + .inter_lock = GPIO_UNDEF, + }, + .status = { + .power_led = GPIO_UNDEF, + .alarm_led = GPIO_UNDEF, + }, + .usb = { + .usb_power = GPIO_UNDEF, + }, + }; + + *global_gpio = gpio_rs214; +} + +static void +Armada_370_214se_GPIO_init(SYNO_ARMADA_GENERIC_GPIO *global_gpio) +{ + SYNO_ARMADA_GENERIC_GPIO gpio_214se = { + .ext_sata_led = { + .hdd1_led_0 = GPIO_UNDEF, + .hdd1_led_1 = GPIO_UNDEF, + .hdd2_led_0 = GPIO_UNDEF, + .hdd2_led_1 = GPIO_UNDEF, + .hdd3_led_0 = GPIO_UNDEF, + .hdd3_led_1 = GPIO_UNDEF, + .hdd4_led_0 = GPIO_UNDEF, + .hdd4_led_1 = GPIO_UNDEF, + .hdd5_led_0 = GPIO_UNDEF, + .hdd5_led_1 = GPIO_UNDEF, + .hdd_led_mask = GPIO_UNDEF, + }, + .soc_sata_led = { + .hdd2_fail_led = 32, + .hdd1_fail_led = 31, + }, + .model = { + .model_id_0 = 55, + .model_id_1 = 56, + .model_id_2 = 57, + .model_id_3 = 58, + }, + .fan = { + .fan_1 = 63, + .fan_2 = 64, + .fan_3 = 65, + .fan_fail = 38, + .fan_fail_2 = GPIO_UNDEF, + .fan_fail_3 = GPIO_UNDEF, + }, + .hdd_pm = { + .hdd1_pm = 37, + .hdd2_pm = 62, + .hdd3_pm = GPIO_UNDEF, + .hdd4_pm = GPIO_UNDEF, + }, + .rack = { + .buzzer_mute_req = GPIO_UNDEF, + .buzzer_mute_ack = GPIO_UNDEF, + .rps1_on = GPIO_UNDEF, + .rps2_on = GPIO_UNDEF, + }, + .multi_bay = { + .inter_lock = GPIO_UNDEF, + }, + .status = { + .power_led = GPIO_UNDEF, + .alarm_led = GPIO_UNDEF, + }, + .usb = { + .usb_power = GPIO_UNDEF, + }, + }; + + *global_gpio = gpio_214se; +} + +static void +Armada_370_414slim_GPIO_init(SYNO_ARMADA_GENERIC_GPIO *global_gpio) +{ + SYNO_ARMADA_GENERIC_GPIO gpio_414slim = { + .ext_sata_led = { + .hdd1_led_0 = GPIO_UNDEF, + .hdd1_led_1 = GPIO_UNDEF, + .hdd2_led_0 = GPIO_UNDEF, + .hdd2_led_1 = GPIO_UNDEF, + .hdd3_led_0 = GPIO_UNDEF, + .hdd3_led_1 = GPIO_UNDEF, + .hdd4_led_0 = GPIO_UNDEF, + .hdd4_led_1 = GPIO_UNDEF, + .hdd5_led_0 = GPIO_UNDEF, + .hdd5_led_1 = GPIO_UNDEF, + .hdd_led_mask = 39, + }, + .soc_sata_led = { + .hdd2_fail_led = GPIO_UNDEF, + .hdd1_fail_led = GPIO_UNDEF, + }, + .model = { + .model_id_0 = 55, + .model_id_1 = 56, + .model_id_2 = 57, + .model_id_3 = 58, + }, + .fan = { + .fan_1 = 65, + .fan_2 = 64, + .fan_3 = 63, + .fan_fail = 38, + .fan_fail_2 = GPIO_UNDEF, + .fan_fail_3 = GPIO_UNDEF, + }, + .hdd_pm = { + .hdd1_pm = GPIO_UNDEF, + .hdd2_pm = GPIO_UNDEF, + .hdd3_pm = GPIO_UNDEF, + .hdd4_pm = GPIO_UNDEF, + }, + .rack = { + .buzzer_mute_req = GPIO_UNDEF, + .buzzer_mute_ack = GPIO_UNDEF, + .rps1_on = GPIO_UNDEF, + .rps2_on = GPIO_UNDEF, + }, + .multi_bay = { + .inter_lock = GPIO_UNDEF, + }, + .status = { + .power_led = GPIO_UNDEF, + .alarm_led = GPIO_UNDEF, + }, + .usb = { + .usb_power = 44, + }, + }; + + *global_gpio = gpio_414slim; +} +static void +ARMADA_default_GPIO_init(SYNO_ARMADA_GENERIC_GPIO *global_gpio) +{ + SYNO_ARMADA_GENERIC_GPIO gpio_default = { + .ext_sata_led = { + .hdd1_led_0 = GPIO_UNDEF, + .hdd1_led_1 = GPIO_UNDEF, + .hdd2_led_0 = GPIO_UNDEF, + .hdd2_led_1 = GPIO_UNDEF, + .hdd3_led_0 = GPIO_UNDEF, + .hdd3_led_1 = GPIO_UNDEF, + .hdd4_led_0 = GPIO_UNDEF, + .hdd4_led_1 = GPIO_UNDEF, + .hdd5_led_0 = GPIO_UNDEF, + .hdd5_led_1 = GPIO_UNDEF, + .hdd_led_mask = GPIO_UNDEF, + }, + .soc_sata_led = { + .hdd2_fail_led = GPIO_UNDEF, + .hdd1_fail_led = GPIO_UNDEF, + }, + .model = { + .model_id_0 = GPIO_UNDEF, + .model_id_1 = GPIO_UNDEF, + .model_id_2 = GPIO_UNDEF, + .model_id_3 = GPIO_UNDEF, + }, + .fan = { + .fan_1 = GPIO_UNDEF, + .fan_2 = GPIO_UNDEF, + .fan_3 = GPIO_UNDEF, + .fan_fail = GPIO_UNDEF, + .fan_fail_2 = GPIO_UNDEF, + .fan_fail_3 = GPIO_UNDEF, + }, + .hdd_pm = { + .hdd1_pm = GPIO_UNDEF, + .hdd2_pm = GPIO_UNDEF, + .hdd3_pm = GPIO_UNDEF, + .hdd4_pm = GPIO_UNDEF, + }, + .rack = { + .buzzer_mute_req = GPIO_UNDEF, + .buzzer_mute_ack = GPIO_UNDEF, + .rps1_on = GPIO_UNDEF, + .rps2_on = GPIO_UNDEF, + }, + .multi_bay = { + .inter_lock = GPIO_UNDEF, + }, + .status = { + .power_led = GPIO_UNDEF, + .alarm_led = GPIO_UNDEF, + }, + .usb = { + .usb_power = GPIO_UNDEF, + }, + }; + + *global_gpio = gpio_default; +} +void synology_gpio_init(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + switch(boardId) { + case SYNO_DS213j_ID: + Armada_370_213j_GPIO_init(&generic_gpio); + printk("Synology Armada370 1, 2 bay GPIO Init\n"); + break; + case SYNO_US3_ID: + Armada_370_us3_GPIO_init(&generic_gpio); + printk("Synology Armada370 US GPIO Init\n"); + break; + case SYNO_RS214_ID: + Armada_370_rs214_GPIO_init(&generic_gpio); + printk("Synology Armada370 RS214 GPIO Init\n"); + break; + case SYNO_DS214se_ID: + Armada_370_214se_GPIO_init(&generic_gpio); + printk("Synology Armada370 DS214se GPIO Init\n"); + break; + case SYNO_DS414slim_ID: + Armada_370_414slim_GPIO_init(&generic_gpio); + printk("Synology Armada370 DS414slim GPIO Init\n"); + break; + + default: + printk("%s BoardID not match\n", __FUNCTION__); + ARMADA_default_GPIO_init(&generic_gpio); + break; + } +} +#endif /* CONFIG_SYNO_ARMADA */ diff --git a/arch/arm/mach-armada370/synology-platform.c b/arch/arm/mach-armada370/synology-platform.c new file mode 100755 index 000000000..b90abf09f --- /dev/null +++ b/arch/arm/mach-armada370/synology-platform.c @@ -0,0 +1,17 @@ +/* Copyright (c) 2013 Synology Inc. */ + +#include + +#include +#include +#include +#include +#include +#include + +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "mvOs.h" + + diff --git a/arch/arm/mach-armada370/sysmap.c b/arch/arm/mach-armada370/sysmap.c new file mode 100755 index 000000000..6f6856a11 --- /dev/null +++ b/arch/arm/mach-armada370/sysmap.c @@ -0,0 +1,174 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +#include "mvSysHwConfig.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "boardEnv/mvBoardEnvLib.h" +#include + +/* for putstr */ +/* #include */ + +MV_CPU_DEC_WIN* mv_sys_map(void); + +#if defined(CONFIG_MV_INCLUDE_CESA) +u32 mv_crypto_phys_base_get(u8 chan); +u32 mv_crypto_virt_base_get(u8 chan); +#endif + +struct map_desc MEM_TABLE[] = { + /* no use for pex mem remap */ + { INTER_REGS_BASE, __phys_to_pfn(INTER_REGS_PHYS_BASE), SZ_1M, MT_DEVICE}, + { PEX0_IO_VIRT_BASE, __phys_to_pfn(PEX0_IO_PHYS_BASE), PEX0_IO_SIZE, MT_DEVICE}, + { PEX1_IO_VIRT_BASE, __phys_to_pfn(PEX1_IO_PHYS_BASE), PEX1_IO_SIZE, MT_DEVICE}, +#ifdef MV_INCLUDE_LEGACY_NAND + { LEGACY_NAND_VIRT_BASE, __phys_to_pfn(LEGACY_NAND_PHYS_BASE), LEGACY_NAND_SIZE, MT_DEVICE}, +#endif + { SPI_CS0_VIRT_BASE, __phys_to_pfn(SPI_CS0_PHYS_BASE), SPI_CS0_SIZE, MT_DEVICE}, + { CRYPT_ENG_VIRT_BASE(0), __phys_to_pfn(CRYPT_ENG_PHYS_BASE(0)), CRYPT_ENG_SIZE, MT_DEVICE} +}; + +MV_CPU_DEC_WIN SYSMAP_ARMADA_370[] = { + /* base low base high size WinNum enable */ + {{SDRAM_CS0_BASE, 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS0 */ + {{SDRAM_CS1_BASE, 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS1 */ + {{SDRAM_CS2_BASE, 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS2 */ + {{SDRAM_CS3_BASE, 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, DIS}, /* SDRAM_CS3 */ + {{DEVICE_CS0_PHYS_BASE, 0, DEVICE_CS0_SIZE, }, 0x5, EN}, /* DEVICE_CS0 */ + {{DEVICE_CS1_PHYS_BASE, 0, DEVICE_CS1_SIZE, }, TBL_UNUSED, DIS}, /* DEVICE_CS1 */ + {{DEVICE_CS2_PHYS_BASE, 0, DEVICE_CS2_SIZE, }, TBL_UNUSED, DIS}, /* DEVICE_CS2 */ + {{DEVICE_CS3_PHYS_BASE, 0, DEVICE_CS3_SIZE, }, TBL_UNUSED, DIS}, /* DEVICE_CS3 */ + {{PEX0_MEM_PHYS_BASE, 0, PEX0_MEM_SIZE }, 0x0, EN}, /* PEX0_MEM */ + {{PEX0_IO_PHYS_BASE, 0, PEX0_IO_SIZE }, 0x1, EN}, /* PEX0_IO */ + {{PEX1_MEM_PHYS_BASE, 0, PEX1_MEM_SIZE }, 0x2, EN}, /* PEX1_MEM */ + {{PEX1_IO_PHYS_BASE, 0, PEX1_IO_SIZE }, 0x3, EN}, /* PEX1_IO */ + {{INTER_REGS_PHYS_BASE, 0, INTER_REGS_SIZE }, 0x14, EN}, /* INTER_REGS */ + {{UART_REGS_BASE, 0, UART_SIZE }, TBL_UNUSED, DIS}, /* DMA_UART */ + {{SPI_CS0_PHYS_BASE, 0, SPI_CS0_SIZE }, 0x6, EN}, /* SPI_CS0 */ + {{TBL_UNUSED, 0, TBL_UNUSED, }, TBL_UNUSED, DIS}, /* SPI_CS1 */ + {{TBL_UNUSED, 0, TBL_UNUSED, }, TBL_UNUSED, DIS}, /* SPI_CS2 */ + {{TBL_UNUSED, 0, TBL_UNUSED, }, TBL_UNUSED, DIS}, /* SPI_CS3 */ + {{TBL_UNUSED, 0, TBL_UNUSED, }, TBL_UNUSED, DIS}, /* SPI_CS4 */ + {{TBL_UNUSED, 0, TBL_UNUSED, }, TBL_UNUSED, DIS}, /* SPI_CS5 */ + {{TBL_UNUSED, 0, TBL_UNUSED, }, TBL_UNUSED, DIS}, /* SPI_CS6 */ + {{TBL_UNUSED, 0, TBL_UNUSED, }, TBL_UNUSED, DIS}, /* SPI_CS7 */ + {{BOOTROM_PHYS_BASE, 0, DEVICE_BOOTCS_SIZE }, 0x6, DIS}, /* BOOTROM */ + {{DEVICE_BOOTCS_PHYS_BASE, 0, DEVICE_BOOTCS_SIZE }, 0x7, EN}, /* DEV_BOOCS */ + {{PMU_SCRATCH_PHYS_BASE, 0, PMU_SCRATCH_SIZE }, TBL_UNUSED, DIS}, /* PMU SCRATCHPAD */ + {{CRYPT_ENG_PHYS_BASE(0), 0, CRYPT_ENG_SIZE }, 0x8, EN}, /* CRYPT0_ENG */ + {{TBL_TERM, TBL_TERM, TBL_TERM }, TBL_TERM, TBL_TERM} +}; + + +MV_CPU_DEC_WIN* mv_sys_map(void) +{ + switch(mvBoardIdGet()) { + case DB_88F6710_BP_ID: + case RD_88F6710_ID: +#if defined(CONFIG_SYNO_ARMADA_ARCH) + case SYNO_DS213j_ID: + case SYNO_US3_ID: + case SYNO_RS214_ID: + case SYNO_DS214se_ID: + case SYNO_DS414slim_ID: +#endif + return SYSMAP_ARMADA_370; + default: + printk("ERROR: can't find system address map\n"); + return NULL; + } +} + + +#if defined(CONFIG_MV_INCLUDE_CESA) +u32 mv_crypto_phys_base_get(u8 chan) +{ + return CRYPT_ENG_PHYS_BASE(chan); +} +u32 mv_crypto_virt_base_get(u8 chan) +{ + return CRYPT_ENG_VIRT_BASE(chan); +} +#endif + +void __init axp_map_io(void) +{ + iotable_init(MEM_TABLE, ARRAY_SIZE(MEM_TABLE)); +} + +#if 0 +static u32 mv_pci_mem_base[] = +{ + PEX0_MEM_PHYS_BASE, + PEX1_MEM_PHYS_BASE +}; + +static u32 mv_pci_mem_size[] = +{ + PEX0_MEM_SIZE, + PEX1_MEM_SIZE +}; + +static u32 mv_pci_io_base[] = +{ + PEX0_IO_PHYS_BASE, + PEX1_IO_PHYS_BASE +}; + +static u32 mv_pci_io_size[] = +{ + PEX0_IO_SIZE, + PEX1_IO_SIZE +}; + +static MV_TARGET mv_pci_io_target[] = +{ + PEX0_IO, + PEX1_IO +}; + +u32 mv_pci_mem_base_get(int ifNum) +{ + return mv_pci_mem_base[ifNum]; +} + +u32 mv_pci_mem_size_get(int ifNum) +{ + return mv_pci_mem_size[ifNum]; +} + +u32 mv_pci_io_base_get(int ifNum) +{ + return mv_pci_io_base[ifNum]; +} + +u32 mv_pci_io_size_get(int ifNum) +{ + return mv_pci_io_size[ifNum]; +} + +MV_TARGET mv_pci_io_target_get(int ifNum) +{ + return mv_pci_io_target[ifNum]; +} + +int mv_is_pci_io_mapped(int ifNum) +{ + /* PCIe IO windows are enabled for both I/F */ + return 1; +} +#endif diff --git a/arch/arm/mach-armada370/time.c b/arch/arm/mach-armada370/time.c new file mode 100755 index 000000000..c251e68b2 --- /dev/null +++ b/arch/arm/mach-armada370/time.c @@ -0,0 +1,244 @@ +/* + * arch/arm/mach-armadaxp/time.c + * + * Marvell Aurora SoC timer handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Timer 0 is used as free-running clocksource, while timer 1 is + * used as clock_event_device. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "boardEnv/mvBoardEnvLib.h" +#include "cpu/mvCpu.h" + +extern void axp_irq_mask(struct irq_data *d); +extern void axp_irq_unmask(struct irq_data *d); + +#define TIMER_CTRL (MV_CNTMR_REGS_OFFSET + 0x0000) +#define TIMER0_EN 0x0001 +#define TIMER0_RELOAD_EN 0x0002 +#define TIMER1_EN 0x0004 +#define TIMER1_RELOAD_EN 0x0008 +#define TIMER0_RELOAD (MV_CNTMR_REGS_OFFSET + 0x0010) +#define TIMER0_VAL (MV_CNTMR_REGS_OFFSET + 0x0014) +#define TIMER1_RELOAD (MV_CNTMR_REGS_OFFSET + 0x0018) +#define TIMER1_VAL (MV_CNTMR_REGS_OFFSET + 0x001c) +#define TIMER_WD_RELOAD (MV_CNTMR_REGS_OFFSET + 0x0020) +#define TIMER_WD_VAL (MV_CNTMR_REGS_OFFSET + 0x0024) +#define TIMER_CAUSE (MV_CNTMR_REGS_OFFSET + 0x0028) +#define INT_TIMER0_CLR ~(1 << 0) +#define INT_TIMER1_CLR ~(1 << 8) + +#define LCL_TIMER_BASE (0x21000 | 0x40) +#define LCL_TIMER_CTRL (LCL_TIMER_BASE + 0x0000) +#define LCL_TIMER0_EN 0x0001 +#define LCL_TIMER0_RELOAD_EN 0x0002 +#define LCL_TIMER1_EN 0x0004 +#define LCL_TIMER1_RELOAD_EN 0x0008 +#define LCL_TIMER0_RELOAD (LCL_TIMER_BASE + 0x0010) +#define LCL_TIMER0_VAL (LCL_TIMER_BASE + 0x0014) +#define LCL_TIMER1_RELOAD (LCL_TIMER_BASE + 0x0018) +#define LCL_TIMER1_VAL (LCL_TIMER_BASE + 0x001c) +#define LCL_TIMER_WD_RELOAD (LCL_TIMER_BASE + 0x0020) +#define LCL_TIMER_WD_VAL (LCL_TIMER_BASE + 0x0024) +#define LCL_TIMER_CAUSE (LCL_TIMER_BASE + 0x0028) +#define LCL_INT_TIMER0_CLR ~(1 << 0) +#define LCL_INT_TIMER1_CLR ~(1 << 8) + +#define BRIDGE_CAUSE (MV_MBUS_REGS_OFFSET | 0x0260) +#define BRIDGE_INT_TIMER0 (1 << 24) +#define BRIDGE_INT_TIMER1 (1 << 25) +#define BRIDGE_MASK (MV_MBUS_REGS_OFFSET | 0x10c4) + +static DEFINE_CLOCK_DATA(cd); + +/* + * Number of timer ticks per jiffy. + */ +static u32 ticks_per_jiffy; + +/* + * Clocksource handling. + */ +static cycle_t axp_clksrc_read(struct clocksource *cs) +{ + return (0xffffffff - MV_REG_READ(TIMER0_VAL)); +} + +static struct clocksource axp_clksrc = { + .name = "armada370_clocksource", + .shift = 20, + .rating = 300, + .read = axp_clksrc_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/* + * Clockevent handling. + */ +int axp_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) +{ + unsigned long flags; + u32 u; + + if (delta == 0) + return -ETIME; + + local_irq_save(flags); + + /* Clear and enable clockevent timer interrupt */ + MV_REG_WRITE(LCL_TIMER_CAUSE, LCL_INT_TIMER0_CLR); + /*axp_irq_unmask(IRQ_LOCALTIMER);*/ + axp_irq_unmask(irq_get_irq_data(IRQ_LOCALTIMER)); + + /* Setup new clockevent timer value */ + MV_REG_WRITE(LCL_TIMER0_VAL, delta); + + /* Enable the timer */ + u = MV_REG_READ(LCL_TIMER_CTRL); + u = (u & ~LCL_TIMER0_RELOAD_EN) | LCL_TIMER0_EN; + MV_REG_WRITE(LCL_TIMER_CTRL, u); + + local_irq_restore(flags); + + return 0; +} + +static void axp_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) +{ + unsigned long flags; + u32 u; + + local_irq_save(flags); + + if (mode == CLOCK_EVT_MODE_PERIODIC) { + /* Setup timer to fire at 1/HZ intervals */ + MV_REG_WRITE(LCL_TIMER0_RELOAD, (ticks_per_jiffy - 1)); + MV_REG_WRITE(LCL_TIMER0_VAL, (ticks_per_jiffy - 1)); + + /* Enable timer interrupt */ + /*axp_irq_unmask(IRQ_LOCALTIMER);*/ + axp_irq_unmask(irq_get_irq_data(IRQ_LOCALTIMER)); + + /* Enable timer */ + u = MV_REG_READ(LCL_TIMER_CTRL); + u |= (LCL_TIMER0_EN | LCL_TIMER0_RELOAD_EN); + MV_REG_WRITE(LCL_TIMER_CTRL, u); + } else { + /* Disable timer */ + u = MV_REG_READ(LCL_TIMER_CTRL); + u &= ~LCL_TIMER0_EN; + MV_REG_WRITE(LCL_TIMER_CTRL, u); + /* Disable timer interrupt */ + axp_irq_mask(irq_get_irq_data(IRQ_LOCALTIMER)); + + /* ACK pending timer interrupt */ + MV_REG_WRITE(LCL_TIMER_CAUSE, LCL_INT_TIMER0_CLR); + } + + local_irq_restore(flags); +} + +static struct clock_event_device axp_clkevt; +static irqreturn_t axp_timer_interrupt(int irq, void *dev_id) +{ + /* ACK timer interrupt and call event handler */ + MV_REG_WRITE(LCL_TIMER_CAUSE, LCL_INT_TIMER0_CLR); + axp_clkevt.event_handler(&axp_clkevt); + + return IRQ_HANDLED; +} + +static struct irqaction axp_timer_irq = { + .name = "armada370_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = axp_timer_interrupt +}; + + +/* + * Setup the local clock events for a CPU. + */ +void __cpuinit mv_timer_setup(struct clock_event_device *clk, unsigned int fabric_clk) +{ + unsigned int cpu = smp_processor_id(); + + clk->features = (CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC), + clk->shift = 32, + clk->rating = 300, + clk->set_next_event = axp_clkevt_next_event, + clk->set_mode = axp_clkevt_mode, + clk->cpumask = cpumask_of(cpu); + clk->mult = div_sc(fabric_clk, NSEC_PER_SEC, clk->shift); + clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); + clk->min_delta_ns = clockevent_delta2ns(0x1, clk); +} + +unsigned long long notrace sched_clock(void) +{ + u32 cyc = ~MV_REG_READ(TIMER0_VAL); + return cyc_to_sched_clock(&cd, cyc, (u32)~0); +} + +static void notrace a370_update_sched_clock(void) +{ + u32 cyc = ~MV_REG_READ(TIMER0_VAL); + update_sched_clock(&cd, cyc, (u32)~0); +} + +static void __init setup_sched_clock(unsigned long tclk) +{ + init_sched_clock(&cd, a370_update_sched_clock, 32, tclk); +} + +void __init axp_time_init(unsigned int fabric_clk) +{ + u32 u; + + printk("a370_time_init\n"); + + ticks_per_jiffy = (fabric_clk + HZ/2) / HZ; + + setup_sched_clock(fabric_clk); + + /* Setup free-running clocksource timer (interrupts disabled) */ + MV_REG_WRITE(TIMER0_VAL, 0xffffffff); + MV_REG_WRITE(TIMER0_RELOAD, 0xffffffff); + u = MV_REG_READ(BRIDGE_MASK); + u &= ~BRIDGE_INT_TIMER0; + MV_REG_WRITE(BRIDGE_MASK, u); + u = MV_REG_READ(TIMER_CTRL); + u |= (TIMER0_EN | TIMER0_RELOAD_EN); + MV_REG_WRITE(TIMER_CTRL, u); + axp_clksrc.mult = clocksource_hz2mult(fabric_clk, axp_clksrc.shift); + clocksource_register(&axp_clksrc); + + /* Setup clockevent timer (interrupt-driven) */ + axp_clkevt.name = "armada370_tick"; + axp_clkevt.irq = IRQ_LOCALTIMER; + mv_timer_setup(&axp_clkevt, fabric_clk); + setup_irq(IRQ_LOCALTIMER, &axp_timer_irq); + clockevents_register_device(&axp_clkevt); +} + +static void axp_timer_init(void) +{ + axp_time_init(mvCpuL2ClkGet()); +} + +struct sys_timer axp_timer = { + .init = axp_timer_init, +}; diff --git a/arch/arm/mach-armada370/usb.c b/arch/arm/mach-armada370/usb.c new file mode 100755 index 000000000..7492c3fb5 --- /dev/null +++ b/arch/arm/mach-armada370/usb.c @@ -0,0 +1,158 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ + +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mvCommon.h" +#include "mvDebug.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysUsbApi.h" +#include "usb/mvUsbRegs.h" +#include "usb/mvUsb.h" + +u32 mvIsUsbHost = 1; + +#define MV_USB_DMA_MASK 0xffffffff +#define MAX_USB_PORTS 2 + +static char usb_dev_name[] = "mv_udc"; +static char usb_host_name[] = "ehci_marvell"; +static char usb_bus_name[] = "platform"; + + +static void mv_usb_release(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + /* normally not freed */ + printk("mv_usb_release\n"); + + kfree(pdev->resource); + kfree(pdev->dev.dma_mask); + kfree(pdev); +} + + +static int __init mv_usb_init(void) +{ + int status, dev, num, isHost; + char* name_ptr; + struct platform_device* mv_usb_dev_ptr; + int irq_num[2] = { IRQ_AURORA_USB0, + IRQ_AURORA_USB1}; + + num = mvCtrlUsbMaxGet(); + if (num > MAX_USB_PORTS) { + printk("WARNING: Limited USB ports number to %d\n", MAX_USB_PORTS); + num = MAX_USB_PORTS; + } + + for(dev=0; devname = name_ptr; + mv_usb_dev_ptr->id = dev; + + mv_usb_dev_ptr->num_resources = 2; + + mv_usb_dev_ptr->resource = (struct resource*)kmalloc(2*sizeof(struct resource), GFP_KERNEL); + if(mv_usb_dev_ptr->resource == NULL) + { + printk("Can't allocate 2 resource structure - %d bytes\n", + 2*sizeof(struct resource) ); + kfree(mv_usb_dev_ptr); + return 1; + } + memset(mv_usb_dev_ptr->resource, 0, 2*sizeof(struct resource)); + + mv_usb_dev_ptr->resource[0].start = + ( INTER_REGS_BASE | MV_USB_CORE_CAP_LENGTH_REG(dev)); + mv_usb_dev_ptr->resource[0].end = + ((INTER_REGS_BASE | MV_USB_CORE_CAP_LENGTH_REG(dev)) + 4096); + mv_usb_dev_ptr->resource[0].flags = IORESOURCE_DMA; + + mv_usb_dev_ptr->resource[1].start = irq_num[dev]; + mv_usb_dev_ptr->resource[1].flags = IORESOURCE_IRQ; + + mv_usb_dev_ptr->dev.dma_mask = kmalloc(sizeof(u64), GFP_KERNEL); + *mv_usb_dev_ptr->dev.dma_mask = MV_USB_DMA_MASK; + + mv_usb_dev_ptr->dev.coherent_dma_mask = ~0; + mv_usb_dev_ptr->dev.release = mv_usb_release; + dev_set_name(&mv_usb_dev_ptr->dev, "%s", usb_bus_name); + + printk("Marvell USB %s controller #%d: %p\n", + isHost ? "EHCI Host" : "Gadget", dev, mv_usb_dev_ptr); + + status = platform_device_register(mv_usb_dev_ptr); + if (status) + { + printk("Can't register Marvell USB EHCI controller #%d, status=%d\n", + dev, status); + return status; + } + } + return 0; +} + +subsys_initcall(mv_usb_init); diff --git a/arch/arm/mach-armadaxp/Kconfig b/arch/arm/mach-armadaxp/Kconfig new file mode 100755 index 000000000..7ea790456 --- /dev/null +++ b/arch/arm/mach-armadaxp/Kconfig @@ -0,0 +1,112 @@ +if ARCH_ARMADA_XP + +config MV_HAL_RULES_PATH + string "path of the mvRules.mk file for HAL drivers" + default "arch/arm/mach-armadaxp/mv_hal_support/mvRules.mk" + ---help--- + +#source "arch/arm/plat-orion/mv_hal_drivers/Kconfig" + +menu "Marvell Armada Options" + +config ARMADA_XP + bool "Armada XP SoC Family" + default y + +choice + prompt "Armada XP Chip revision" + depends on ARMADA_XP + default ARMADA_XP_REV_B0 + +config ARMADA_XP_REV_Z1 + bool "MV88F78x30 and MV88F78x60 Z1 SoC devices" + select ARMADA_XP_ERRATA_SMI_1 +# select ARMADA_XP_DEEP_IDLE_L2_WA if CACHE_AURORA_L2 +# select ARMADA_XP_DEEP_IDLE_UNMASK_INTS_WA + select SHEEVA_ERRATA_ARM_CPU_4742 + select SHEEVA_ERRATA_ARM_CPU_4786 if (ARM_THUMB && VFP) +# select SHEEVA_ERRATA_ARM_CPU_5315 + select SHEEVA_ERRATA_ARM_CPU_4413 + select SHEEVA_ERRATA_ARM_CPU_4659 + select SHEEVA_ERRATA_ARM_CPU_5114 if (CPU_SHEEVA_PJ4B_V6 && AURORA_IO_CACHE_COHERENCY) + select SHEEVA_ERRATA_ARM_CPU_4611 +# select SHEEVA_ERRATA_ARM_CPU_4948 + select SHEEVA_ERRATA_ARM_CPU_PMU_RESET + select SHEEVA_ERRATA_ARM_CPU_BTS61 if (SMP || AURORA_IO_CACHE_COHERENCY) + ---help--- + Choosing this option will generate a linux kernel for the + MV78x30 and MV78x60 devices with revision Z1 + +config ARMADA_XP_REV_A0 + bool "MV88F78x30 and MV88F78x60 A0 SoC devices" + ---help--- + Choosing this option will generate a linux kernel for the + MV78x30 and MV78x60 devices with revision A0 + +config ARMADA_XP_REV_B0 + bool "MV88F78x30 and MV88F78x60 B0 SoC devices" + ---help--- + Choosing this option will generate a linux kernel for the + MV78x30 and MV78x60 devices with revision B0 + +endchoice + +config ARMADA_XP_A0_WITH_B0 + bool "Armada XP A0 and B0 Runtime Support" + default n + depends on ARMADA_XP_REV_B0 + ---help--- + Choosing this option will generate a linux kernel supporting both A0 and B0 revisions + Selection is done at runtime based on silicon revision. + Due to performance impact, it is recommended to disable this option in case of B0 only. + + +config MACH_ARMADA_XP_DB + bool "Marvell Armada XP Development Board" + default y + help + +config MACH_ARMADA_XP_GP + bool "Marvell Armada XP General Purpose Board" + default y + help + +config MACH_ARMADA_XP_RDSRV + bool "Marvell Armada XP Server Board" + default y + help + +config MACH_ARMADA_XP_RD_NAS + bool "Marvell Armada XP NAS RD Board" + default y + help + +config MACH_ARMADA_XP_FPGA + bool "Marvell Armada XP FPGA Board" + depends on !MACH_ARMADA_XP_DB && !MACH_ARMADA_XP_RDSRV + default y + help + +config CFU_DRAM_BYPASS + bool "Bypass CFU to DRAM via Punit" + default n + help + +config ARMADA_XP_SPARSEMEM + bool "Use sparse memory model" + select ARCH_SPARSEMEM_ENABLE + default n + +config ARMADAXP_USE_IRQ_INTERRUPT_ACK + bool "Use Interrupt Ack register to detect pending interrupts" + default n + help + +config ARMADA_XP_BTNS_DEVICE + bool "Add support for ArmadaXP buttons driver for GPIOs" + default n + help + +endmenu + +endif diff --git a/arch/arm/mach-armadaxp/Makefile b/arch/arm/mach-armadaxp/Makefile new file mode 100755 index 000000000..4aad6ced5 --- /dev/null +++ b/arch/arm/mach-armadaxp/Makefile @@ -0,0 +1,159 @@ +#******************************************************************************* +# Marvell GPL License Option +# +# If you received this File from Marvell, you may opt to use, redistribute and/or +# modify this File in accordance with the terms and conditions of the General +# Public License Version 2, June 1991 (the "GPL License"), a copy of which is +# available along with the File in the license.txt file or by writing to the Free +# Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +# on the worldwide web at http://www.gnu.org/licenses/gpl.txt. +# +# THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +# DISCLAIMED. The GPL License provides additional details about this warranty +# disclaimer. +#*******************************************************************************/ +include $(srctree)/arch/arm/mach-armadaxp/config/mvRules.mk + + +# Objects list +COMMON_OBJS = $(COMMON_DIR)/mvDebug.o $(COMMON_DIR)/mvCommon.o $(COMMON_DIR)/mvStack.o $(COMMON_DIR)/mvList.o $(COMMON_DIR)/mvIpc.o + +OSSERVICES_OBJS = $(OSSERV_DIR)/mvOs.o + +HAL_OBJS = $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o $(HAL_IF_DIR)/mvSysCntmr.o \ + $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_DRAM_DIR)/mvDramIf.o \ + $(HAL_IF_DIR)/mvSysDdr.o +# $(HAL_DRAM_SPD_DIR)/mvSpd.o + +KW_FAM_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvSpec.o $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o \ + $(SOC_SYS_DIR)/mvAhbToMbus.o $(SOC_SYS_DIR)/mvCpuIf.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o + +QD_OBJS = $(HAL_QD_DIR)/src/driver/gtDrvConfig.o $(HAL_QD_DIR)/src/driver/gtDrvEvents.o \ + $(HAL_QD_DIR)/src/driver/gtHwCntl.o $(HAL_QD_DIR)/src/platform/gtMiiSmiIf.o \ + $(HAL_QD_DIR)/src/platform/platformDeps.o $(HAL_QD_DIR)/src/platform/gtSem.o \ + $(HAL_QD_DIR)/src/platform/gtDebug.o $(HAL_QD_DIR)/src/msapi/gtBrgFdb.o \ + $(HAL_QD_DIR)/src/msapi/gtBrgStp.o $(HAL_QD_DIR)/src/msapi/gtBrgVlan.o \ + $(HAL_QD_DIR)/src/msapi/gtEvents.o $(HAL_QD_DIR)/src/msapi/gtPortCtrl.o \ + $(HAL_QD_DIR)/src/msapi/gtPortStat.o $(HAL_QD_DIR)/src/msapi/gtPortStatus.o \ + $(HAL_QD_DIR)/src/msapi/gtQosMap.o $(HAL_QD_DIR)/src/msapi/gtPIRL.o \ + $(HAL_QD_DIR)/src/msapi/gtPhyCtrl.o $(HAL_QD_DIR)/src/msapi/gtPhyInt.o \ + $(HAL_QD_DIR)/src/msapi/gtSysConfig.o $(HAL_QD_DIR)/src/msapi/gtSysCtrl.o \ + $(HAL_QD_DIR)/src/msapi/gtVersion.o $(HAL_QD_DIR)/src/msapi/gtUtils.o \ + $(HAL_QD_DIR)/src/msapi/gtBrgVtu.o $(HAL_QD_DIR)/src/msapi/gtPortRmon.o \ + $(HAL_QD_DIR)/src/msapi/gtSysStatus.o $(HAL_QD_DIR)/src/msapi/gtPortRateCtrl.o\ + $(HAL_QD_DIR)/src/msapi/gtPortPav.o $(HAL_QD_DIR)/src/msapi/gtVct.o \ + $(HAL_QD_DIR)/src/msapi/gtPIRL2.o $(HAL_QD_DIR)/src/msapi/gtCCPVT.o \ + $(HAL_QD_DIR)/src/msapi/gtPCSCtrl.o + +LSP_OBJS = core.o irq.o time.o leds.o sysmap.o export.o clock.o +ifeq ($(CONFIG_SYNO_ARMADA_ARCH),y) +LSP_OBJS += synology-gpio.o +endif + +obj-y := armadaxp.o +armadaxp-objs :=$(LSP_OBJS) $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) \ + $(KW_FAM_OBJS) + +armadaxp-$(CONFIG_MV_INCLUDE_SDIO) += $(HAL_SDMMC_DIR)/mvSdmmcAddrDec.o +armadaxp-$(CONFIG_MV_INCLUDE_XOR) += $(HAL_XOR_DIR)/mvXor.o $(HAL_XOR_DIR)/mvXorAddrDec.o \ + $(HAL_IF_DIR)/mvSysXor.o +armadaxp-$(CONFIG_MV_INCLUDE_PEX) += $(HAL_PEX_DIR)/mvPex.o \ + $(HAL_IF_DIR)/mvSysPex.o $(HAL_PEX_DIR)/mvPexAddrDec.o +armadaxp-$(CONFIG_MV_INCLUDE_PCI) += $(HAL_PCI_DIR)/mvPci.o $(HAL_IF_DIR)/mvSysPci.o +armadaxp-$(CONFIG_MV_INCLUDE_USB) += $(HAL_USB_DIR)/mvUsb.o $(HAL_USB_DIR)/mvUsbAddrDec.o \ + $(HAL_IF_DIR)/mvSysUsb.o +armadaxp-y += $(HAL_ETHPHY_DIR)/mvEthPhy.o $(HAL_IF_DIR)/mvSysEthPhy.o + +# Legacy Giga driver +ifeq ($(CONFIG_MV_ETH_LEGACY),y) +armadaxp-$(CONFIG_MV_ETH_LEGACY) += $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_ETH_GBE_DIR)/mvEthDebug.o \ + $(HAL_ETH_GBE_DIR)/mvEthAddrDec.o $(HAL_IF_DIR)/mvSysEth.o +endif + +# NETA Giga driver +ifeq ($(CONFIG_MV_ETH_NETA),y) +armadaxp-$(CONFIG_MV_ETH_NETA) += $(HAL_ETH_GBE_DIR)/mvNeta.o $(HAL_ETH_GBE_DIR)/mvNetaDebug.o \ + $(HAL_ETH_GBE_DIR)/mvNetaAddrDec.o $(HAL_IF_DIR)/mvSysNeta.o +armadaxp-$(CONFIG_MV_ETH_PNC) += $(HAL_ETH_PNC_DIR)/mvTcam.o $(HAL_ETH_PNC_DIR)/mvPncAging.o \ + $(HAL_ETH_PNC_DIR)/mvPnc.o $(HAL_ETH_PNC_DIR)/mvPncLb.o +armadaxp-$(CONFIG_MV_ETH_PNC_L3_FLOW) += $(HAL_ETH_PNC_DIR)/mvPncRxq.o +armadaxp-$(CONFIG_MV_ETH_PNC_WOL) += $(HAL_ETH_PNC_DIR)/mvPncWol.o +armadaxp-$(CONFIG_MV_ETH_BM) += $(HAL_ETH_BM_DIR)/mvBm.o +armadaxp-$(CONFIG_MV_ETH_PMT) += $(HAL_ETH_PMT_DIR)/mvPmt.o +armadaxp-$(CONFIG_MV_ETH_HWF) += $(HAL_ETH_GBE_DIR)/mvHwf.o +endif + +armadaxp-$(CONFIG_MV_INCLUDE_CESA) += $(HAL_CESA_DIR)/mvCesa.o $(HAL_CESA_DIR)/mvCesaDebug.o \ + $(HAL_CESA_DIR)/mvCesaAddrDec.o \ + $(HAL_CESA_DIR)/mvMD5.o $(HAL_CESA_DIR)/mvSHA1.o \ + $(HAL_CESA_DIR)/mvSHA256.o \ + $(HAL_CESA_AES_DIR)/mvAesAlg.o $(HAL_CESA_AES_DIR)/mvAesApi.o\ + $(HAL_IF_DIR)/mvSysCesa.o + +armadaxp-$(CONFIG_MV_INCLUDE_INTEG_SATA)+= $(HAL_IF_DIR)/mvSysSata.o $(HAL_SATA_DIR)/mvSataSoc.o \ + $(HAL_SATA_DIR)/mvSataAddrDec.o +armadaxp-$(CONFIG_MV_INCLUDE_SPI) += $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o \ + $(HAL_SFLASH_DIR)/mvSFlash.o $(HAL_IF_DIR)/mvSysSFlash.o \ + $(HAL_IF_DIR)/mvSysSpi.o +armadaxp-$(CONFIG_MV_INCLUDE_NFC) += $(HAL_NFC_DIR)/mvNfc.o +armadaxp-$(CONFIG_MV_INCLUDE_AUDIO) += $(HAL_AUDIO_DIR)/mvAudio.o $(HAL_IF_DIR)/mvSysAudio.o \ + $(HAL_AUDIO_DIR)/mvAudioAddrDec.o +armadaxp-$(CONFIG_MV_INCLUDE_TS) += $(HAL_TS_DIR)/mvTsu.o $(HAL_IF_DIR)/mvSysTs.o \ + $(HAL_TS_DIR)/mvTsuAddrDec.o +armadaxp-$(CONFIG_MV_CPU_PERF_CNTRS) += $(HAL_CPU_DIR)/mvCpuCntrs.o $(HAL_CPU_DIR)/pj4/mvPJ4Cntrs.o +armadaxp-$(CONFIG_MV_CPU_L2_PERF_CNTRS) += $(HAL_CPU_DIR)/mvCpuL2Cntrs.o + +obj-$(CONFIG_MV_INCLUDE_SWITCH) += $(QD_OBJS) + +# drivers part + +ifeq ($(CONFIG_MV_ETH_NETA),y) +obj-$(CONFIG_MV_ETH_PNC) += $(LSP_PNC_DIR)/pnc_sysfs.o +obj-$(CONFIG_MV_ETH_PNC_L3_FLOW) += $(LSP_PNC_DIR)/rxq_map_sysfs.o +obj-$(CONFIG_MV_ETH_BM) += $(LSP_BM_DIR)/bm_sysfs.o $(LSP_BM_DIR)/mv_eth_bm.o +obj-$(CONFIG_MV_ETH_PNC_WOL) += $(LSP_PNC_DIR)/wol_sysfs.o +obj-$(CONFIG_MV_ETH_PMT) += $(LSP_PMT_DIR)/pmt_sysfs.o +obj-$(CONFIG_MV_ETH_HWF) += $(LSP_HWF_DIR)/hwf_sysfs.o +ifndef CONFIG_MV_ETH_BM_CPU +obj-$(CONFIG_MV_ETH_HWF) += $(LSP_HWF_DIR)/hwf_bm.o +endif +obj-$(CONFIG_MV_ETH_L2FW) += $(LSP_L2FW_DIR)/l2fw_sysfs.o $(LSP_L2FW_DIR)/mv_eth_l2fw.o +obj-$(CONFIG_MV_ETH_L2SEC) += $(LSP_L2FW_DIR)/mv_eth_l2sec.o +endif + +obj-$(CONFIG_MV_INCLUDE_GIG_ETH) += $(LSP_PHY_DIR)/phy_sysfs.o +obj-$(CONFIG_ERROR_HANDLING) += $(LSP_ERR_DIR)/mv_error.o + +obj-$(CONFIG_MV_USE_XOR_ENGINE) += $(PLAT_DRIVERS)/mv_xor/ +obj-$(CONFIG_MV_CESA) += $(PLAT_DRIVERS)/mv_cesa/ +obj-$(CONFIG_MV_IPC_DRIVER) += $(PLAT_DRIVERS)/mv_ipc/ +obj-$(CONFIG_MV_IPC_NET) += $(PLAT_DRIVERS)/mv_ipc_net/ +obj-$(CONFIG_GENERIC_GPIO) += $(PLAT_DRIVERS)/mv_btns/ +obj-$(CONFIG_GENERIC_GPIO) += $(PLAT_ORION_PATH)/gpio.o +obj-$(CONFIG_ARMADA_XP_BTNS_DEVICE) += btns_device.o +#obj-$(CONFIG_GENERIC_GPIO) += $(PLAT_DRIVERS)/mv_gpio/ +obj-$(CONFIG_MV_DBG_TRACE) += $(PLAT_DRIVERS)/mv_trace/ +obj-$(CONFIG_MV_INCLUDE_SWITCH) += $(LSP_SWITCH_DIR)/ +obj-$(CONFIG_SENSORS_ARMADA) += hwmon.o +# The rest of the drivers are compiled through the driver dir directly. + + +# LSP part +armadaxp-$(CONFIG_MV_INCLUDE_USB) += usb.o +armadaxp-$(CONFIG_MV_INCLUDE_PCI) += pci.o +armadaxp-$(CONFIG_MV_INCLUDE_PEX) += pex.o +armadaxp-$(CONFIG_FEROCEON_PROC) += $(PLAT_DRIVERS)/mv_proc/proc.o +armadaxp-$(CONFIG_SMP) += platsmp.o headsmp.o +armadaxp-$(CONFIG_MV_AMP_ENABLE) += $(SOC_ENV_DIR)/mvUnitMap.o +armadaxp-$(CONFIG_MV_AMP_ENABLE) += $(SOC_ENV_DIR)/mvSemaphore.o +armadaxp-$(CONFIG_PROC_FS) += dump_cp15_regs.o +obj-$(CONFIG_FB_DOVE_CLCD) += clcd.o +obj-$(CONFIG_PM) += pm.o + + diff --git a/arch/arm/mach-armadaxp/Makefile.boot b/arch/arm/mach-armadaxp/Makefile.boot new file mode 100755 index 000000000..0ef7d93cc --- /dev/null +++ b/arch/arm/mach-armadaxp/Makefile.boot @@ -0,0 +1,9 @@ +ifdef CONFIG_MV_AMP_ENABLE + zreladdr-y := $(CONFIG_MV_ZREL_ADDR) +params_phys-y := $(CONFIG_MV_PARAM_PHYS) +initrd_phys-y := $(CONFIG_MV_INITRD_PHYS) +else + zreladdr-y := 0x00008000 + params_phys-y := 0x00000100 + initrd_phys-y := 0x00800000 +endif diff --git a/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvLib.c b/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvLib.c new file mode 100755 index 000000000..a115659c5 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvLib.c @@ -0,0 +1,2713 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "cntmr/mvCntmr.h" +#include "gpp/mvGpp.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPex.h" +#include "device/mvDevice.h" +#include "neta/gbe/mvEthRegs.h" +#include "gpp/mvGppRegs.h" + +/* defines */ +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#define DB1(x) x +#else +#define DB(x) +#define DB1(x) +#endif + +#define CODE_IN_ROM MV_FALSE +#define CODE_IN_RAM MV_TRUE + +extern MV_BOARD_INFO *boardInfoTbl[]; +#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] + +/* Locals */ +static MV_DEV_CS_INFO *boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +MV_U32 tClkRate = -1; +extern MV_U8 mvDbDisableModuleDetection; + +MV_U32 gSerdesZ1AMode = 0; + +/******************************************************************************* +* mvBoardEnvInit - Init board +* +* DESCRIPTION: +* In this function the board environment take care of device bank +* initialization. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardEnvInit(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_U32 nandDev; + MV_U32 norDev; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); + return; + } + +#ifdef CONFIG_SYNO_ARMADA_ARCH + /* Board env already set in uboot, so we don't double set again */ +#else + nandDev = boardGetDevCSNum(0, BOARD_DEV_NAND_FLASH); + if (nandDev != 0xFFFFFFFF) { + /* Set NAND interface access parameters */ + nandDev = BOOT_CS; + MV_REG_WRITE(DEV_BANK_PARAM_REG(nandDev), BOARD_INFO(boardId)->nandFlashReadParams); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(nandDev), BOARD_INFO(boardId)->nandFlashWriteParams); + MV_REG_WRITE(DEV_NAND_CTRL_REG, BOARD_INFO(boardId)->nandFlashControl); + } + + norDev = boardGetDevCSNum(0, BOARD_DEV_NOR_FLASH); + if (norDev != 0xFFFFFFFF) { + /* Set NOR interface access parameters */ + MV_REG_WRITE(DEV_BANK_PARAM_REG(norDev), BOARD_INFO(boardId)->norFlashReadParams); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(norDev), BOARD_INFO(boardId)->norFlashWriteParams); + MV_REG_WRITE(DEV_BUS_SYNC_CTRL, 0x11); + } + + /* Set GPP Out value */ + MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); + MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValMid); + MV_REG_WRITE(GPP_DATA_OUT_REG(2), BOARD_INFO(boardId)->gppOutValHigh); + + /* set GPP polarity */ + mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); + mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValMid); + mvGppPolaritySet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); + + /* Set GPP Out Enable */ + mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); + mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValMid); + mvGppTypeSet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); +#endif +} +/******************************************************************************* +* mvBoardModelGet - Get Board model +* +* DESCRIPTION: +* This function returns 16bit describing board model. +* Board model is constructed of one byte major and minor numbers in the +* following manner: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardModelGet(MV_VOID) +{ + return (mvBoardIdGet() >> 16); +} +/******************************************************************************* +* mbBoardRevlGet - Get Board revision +* +* DESCRIPTION: +* This function returns a 32bit describing the board revision. +* Board revision is constructed of 4bytes. 2bytes describes major number +* and the other 2bytes describes minor munber. +* For example for board revision 3.4 the function will return +* 0x00030004. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardRevGet(MV_VOID) +{ + return (mvBoardIdGet() & 0xFFFF); +} +/******************************************************************************* +* mvBoardNameGet - Get Board name +* +* DESCRIPTION: +* This function returns a string describing the board model and revision. +* String is extracted from board I2C EEPROM. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvBoardNameGet(char *pNameBuff) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsSPrintf(pNameBuff, "Board unknown.\n"); + return MV_ERROR; + } + if (mvCtrlModelRevGet() == MV_6710_Z1_ID) + mvOsSPrintf(pNameBuff, "%s", "DB-6710-Z1"); + else + mvOsSPrintf(pNameBuff, "%s", BOARD_INFO(boardId)->boardName); + + + return MV_OK; +} +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + switch (boardId) { + case DB_88F78XX0_BP_REV2_ID: + case DB_88F78XX0_BP_ID: /* need to update since Gunit0 can be SGMII */ + if (ethPortNum > 1) + return MV_TRUE; + break; + case DB_78X60_AMC_ID: + if (ethPortNum > 0) + return MV_TRUE; + break; + case RD_78460_SERVER_ID: + case RD_78460_SERVER_REV2_ID: + if (ethPortNum > 0) + return MV_TRUE; + break; + case DB_78X60_PCAC_ID: + case DB_784MP_GP_ID: + case RD_78460_NAS_ID: + case RD_78460_CUSTOMER_ID: + case DB_78X60_PCAC_REV2_ID: + return MV_TRUE; + break; +#ifdef CONFIG_SYNO_ARMADA_ARCH + case SYNO_AXP_4BAY_2BAY: + case SYNO_AXP_4BAY_RACK: + return MV_FALSE; + break; + case SYNO_AXP_2BAY: + return MV_TRUE; + break; +#endif + + default: + DB(mvOsPrintf("mvBoardSerdesCfgGet: Unsupported board!\n")); + return MV_FALSE; + } + + return MV_FALSE; +} +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInGmii(MV_U32 ethPortNum) +{ + if (mvBoardIsGMIIModuleConnected() && (ethPortNum ==0)) + return MV_TRUE; + else + return MV_FALSE; +} + + +/******************************************************************************* +* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port +* +* DESCRIPTION: +* This routine returns the Switch CPU port. +* +* INPUT: +* switchIdx - index of the switch. Only 0 is supported. +* +* OUTPUT: +* None. +* +* RETURN: +* the Switch CPU port, -1 if the switch is not connected. +* +*******************************************************************************/ +MV_32 mvBoardSwitchCpuPortGet(MV_U32 switchIdx) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); + return -1; + } + if ((BOARD_INFO(boardId)->switchInfoNum == 0) || (switchIdx >= BOARD_INFO(boardId)->switchInfoNum)) + return -1; + + return BOARD_INFO(boardId)->pSwitchInfo[switchIdx].cpuPort; +} + +/******************************************************************************* +* mvBoardPhyAddrGet - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; +} +/******************************************************************************* +* mvBoardQuadPhyAddr0Get - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardQuadPhyAddr0Get(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardQuadPhyAddr0Get: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr0; +} + +/******************************************************************************* +* mvBoardPhyLinkCryptPortAddrGet - Get the phy gbe address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyLinkCryptPortAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardPhyLinkCryptPortAddrGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].LinkCryptPortAddr; +} + +MV_BOOL mvBoardIsPortInRgmii(MV_U32 ethPortNum) +{ + return !mvBoardIsPortInGmii(ethPortNum); +} + +/******************************************************************************* +* mvBoardMacSpeedGet - Get the Mac speed +* +* DESCRIPTION: +* This routine returns the Mac speed if pre define of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); + return MV_ERROR; + } + + if (boardId == RD_78460_NAS_ID) { + if (mvBoardIsSwitchModuleConnected()) + return BOARD_MAC_SPEED_1000M; + } + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; +} + +/******************************************************************************* +* mvBoardSpecInitGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, +* otherwise return MV_FALSE. +* +* +*******************************************************************************/ +MV_BOOL mvBoardSpecInitGet(MV_U32 *regOff, MV_U32 *data) +{ + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTclkGet - Get the board Tclk (Controller clock) +* +* DESCRIPTION: +* This routine extract the controller core clock. +* This function uses the controller counters to make identification. +* Note: In order to avoid interference, make sure task context switch +* and interrupts will not occure during this function operation +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardTclkGet(MV_VOID) +{ + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return MV_FPGA_CLK; /* FPGA is limited to 25Mhz */ + + if ((MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_TCLK_MASK) != 0) + return MV_BOARD_TCLK_200MHZ; + else + return MV_BOARD_TCLK_250MHZ; +} + +/******************************************************************************* +* mvBoardSysClkGet - Get the board SysClk (CPU bus clock , i.e. DDR clock) +* +* DESCRIPTION: +* This routine extract the CPU bus clock. +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardSysClkGet(MV_VOID) +{ + MV_U32 idx; + MV_U32 cpuFreqMhz, ddrFreqMhz; + MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL; + + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return MV_FPGA_CLK; /* FPGA is limited to 25Mhz */ + + idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)), + MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + if (clockRatioTbl[idx].vco2cpu != 0) { /* valid ratio ? */ + cpuFreqMhz = mvCpuPclkGet() / 1000000; /* obtain CPU freq */ + cpuFreqMhz *= clockRatioTbl[idx].vco2cpu; /* compute VCO freq */ + ddrFreqMhz = cpuFreqMhz / clockRatioTbl[idx].vco2ddr; + /* round up to integer MHz */ + if (((cpuFreqMhz % clockRatioTbl[idx].vco2ddr) * 10 / clockRatioTbl[idx].vco2ddr) >= 5) + ddrFreqMhz++; + + return ddrFreqMhz * 1000000; + } else + return 0; +} + +/******************************************************************************* +* mvBoardDebugLedNumGet - Get number of debug Leds +* +* DESCRIPTION: +* INPUT: +* boardId +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) +{ + return BOARD_INFO(boardId)->activeLedsNumber; +} + +/******************************************************************************* +* mvBoardDebugLeg - Set the board debug Leds +* +* DESCRIPTION: turn on/off status leds. +* Note: assume MPP leds are part of group 0 only. +* +* INPUT: +* hexNum - Number to be displied in hex by Leds. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebugLed(MV_U32 hexNum) +{ + MV_U32 val[MV_GPP_MAX_GROUP] = {0}; + MV_U32 mask[MV_GPP_MAX_GROUP] = {0}; + MV_U32 digitMask; + MV_U32 i, pinNum, gppGroup; + MV_U32 boardId = mvBoardIdGet(); + + if (BOARD_INFO(boardId)->pLedGppPin == NULL) + return; + + hexNum &= (1 << BOARD_INFO(boardId)->activeLedsNumber) - 1; + + for (i = 0, digitMask = 1; i < BOARD_INFO(boardId)->activeLedsNumber; i++, digitMask <<= 1) { + pinNum = BOARD_INFO(boardId)->pLedGppPin[i]; + gppGroup = pinNum / 32; + if (hexNum & digitMask) + val[gppGroup] |= (1 << (pinNum - gppGroup * 32)); + mask[gppGroup] |= (1 << (pinNum - gppGroup * 32)); + } + + for (gppGroup = 0; gppGroup < MV_GPP_MAX_GROUP; gppGroup++) { + /* If at least one bit is set in the mask, update the whole GPP group */ + if (mask[gppGroup]) + mvGppValueSet(gppGroup, mask[gppGroup], BOARD_INFO(boardId)->ledsPolarity == 0 ? + val[gppGroup] : ~val[gppGroup]); + } +} + +/******************************************************************************* +* mvBoarGpioPinGet - mvBoarGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* gppClass - MV_BOARD_GPP_CLASS enum. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS gppClass, MV_U32 index) +{ + MV_U32 boardId, i; + MV_U32 indexFound = 0; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) { + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == gppClass) { + if (indexFound == index) + return (MV_U32) BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + else + indexFound++; + } + } + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardReset - mvBoardReset +* +* DESCRIPTION: +* Reset the board +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvBoardReset(MV_VOID) +{ + MV_32 resetPin; + + /* Get gpp reset pin if define */ + resetPin = mvBoardResetGpioPinGet(); + if (resetPin != MV_ERROR) + MV_REG_BIT_RESET(GPP_DATA_OUT_REG((int)(resetPin/32)), (1 << (resetPin % 32))); + else + { + /* No gpp reset pin was found, try to reset using system reset out */ + MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT0); + MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); + } +} + +/******************************************************************************* +* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardResetGpioPinGet(MV_VOID) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); +} + +/******************************************************************************* +* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet +* +* DESCRIPTION: +* used for hotswap detection +* INPUT: +* type - Type of SDIO GPP to get. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardSDIOGpioPinGet(MV_BOARD_GPP_CLASS type) +{ + if ((type != BOARD_GPP_SDIO_POWER) && (type != BOARD_GPP_SDIO_DETECT) && (type != BOARD_GPP_SDIO_WP)) + return MV_FAIL; + + return mvBoarGpioPinNumGet(type, 0); +} + +/******************************************************************************* +* mvBoardUSBVbusGpioPinGet - return Vbus input GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); +} + +/******************************************************************************* +* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); +} + +/******************************************************************************* +* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins +* +* DESCRIPTION: +* This function returns a 32-bit mask of GPP pins that connected to +* interrupt generating sources on board. +* For example if UART channel A is hardwired to GPP pin 8 and +* UART channel B is hardwired to GPP pin 4 the fuinction will return +* the value 0x000000110 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* See description. The function return -1 if board is not identified. +* +*******************************************************************************/ +MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + } + + switch (gppGrp) { + case (0): + return BOARD_INFO(boardId)->intsGppMaskLow; + break; + case (1): + return BOARD_INFO(boardId)->intsGppMaskMid; + break; + case (2): + return BOARD_INFO(boardId)->intsGppMaskHigh; + break; + default: + return MV_ERROR; + } +} + +/******************************************************************************* +* mvBoardMppGet - Get board dependent MPP register value +* +* DESCRIPTION: +* MPP settings are derived from board design. +* MPP group consist of 8 MPPs. An MPP group represents MPP +* control register. +* This function retrieves board dependend MPP register value. +* +* INPUT: +* mppGroupNum - MPP group number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit value describing MPP control register value. +* +*******************************************************************************/ +MV_32 mvBoardMppGet(MV_U32 mppGroupNum) +{ + MV_U32 boardId; + MV_U32 mppMod; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + } + + mppMod = BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod; + if (mppMod >= BOARD_INFO(boardId)->numBoardMppConfigValue) + mppMod = 0; /* default */ + + return BOARD_INFO(boardId)->pBoardMppConfigValue[mppMod].mppGroup[mppGroupNum]; +} + +/******************************************************************************* +* mvBoardGppConfigGet +* +* DESCRIPTION: +* Get board configuration according to the input configuration GPP's. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The value of the board configuration GPP's. +* +*******************************************************************************/ +MV_U32 mvBoardGppConfigGet(void) +{ + MV_U32 boardId, i; + MV_U32 result = 0; + MV_U32 gpp; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGppConfigGet: Board unknown.\n"); + return 0; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) { + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == BOARD_GPP_CONF) { + gpp = BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + result <<= 1; + result |= (mvGppValueGet(gpp >> 5, 1 << (gpp & 0x1F)) >> (gpp & 0x1F)); + } + } + return result; + +} + +/******************************************************************************* +* mvBoardTdmSpiModeGet - return SLIC/DAA connection +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_32 mvBoardTdmSpiModeGet(MV_VOID) +{ + return DUAL_CHIP_SELECT_MODE; +} + +/******************************************************************************* +* mvBoardTdmDevicesCountGet +* +* DESCRIPTION: +* Return the number of TDM devices on board. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Number of devices. +* +*******************************************************************************/ +MV_U8 mvBoardTdmDevicesCountGet(void) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_16 index; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmDevicesCountGet: Board unknown.\n"); + return 0; + } + + index = BOARD_INFO(boardId)->boardTdmInfoIndex; + if (index == -1) + return 0; + + return BOARD_INFO(boardId)->numBoardTdmInfo[index]; +} + +/******************************************************************************* +* mvBoardTdmSpiCsGet +* +* DESCRIPTION: +* Return the SPI Chip-select number for a given device. +* +* INPUT: +* devId - The Slic device ID to get the SPI CS for. +* +* OUTPUT: +* None. +* +* RETURN: +* The SPI CS if found, -1 otherwise. +* +*******************************************************************************/ +MV_U8 mvBoardTdmSpiCsGet(MV_U8 devId) +{ + MV_U32 boardId = mvBoardIdGet(); + MV_16 index; + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardTdmDevicesCountGet: Board unknown.\n"); + return -1; + } + + index = BOARD_INFO(boardId)->boardTdmInfoIndex; + if (index == -1) + return 0; + + if (devId >= BOARD_INFO(boardId)->numBoardTdmInfo[index]) + return -1; + + return BOARD_INFO(boardId)->pBoardTdmInt2CsInfo[index][devId].spiCs; +} + +/******************************************************************************* +* mvBoardModuleTypePrint +* +* DESCRIPTION: +* Print on-board detected modules. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardMppModuleTypePrint(MV_VOID) +{ + mvOsOutput("Modules Detected:\n"); + + /* TDM */ + if (mvBoardTdmDevicesCountGet() > 0) + mvOsOutput(" TDM module.\n"); + + /* LCD DVI Module */ + if (mvBoardIsLcdDviModuleConnected()) + mvOsOutput(" LCD DVI module.\n"); + + /* Switch Module */ + if (mvBoardIsSwitchModuleConnected()) + mvOsOutput(" Switch module.\n"); + + /* GMII Module */ + if (mvBoardIsGMIIModuleConnected()) + mvOsOutput(" GMII module.\n"); + + return; +} + +MV_VOID mvBoardOtherModuleTypePrint(MV_VOID) +{ + /* Pex Module */ + if (mvBoardIsPexModuleConnected()) + mvOsOutput(" PEX module.\n"); + /* SETM Module */ + if (mvBoardIsSetmModuleConnected()) + mvOsOutput(" SETM module.\n"); + /* LVDS Module */ + if (mvBoardIsLvdsModuleConnected()) + mvOsOutput(" LVDS module.\n"); + + return; +} + +/******************************************************************************* +* mvBoardIsGbEPortConnected +* +* DESCRIPTION: +* Checks if a given GbE port is actually connected to the GE-PHY, internal Switch or any RGMII module. +* +* INPUT: +* port - GbE port number (0 or 1). +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if port is connected, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_BOOL mvBoardIsGbEPortConnected(MV_U32 ethPortNum) +{ +#ifdef CONFIG_SYNO_ARMADA_ARCH + MV_U32 boardId = mvBoardIdGet(); + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardIsGbEPortConnected: Board unknown.\n"); + return MV_FALSE; + } + if (ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) + return MV_FALSE; +#endif + switch (ethPortNum) { + case 0: + if (mvBoardIsLcdDviModuleConnected()) + return MV_FALSE; + break; + case 1: + if (mvBoardIsLcdDviModuleConnected()) + return MV_FALSE; + else if (mvBoardIsGMIIModuleConnected()) + return MV_FALSE; + break; + case 2: + if ( (mvBoardIsPexModuleConnected()) || (mvBoardIsSetmModuleConnected()) ) + return MV_FALSE; + break; + case 3: + break; + default: + break; + } + + return MV_TRUE; +} + +/* Board devices API managments */ + +/******************************************************************************* +* mvBoardGetDeviceNumber - Get number of device of some type on the board +* +* DESCRIPTION: +* +* INPUT: +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* number of those devices else the function returns 0 +* +* +*******************************************************************************/ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, devNum; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); + return 0xFFFFFFFF; + } + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) { + if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) + foundIndex++; + } + + return foundIndex; +} + +/******************************************************************************* +* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Base address else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Bus width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->busWidth; + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceWidth - Get dev width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* window size else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* boardGetDevEntry - returns the entry pointer of a device on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +*******************************************************************************/ +static MV_DEV_CS_INFO *boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, devIndex; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("boardGetDevEntry: Board unknown.\n"); + return NULL; + } + + for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) { + if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) { + if (foundIndex == devNum) + return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); + foundIndex++; + } + } + + /* device not found */ + return NULL; +} + +/******************************************************************************* +* boardGetDevCSNum +* +* DESCRIPTION: +* Return the device's chip-select number. +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +*******************************************************************************/ +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO *devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum, devClass); + if (devEntry != NULL) + return devEntry->deviceCS; + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardTwsiAddrTypeGet - +* +* DESCRIPTION: +* Return the TWSI address type for a given twsi device class. +* +* INPUT: +* twsiClass - The TWSI device to return the address type for. +* index - The TWSI device index (Pass 0 in case of a single +* device) +* +* OUTPUT: +* None. +* +* RETURN: +* The TWSI address type. +* +*******************************************************************************/ +MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId = mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) { + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == twsiClass) { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + else + indexFound++; + } + } + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardTwsiAddrGet - +* +* DESCRIPTION: +* Return the TWSI address for a given twsi device class. +* +* INPUT: +* twsiClass - The TWSI device to return the address type for. +* index - The TWSI device index (Pass 0 in case of a single +* device) +* +* OUTPUT: +* None. +* +* RETURN: +* The TWSI address. +* +*******************************************************************************/ +MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId = mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) { + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == twsiClass) { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + else + indexFound++; + } + } + return (0xFF); +} + +/******************************************************************************* +* mvBoardNandWidthGet - +* +* DESCRIPTION: Get the width of the first NAND device in bytes +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: 1, 2, 4 or MV_ERROR +* +* +*******************************************************************************/ +MV_32 mvBoardNandWidthGet(void) +{ + MV_U32 devNum; + MV_U32 devWidth; + MV_U32 boardId = mvBoardIdGet(); + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) { + devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); + if (devWidth != MV_ERROR) + return (devWidth / 8); + } + + /* NAND wasn't found */ + return MV_ERROR; +} + +MV_U32 gBoardId = -1; +/******************************************************************************* +* mvBoardIdSet - Set Board model +* +* DESCRIPTION: +* This function sets the board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* void +* +*******************************************************************************/ +MV_VOID mvBoardIdSet(MV_VOID) +{ + if (gBoardId == -1) { +#if defined(DB_88F78X60) + gBoardId = DB_88F78XX0_BP_ID; +#elif defined(RD_88F78460_SERVER) + gBoardId = RD_78460_SERVER_ID; +#elif defined(RD_78460_SERVER_REV2) + gBoardId = RD_78460_SERVER_REV2_ID; +#elif defined(DB_78X60_PCAC) + gBoardId = DB_78X60_PCAC_ID; +#elif defined(DB_88F78X60_REV2) + gBoardId = DB_88F78XX0_BP_REV2_ID; +#elif defined(RD_78460_NAS) + gBoardId = RD_78460_NAS_ID; +#elif defined(DB_78X60_AMC) + gBoardId = DB_78X60_AMC_ID; +#elif defined(DB_78X60_PCAC_REV2) + gBoardId = DB_78X60_PCAC_REV2_ID; +#elif defined(DB_784MP_GP) + gBoardId = DB_784MP_GP_ID; +#elif defined(RD_78460_CUSTOMER) + gBoardId = RD_78460_CUSTOMER_ID; +#else + mvOsPrintf("mvBoardIdSet: Board ID must be defined!\n"); + while (1) { + continue; + } +#endif + } +} +/******************************************************************************* +* mvBoardIdGet - Get Board model +* +* DESCRIPTION: +* This function returns board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board ID number, '-1' if board is undefined. +* +*******************************************************************************/ +MV_U32 mvBoardIdGet(MV_VOID) +{ + if (gBoardId == -1) { + mvOsWarning(); + return INVALID_BAORD_ID; + } + + return gBoardId; +} + +/******************************************************************************* +* mvBoardTwsiSatRGet - +* +* DESCRIPTION: +* +* INPUT: +* device num - one of three devices +* reg num - 0 or 1 +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_U8 mvBoardTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U8 data; + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: Read S@R device read\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_SATR, devNum); + if (0xFF == twsiSlave.slaveAddr.address) + return MV_ERROR; + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_DEV_TWSI_SATR, devNum); + + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + twsiSlave.validOffset = MV_TRUE; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + + if (MV_OK != mvTwsiRead(0, &twsiSlave, &data, 1)) { + DB(mvOsPrintf("Board: Read S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Read S@R succeded\n")); + + return data; +} + +/******************************************************************************* +* mvBoardTwsiSatRSet - +* +* DESCRIPTION: +* +* INPUT: +* devNum - one of three devices +* regNum - 0 or 1 +* regVal - value +* +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + /* Read MPP module ID */ + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_DEV_TWSI_SATR, devNum); + if (0xFF == twsiSlave.slaveAddr.address) + return MV_ERROR; + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_DEV_TWSI_SATR, devNum); + twsiSlave.validOffset = MV_TRUE; + DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", + twsiSlave.slaveAddr.address, twsiSlave.slaveAddr.type, regVal)); + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + if (MV_OK != mvTwsiWrite(0, &twsiSlave, ®Val, 1)) { + DB1(mvOsPrintf("Board: Write S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Write S@R succeded\n")); + + return MV_OK; +} + +/******************************************************************************* +* SatR Configuration functions +*******************************************************************************/ +MV_U8 mvBoardFabFreqGet(MV_VOID) +{ + MV_U8 sar0; + MV_U8 sar1; + MV_U32 boardId = mvBoardIdGet(); + + sar0 = mvBoardTwsiSatRGet(2, 0); + if ((MV_8)MV_ERROR == (MV_8)sar0) + return MV_ERROR; + + if (DB_784MP_GP_ID == boardId) + return (sar0 & 0x1f); + + sar1 = mvBoardTwsiSatRGet(3, 0); + if ((MV_8)MV_ERROR == (MV_8)sar1) + return MV_ERROR; + + return ( ((sar1 & 0x1) << 4) | ((sar0 & 0x1E) >> 1) ); +} + +/*******************************************************************************/ +MV_STATUS mvBoardFabFreqSet(MV_U8 freqVal) +{ + MV_U8 sar0; + MV_U32 boardId = mvBoardIdGet(); + + sar0 = mvBoardTwsiSatRGet(2, 0); + if ((MV_8)MV_ERROR == (MV_8)sar0) + return MV_ERROR; + if (DB_784MP_GP_ID == boardId) { + sar0 &= ~(0x1F); + sar0 |= (freqVal & 0x1F); + if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar0)) { + DB1(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + return MV_OK; + } + + sar0 &= ~(0xF << 1); + sar0 |= (freqVal & 0xF) << 1; + if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar0)) { + DB1(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + sar0 = mvBoardTwsiSatRGet(3, 0); + if ((MV_8)MV_ERROR == (MV_8)sar0) + return MV_ERROR; + + sar0 &= ~(0x1); + sar0 |= ( (freqVal >> 4) & 0x1); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar0)) { + DB1(mvOsPrintf("Board: Write FreqOpt S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write FreqOpt S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardCpuFreqGet(MV_VOID) +{ + MV_U8 sar; + MV_U8 sarMsb; + MV_U32 boardId = mvBoardIdGet(); + + sar = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + if (DB_784MP_GP_ID == boardId) { + return (sar & 0x0f); + } + + sarMsb = mvBoardTwsiSatRGet(2, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + return ( ((sarMsb & 0x1) << 3) | ((sar & 0x1C) >> 2)); +} + +/*******************************************************************************/ +MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal) +{ + MV_U8 sar; + MV_U32 boardId = mvBoardIdGet(); + + sar = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + if (DB_784MP_GP_ID == boardId) { + sar &= ~0x0f; + sar |= (freqVal & 0x0f); + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB1(mvOsPrintf("Board: Write CpuFreq S@R fail\n")); + return MV_ERROR; + } + } + else{ + sar &= ~(0x7 << 2); + sar |= (freqVal & 0x7) << 2; + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB1(mvOsPrintf("Board: Write CpuFreq S@R fail\n")); + return MV_ERROR; + } + sar = mvBoardTwsiSatRGet(2, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + sar &= ~(0x1); + sar |= ( (freqVal >> 3) & 0x1); + if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar)) { + DB1(mvOsPrintf("Board: Write CpuFreq S@R fail\n")); + return MV_ERROR; + } + + sar = mvBoardTwsiSatRGet(2, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + sar &= ~(0x1); + sar |= ( (freqVal >> 3) & 0x1); + if (MV_OK != mvBoardTwsiSatRSet(2, 0, sar)) { + DB1(mvOsPrintf("Board: Write CpuFreq S@R fail\n")); + return MV_ERROR; + } + } + + DB(mvOsPrintf("Board: Write CpuFreq S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U8 mvBoardBootDevGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + if (DB_784MP_GP_ID == mvBoardIdGet()) + sar = (sar >> 1); + + return (sar & 0x7); +} +/*******************************************************************************/ +MV_STATUS mvBoardBootDevSet(MV_U8 val) +{ + MV_U8 sar; + MV_U32 boardId = mvBoardIdGet(); + + sar = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + if (DB_784MP_GP_ID == boardId) { + sar &= ~(0x7 << 1); + sar |= ((val & 0x7) << 1); + } + else { + sar &= ~(0x7); + sar |= (val & 0x7); + } + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) { + DB1(mvOsPrintf("Board: Write BootDev S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write BootDev S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardBootDevWidthGet(MV_VOID) +{ + MV_U8 sar; + MV_U32 boardId = mvBoardIdGet(); + + sar = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + if (DB_784MP_GP_ID == boardId) + return (sar & 1); + + return (sar & 0x18) >> 3; +} +/*******************************************************************************/ +MV_STATUS mvBoardBootDevWidthSet(MV_U8 val) +{ + MV_U8 sar; + MV_U32 boardId = mvBoardIdGet(); + + sar = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + if (DB_784MP_GP_ID == boardId) { + sar &= ~(1); + sar |= (val & 0x1); + } + else { + sar &= ~(0x3 << 3); + sar |= ((val & 0x3) << 3); + } + + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) { + DB1(mvOsPrintf("Board: Write BootDevWidth S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write BootDevWidth S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardCpu0EndianessGet(MV_VOID) +{ + MV_U8 sar; + if (DB_784MP_GP_ID == mvBoardIdGet()) + return 0; + + sar = mvBoardTwsiSatRGet(3, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + return (sar & 0x08) >> 3; +} +/*******************************************************************************/ +MV_STATUS mvBoardCpu0EndianessSet(MV_U8 val) +{ + MV_U8 sar; + if (DB_784MP_GP_ID == mvBoardIdGet()) + return MV_OK; + + sar = mvBoardTwsiSatRGet(3, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + sar &= ~(0x1 << 3); + sar |= ((val & 0x1) << 3); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) { + DB1(mvOsPrintf("Board: Write Cpu0CoreMode S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write Cpu0CoreMode S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardL2SizeGet(MV_VOID) +{ + MV_U8 sar; + MV_U32 boardId = mvBoardIdGet(); + if (DB_784MP_GP_ID == boardId) { + sar = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + return (((sar & 0x10)>>3)+ 1); + } + + sar = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + return (sar & 0x3); +} +/*******************************************************************************/ +MV_STATUS mvBoardL2SizeSet(MV_U8 val) +{ + MV_U8 sar; + if (DB_784MP_GP_ID == mvBoardIdGet()) { + sar = mvBoardTwsiSatRGet(0, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + sar &= ~(0x1 << 4); + sar |= ((val & 0x2) << 3); + if (MV_OK != mvBoardTwsiSatRSet(0, 0, sar)) { + DB1(mvOsPrintf("Board: Write L2Size S@R fail\n")); + return MV_ERROR; + } + return MV_OK; + } + + sar = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + sar &= ~(0x3); + sar |= (val & 0x3); + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB1(mvOsPrintf("Board: Write L2Size S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write L2Size S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U8 mvBoardCpuCoresNumGet(MV_VOID) +{ + MV_U8 sar; + + if (DB_784MP_GP_ID == mvBoardIdGet()) { + sar = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + sar &=0x10; + return (1+(sar >>3)); + } + sar = mvBoardTwsiSatRGet(3, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + sar = (sar & 0x6) >> 1; + if (sar == 1) + sar = 2; + else if (sar == 2) + sar =1; + return sar; +} +/*******************************************************************************/ +MV_STATUS mvBoardCpuCoresNumSet(MV_U8 val) +{ + MV_U8 sar; + if (DB_784MP_GP_ID == mvBoardIdGet()) { + sar = mvBoardTwsiSatRGet(1, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + sar &=~0x10; + val &= 2; + sar |= (val<<3); + if (MV_OK != mvBoardTwsiSatRSet(1, 0, sar)) { + DB1(mvOsPrintf("Board: Write CpuCoreNum S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Write CpuCoreNum S@R succeeded\n")); + return MV_OK; + } + sar = mvBoardTwsiSatRGet(3, 0); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + /* MSB and LSB are swapped on DB board */ + if (val == 1) + val = 2; + else if (val == 2) + val =1; + + sar &= ~(0x3 << 1); + sar |= ((val & 0x3) << 1); + if (MV_OK != mvBoardTwsiSatRSet(3, 0, sar)) { + DB1(mvOsPrintf("Board: Write CpuCoreNum S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write CpuCoreNum S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_STATUS mvBoardConfIdSet(MV_U16 conf) +{ + if (MV_OK != mvBoardTwsiSatRSet(0, 1, conf)) { + DB1(mvOsPrintf("Board: Write confID S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write confID S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U16 mvBoardConfIdGet(MV_VOID) +{ + MV_U8 sar; + + sar = mvBoardTwsiSatRGet(0, 1); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + return (sar & 0xFF); +} +/*******************************************************************************/ +MV_STATUS mvBoardPexCapabilitySet(MV_U16 conf) +{ + MV_U8 sar; + sar = mvBoardTwsiSatRGet(1, 1); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + sar &= ~(0x1); + sar |= (conf & 0x1); + + if (MV_OK != mvBoardTwsiSatRSet(1, 1, sar)) { + DB(mvOsPrintf("Board: Write confID S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write confID S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U16 gPexCap = 0; +MV_U16 mvBoardPexCapabilityGet(MV_VOID) +{ + MV_U8 sar; + MV_U32 boardId; + + if (gPexCap) + return gPexCap; + + boardId = mvBoardIdGet(); + switch (boardId) { + case DB_78X60_PCAC_ID: + case RD_78460_NAS_ID: + case RD_78460_CUSTOMER_ID: + case DB_78X60_AMC_ID: + case DB_78X60_PCAC_REV2_ID: + case RD_78460_SERVER_ID: + case RD_78460_SERVER_REV2_ID: +#ifdef CONFIG_SYNO_ARMADA_ARCH + case SYNO_AXP_4BAY_2BAY: + case SYNO_AXP_2BAY: + case SYNO_AXP_4BAY_RACK: +#endif + sar = 0x1; /* Gen2 */ + break; + case DB_784MP_GP_ID: + case DB_88F78XX0_BP_ID: + case FPGA_88F78XX0_ID: + case DB_88F78XX0_BP_REV2_ID: + default: + sar = mvBoardTwsiSatRGet(1, 1); + break; + } + gPexCap = sar & 0x1; + + return (gPexCap); +} +/*******************************************************************************/ +MV_STATUS mvBoardPexModeSet(MV_U16 conf) +{ + MV_U8 sar; + sar = mvBoardTwsiSatRGet(1, 1); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + sar &= ~(0x3 << 1); + sar |= ((conf & 0x3) << 1); + + if (MV_OK != mvBoardTwsiSatRSet(1, 1, sar)) { + DB(mvOsPrintf("Board: Write confID S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write confID S@R succeeded\n")); + return MV_OK; +} +/*******************************************************************************/ +MV_U16 mvBoardPexModeGet(MV_VOID) +{ + MV_U8 sar; +#ifdef CONFIG_SYNO_ARMADA_ARCH + MV_U32 boardID = mvBoardIdGet(); + + if (SYNO_AXP_4BAY_2BAY == boardID || + SYNO_AXP_2BAY == boardID || + SYNO_AXP_4BAY_RACK == boardID) + { + return 0x1; + } +#endif + + sar = mvBoardTwsiSatRGet(1, 1); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + return (sar & 0x6) >> 1; + +} +/*******************************************************************************/ +MV_STATUS mvBoardDramEccSet(MV_U16 ecc) +{ + MV_U8 sar; + MV_U8 devNum; + if (DB_784MP_GP_ID == mvBoardIdGet()) + devNum = 2; + else + devNum = 3; + + sar = mvBoardTwsiSatRGet(devNum, 1); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + sar &= ~(0x2); + sar |= ((ecc & 0x1) << 1); + + if (MV_OK != mvBoardTwsiSatRSet(devNum, 1, sar)) { + DB(mvOsPrintf("Board: Write eccID S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write eccID S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U16 mvBoardDramEccGet(MV_VOID) +{ + MV_U8 sar; + MV_U8 devNum; + if (DB_784MP_GP_ID == mvBoardIdGet()) + devNum = 2; + else + devNum = 3; + + sar = mvBoardTwsiSatRGet(devNum, 1); + return ((sar & 0x2) >> 1); +} + +/*******************************************************************************/ +MV_STATUS mvBoardDramBusWidthSet(MV_U16 dramBusWidth) +{ + MV_U8 sar; + MV_U8 devNum; + if (DB_784MP_GP_ID == mvBoardIdGet()) + devNum = 2; + else + devNum = 3; + + sar = mvBoardTwsiSatRGet(devNum, 1); + if ((MV_8)MV_ERROR == (MV_8)sar) + return MV_ERROR; + + sar &= ~(0x1); + sar |= (dramBusWidth & 0x1); + + if (MV_OK != mvBoardTwsiSatRSet(devNum, 1, sar)) { + DB(mvOsPrintf("Board: Write dramBusWidthID S@R fail\n")); + return MV_ERROR; + } + + DB(mvOsPrintf("Board: Write dramBusWidthID S@R succeeded\n")); + return MV_OK; +} + +/*******************************************************************************/ +MV_U16 mvBoardDramBusWidthGet(MV_VOID) +{ + MV_U8 sar; + + MV_U8 devNum; + if (DB_784MP_GP_ID == mvBoardIdGet()) + devNum = 2; + else + devNum = 3; + + sar = mvBoardTwsiSatRGet(devNum, 1); + return (sar & 0x1); +} + +/*******************************************************************************/ +MV_U8 mvBoardAltFabFreqGet(MV_VOID) +{ + MV_U8 sar0; + if (DB_784MP_GP_ID == mvBoardIdGet()) + return 5; + + sar0 = mvBoardTwsiSatRGet(2, 1); + if ((MV_8)MV_ERROR == (MV_8)sar0) + return MV_ERROR; + + return (sar0 & 0x1F); +} +/*******************************************************************************/ +MV_STATUS mvBoardAltFabFreqSet(MV_U8 freqVal) +{ + if (DB_784MP_GP_ID == mvBoardIdGet()) + return MV_OK; + + if (MV_OK != mvBoardTwsiSatRSet(2, 1, freqVal)) { + DB1(mvOsPrintf("Board: Write Alt FreqOpt S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Write Alt FreqOpt S@R succeeded\n")); + return MV_OK; +} +/******************************************************************************* +* End of SatR Configuration functions +*******************************************************************************/ + +/******************************************************************************* +* mvBoardMppModulesScan +* +* DESCRIPTION: +* Scan for modules connected through MPP lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardMppModulesScan(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave; + MV_U32 boardId = mvBoardIdGet(); + + /* Perform scan only for DB board */ + if ( (boardId == DB_88F78XX0_BP_ID) || (boardId == DB_88F78XX0_BP_REV2_ID) ) { + twsiSlave.slaveAddr.address = MV_BOARD_MPP_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_MPP_MODULE_ADDR_TYPE; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + switch (regVal) { + case MV_BOARD_LCD_DVI_MODULE_ID: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_LCD_DVI; + return MV_OK; + + case MV_BOARD_MII_GMII_MODULE_ID: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_MII_GMII; + BOARD_INFO(boardId)->pBoardMacInfo[0].boardEthSmiAddr = 0x8; + + return MV_OK; + + case MV_BOARD_TDM_MODULE_ID: + /* + TODO - how to distinguish between SLIC types? + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_3215; + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_880; + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_792; + return MV_OK; + */ + BOARD_INFO(boardId)->boardTdmInfoIndex = BOARD_TDM_SLIC_OTHER; + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_TDM_32CH; + return MV_OK; + + default: + BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod = MV_BOARD_OTHER; + DB1(mvOsPrintf("mvBoardMppModulesScan: Unsupported module!\n")); + break; + } + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardOtherModulesScan +* +* DESCRIPTION: +* Scan for modules connected through SERDES/LVDS/... lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardOtherModulesScan(void) +{ + MV_U8 regVal; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U32 boardId = mvBoardIdGet(); + + /* Perform scan only for DB board */ + if ( (boardId == DB_88F78XX0_BP_ID) || (boardId == DB_88F78XX0_BP_REV2_ID) ) { + /* reset modules flags */ + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_NONE; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED , mvBoardTclkGet(), &slave, 0); + + /* SERDES module (PEX module and SETM module are supported now) */ + twsiSlave.slaveAddr.address = MV_BOARD_PEX_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_PEX_MODULE_ADDR_TYPE; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if (regVal == MV_BOARD_PEX_MODULE_ID) { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "PEX module DETECTED!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_PEX; + } else { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "Unknown ID @ PEX module address!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_UNKNOWN; + } + } + + /* SERDES module (PEX module and SETM module are supported now) */ + twsiSlave.slaveAddr.address = MV_BOARD_SETM_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_SETM_MODULE_ADDR_TYPE; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if (regVal == MV_BOARD_SETM_MODULE_ID) { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "SETM module DETECTED!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_SETM; + } else { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "Unknown ID @ PEX module address!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_UNKNOWN; + } + } + + /* LVDS (LCD) module */ + twsiSlave.slaveAddr.address = MV_BOARD_LVDS_MODULE_ADDR; + twsiSlave.slaveAddr.type = MV_BOARD_LVDS_MODULE_ADDR_TYPE; + if (mvTwsiRead(0, &twsiSlave, ®Val, 1) == MV_OK) { + if (regVal == MV_BOARD_LVDS_MODULE_ID) { + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_LVDS; + mvCpuIfLvdsPadsEnable(MV_TRUE); + } else { + DB(mvOsPrintf("mvBoardOtherModulesScan: " "Unknown ID @ LVDS module address!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_UNKNOWN; + } + } + } else if (boardId == RD_78460_NAS_ID) { + if ((MV_REG_READ(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0) { + DB(mvOsPrintf("mvBoardOtherModulesScan: SWITCH module DETECTED!\n")); + BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod |= MV_BOARD_SWITCH; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPexModuleConnected +* +* DESCRIPTION: +* Check if PEX module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsPexModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if ( (boardId != DB_88F78XX0_BP_ID) && (boardId != DB_88F78XX0_BP_REV2_ID) ) + DB(mvOsPrintf("mvBoardIsPexModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod & MV_BOARD_PEX) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsSetmModuleConnected +* +* DESCRIPTION: +* Check if SETM module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsSetmModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if ( (boardId != DB_88F78XX0_BP_ID) && (boardId != DB_88F78XX0_BP_REV2_ID) ) + DB(mvOsPrintf("mvBoardIsSetmModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod & MV_BOARD_SETM) + return MV_TRUE; + return MV_FALSE; +} +/******************************************************************************* +* mvBoardIsPexModuleConnected +* +* DESCRIPTION: +* Check if PEX module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsSwitchModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (boardId != RD_78460_NAS_ID) + DB(mvOsPrintf("mvBoardIsSwitchModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod & MV_BOARD_SWITCH) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsLvdsModuleConnected +* +* DESCRIPTION: +* Check if LVDS module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsLvdsModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if ( (boardId != DB_88F78XX0_BP_ID) && (boardId != DB_88F78XX0_BP_REV2_ID) ) + DB(mvOsPrintf("mvBoardIsLvdsModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardOtherMod & MV_BOARD_LVDS) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsLcdDviModuleConnected +* +* DESCRIPTION: +* Check if LVDS module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsLcdDviModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if ( (boardId != DB_88F78XX0_BP_ID) && (boardId != DB_88F78XX0_BP_REV2_ID) ) + DB(mvOsPrintf("mvBoardIsLcdDviModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod == MV_BOARD_LCD_DVI) + return MV_TRUE; + + return MV_FALSE; +} + + +/******************************************************************************* +* mvBoardIsGMIIModuleConnected +* +* DESCRIPTION: +* Check if GMII module is connected to the board. +* +* INPUT: +* None. +* +* OUTPUT: +* None +* +* RETURN: +* MV_TRUE / MV_FALSE +* +*******************************************************************************/ +MV_BOOL mvBoardIsGMIIModuleConnected(void) +{ + MV_U32 boardId = mvBoardIdGet(); + + if ( (boardId != DB_88F78XX0_BP_ID) && (boardId != DB_88F78XX0_BP_REV2_ID) ) + DB(mvOsPrintf("mvBoardIsGMIIModuleConnected: Unsupported board!\n")); + else if (BOARD_INFO(boardId)->pBoardModTypeValue->boardMppMod == MV_BOARD_MII_GMII) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTwsiMuxChannelSet +* +* DESCRIPTION: +* Set the channel number of the on-board TWSI mux. +* +* INPUT: +* chNum - The channel number to set. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiMuxChannelSet(MV_U8 muxChNum) +{ + static MV_U8 currChNum = 0xFF; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if (currChNum == muxChNum) + return MV_OK; + + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + twsiSlave.slaveAddr.address = mvBoardTwsiAddrGet(BOARD_TWSI_MUX, 0); + twsiSlave.slaveAddr.type = mvBoardTwsiAddrTypeGet(BOARD_TWSI_MUX, 0); + twsiSlave.validOffset = 0; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + muxChNum += 4; + return mvTwsiWrite(0, &twsiSlave, &muxChNum, 1); +} + +/******************************************************************************* +* mvBoardTwsiReadByteThruMux +* +* DESCRIPTION: +* Read a single byte from a TWSI device through the TWSI Mux. +* +* INPUT: +* muxChNum - The Twsi Mux channel number to read through. +* chNum - The TWSI channel number. +* pTwsiSlave - The TWSI slave address. +* data - Buffer to read into (1 byte). +* +* OUTPUT: +* None. +* +* RETURN: +* MV_STATUS - MV_OK, MV_ERROR. +* +*******************************************************************************/ +MV_STATUS mvBoardTwsiReadByteThruMux(MV_U8 muxChNum, MV_U8 chNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *data) +{ + MV_STATUS res; + + /* Set Mux channel */ + res = mvBoardTwsiMuxChannelSet(muxChNum); + if (res == MV_OK) + res = mvTwsiRead(chNum, pTwsiSlave, data, 1); + + return res; +} + +/******************************************************************************* +* mvBoardSerdesZ1ASupport - Support Z1A silicon serdes configuration +* +* DESCRIPTION: +* Default is fixed silicone Z1B. This routine should be called before +* calling the serdes initialization in ctrlEnvinit +* +* INPUT: +* None. +* OUTPUT: +* None. +* RETURN: +* SERDES configuration structure or NULL on error +* +*******************************************************************************/ +MV_VOID mvBoardSerdesZ1ASupport(void) +{ + gSerdesZ1AMode = 1; +} + +/******************************************************************************* +* mvBoardSmiScanModeGet - Get Switch SMI scan mode +* +* DESCRIPTION: +* This routine returns Switch SMI scan mode. +* +* INPUT: +* switchIdx - index of the switch. Only 0 is supported. +* +* OUTPUT: +* None. +* +* RETURN: +* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE) && (boardId < MV_MAX_BOARD_ID))) { + mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); + return -1; + } + + return BOARD_INFO(boardId)->pSwitchInfo[switchIdx].smiScanMode; +} +/******************************************************************************* +* mvBoardSledCpuNumGet - Get board SERDES configuration +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* SERDES configuration structure or NULL on error +* +*******************************************************************************/ +MV_U32 mvBoardSledCpuNumGet(MV_VOID) +{ + MV_U32 reg; + + reg = MV_REG_READ(GPP_DATA_IN_REG(0)); + + return ((reg & 0xF0000) >> 16); +} + +/******************************************************************************* +* mvBoardPexInfoGet - Get board PEX Info +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +*******************************************************************************/ +MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + switch (boardId) { + case DB_88F78XX0_BP_ID: + case RD_78460_SERVER_ID: + case RD_78460_SERVER_REV2_ID: + case DB_78X60_PCAC_ID: + case FPGA_88F78XX0_ID: + case DB_88F78XX0_BP_REV2_ID: + case RD_78460_NAS_ID: + case DB_784MP_GP_ID: + case RD_78460_CUSTOMER_ID: + case DB_78X60_AMC_ID: + case DB_78X60_PCAC_REV2_ID: +#ifdef CONFIG_SYNO_ARMADA_ARCH + case SYNO_AXP_4BAY_2BAY: + case SYNO_AXP_2BAY: + case SYNO_AXP_4BAY_RACK: +#endif + return &BOARD_INFO(boardId)->boardPexInfo; + break; + default: + DB(mvOsPrintf("mvBoardSerdesCfgGet: Unsupported board!\n")); + return NULL; + } +} diff --git a/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvLib.h b/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvLib.h new file mode 100755 index 000000000..77d40ce9a --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvLib.h @@ -0,0 +1,457 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvBoardEnvLibh +#define __INCmvBoardEnvLibh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +/* The below constant macros defines the board I2C EEPROM data offsets */ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + +/* DUART stuff for Tclk detection only */ +#define DUART_BAUD_RATE 115200 +#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ + +/* Voice devices assembly modes */ +#define DAISY_CHAIN_MODE 1 +#define DUAL_CHIP_SELECT_MODE 0 +#define INTERRUPT_TO_MPP 1 +#define INTERRUPT_TO_TDM 0 + +/* +#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS +*/ +#define BOARD_ETH_SWITCH_PORT_NUM 5 +#define MV_BOARD_MAX_USB_IF 3 +#define MV_BOARD_MAX_MPP 9 /* number of MPP conf registers */ +#define MV_BOARD_NAME_LEN 0x20 + +/* EPPROM Modules detection information */ + +#define MV_BOARD_EEPROM_MODULE_ADDR 0x50 +#define MV_BOARD_EEPROM_MODULE_ADDR_TYPE ADDR7_BIT + +#define MV_BOARD_PEX_MODULE_ADDR 0x23 +#define MV_BOARD_PEX_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_PEX_MODULE_ID 0 + +#define MV_BOARD_LVDS_MODULE_ADDR 0x21 +#define MV_BOARD_LVDS_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_LVDS_MODULE_ID 0 + +#define MV_BOARD_SETM_MODULE_ADDR 0x23 +#define MV_BOARD_SETM_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_SETM_MODULE_ID 1 + +#define MV_BOARD_MPP_MODULE_ADDR 0x20 +#define MV_BOARD_MPP_MODULE_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_LCD_DVI_MODULE_ID 0 +#define MV_BOARD_TDM_MODULE_ID 1 +#define MV_BOARD_MII_GMII_MODULE_ID 4 + +typedef enum { + BOARD_EPON_CONFIG, + BOARD_GPON_CONFIG, + BOARD_PON_NONE, + BOARD_PON_AUTO +} MV_BOARD_PON_CONFIG; + +typedef struct _boardData { + MV_U32 magic; + MV_U16 boardId; + MV_U8 boardVer; + MV_U8 boardRev; + MV_U32 reserved1; + MV_U32 reserved2; +} BOARD_DATA; + +typedef enum _devBoardMppGroupClass { + MV_BOARD_MPP_GROUP_1, + MV_BOARD_MPP_GROUP_2, + MV_BOARD_MPP_GROUP_3, + MV_BOARD_MAX_MPP_GROUP +} MV_BOARD_MPP_GROUP_CLASS; + +typedef enum _devBoardMppTypeClass { + MV_BOARD_AUTO = 0, + MV_BOARD_TDM_32CH, + MV_BOARD_LCD_DVI, + MV_BOARD_MII_GMII, + MV_BOARD_OTHER +} MV_BOARD_MPP_TYPE_CLASS; + +typedef enum _devBoardOtherTypeClass { + MV_BOARD_NONE = 0x00000000, + MV_BOARD_LVDS = 0x00000001, + MV_BOARD_PEX = 0x00000002, + MV_BOARD_SWITCH = 0x00000004, + MV_BOARD_SETM = 0x00000008, + MV_BOARD_UNKNOWN = 0x80000000 +} MV_BOARD_OTHER_TYPE_CLASS; + + +#define MV_BOARD_TDM MV_BOARD_TDM_32CH + +typedef struct _boardModuleTypeInfo { + MV_BOARD_MPP_TYPE_CLASS boardMppMod; + MV_BOARD_OTHER_TYPE_CLASS boardOtherMod; +} MV_BOARD_MODULE_TYPE_INFO; + +typedef enum _devBoardClass { + BOARD_DEV_NOR_FLASH, + BOARD_DEV_NAND_FLASH, + BOARD_DEV_SEVEN_SEG, + BOARD_DEV_FPGA, + BOARD_DEV_SRAM, + BOARD_DEV_SPI_FLASH, + BOARD_DEV_OTHER +} MV_BOARD_DEV_CLASS; + +typedef enum _devTwsiBoardClass { + BOARD_TWSI_RTC, + BOARD_DEV_TWSI_EXP, + BOARD_DEV_TWSI_SATR, + BOARD_TWSI_MUX, + BOARD_TWSI_OTHER +} MV_BOARD_TWSI_CLASS; + +typedef enum _devGppBoardClass { + BOARD_GPP_RTC, + BOARD_GPP_MV_SWITCH, + BOARD_GPP_USB_VBUS, + BOARD_GPP_USB_VBUS_EN, + BOARD_GPP_USB_OC, + BOARD_GPP_USB_HOST_DEVICE, + BOARD_GPP_REF_CLCK, + BOARD_GPP_VOIP_SLIC, + BOARD_GPP_LIFELINE, + BOARD_GPP_BUTTON, + BOARD_GPP_TS_BUTTON_C, + BOARD_GPP_TS_BUTTON_U, + BOARD_GPP_TS_BUTTON_D, + BOARD_GPP_TS_BUTTON_L, + BOARD_GPP_TS_BUTTON_R, + BOARD_GPP_POWER_BUTTON, + BOARD_GPP_RESTOR_BUTTON, + BOARD_GPP_WPS_BUTTON, + BOARD_GPP_HDD0_POWER, + BOARD_GPP_HDD1_POWER, + BOARD_GPP_FAN_POWER, + BOARD_GPP_RESET, + BOARD_GPP_POWER_ON_LED, + BOARD_GPP_HDD_POWER, + BOARD_GPP_SDIO_POWER, + BOARD_GPP_SDIO_DETECT, + BOARD_GPP_SDIO_WP, + BOARD_GPP_SWITCH_PHY_INT, + BOARD_GPP_TSU_DIRCTION, + BOARD_GPP_CONF, + BOARD_GPP_OTHER +} MV_BOARD_GPP_CLASS; + +typedef struct _devCsInfo { + MV_U8 deviceCS; + MV_U32 params; + MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ + MV_U8 devWidth; + MV_U8 busWidth; +} MV_DEV_CS_INFO; + +typedef struct _boardSwitchInfo { + MV_32 switchIrq; + MV_32 switchPort[BOARD_ETH_SWITCH_PORT_NUM]; + MV_32 cpuPort; + MV_32 connectedPort[MV_ETH_MAX_PORTS]; + MV_32 smiScanMode; + MV_32 quadPhyAddr; + MV_U32 forceLinkMask; /* Bitmask of switch ports to have force link (1Gbps) */ +} MV_BOARD_SWITCH_INFO; +typedef struct _boardLedInfo { + MV_U8 activeLedsNumber; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + MV_U8 *gppPinNum; /* Pointer to GPP values */ +} MV_BOARD_LED_INFO; + +typedef struct _boardGppInfo { + MV_BOARD_GPP_CLASS devClass; + MV_U8 gppPinNum; +} MV_BOARD_GPP_INFO; + +typedef struct _boardTwsiInfo { + MV_BOARD_TWSI_CLASS devClass; + MV_U8 twsiDevAddr; + MV_U8 twsiDevAddrType; +} MV_BOARD_TWSI_INFO; + +typedef enum _boardMacSpeed { + BOARD_MAC_SPEED_10M, + BOARD_MAC_SPEED_100M, + BOARD_MAC_SPEED_1000M, + BOARD_MAC_SPEED_AUTO +} MV_BOARD_MAC_SPEED; + +typedef struct _boardMacInfo { + MV_BOARD_MAC_SPEED boardMacSpeed; + MV_U8 boardEthSmiAddr; + MV_U16 LinkCryptPortAddr; + MV_U8 boardEthSmiAddr0; +} MV_BOARD_MAC_INFO; + +typedef struct _boardMppInfo { + MV_U32 mppGroup[MV_BOARD_MAX_MPP]; +} MV_BOARD_MPP_INFO; + +typedef struct { + MV_U8 spiCs; +} MV_BOARD_TDM_INFO; + +typedef struct _boardPexUnitCfg { + MV_PEX_UNIT_CFG pexCfg; + MV_U8 pexLaneStat[4]; /* 1: enabled, 2: disabled */ +} MV_BOARD_PEX_UNIT_CFG; + +typedef struct _boardPexInfo { + MV_PEXIF_INDX pexMapping[MV_PEX_MAX_IF]; + MV_BOARD_PEX_UNIT_CFG pexUnitCfg[MV_PEX_MAX_UNIT]; + MV_U32 boardPexIfNum; +} MV_BOARD_PEX_INFO; + +typedef enum { + BOARD_TDM_SLIC_880 = 0, + BOARD_TDM_SLIC_792, + BOARD_TDM_SLIC_3215, + BOARD_TDM_SLIC_OTHER, + BOARD_TDM_SLIC_COUNT +} MV_BOARD_TDM_SLIC_TYPE; + +typedef struct _boardInfo { + char boardName[MV_BOARD_NAME_LEN]; + MV_U8 numBoardMppTypeValue; + MV_BOARD_MODULE_TYPE_INFO *pBoardModTypeValue; + MV_U8 numBoardMppConfigValue; + MV_BOARD_MPP_INFO *pBoardMppConfigValue; + MV_U32 intsGppMaskLow; + MV_U32 intsGppMaskMid; + MV_U32 intsGppMaskHigh; + MV_U8 numBoardDeviceIf; + MV_DEV_CS_INFO *pDevCsInfo; + MV_U8 numBoardTwsiDev; + MV_BOARD_TWSI_INFO *pBoardTwsiDev; + MV_U8 numBoardMacInfo; + MV_BOARD_MAC_INFO *pBoardMacInfo; + MV_U8 numBoardGppInfo; + MV_BOARD_GPP_INFO *pBoardGppInfo; + MV_U8 activeLedsNumber; + MV_U8 *pLedGppPin; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + + MV_U8 pmuPwrUpPolarity; + MV_U32 pmuPwrUpDelay; + /* GPP values */ + MV_U32 gppOutEnValLow; + MV_U32 gppOutEnValMid; + MV_U32 gppOutEnValHigh; + MV_U32 gppOutValLow; + MV_U32 gppOutValMid; + MV_U32 gppOutValHigh; + MV_U32 gppPolarityValLow; + MV_U32 gppPolarityValMid; + MV_U32 gppPolarityValHigh; + + /* External Switch Configuration */ + MV_BOARD_SWITCH_INFO *pSwitchInfo; + MV_U32 switchInfoNum; + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + MV_U8 numBoardTdmInfo[BOARD_TDM_SLIC_COUNT]; + MV_BOARD_TDM_INFO *pBoardTdmInt2CsInfo[BOARD_TDM_SLIC_COUNT]; + MV_16 boardTdmInfoIndex; + + /* NAND init params */ + MV_U32 nandFlashReadParams; + MV_U32 nandFlashWriteParams; + MV_U32 nandFlashControl; + MV_BOARD_PEX_INFO boardPexInfo; /* filled in runtime */ + MV_U32 norFlashReadParams; + MV_U32 norFlashWriteParams; + +} MV_BOARD_INFO; + +/* For backward compatability with Legacy mode */ +#define mvBoardSwitchConnectedPortGet(port) (-1) +#define mvBoardIsSwitchConnected(port) (mvBoardSwitchConnectedPortGet(port) != -1) +/*#define mvBoardLinkStatusIrqGet(port) mvBoardSwitchIrqGet()*/ + +MV_VOID mvBoardEnvInit(MV_VOID); +MV_U16 mvBoardModelGet(MV_VOID); +MV_U16 mvBoardRevGet(MV_VOID); +MV_STATUS mvBoardNameGet(char *pNameBuff); +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInGmii(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInRgmii(MV_U32 ethPortNum); +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); + +MV_32 mvBoardQuadPhyAddr0Get(MV_U32 ethPortNum); +MV_32 mvBoardPhyLinkCryptPortAddrGet(MV_U32 ethPortNum); +MV_32 mvBoardSwitchCpuPortGet(MV_U32 switchIdx); +MV_32 mvBoardSmiScanModeGet(MV_U32 switchIdx); +MV_BOOL mvBoardSpecInitGet(MV_U32 *regOff, MV_U32 *data); +MV_U32 mvBoardTclkGet(MV_VOID); +MV_U32 mvBoardSysClkGet(MV_VOID); +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); +MV_VOID mvBoardDebugLed(MV_U32 hexNum); +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); +MV_VOID mvBoardReset(MV_VOID); +MV_32 mvBoardResetGpioPinGet(MV_VOID); +MV_32 mvBoardSDIOGpioPinGet(MV_BOARD_GPP_CLASS type); +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId); +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId); +MV_U32 mvBoardGpioIntMaskGet(MV_U32 gppGrp); +MV_32 mvBoardMppGet(MV_U32 mppGroupNum); +MV_U32 mvBoardGppConfigGet(void); +MV_32 mvBoardTdmSpiModeGet(MV_VOID); +MV_U8 mvBoardTdmDevicesCountGet(void); +MV_U8 mvBoardTdmSpiCsGet(MV_U8 devId); +MV_VOID mvBoardMppModuleTypePrint(MV_VOID); +MV_VOID mvBoardOtherModuleTypePrint(MV_VOID); +MV_BOOL mvBoardIsGbEPortConnected(MV_U32 ethPortNum); +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U8 mvBoardTwsiAddrTypeGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index); +MV_U8 mvBoardTwsiAddrGet(MV_BOARD_TWSI_CLASS twsiClass, MV_U32 index); +MV_32 mvBoardNandWidthGet(void); +MV_U32 mvBoardIdGet(MV_VOID); +MV_VOID mvBoardIdSet(MV_VOID); +MV_U32 mvBoardSledCpuNumGet(MV_VOID); + +MV_U8 mvBoardTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); +MV_STATUS mvBoardTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); +MV_U8 mvBoardFabFreqGet(MV_VOID); +MV_STATUS mvBoardFabFreqSet(MV_U8 freqVal); +MV_U8 mvBoardCpuFreqGet(MV_VOID); +MV_STATUS mvBoardCpuFreqSet(MV_U8 freqVal); +MV_U8 mvBoardCpuFreqModeGet(MV_VOID); +MV_STATUS mvBoardCpuFreqModeSet(MV_U8 freqVal); +MV_STATUS mvBoardFabFreqModeSet(MV_U8 freqVal); +MV_U8 mvBoardBootDevGet(MV_VOID); +MV_STATUS mvBoardBootDevSet(MV_U8 val); +MV_U8 mvBoardBootDevWidthGet(MV_VOID); +MV_STATUS mvBoardBootDevWidthSet(MV_U8 val); +MV_U8 mvBoardCpu0EndianessGet(MV_VOID); +MV_STATUS mvBoardCpu0EndianessSet(MV_U8 val); +MV_U8 mvBoardL2SizeGet(MV_VOID); +MV_STATUS mvBoardL2SizeSet(MV_U8 val); +MV_U8 mvBoardCpuCoresNumGet(MV_VOID); +MV_STATUS mvBoardCpuCoresNumSet(MV_U8 val); +MV_STATUS mvBoardConIdSet(MV_U16 conf); +MV_U16 mvBoardConfIdGet(MV_VOID); +MV_STATUS mvBoardPexCapabilitySet(MV_U16 conf); +MV_U16 mvBoardPexCapabilityGet(MV_VOID); +MV_STATUS mvBoardDramEccSet(MV_U16 conf); +MV_U16 mvBoardDramEccGet(MV_VOID); +MV_STATUS mvBoardDramBusWidthSet(MV_U16 conf); +MV_U16 mvBoardDramBusWidthGet(MV_VOID); +MV_U8 mvBoardAltFabFreqGet(MV_VOID); +MV_STATUS mvBoardAltFabFreqSet(MV_U8 freqVal); +MV_STATUS mvBoardMppModulesScan(void); +MV_STATUS mvBoardOtherModulesScan(void); +MV_BOOL mvBoardIsPexModuleConnected(void); +MV_BOOL mvBoardIsSetmModuleConnected(void); +MV_BOOL mvBoardIsSwitchModuleConnected(void); +MV_BOOL mvBoardIsLvdsModuleConnected(void); +MV_BOOL mvBoardIsLcdDviModuleConnected(void); +MV_BOOL mvBoardIsGMIIModuleConnected(void); +MV_STATUS mvBoardTwsiMuxChannelSet(MV_U8 muxChNum); +MV_STATUS mvBoardTwsiReadByteThruMux(MV_U8 muxChNum, MV_U8 chNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *data); +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); +MV_VOID mvBoardSerdesZ1ASupport(void); +MV_BOARD_PEX_INFO *mvBoardPexInfoGet(void); +MV_STATUS mvBoardConfIdSet(MV_U16 conf); +MV_U16 mvBoardPexModeGet(MV_VOID); +MV_STATUS mvBoardPexModeSet(MV_U16 conf); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* __INCmvBoardEnvLibh */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvSpec.c b/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvSpec.c new file mode 100755 index 000000000..1fc1afdd2 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvSpec.c @@ -0,0 +1,1725 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvCommon.h" +#include "mvBoardEnvLib.h" +#include "mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPexRegs.h" + +#define ARRSZ(x) (sizeof(x)/sizeof(x[0])) + +/**********************/ +/* ARMADA-XP DB BOARD */ +/**********************/ +#define DB_88F78XX0_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F78XX0_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define DB_88F78XX0_BOARD_NAND_CONTROL 0x01c00543 + +#define DB_88F78XX0_BOARD_NOR_READ_PARAMS 0x403E07CF +#define DB_88F78XX0_BOARD_NOR_WRITE_PARAMS 0x000F0F0F + +MV_U8 mvDbDisableModuleDetection = 0; + +MV_U8 db88f6781InfoBoardDebugLedIf[] = {26, 27, 48}; + +MV_BOARD_TWSI_INFO db88f78XX0InfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO db88f78XX0InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x0,0x0, 0x0,}, + {BOARD_MAC_SPEED_AUTO, 0x1,0x0, 0x1,}, + {BOARD_MAC_SPEED_AUTO, 0x19,0x800 , 0x18}, /* Port 1 */ + {BOARD_MAC_SPEED_AUTO, 0x1B,0x1800, 0x18} /* Port 3 */ +}; + +MV_BOARD_MODULE_TYPE_INFO db88f78XX0InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO db88f78XX0InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24}, /* from MPP map */ + {BOARD_GPP_RESET, 47}, +}; + +MV_DEV_CS_INFO db88f78XX0InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db88f78XX0InfoBoardMppConfigValue[] = { + { { + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_TDM_32CH */ + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + (DB_88F78XX0_MPP24_31 & 0x00000000) | 0x33333333, + (DB_88F78XX0_MPP32_39 & 0xFFFF0000) | 0x00003333, + (DB_88F78XX0_MPP40_47 & 0xFFFFF0FF) | 0x00000300, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_LCD_DVI */ + (DB_88F78XX0_MPP0_7 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP8_15 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP16_23 & 0x00000000) | 0x44444444, + (DB_88F78XX0_MPP24_31 & 0xFFFF0000) | 0x00004444, + DB_88F78XX0_MPP32_39, + (DB_88F78XX0_MPP40_47 & 0xFFFFFF00) | 0x00000044, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_MII_GMII */ + (DB_88F78XX0_MPP0_7 & 0x00000000) | 0x11111111, + (DB_88F78XX0_MPP8_15 & 0x00000000) | 0x11111111, + (DB_88F78XX0_MPP16_23 & 0x000000FF) | 0x11111100, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, + { { /* MV_BOARD_OTHER */ + DB_88F78XX0_MPP0_7, + DB_88F78XX0_MPP8_15, + DB_88F78XX0_MPP16_23, + DB_88F78XX0_MPP24_31, + DB_88F78XX0_MPP32_39, + DB_88F78XX0_MPP40_47, + DB_88F78XX0_MPP48_55, + DB_88F78XX0_MPP56_63, + DB_88F78XX0_MPP64_67, + } }, +}; + +MV_BOARD_TDM_INFO db88f78XX0Tdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO db88f78XX0Tdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO db88f78XX0Tdm3215[] = { {1} }; + +MV_BOARD_INFO db88f78XX0Info = { + .boardName = "DB-78460-BP", + .numBoardMppTypeValue = ARRSZ(db88f78XX0InfoBoardModTypeInfo), + .pBoardModTypeValue = db88f78XX0InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(db88f78XX0InfoBoardMppConfigValue), + .pBoardMppConfigValue = db88f78XX0InfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(db88f78XX0InfoBoardDeCsInfo), + .pDevCsInfo = db88f78XX0InfoBoardDeCsInfo, + .numBoardTwsiDev = ARRSZ(db88f78XX0InfoBoardTwsiDev), + .pBoardTwsiDev = db88f78XX0InfoBoardTwsiDev, + .numBoardMacInfo = ARRSZ(db88f78XX0InfoBoardMacInfo), + .pBoardMacInfo = db88f78XX0InfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(db88f78XX0InfoBoardGppInfo), + .pBoardGppInfo = db88f78XX0InfoBoardGppInfo, + .activeLedsNumber = ARRSZ(db88f6781InfoBoardDebugLedIf), + .pLedGppPin = db88f6781InfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = DB_88F78XX0_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_88F78XX0_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_88F78XX0_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_88F78XX0_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_88F78XX0_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_88F78XX0_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_88F78XX0_GPP_POL_LOW, + .gppPolarityValMid = DB_88F78XX0_GPP_POL_MID, + .gppPolarityValHigh = DB_88F78XX0_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {2, 6, 1}, + .pBoardTdmInt2CsInfo = {db88f78XX0Tdm880, + db88f78XX0Tdm792, + db88f78XX0Tdm3215}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = DB_88F78XX0_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = DB_88F78XX0_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = DB_88F78XX0_BOARD_NAND_CONTROL, + /* NOR init params */ + .norFlashReadParams = DB_88F78XX0_BOARD_NOR_READ_PARAMS, + .norFlashWriteParams = DB_88F78XX0_BOARD_NOR_WRITE_PARAMS +}; + +/***************************/ +/* ARMADA-XP DB REV2 BOARD */ +/***************************/ +#define DB_88F78XX0_REV2_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F78XX0_REV2_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define DB_88F78XX0_REV2_BOARD_NAND_CONTROL 0x01c00543 + +#define DB_88F78XX0_REV2_BOARD_NOR_READ_PARAMS 0x403E07CF +#define DB_88F78XX0_REV2_BOARD_NOR_WRITE_PARAMS 0x000F0F0F + +MV_U8 mvDbDisableModuleDetection_rev2 = 0; + +MV_U8 db88f6781InfoBoardDebugLedIf_rev2[] = {26, 27, 48}; + +MV_BOARD_TWSI_INFO db88f78XX0rev2InfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO db88f78XX0rev2InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x0,0x0 , 0x0 }, + {BOARD_MAC_SPEED_AUTO, 0x1,0x0 , 0x1 }, + {BOARD_MAC_SPEED_AUTO, 0x19,0x800 , 0x18}, /* Port 1 */ + {BOARD_MAC_SPEED_AUTO, 0x1B,0x1800, 0x18} /* Port 3 */ +}; + +MV_BOARD_MODULE_TYPE_INFO db88f78XX0rev2InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO db88f78XX0rev2InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ + /*{BOARD_GPP_RESET, 47},*/ +}; + +MV_DEV_CS_INFO db88f78XX0rev2InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db88f78XX0rev2InfoBoardMppConfigValue[] = { + { { + DB_88F78XX0_REV2_MPP0_7, + DB_88F78XX0_REV2_MPP8_15, + DB_88F78XX0_REV2_MPP16_23, + DB_88F78XX0_REV2_MPP24_31, + DB_88F78XX0_REV2_MPP32_39, + DB_88F78XX0_REV2_MPP40_47, + DB_88F78XX0_REV2_MPP48_55, + DB_88F78XX0_REV2_MPP56_63, + DB_88F78XX0_REV2_MPP64_67, + } }, + { { /* MV_BOARD_TDM_32CH */ + DB_88F78XX0_REV2_MPP0_7, + DB_88F78XX0_REV2_MPP8_15, + DB_88F78XX0_REV2_MPP16_23, + (DB_88F78XX0_REV2_MPP24_31 & 0x00000000) | 0x33333333, + (DB_88F78XX0_REV2_MPP32_39 & 0xFFFF0000) | 0x00003333, + (DB_88F78XX0_REV2_MPP40_47 & 0xFFFFF0FF) | 0x00000300, + DB_88F78XX0_REV2_MPP48_55, + DB_88F78XX0_REV2_MPP56_63, + DB_88F78XX0_REV2_MPP64_67, + } }, + { { /* MV_BOARD_LCD_DVI */ + (DB_88F78XX0_REV2_MPP0_7 & 0x00000000) | 0x44444444, + (DB_88F78XX0_REV2_MPP8_15 & 0x00000000) | 0x44444444, + (DB_88F78XX0_REV2_MPP16_23 & 0x00000000) | 0x44444444, + (DB_88F78XX0_REV2_MPP24_31 & 0xFFFF0000) | 0x00004444, + DB_88F78XX0_REV2_MPP32_39, + (DB_88F78XX0_REV2_MPP40_47 & 0xFFFFFF00) | 0x00000044, + DB_88F78XX0_REV2_MPP48_55, + DB_88F78XX0_REV2_MPP56_63, + DB_88F78XX0_REV2_MPP64_67, + } }, + { { /* MV_BOARD_MII_GMII */ + (DB_88F78XX0_REV2_MPP0_7 & 0x00000000) | 0x11111111, + (DB_88F78XX0_REV2_MPP8_15 & 0x00000000) | 0x11111111, + (DB_88F78XX0_REV2_MPP16_23 & 0x000000FF) | 0x11111100, + DB_88F78XX0_REV2_MPP24_31, + DB_88F78XX0_REV2_MPP32_39, + DB_88F78XX0_REV2_MPP40_47, + DB_88F78XX0_REV2_MPP48_55, + DB_88F78XX0_REV2_MPP56_63, + DB_88F78XX0_REV2_MPP64_67, + } }, + { { /* MV_BOARD_OTHER */ + DB_88F78XX0_REV2_MPP0_7, + DB_88F78XX0_REV2_MPP8_15, + DB_88F78XX0_REV2_MPP16_23, + DB_88F78XX0_REV2_MPP24_31, + DB_88F78XX0_REV2_MPP32_39, + DB_88F78XX0_REV2_MPP40_47, + DB_88F78XX0_REV2_MPP48_55, + DB_88F78XX0_REV2_MPP56_63, + DB_88F78XX0_REV2_MPP64_67, + } }, +}; + +MV_BOARD_TDM_INFO db88f78XX0rev2Tdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO db88f78XX0rev2Tdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO db88f78XX0rev2Tdm3215[] = { {1} }; + +MV_BOARD_INFO db88f78XX0rev2Info = { + .boardName = "DB-78460-BP rev 2.0", + .numBoardMppTypeValue = ARRSZ(db88f78XX0rev2InfoBoardModTypeInfo), + .pBoardModTypeValue = db88f78XX0rev2InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(db88f78XX0rev2InfoBoardMppConfigValue), + .pBoardMppConfigValue = db88f78XX0rev2InfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(db88f78XX0rev2InfoBoardDeCsInfo), + .pDevCsInfo = db88f78XX0rev2InfoBoardDeCsInfo, + .numBoardTwsiDev = ARRSZ(db88f78XX0rev2InfoBoardTwsiDev), + .pBoardTwsiDev = db88f78XX0rev2InfoBoardTwsiDev, + .numBoardMacInfo = ARRSZ(db88f78XX0rev2InfoBoardMacInfo), + .pBoardMacInfo = db88f78XX0rev2InfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(db88f78XX0rev2InfoBoardGppInfo), + .pBoardGppInfo = db88f78XX0rev2InfoBoardGppInfo, + .activeLedsNumber = ARRSZ(db88f6781InfoBoardDebugLedIf), + .pLedGppPin = db88f6781InfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = DB_88F78XX0_REV2_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_88F78XX0_REV2_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_88F78XX0_REV2_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_88F78XX0_REV2_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_88F78XX0_REV2_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_88F78XX0_REV2_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_88F78XX0_REV2_GPP_POL_LOW, + .gppPolarityValMid = DB_88F78XX0_REV2_GPP_POL_MID, + .gppPolarityValHigh = DB_88F78XX0_REV2_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {2, 6, 1}, + .pBoardTdmInt2CsInfo = {db88f78XX0rev2Tdm880, + db88f78XX0rev2Tdm792, + db88f78XX0rev2Tdm3215}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = DB_88F78XX0_REV2_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = DB_88F78XX0_REV2_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = DB_88F78XX0_REV2_BOARD_NAND_CONTROL, + /* NOR init params */ + .norFlashReadParams = DB_88F78XX0_REV2_BOARD_NOR_READ_PARAMS, + .norFlashWriteParams = DB_88F78XX0_REV2_BOARD_NOR_WRITE_PARAMS +}; + +/***************************/ +/* ARMADA-XP RD NAS BOARD */ +/***************************/ +#define RD_78460_NAS_BOARD_NAND_READ_PARAMS 0x000C0282 +#define RD_78460_NAS_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define RD_78460_NAS_BOARD_NAND_CONTROL 0x01c00543 + +#define RD_78460_NAS_BOARD_NOR_READ_PARAMS 0x403E07CF +#define RD_78460_NAS_BOARD_NOR_WRITE_PARAMS 0x000F0F0F + +MV_BOARD_MAC_INFO rd78460nasInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + /* speed will toggle to force link 1000 when SW module detected */ + {BOARD_MAC_SPEED_AUTO, 0x10,0x0, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x11,0x0, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x12,0x0, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x13,0x0, 0x10} +}; + +MV_BOARD_MODULE_TYPE_INFO rd78460nasInfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO rd78460nasInfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_RESET, 21} +}; + +MV_DEV_CS_INFO rd78460nasInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO rd78460nasInfoBoardMppConfigValue[] = { + { { + RD_78460_NAS_MPP0_7, + RD_78460_NAS_MPP8_15, + RD_78460_NAS_MPP16_23, + RD_78460_NAS_MPP24_31, + RD_78460_NAS_MPP32_39, + RD_78460_NAS_MPP40_47, + RD_78460_NAS_MPP48_55, + RD_78460_NAS_MPP56_63, + RD_78460_NAS_MPP64_67, + } } +}; + +MV_BOARD_INFO rd78460nasInfo = { + .boardName = "RD-AXP-NAS rev 1.0", + .numBoardMppTypeValue = ARRSZ(rd78460nasInfoBoardModTypeInfo), + .pBoardModTypeValue = rd78460nasInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(rd78460nasInfoBoardMppConfigValue), + .pBoardMppConfigValue = rd78460nasInfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(rd78460nasInfoBoardDeCsInfo), + .pDevCsInfo = rd78460nasInfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(rd78460nasInfoBoardMacInfo), + .pBoardMacInfo = rd78460nasInfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(rd78460nasInfoBoardGppInfo), + .pBoardGppInfo = rd78460nasInfoBoardGppInfo, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = RD_78460_NAS_GPP_OUT_ENA_LOW, + .gppOutEnValMid = RD_78460_NAS_GPP_OUT_ENA_MID, + .gppOutEnValHigh = RD_78460_NAS_GPP_OUT_ENA_HIGH, + .gppOutValLow = RD_78460_NAS_GPP_OUT_VAL_LOW, + .gppOutValMid = RD_78460_NAS_GPP_OUT_VAL_MID, + .gppOutValHigh = RD_78460_NAS_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = RD_78460_NAS_GPP_POL_LOW, + .gppPolarityValMid = RD_78460_NAS_GPP_POL_MID, + .gppPolarityValHigh = RD_78460_NAS_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = RD_78460_NAS_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = RD_78460_NAS_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = RD_78460_NAS_BOARD_NAND_CONTROL, + /* NOR init params */ + .norFlashReadParams = RD_78460_NAS_BOARD_NOR_READ_PARAMS, + .norFlashWriteParams = RD_78460_NAS_BOARD_NOR_WRITE_PARAMS +}; + +/*****************************/ +/* ARMADA-XP RD SERVER BOARD */ +/*****************************/ +#define RD_78460_BOARD_NAND_READ_PARAMS 0x000C0282 +#define RD_78460_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define RD_78460_BOARD_NAND_CONTROL 0x01c00543 + +MV_BOARD_MAC_INFO rd78460InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_1000M, 0x1, 0x0, 0x1}, + {BOARD_MAC_SPEED_1000M, 0x2, 0x0, 0x2}, + {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, 0x0}, + {BOARD_MAC_SPEED_1000M, 0x1B,0x0,0x18} +}; + +MV_BOARD_MODULE_TYPE_INFO rd78460InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_DEV_CS_INFO rd78460InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO rd78460InfoBoardMppConfigValue[] = { + { { + RD_78460_MPP0_7, + RD_78460_MPP8_15, + RD_78460_MPP16_23, + RD_78460_MPP24_31, + RD_78460_MPP32_39, + RD_78460_MPP40_47, + RD_78460_MPP48_55, + RD_78460_MPP56_63, + RD_78460_MPP64_67, + } } +}; + +MV_BOARD_INFO rd78460Info = { + .boardName = "RD-78460-SERVER", + .numBoardMppTypeValue = ARRSZ(rd78460InfoBoardModTypeInfo), + .pBoardModTypeValue = rd78460InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(rd78460InfoBoardMppConfigValue), + .pBoardMppConfigValue = rd78460InfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(rd78460InfoBoardDeCsInfo), + .pDevCsInfo = rd78460InfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(rd78460InfoBoardMacInfo), + .pBoardMacInfo = rd78460InfoBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = RD_78460_GPP_OUT_ENA_LOW, + .gppOutEnValMid = RD_78460_GPP_OUT_ENA_MID, + .gppOutEnValHigh = RD_78460_GPP_OUT_ENA_HIGH, + .gppOutValLow = RD_78460_GPP_OUT_VAL_LOW, + .gppOutValMid = RD_78460_GPP_OUT_VAL_MID, + .gppOutValHigh = RD_78460_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = RD_78460_GPP_POL_LOW, + .gppPolarityValMid = RD_78460_GPP_POL_MID, + .gppPolarityValHigh = RD_78460_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = RD_78460_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = RD_78460_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = RD_78460_BOARD_NAND_CONTROL +}; + + +/*****************************/ +/* ARMADA-XP RD SERVER REV2 BOARD */ +/*****************************/ +#define RD_78460_SERVER_REV2_BOARD_NAND_READ_PARAMS 0x000C0282 +#define RD_78460_SERVER_REV2_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define RD_78460_SERVER_REV2_BOARD_NAND_CONTROL 0x01c00543 + +MV_BOARD_MAC_INFO rd78460ServerRev2InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_1000M, 0x1,0x0, 0x1}, + {BOARD_MAC_SPEED_1000M, 0x2,0x0, 0x1}, + {BOARD_MAC_SPEED_AUTO, 0x0,0x0, 0x1}, + {BOARD_MAC_SPEED_1000M, 0x1B,0x0,0x18} +}; + +MV_BOARD_MODULE_TYPE_INFO rd78460ServerRev2InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_DEV_CS_INFO rd78460ServerRev2InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO rd78460ServerRev2InfoBoardMppConfigValue[] = { + { { + RD_78460_SERVER_REV2_MPP0_7, + RD_78460_SERVER_REV2_MPP8_15, + RD_78460_SERVER_REV2_MPP16_23, + RD_78460_SERVER_REV2_MPP24_31, + RD_78460_SERVER_REV2_MPP32_39, + RD_78460_SERVER_REV2_MPP40_47, + RD_78460_SERVER_REV2_MPP48_55, + RD_78460_SERVER_REV2_MPP56_63, + RD_78460_SERVER_REV2_MPP64_67, + } } +}; + +MV_BOARD_INFO rd78460ServerRev2Info = { + .boardName = "RD-78460-SERVER-REV2", + .numBoardMppTypeValue = ARRSZ(rd78460ServerRev2InfoBoardModTypeInfo), + .pBoardModTypeValue = rd78460ServerRev2InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(rd78460ServerRev2InfoBoardMppConfigValue), + .pBoardMppConfigValue = rd78460ServerRev2InfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(rd78460ServerRev2InfoBoardDeCsInfo), + .pDevCsInfo = rd78460ServerRev2InfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(rd78460ServerRev2InfoBoardMacInfo), + .pBoardMacInfo = rd78460ServerRev2InfoBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = RD_78460_SERVER_REV2_GPP_OUT_ENA_LOW, + .gppOutEnValMid = RD_78460_SERVER_REV2_GPP_OUT_ENA_MID, + .gppOutEnValHigh = RD_78460_SERVER_REV2_GPP_OUT_ENA_HIGH, + .gppOutValLow = RD_78460_SERVER_REV2_GPP_OUT_VAL_LOW, + .gppOutValMid = RD_78460_SERVER_REV2_GPP_OUT_VAL_MID, + .gppOutValHigh = RD_78460_SERVER_REV2_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = RD_78460_SERVER_REV2_GPP_POL_LOW, + .gppPolarityValMid = RD_78460_SERVER_REV2_GPP_POL_MID, + .gppPolarityValHigh = RD_78460_SERVER_REV2_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = RD_78460_SERVER_REV2_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = RD_78460_SERVER_REV2_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = RD_78460_SERVER_REV2_BOARD_NAND_CONTROL +}; +/***************************/ +/* ARMADA-XP DB PCAC BOARD */ +/***************************/ +#define DB_78X60_PCAC_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_78X60_PCAC_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define DB_78X60_PCAC_BOARD_NAND_CONTROL 0x01c00543 + +MV_U8 db78X60pcacInfoBoardDebugLedIf[] = {53, 54, 55, 56}; + +MV_BOARD_TWSI_INFO db78X60pcacInfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO db78X60pcacInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x3,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x2,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x0,0x0,0x0} /* Dummy */ +}; + + +MV_BOARD_MODULE_TYPE_INFO db78X60pcacInfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO db78X60pcacInfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 23} /* from MPP map */ +}; + +MV_DEV_CS_INFO db78X60pcacInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db78X60pcacInfoBoardMppConfigValue[] = { + { { + DB_78X60_PCAC_MPP0_7, + DB_78X60_PCAC_MPP8_15, + DB_78X60_PCAC_MPP16_23, + DB_78X60_PCAC_MPP24_31, + DB_78X60_PCAC_MPP32_39, + DB_78X60_PCAC_MPP40_47, + DB_78X60_PCAC_MPP48_55, + DB_78X60_PCAC_MPP56_63, + DB_78X60_PCAC_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO db78X60pcacTdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO db78X60pcacTdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO db78X60pcacTdm3215[] = { {1} }; + +MV_BOARD_INFO db78X60pcacInfo = { + .boardName = "DB-78460-PCAC", + .numBoardMppTypeValue = ARRSZ(db78X60pcacInfoBoardModTypeInfo), + .pBoardModTypeValue = db78X60pcacInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(db78X60pcacInfoBoardMppConfigValue), + .pBoardMppConfigValue = db78X60pcacInfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(db78X60pcacInfoBoardDeCsInfo), + .pDevCsInfo = db78X60pcacInfoBoardDeCsInfo, + .numBoardTwsiDev = ARRSZ(db78X60pcacInfoBoardTwsiDev), + .pBoardTwsiDev = db78X60pcacInfoBoardTwsiDev, + .numBoardMacInfo = ARRSZ(db78X60pcacInfoBoardMacInfo), + .pBoardMacInfo = db78X60pcacInfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(db78X60pcacInfoBoardGppInfo), + .pBoardGppInfo = db78X60pcacInfoBoardGppInfo, + .activeLedsNumber = ARRSZ(db78X60pcacInfoBoardDebugLedIf), + .pLedGppPin = db78X60pcacInfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = DB_78X60_PCAC_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_78X60_PCAC_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_78X60_PCAC_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_78X60_PCAC_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_78X60_PCAC_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_78X60_PCAC_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_78X60_PCAC_GPP_POL_LOW, + .gppPolarityValMid = DB_78X60_PCAC_GPP_POL_MID, + .gppPolarityValHigh = DB_78X60_PCAC_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {2, 6, 1}, + .pBoardTdmInt2CsInfo = {db78X60pcacTdm880, + db78X60pcacTdm792, + db78X60pcacTdm3215}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = DB_78X60_PCAC_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = DB_78X60_PCAC_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = DB_78X60_PCAC_BOARD_NAND_CONTROL +}; + +/********************************/ +/* ARMADA-XP DB PCAC REV2 BOARD */ +/********************************/ +#define DB_78X60_PCAC_REV2_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_78X60_PCAC_REV2_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define DB_78X60_PCAC_REV2_BOARD_NAND_CONTROL 0x01c00543 + +MV_U8 db78X60pcacrev2InfoBoardDebugLedIf[] = {53, 54, 55, 56}; + +MV_BOARD_MAC_INFO db78X60pcacrev2InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x3,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x2,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x0,0x0,0x0} /* Dummy */ +}; + + +MV_BOARD_MODULE_TYPE_INFO db78X60pcacrev2InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO db78X60pcacrev2InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 23} /* from MPP map */ +}; + +MV_DEV_CS_INFO db78X60pcacrev2InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db78X60pcacrev2InfoBoardMppConfigValue[] = { + { { + DB_78X60_PCAC_REV2_MPP0_7, + DB_78X60_PCAC_REV2_MPP8_15, + DB_78X60_PCAC_REV2_MPP16_23, + DB_78X60_PCAC_REV2_MPP24_31, + DB_78X60_PCAC_REV2_MPP32_39, + DB_78X60_PCAC_REV2_MPP40_47, + DB_78X60_PCAC_REV2_MPP48_55, + DB_78X60_PCAC_REV2_MPP56_63, + DB_78X60_PCAC_REV2_MPP64_67, + } } +}; + +MV_BOARD_INFO db78X60pcacrev2Info = { + .boardName = "DB-78460-PCAC-REV2", + .numBoardMppTypeValue = ARRSZ(db78X60pcacrev2InfoBoardModTypeInfo), + .pBoardModTypeValue = db78X60pcacrev2InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(db78X60pcacrev2InfoBoardMppConfigValue), + .pBoardMppConfigValue = db78X60pcacrev2InfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(db78X60pcacrev2InfoBoardDeCsInfo), + .pDevCsInfo = db78X60pcacrev2InfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(db78X60pcacrev2InfoBoardMacInfo), + .pBoardMacInfo = db78X60pcacrev2InfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(db78X60pcacrev2InfoBoardGppInfo), + .pBoardGppInfo = db78X60pcacrev2InfoBoardGppInfo, + .activeLedsNumber = ARRSZ(db78X60pcacrev2InfoBoardDebugLedIf), + .pLedGppPin = db78X60pcacrev2InfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = DB_78X60_PCAC_REV2_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_78X60_PCAC_REV2_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_78X60_PCAC_REV2_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_78X60_PCAC_REV2_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_78X60_PCAC_REV2_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_78X60_PCAC_REV2_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_78X60_PCAC_REV2_GPP_POL_LOW, + .gppPolarityValMid = DB_78X60_PCAC_REV2_GPP_POL_MID, + .gppPolarityValHigh = DB_78X60_PCAC_REV2_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = DB_78X60_PCAC_REV2_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = DB_78X60_PCAC_REV2_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = DB_78X60_PCAC_REV2_BOARD_NAND_CONTROL +}; + +/************************/ +/* ARMADA-XP FPGA BOARD */ +/************************/ +#define FPGA_88F78XX0_BOARD_NAND_READ_PARAMS 0x000C0282 +#define FPGA_88F78XX0_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define FPGA_88F78XX0_BOARD_NAND_CONTROL 0x01c00543 + +MV_BOARD_TWSI_INFO fpga88f78XX0InfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO fpga88f78XX0InfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x2,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x3,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x4,0x0,0x0} +}; + +MV_BOARD_MODULE_TYPE_INFO fpga88f78XX0InfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO fpga88f78XX0InfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ +}; + +MV_DEV_CS_INFO fpga88f78XX0InfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO fpga88f78XX0InfoBoardMppConfigValue[] = { + { { + FPGA_88F78XX0_MPP0_7, + FPGA_88F78XX0_MPP8_15, + FPGA_88F78XX0_MPP16_23, + FPGA_88F78XX0_MPP24_31, + FPGA_88F78XX0_MPP32_39, + FPGA_88F78XX0_MPP40_47, + FPGA_88F78XX0_MPP48_55, + FPGA_88F78XX0_MPP56_63, + FPGA_88F78XX0_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO fpga88f78XX0Tdm880[] = { {1}, {2} }; +MV_BOARD_TDM_INFO fpga88f78XX0Tdm792[] = { {1}, {2}, {3}, {4}, {6}, {7} }; +MV_BOARD_TDM_INFO fpga88f78XX0Tdm3215[] = { {1} }; + +MV_BOARD_INFO fpga88f78XX0Info = { + .boardName = "FPGA-88F78XX0", + .numBoardMppTypeValue = ARRSZ(fpga88f78XX0InfoBoardModTypeInfo), + .pBoardModTypeValue = fpga88f78XX0InfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(fpga88f78XX0InfoBoardMppConfigValue), + .pBoardMppConfigValue = fpga88f78XX0InfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(fpga88f78XX0InfoBoardDeCsInfo), + .pDevCsInfo = fpga88f78XX0InfoBoardDeCsInfo, + .numBoardTwsiDev = ARRSZ(fpga88f78XX0InfoBoardTwsiDev), + .pBoardTwsiDev = fpga88f78XX0InfoBoardTwsiDev, + .numBoardMacInfo = ARRSZ(fpga88f78XX0InfoBoardMacInfo), + .pBoardMacInfo = fpga88f78XX0InfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(fpga88f78XX0InfoBoardGppInfo), + .pBoardGppInfo = fpga88f78XX0InfoBoardGppInfo, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = FPGA_88F78XX0_GPP_OUT_ENA_LOW, + .gppOutEnValMid = FPGA_88F78XX0_GPP_OUT_ENA_MID, + .gppOutEnValHigh = FPGA_88F78XX0_GPP_OUT_ENA_HIGH, + .gppOutValLow = FPGA_88F78XX0_GPP_OUT_VAL_LOW, + .gppOutValMid = FPGA_88F78XX0_GPP_OUT_VAL_MID, + .gppOutValHigh = FPGA_88F78XX0_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = FPGA_88F78XX0_GPP_POL_LOW, + .gppPolarityValMid = FPGA_88F78XX0_GPP_POL_MID, + .gppPolarityValHigh = FPGA_88F78XX0_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = { 2, 6, 1 }, + .pBoardTdmInt2CsInfo = { fpga88f78XX0Tdm880, + fpga88f78XX0Tdm792, + fpga88f78XX0Tdm3215 + }, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = FPGA_88F78XX0_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = FPGA_88F78XX0_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = FPGA_88F78XX0_BOARD_NAND_CONTROL +}; + +/***************************/ +/* ARMADA-XP AMC BOARD */ +/***************************/ +#define DB_78X60_AMC_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_78X60_AMC_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define DB_78X60_AMC_BOARD_NAND_CONTROL 0x01c00543 + +MV_U8 db78X60amcInfoBoardDebugLedIf[] = {53, 54, 55, 56}; /* 7 segment MPPs*/ + +MV_BOARD_TWSI_INFO db78X60amcInfoBoardTwsiDev[] = { + /* No TWSI devices on board*/ +}; + +MV_BOARD_MAC_INFO db78X60amcInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0xF,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0xE,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x0,0x0,0x0} +}; + + +MV_BOARD_MODULE_TYPE_INFO db78X60amcInfoBoardModTypeInfo[] = { + /* No Modules */ +}; + +MV_BOARD_GPP_INFO db78X60amcInfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 46} /* from MPP map */ +}; + +MV_DEV_CS_INFO db78X60amcInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO db78X60amcInfoBoardMppConfigValue[] = { + { { + DB_78X60_AMC_MPP0_7, + DB_78X60_AMC_MPP8_15, + DB_78X60_AMC_MPP16_23, + DB_78X60_AMC_MPP24_31, + DB_78X60_AMC_MPP32_39, + DB_78X60_AMC_MPP40_47, + DB_78X60_AMC_MPP48_55, + DB_78X60_AMC_MPP56_63, + DB_78X60_AMC_MPP64_67, + } } +}; + +MV_BOARD_TDM_INFO db78X60amcTdm880[] = {}; +MV_BOARD_TDM_INFO db78X60amcTdm792[] = {}; +MV_BOARD_TDM_INFO db78X60amcTdm3215[] = {}; + +MV_BOARD_INFO db78X60amcInfo = { + .boardName = "DB-78460-AMC", + .numBoardMppTypeValue = ARRSZ(db78X60amcInfoBoardModTypeInfo), + .pBoardModTypeValue = db78X60amcInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(db78X60amcInfoBoardMppConfigValue), + .pBoardMppConfigValue = db78X60amcInfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(db78X60amcInfoBoardDeCsInfo), + .pDevCsInfo = db78X60amcInfoBoardDeCsInfo, + .numBoardTwsiDev = ARRSZ(db78X60amcInfoBoardTwsiDev), + .pBoardTwsiDev = db78X60amcInfoBoardTwsiDev, + .numBoardMacInfo = ARRSZ(db78X60amcInfoBoardMacInfo), + .pBoardMacInfo = db78X60amcInfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(db78X60amcInfoBoardGppInfo), + .pBoardGppInfo = db78X60amcInfoBoardGppInfo, + .activeLedsNumber = ARRSZ(db78X60amcInfoBoardDebugLedIf), + .pLedGppPin = db78X60amcInfoBoardDebugLedIf, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = DB_78X60_AMC_GPP_OUT_ENA_LOW, + .gppOutEnValMid = DB_78X60_AMC_GPP_OUT_ENA_MID, + .gppOutEnValHigh = DB_78X60_AMC_GPP_OUT_ENA_HIGH, + .gppOutValLow = DB_78X60_AMC_GPP_OUT_VAL_LOW, + .gppOutValMid = DB_78X60_AMC_GPP_OUT_VAL_MID, + .gppOutValHigh = DB_78X60_AMC_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = DB_78X60_AMC_GPP_POL_LOW, + .gppPolarityValMid = DB_78X60_AMC_GPP_POL_MID, + .gppPolarityValHigh = DB_78X60_AMC_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = DB_78X60_AMC_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = DB_78X60_AMC_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = DB_78X60_AMC_BOARD_NAND_CONTROL +}; + +/*********************************************************************************/ + +/***************************/ +/* ARMADA-XP RD GP BOARD */ +/***************************/ +#define RD_78460_GP_BOARD_NAND_READ_PARAMS 0x000C0282 +#define RD_78460_GP_BOARD_NAND_WRITE_PARAMS 0x00010305 + +#define RD_78460_GP_BOARD_NAND_CONTROL 0x01c00543 + +#define RD_78460_GP_BOARD_NOR_READ_PARAMS 0x403E07CF +#define RD_78460_GP_BOARD_NOR_WRITE_PARAMS 0x000F0F0F + + +MV_BOARD_TWSI_INFO rd78460gpInfoBoardTwsiDev[] = { + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT} +}; + +MV_BOARD_MAC_INFO rd78460gpInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + /* speed will toggle to force link 1000 when SW module detected */ + {BOARD_MAC_SPEED_AUTO, 0x10,0x0000, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x11,0x0800, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x12,0x1000, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x13,0x1800, 0x10} +}; + +MV_BOARD_MODULE_TYPE_INFO rd78460gpInfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO rd78460gpInfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_RESET, 21} +}; + +MV_DEV_CS_INFO rd78460gpInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +#endif +#if defined(MV_INCLUDE_NOR) + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16} /* NOR DEV */ +#endif +}; + +MV_BOARD_MPP_INFO rd78460gpInfoBoardMppConfigValue[] = { + { { + RD_78460_GP_MPP0_7, + RD_78460_GP_MPP8_15, + RD_78460_GP_MPP16_23, + RD_78460_GP_MPP24_31, + RD_78460_GP_MPP32_39, + RD_78460_GP_MPP40_47, + RD_78460_GP_MPP48_55, + RD_78460_GP_MPP56_63, + RD_78460_GP_MPP64_67, + } } +}; + +MV_BOARD_INFO rd78460gpInfo = { + .boardName = "RD-AXP-GP rev 1.0", + .numBoardMppTypeValue = ARRSZ(rd78460gpInfoBoardModTypeInfo), + .pBoardModTypeValue = rd78460gpInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(rd78460gpInfoBoardMppConfigValue), + .pBoardMppConfigValue = rd78460gpInfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(rd78460gpInfoBoardDeCsInfo), + .pDevCsInfo = rd78460gpInfoBoardDeCsInfo, + .numBoardTwsiDev = ARRSZ(rd78460gpInfoBoardTwsiDev), + .pBoardTwsiDev = rd78460gpInfoBoardTwsiDev, + .numBoardMacInfo = ARRSZ(rd78460gpInfoBoardMacInfo), + .pBoardMacInfo = rd78460gpInfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(rd78460gpInfoBoardGppInfo), + .pBoardGppInfo = rd78460gpInfoBoardGppInfo, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = RD_78460_GP_GPP_OUT_ENA_LOW, + .gppOutEnValMid = RD_78460_GP_GPP_OUT_ENA_MID, + .gppOutEnValHigh = RD_78460_GP_GPP_OUT_ENA_HIGH, + .gppOutValLow = RD_78460_GP_GPP_OUT_VAL_LOW, + .gppOutValMid = RD_78460_GP_GPP_OUT_VAL_MID, + .gppOutValHigh = RD_78460_GP_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = RD_78460_GP_GPP_POL_LOW, + .gppPolarityValMid = RD_78460_GP_GPP_POL_MID, + .gppPolarityValHigh = RD_78460_GP_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = RD_78460_GP_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = RD_78460_GP_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = RD_78460_GP_BOARD_NAND_CONTROL, + /* NOR init params */ + .norFlashReadParams = RD_78460_GP_BOARD_NOR_READ_PARAMS, + .norFlashWriteParams = RD_78460_GP_BOARD_NOR_WRITE_PARAMS +}; + +/***************************/ +/* ARMADA-XP CUSTOMER BOARD */ +/***************************/ +#define RD_78460_CUSTOMER_BOARD_NAND_READ_PARAMS 0x000C0282 +#define RD_78460_CUSTOMER_BOARD_NAND_WRITE_PARAMS 0x00010305 +/*NAND care support for small page chips*/ +#define RD_78460_CUSTOMER_BOARD_NAND_CONTROL 0x01c00543 + +#define RD_78460_CUSTOMER_BOARD_NOR_READ_PARAMS 0x403E07CF +#define RD_78460_CUSTOMER_BOARD_NOR_WRITE_PARAMS 0x000F0F0F + +MV_BOARD_MAC_INFO rd78460customerInfoBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x10,0x0000, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x11,0x0800, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x12,0x1000, 0x10}, + {BOARD_MAC_SPEED_AUTO, 0x13,0x1800, 0x10} +}; + +MV_BOARD_MODULE_TYPE_INFO rd78460customerInfoBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; +/*********************************************************************************/ + + +MV_BOARD_GPP_INFO rd78460customerInfoBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_RESET, 21} +}; + +MV_DEV_CS_INFO rd78460customerInfoBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ +#if defined(MV_INCLUDE_SPI) + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8} /* SPI DEV */ +#endif +}; + +MV_BOARD_MPP_INFO rd78460customerInfoBoardMppConfigValue[] = { + { { + RD_78460_CUSTOMER_MPP0_7, + RD_78460_CUSTOMER_MPP8_15, + RD_78460_CUSTOMER_MPP16_23, + RD_78460_CUSTOMER_MPP24_31, + RD_78460_CUSTOMER_MPP32_39, + RD_78460_CUSTOMER_MPP40_47, + RD_78460_CUSTOMER_MPP48_55, + RD_78460_CUSTOMER_MPP56_63, + RD_78460_CUSTOMER_MPP64_67, + } } +}; + +MV_BOARD_INFO rd78460customerInfo = { + .boardName = "RD-AXP-CUSTOMER", + .numBoardMppTypeValue = ARRSZ(rd78460customerInfoBoardModTypeInfo), + .pBoardModTypeValue = rd78460customerInfoBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(rd78460customerInfoBoardMppConfigValue), + .pBoardMppConfigValue = rd78460customerInfoBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(rd78460customerInfoBoardDeCsInfo), + .pDevCsInfo = rd78460customerInfoBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(rd78460customerInfoBoardMacInfo), + .pBoardMacInfo = rd78460customerInfoBoardMacInfo, + .numBoardGppInfo = ARRSZ(rd78460customerInfoBoardGppInfo), + .pBoardGppInfo = rd78460customerInfoBoardGppInfo, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = RD_78460_CUSTOMER_GPP_OUT_ENA_LOW, + .gppOutEnValMid = RD_78460_CUSTOMER_GPP_OUT_ENA_MID, + .gppOutEnValHigh = RD_78460_CUSTOMER_GPP_OUT_ENA_HIGH, + .gppOutValLow = RD_78460_CUSTOMER_GPP_OUT_VAL_LOW, + .gppOutValMid = RD_78460_CUSTOMER_GPP_OUT_VAL_MID, + .gppOutValHigh = RD_78460_CUSTOMER_GPP_OUT_VAL_HIGH, + .gppPolarityValLow = RD_78460_CUSTOMER_GPP_POL_LOW, + .gppPolarityValMid = RD_78460_CUSTOMER_GPP_POL_MID, + .gppPolarityValHigh = RD_78460_CUSTOMER_GPP_POL_HIGH, + + /* External Switch Configuration */ + .pSwitchInfo = NULL, + .switchInfoNum = 0, + + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = RD_78460_CUSTOMER_BOARD_NAND_READ_PARAMS, + .nandFlashWriteParams = RD_78460_CUSTOMER_BOARD_NAND_WRITE_PARAMS, + .nandFlashControl = RD_78460_CUSTOMER_BOARD_NAND_CONTROL, + /* NOR init params */ + .norFlashReadParams = RD_78460_CUSTOMER_BOARD_NOR_READ_PARAMS, + .norFlashWriteParams = RD_78460_CUSTOMER_BOARD_NOR_WRITE_PARAMS +}; +/*********************************************************************************/ + +#ifdef CONFIG_SYNO_ARMADA_ARCH +/************************************************************************************* + * + * Synology customized board + * +**/ + +/***************************/ +/* ARMADA-XP B0 4Bay */ +/***************************/ + +MV_BOARD_MAC_INFO Syno78230AxpBoardMacInfo[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1,0x0,0x0}, + {BOARD_MAC_SPEED_AUTO, 0x0,0x0,0x0}, +}; + +MV_BOARD_MODULE_TYPE_INFO Syno78230AxpBoardModTypeInfo[] = { + { + .boardMppMod = MV_BOARD_AUTO, + .boardOtherMod = MV_BOARD_NONE + } +}; + +MV_BOARD_GPP_INFO Syno78230AxpBoardGppInfo[] = { + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {BOARD_GPP_USB_VBUS, 24} /* from MPP map */ + /*{BOARD_GPP_RESET, 47},*/ +}; + +MV_DEV_CS_INFO Syno78230AxpBoardDeCsInfo[] = { + /*{deviceCS, params, devType, devWidth, busWidth }*/ + {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8}, /* SPI DEV */ +}; + +#define SYNOAXP_4BAY_MPP0_7 0x11111111 +#define SYNOAXP_4BAY_MPP8_15 0x22221111 +#define SYNOAXP_4BAY_MPP16_23 0x22222222 +#define SYNOAXP_4BAY_MPP24_31 0x00000000 +#define SYNOAXP_4BAY_MPP32_39 0x11110000 +#define SYNOAXP_4BAY_MPP40_47 0x00004000 +#define SYNOAXP_4BAY_MPP48_55 0x00000000 +#define SYNOAXP_4BAY_MPP56_63 0x00000000 +#define SYNOAXP_4BAY_MPP64_67 0x00000000 + +MV_BOARD_MPP_INFO Syno78230AxpBoardMppConfigValue[] = { + { { + SYNOAXP_4BAY_MPP0_7, + SYNOAXP_4BAY_MPP8_15, + SYNOAXP_4BAY_MPP16_23, + SYNOAXP_4BAY_MPP24_31, + SYNOAXP_4BAY_MPP32_39, + SYNOAXP_4BAY_MPP40_47, + SYNOAXP_4BAY_MPP48_55, + SYNOAXP_4BAY_MPP56_63, + SYNOAXP_4BAY_MPP64_67, + } }, +}; + +MV_BOARD_INFO Syno78230AxpInfo = { + .boardName = "Synology AXP 78230", + .numBoardMppTypeValue = ARRSZ(Syno78230AxpBoardModTypeInfo), + .pBoardModTypeValue = Syno78230AxpBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(Syno78230AxpBoardMppConfigValue), + .pBoardMppConfigValue = Syno78230AxpBoardMppConfigValue, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(Syno78230AxpBoardDeCsInfo), + .pDevCsInfo = Syno78230AxpBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(Syno78230AxpBoardMacInfo), + .pBoardMacInfo = Syno78230AxpBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = (~(BIT25 | BIT30)), + .gppOutEnValMid = (~(BIT10 | BIT12 | BIT13 | BIT14 | BIT15)), + .gppOutEnValHigh = (~(0x0)), + .gppOutValLow = BIT25 | BIT30, + .gppOutValMid = BIT10, + .gppOutValHigh = 0x0, + .gppPolarityValLow = 0x0, + .gppPolarityValMid = 0x0, + .gppPolarityValHigh = 0x0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = 0, + .nandFlashWriteParams = 0, + .nandFlashControl = 0, + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0 +}; + +/***************************/ +/* ARMADA-XP B0 2Bay */ +/***************************/ + +MV_BOARD_MAC_INFO Syno78230AxpBoardMacInfo_2bay[] = { + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {BOARD_MAC_SPEED_AUTO, 0x1,0x0,0x0}, +}; + +#define SYNOAXP_2BAY_MPP0_7 0x00000000 +#define SYNOAXP_2BAY_MPP8_15 0x00000000 +#define SYNOAXP_2BAY_MPP16_23 0x00000000 +#define SYNOAXP_2BAY_MPP24_31 0x00000000 // disable MPP[24,25] sata present, enable in synobios +#define SYNOAXP_2BAY_MPP32_39 0x11110000 +#define SYNOAXP_2BAY_MPP40_47 0x00004000 +#define SYNOAXP_2BAY_MPP48_55 0x00000000 +#define SYNOAXP_2BAY_MPP56_63 0x00000000 +#define SYNOAXP_2BAY_MPP64_67 0x00000000 + +MV_BOARD_MPP_INFO Syno78230AxpBoardMppConfigValue_2bay[] = { + { { + SYNOAXP_2BAY_MPP0_7, + SYNOAXP_2BAY_MPP8_15, + SYNOAXP_2BAY_MPP16_23, + SYNOAXP_2BAY_MPP24_31, + SYNOAXP_2BAY_MPP32_39, + SYNOAXP_2BAY_MPP40_47, + SYNOAXP_2BAY_MPP48_55, + SYNOAXP_2BAY_MPP56_63, + SYNOAXP_2BAY_MPP64_67, + } }, +}; + +MV_BOARD_INFO Syno78230AxpInfo_2bay = { + .boardName = "Synology AXP 78230 2 bay", + .numBoardMppTypeValue = ARRSZ(Syno78230AxpBoardModTypeInfo), + .pBoardModTypeValue = Syno78230AxpBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(Syno78230AxpBoardMppConfigValue_2bay), + .pBoardMppConfigValue = Syno78230AxpBoardMppConfigValue_2bay, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(Syno78230AxpBoardDeCsInfo), + .pDevCsInfo = Syno78230AxpBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(Syno78230AxpBoardMacInfo_2bay), + .pBoardMacInfo = Syno78230AxpBoardMacInfo_2bay, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* PMU Power */ + .pmuPwrUpPolarity = 0, + .pmuPwrUpDelay = 80000, + + /* GPP values */ + .gppOutEnValLow = (~(BIT24 | BIT25)), /* low active */ + .gppOutEnValMid = (~(BIT12 | BIT13 | BIT14)), + .gppOutEnValHigh = (~(0x0)), + .gppOutValLow = 0x0, + .gppOutValMid = BIT12, + .gppOutValHigh = 0x0, + .gppPolarityValLow = 0x0, + .gppPolarityValMid = 0x0, + .gppPolarityValHigh = 0x0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = 0, + .nandFlashWriteParams = 0, + .nandFlashControl = 0, + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0 +}; + +/***************************/ +/* ARMADA-XP B0 4Bay rack */ +/***************************/ + +#define SYNOAXP_4_RACK_MPP0_7 0x11111111 +#define SYNOAXP_4_RACK_MPP8_15 0x22221111 +#define SYNOAXP_4_RACK_MPP16_23 0x22222222 +#define SYNOAXP_4_RACK_MPP24_31 0x00000000 +#define SYNOAXP_4_RACK_MPP32_39 0x11110000 +#define SYNOAXP_4_RACK_MPP40_47 0x00004000 +#define SYNOAXP_4_RACK_MPP48_55 0x00000000 +#define SYNOAXP_4_RACK_MPP56_63 0x00000000 +#define SYNOAXP_4_RACK_MPP64_67 0x00000000 + +MV_BOARD_MPP_INFO Syno78230AxpBoardMppConfigValue_4bay_rack[] = { + { { + SYNOAXP_4_RACK_MPP0_7, + SYNOAXP_4_RACK_MPP8_15, + SYNOAXP_4_RACK_MPP16_23, + SYNOAXP_4_RACK_MPP24_31, + SYNOAXP_4_RACK_MPP32_39, + SYNOAXP_4_RACK_MPP40_47, + SYNOAXP_4_RACK_MPP48_55, + SYNOAXP_4_RACK_MPP56_63, + SYNOAXP_4_RACK_MPP64_67, + } }, +}; + +MV_BOARD_INFO Syno78230AxpInfo_4bay_rack = { + .boardName = "Synology AXP 78230 4-bay rack", + .numBoardMppTypeValue = ARRSZ(Syno78230AxpBoardModTypeInfo), + .pBoardModTypeValue = Syno78230AxpBoardModTypeInfo, + .numBoardMppConfigValue = ARRSZ(Syno78230AxpBoardMppConfigValue_4bay_rack), + .pBoardMppConfigValue = Syno78230AxpBoardMppConfigValue_4bay_rack, + .intsGppMaskLow = 0, + .intsGppMaskMid = 0, + .intsGppMaskHigh = 0, + .numBoardDeviceIf = ARRSZ(Syno78230AxpBoardDeCsInfo), + .pDevCsInfo = Syno78230AxpBoardDeCsInfo, + .numBoardTwsiDev = 0, + .pBoardTwsiDev = NULL, + .numBoardMacInfo = ARRSZ(Syno78230AxpBoardMacInfo), + .pBoardMacInfo = Syno78230AxpBoardMacInfo, + .numBoardGppInfo = 0, + .pBoardGppInfo = NULL, + .activeLedsNumber = 0, + .pLedGppPin = NULL, + .ledsPolarity = 0, + + /* GPP values */ + .gppOutEnValLow = (~(0x0)), /* low active */ + .gppOutEnValMid = (~(BIT8 | BIT13 | BIT15)), + .gppOutEnValHigh = (~(0x0)), + .gppOutValLow = 0x0, + .gppOutValMid = BIT15, + .gppOutValHigh = 0x0, + .gppPolarityValLow = 0x0, + .gppPolarityValMid = 0x0, + .gppPolarityValHigh = 0x0, + + /* TDM configuration */ + /* We hold a different configuration array for each possible slic that + ** can be connected to board. + ** When modules are scanned, then we select the index of the relevant + ** slic's information array. + ** For RD and Customers boards we only need to initialize a single + ** entry of the arrays below, and set the boardTdmInfoIndex to 0. + */ + .numBoardTdmInfo = {}, + .pBoardTdmInt2CsInfo = {}, + .boardTdmInfoIndex = -1, + + /* NAND init params */ + .nandFlashReadParams = 0, + .nandFlashWriteParams = 0, + .nandFlashControl = 0, + /* NOR init params */ + .norFlashReadParams = 0, + .norFlashWriteParams = 0 +}; +#endif + +MV_BOARD_INFO *boardInfoTbl[] = { + &db88f78XX0Info, + &rd78460Info, + &db78X60pcacInfo, + &fpga88f78XX0Info, + &db88f78XX0rev2Info, + &rd78460nasInfo, + &db78X60amcInfo, + &db78X60pcacrev2Info, + &rd78460ServerRev2Info, + &rd78460gpInfo, + &rd78460customerInfo +#ifdef CONFIG_SYNO_ARMADA_ARCH + ,NULL + ,NULL + ,NULL + ,NULL + ,NULL + ,&Syno78230AxpInfo + ,&Syno78230AxpInfo_2bay + ,&Syno78230AxpInfo_4bay_rack +#endif +}; diff --git a/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvSpec.h b/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvSpec.h new file mode 100755 index 000000000..b9cf65e3e --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/boardEnv/mvBoardEnvSpec.h @@ -0,0 +1,584 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoardEnvSpech +#define __INCmvBoardEnvSpech + +#include "mvSysHwConfig.h" + +/* For future use */ +#define BD_ID_DATA_START_OFFS 0x0 +#define BD_DETECT_SEQ_OFFS 0x0 +#define BD_SYS_NUM_OFFS 0x4 +#define BD_NAME_OFFS 0x8 + +/* I2C bus addresses TODO - take from board design */ +#define MV_BOARD_DIMM0_I2C_ADDR 0x56 +#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM1_I2C_ADDR 0x57 +#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 + + +/* Board specific configuration */ +/* ============================ */ + +/* boards ID numbers */ +#define BOARD_ID_BASE 0x0 + +/* New board ID numbers */ +#define DB_88F78XX0_BP_ID (BOARD_ID_BASE) +#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1) +#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1) +#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1) +#define DB_88F78XX0_BP_REV2_ID (FPGA_88F78XX0_ID + 1) +#define RD_78460_NAS_ID (DB_88F78XX0_BP_REV2_ID + 1) +#define DB_78X60_AMC_ID (RD_78460_NAS_ID + 1) +#define DB_78X60_PCAC_REV2_ID (DB_78X60_AMC_ID + 1) +#define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1) +#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1) +#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID+ 1) + +#ifdef CONFIG_SYNO_ARMADA_ARCH +#define SYNO_AXP_4BAY_2BAY (0xf + 1) +#define SYNO_AXP_2BAY (SYNO_AXP_4BAY_2BAY + 1) +#define SYNO_AXP_4BAY_RACK (SYNO_AXP_2BAY + 1) +#define MV_MAX_BOARD_ID (SYNO_AXP_4BAY_RACK + 1) +#else +#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1) +#endif + +#define INVALID_BAORD_ID 0xFFFFFFFF + +/******************/ +/* DB-88F78XX0-BP */ +/******************/ +#define DB_88F78XX0_MPP0_7 0x11111111 +#define DB_88F78XX0_MPP8_15 0x22221111 +#define DB_88F78XX0_MPP16_23 0x22222222 +/* TODO Kostap - change MPP29 (CPU0 Vdd) back to default value 5 + when PM configuration changed to have it as active "high" + Otherwise setting it to default value will shut down CPU0 */ +#define DB_88F78XX0_MPP24_31 0x11040000 /* bits[27:24] = 0x5 to enable PMm for CPU0 */ +#define DB_88F78XX0_MPP32_39 0x11111111 +#define DB_88F78XX0_MPP40_47 0x04221130 /* bits[3:0] = 0x3 to enable PM for CPU1 */ +#define DB_88F78XX0_MPP48_55 0x11111110 +#define DB_88F78XX0_MPP56_63 0x11111101 /* bits[7:4] = 0x1 to enable PM for CPU2/3 */ +#define DB_88F78XX0_MPP64_67 0x00002111 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +24 UsbDevice_Vbus IN +25 Touch SG/ MII Int# IN +26 7seg bit0 OUT +27 7seg bit1 OUT +48 7seg bit2 OUT +*/ +#define DB_88F78XX0_GPP_OUT_ENA_LOW (~(BIT26 | BIT27)) +#define DB_88F78XX0_GPP_OUT_ENA_MID (~(BIT16 | BIT15)) +#define DB_88F78XX0_GPP_OUT_ENA_HIGH (~(0x0)) + +#define DB_88F78XX0_GPP_OUT_VAL_LOW 0x0 +#define DB_88F78XX0_GPP_OUT_VAL_MID BIT15 +#define DB_88F78XX0_GPP_OUT_VAL_HIGH 0x0 + +#define DB_88F78XX0_GPP_POL_LOW 0x0 +#define DB_88F78XX0_GPP_POL_MID 0x0 +#define DB_88F78XX0_GPP_POL_HIGH 0x0 + +/**********************/ +/* DB-88F78XX0-BP Rev2*/ +/**********************/ +#define DB_88F78XX0_REV2_MPP0_7 0x11111111 +#define DB_88F78XX0_REV2_MPP8_15 0x22221111 +#define DB_88F78XX0_REV2_MPP16_23 0x22222222 +/* TODO Kostap - change MPP29 (CPU0 Vdd) back to default value 5 + when PM configuration changed to have it as active "high" + Otherwise setting it to default value will shut down CPU0 */ +#define DB_88F78XX0_REV2_MPP24_31 0x11040000 /* bits[27:24] = 0x5 to enable PMm for CPU0 */ +#define DB_88F78XX0_REV2_MPP32_39 0x11111111 +#define DB_88F78XX0_REV2_MPP40_47 0x04221130 /* bits[3:0] = 0x3 to enable PM for CPU1 */ +#define DB_88F78XX0_REV2_MPP48_55 0x11111113 +#define DB_88F78XX0_REV2_MPP56_63 0x11111101 /* bits[7:4] = 0x1 to enable PM for CPU2/3 */ +#define DB_88F78XX0_REV2_MPP64_67 0x00002111 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +24 UsbDevice_Vbus IN +25 Touch SG/ MII Int# IN +26 7seg bit0 OUT +27 7seg bit1 OUT +48 7seg bit2 OUT +*/ +#define DB_88F78XX0_REV2_GPP_OUT_ENA_LOW (~(BIT26 | BIT27)) +#define DB_88F78XX0_REV2_GPP_OUT_ENA_MID (~(BIT16 | BIT15)) +#define DB_88F78XX0_REV2_GPP_OUT_ENA_HIGH (~(0x0)) + +#define DB_88F78XX0_REV2_GPP_OUT_VAL_LOW 0x0 +#define DB_88F78XX0_REV2_GPP_OUT_VAL_MID BIT15 +#define DB_88F78XX0_REV2_GPP_OUT_VAL_HIGH 0x0 + +#define DB_88F78XX0_REV2_GPP_POL_LOW 0x0 +#define DB_88F78XX0_REV2_GPP_POL_MID 0x0 +#define DB_88F78XX0_REV2_GPP_POL_HIGH 0x0 + +/**********************/ +/* DB-AXP-NAS */ +/**********************/ + +#define RD_78460_NAS_MPP0_7 0x00000000 +#define RD_78460_NAS_MPP8_15 0x00000000 +#define RD_78460_NAS_MPP16_23 0x33000000 +#define RD_78460_NAS_MPP24_31 0x11000000 /* bits[27:24] = 0x5 to enable PMm for CPU0 */ +#define RD_78460_NAS_MPP32_39 0x11111111 +#define RD_78460_NAS_MPP40_47 0x00221100 /* bits[3:0] = 0x3 to enable PM for CPU1 */ +#define RD_78460_NAS_MPP48_55 0x00000003 +#define RD_78460_NAS_MPP56_63 0x00000000 /* bits[7:4] = 0x1 to enable PM for CPU2/3 */ +#define RD_78460_NAS_MPP64_67 0x00000000 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +21 SW_Reset_ OUT +25 Phy_Int# IN +28 SDI_WP IN +29 SDI_Status IN +54-61 On GPP Connector ? +62 Switch Interrupt IN +63-65 Reserved from SW Board ? +66 SW_BRD connected IN + +*/ +#define RD_78460_NAS_GPP_OUT_ENA_LOW (~(BIT21)) +#define RD_78460_NAS_GPP_OUT_ENA_MID (~(0x0)) +#define RD_78460_NAS_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_NAS_GPP_OUT_VAL_LOW (BIT21) +#define RD_78460_NAS_GPP_OUT_VAL_MID 0x0 +#define RD_78460_NAS_GPP_OUT_VAL_HIGH 0x0 + +#define RD_78460_NAS_GPP_POL_LOW 0x0 +#define RD_78460_NAS_GPP_POL_MID 0x0 +#define RD_78460_NAS_GPP_POL_HIGH 0x0 + + +/*******************/ +/* RD-78460-SERVER */ +/*******************/ +#define RD_78460_MPP0_7 0x00000000 +#define RD_78460_MPP8_15 0x00000000 +#define RD_78460_MPP16_23 0x00000000 +#define RD_78460_MPP24_31 0x00000000 +#define RD_78460_MPP32_39 0x11110000 +#define RD_78460_MPP40_47 0x00000000 +#define RD_78460_MPP48_55 0x00000000 +#define RD_78460_MPP56_63 0x00000000 +#define RD_78460_MPP64_67 0x00000000 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +16 CPU ID IN +17 CPU ID IN +18 CPU ID IN +19 CPU ID IN +23 USER LED OUT +25 Touch SG/ MII Int# IN +28 RESET GPIO FOR OTHER DEVICES +29 RESET GPIO FOR OTHER DEVICES +30 RESET GPIO FOR OTHER DEVICES +31 RESET GPIO FOR OTHER DEVICES +32 RESET GPIO FOR OTHER DEVICES +33 RESET GPIO FOR OTHER DEVICES + +40 GPIOs TO SLED CONNECTOR(CPU0 ONLY) +41 GPIOs TO SLED CONNECTOR(CPU0 ONLY) +42 GPIOs TO SLED CONNECTOR(CPU0 ONLY) +43 GPIOs TO SLED CONNECTOR(CPU0 ONLY) +44 GPIOs TO SLED CONNECTOR(CPU0 ONLY) + +*/ + +#define RD_78460_GPP_OUT_ENA_LOW (~(BIT23 | BIT28 | BIT29 | BIT30 | BIT31)) +#define RD_78460_GPP_OUT_ENA_MID (~(BIT0 | BIT1 | BIT2 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12)) +#define RD_78460_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_GPP_OUT_VAL_LOW (BIT28 | BIT29 | BIT30 | BIT31) +#define RD_78460_GPP_OUT_VAL_MID (BIT0) +#define RD_78460_GPP_OUT_VAL_HIGH 0x0 + +#define RD_78460_GPP_POL_LOW 0x0 +/* (BIT16 | BIT17 | BIT18 | BIT19) */ +#define RD_78460_GPP_POL_MID 0x0 +#define RD_78460_GPP_POL_HIGH 0x0 + +/************************/ +/* RD-78460-SERVER-REV2 */ +/************************/ +#define RD_78460_SERVER_REV2_MPP0_7 0x00000000 +#define RD_78460_SERVER_REV2_MPP8_15 0x00000000 +#define RD_78460_SERVER_REV2_MPP16_23 0x00000000 +#define RD_78460_SERVER_REV2_MPP24_31 0x00000000 +#define RD_78460_SERVER_REV2_MPP32_39 0x11110000 +#define RD_78460_SERVER_REV2_MPP40_47 0x00000000 +#define RD_78460_SERVER_REV2_MPP48_55 0x00000000 +#define RD_78460_SERVER_REV2_MPP56_63 0x00000000 +#define RD_78460_SERVER_REV2_MPP64_67 0x00000000 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +16 CPU ID IN +17 CPU ID IN +18 CPU ID IN +19 CPU ID IN +23 USER LED OUT +25 Touch SG/ MII Int# IN +28 RESET GPIO FOR OTHER DEVICES +29 RESET GPIO FOR OTHER DEVICES +30 RESET GPIO FOR OTHER DEVICES +31 RESET GPIO FOR OTHER DEVICES +32 RESET GPIO FOR OTHER DEVICES +33 RESET GPIO FOR OTHER DEVICES + +40 GPIOs TO SLED CONNECTOR(CPU0 ONLY) +41 GPIOs TO SLED CONNECTOR(CPU0 ONLY) +42 GPIOs TO SLED CONNECTOR(CPU0 ONLY) +43 GPIOs TO SLED CONNECTOR(CPU0 ONLY) +44 GPIOs TO SLED CONNECTOR(CPU0 ONLY) + +*/ + +#define RD_78460_SERVER_REV2_GPP_OUT_ENA_LOW (~(BIT23 | BIT28 | BIT29 | BIT30 | BIT31)) +#define RD_78460_SERVER_REV2_GPP_OUT_ENA_MID (~(BIT0 | BIT1 | BIT2 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12)) +#define RD_78460_SERVER_REV2_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_SERVER_REV2_GPP_OUT_VAL_LOW (BIT28 | BIT29 | BIT30 | BIT31) +#define RD_78460_SERVER_REV2_GPP_OUT_VAL_MID (BIT0) +#define RD_78460_SERVER_REV2_GPP_OUT_VAL_HIGH 0x0 + +#define RD_78460_SERVER_REV2_GPP_POL_LOW 0x0 +/* (BIT16 | BIT17 | BIT18 | BIT19) */ +#define RD_78460_SERVER_REV2_GPP_POL_MID 0x0 +#define RD_78460_SERVER_REV2_GPP_POL_HIGH 0x0 + + +/********************/ +/* DB-88F78XX0-PCAC */ +/********************/ + +#define DB_78X60_PCAC_MPP0_7 0x00000000 +#define DB_78X60_PCAC_MPP8_15 0x00000000 +#define DB_78X60_PCAC_MPP16_23 0x00000000 +#define DB_78X60_PCAC_MPP24_31 0x11000000 +#define DB_78X60_PCAC_MPP32_39 0x11111111 +#define DB_78X60_PCAC_MPP40_47 0x00221105 +#define DB_78X60_PCAC_MPP48_55 0x00000000 +#define DB_78X60_PCAC_MPP56_63 0x00000000 +#define DB_78X60_PCAC_MPP64_67 0x00000000 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +16 Jumper 1 IN +17 Jumper 2 IN +18 Jumper 3 IN +19 Jumper 4 IN +20 Jumper 5 IN +21 GP OUT +23 UsbDevice_Vbus IN +53 7seg bit0 OUT +54 7seg bit1 OUT +55 7seg bit2 OUT +56 7seg bit3 OUT +*/ + +#define DB_78X60_PCAC_GPP_OUT_ENA_LOW (~(BIT26 | BIT27)) +#define DB_78X60_PCAC_GPP_OUT_ENA_MID (~(BIT16 | BIT21 | BIT22 | BIT23 | BIT24)) +#define DB_78X60_PCAC_GPP_OUT_ENA_HIGH (~(0x0)) + +#define DB_78X60_PCAC_GPP_OUT_VAL_LOW 0x0 +#define DB_78X60_PCAC_GPP_OUT_VAL_MID 0x0 +#define DB_78X60_PCAC_GPP_OUT_VAL_HIGH 0x0 + +#define DB_78X60_PCAC_GPP_POL_LOW 0x0 +#define DB_78X60_PCAC_GPP_POL_MID 0x0 +#define DB_78X60_PCAC_GPP_POL_HIGH 0x0 + +/*************************/ +/* DB-88F78XX0-PCAC-REV2 */ +/*************************/ + +#define DB_78X60_PCAC_REV2_MPP0_7 0x00000000 +#define DB_78X60_PCAC_REV2_MPP8_15 0x00000000 +#define DB_78X60_PCAC_REV2_MPP16_23 0x00000000 +#define DB_78X60_PCAC_REV2_MPP24_31 0x11000000 +#define DB_78X60_PCAC_REV2_MPP32_39 0x11111111 +#define DB_78X60_PCAC_REV2_MPP40_47 0x00221105 +#define DB_78X60_PCAC_REV2_MPP48_55 0x00000000 +#define DB_78X60_PCAC_REV2_MPP56_63 0x00000000 +#define DB_78X60_PCAC_REV2_MPP64_67 0x00000000 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +16 Jumper 1 IN +17 Jumper 2 IN +18 Jumper 3 IN +19 Jumper 4 IN +20 Jumper 5 IN +21 GP OUT +23 UsbDevice_Vbus IN +53 7seg bit0 OUT +54 7seg bit1 OUT +55 7seg bit2 OUT +56 7seg bit3 OUT +*/ + +#define DB_78X60_PCAC_REV2_GPP_OUT_ENA_LOW (~(BIT26 | BIT27)) +#define DB_78X60_PCAC_REV2_GPP_OUT_ENA_MID (~(BIT16 | BIT21 | BIT22 | BIT23 | BIT24)) +#define DB_78X60_PCAC_REV2_GPP_OUT_ENA_HIGH (~(0x0)) + +#define DB_78X60_PCAC_REV2_GPP_OUT_VAL_LOW 0x0 +#define DB_78X60_PCAC_REV2_GPP_OUT_VAL_MID 0x0 +#define DB_78X60_PCAC_REV2_GPP_OUT_VAL_HIGH 0x0 + +#define DB_78X60_PCAC_REV2_GPP_POL_LOW 0x0 +#define DB_78X60_PCAC_REV2_GPP_POL_MID 0x0 +#define DB_78X60_PCAC_REV2_GPP_POL_HIGH 0x0 + +/********************/ +/* FPGA-88F78XX0-BP */ +/********************/ +#define FPGA_88F78XX0_MPP0_7 0x11111111 +#define FPGA_88F78XX0_MPP8_15 0x22221111 +#define FPGA_88F78XX0_MPP16_23 0x22222222 +#define FPGA_88F78XX0_MPP24_31 0x11500000 +#define FPGA_88F78XX0_MPP32_39 0x11111111 +#define FPGA_88F78XX0_MPP40_47 0x44221133 +#define FPGA_88F78XX0_MPP48_55 0x11111111 +#define FPGA_88F78XX0_MPP56_63 0x11111111 +#define FPGA_88F78XX0_MPP64_67 0x00002111 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +24 UsbDevice_Vbus IN +25 Touch SG/ MII Int# IN +26 7seg bit0 OUT +27 7seg bit1 OUT +48 7seg bit2 OUT +*/ +#define FPGA_88F78XX0_GPP_OUT_ENA_LOW (BIT26 | BIT27) +#define FPGA_88F78XX0_GPP_OUT_ENA_MID (BIT16) +#define FPGA_88F78XX0_GPP_OUT_ENA_HIGH 0x0 + +#define FPGA_88F78XX0_GPP_OUT_VAL_LOW 0x0 +#define FPGA_88F78XX0_GPP_OUT_VAL_MID 0x0 +#define FPGA_88F78XX0_GPP_OUT_VAL_HIGH 0x0 + +#define FPGA_88F78XX0_GPP_POL_LOW 0x0 +#define FPGA_88F78XX0_GPP_POL_MID 0x0 +#define FPGA_88F78XX0_GPP_POL_HIGH 0x0 + + + +/********************/ +/* DB-78460-AMC */ +/********************/ + +#define DB_78X60_AMC_MPP0_7 0x11111111 +#define DB_78X60_AMC_MPP8_15 0x00001111 +#define DB_78X60_AMC_MPP16_23 0x00000000 +#define DB_78X60_AMC_MPP24_31 0x00000000 +#define DB_78X60_AMC_MPP32_39 0x11110000 +#define DB_78X60_AMC_MPP40_47 0x00004000 +#define DB_78X60_AMC_MPP48_55 0x00001113 +#define DB_78X60_AMC_MPP56_63 0x11111110 +#define DB_78X60_AMC_MPP64_67 0x00000111 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +16 MB_INT# IN +17 Phy1_INT# IN +18 Phy2_INT# IN +19 Brd_Led_0 IN (for next board) +21 Brd_Led_1 OUT +23 Brd_Led_2 OUT +29 Brd_Led_3 OUT +30 Brd_Led_4 OUT +34 Dbg_JP0 IN +35 Dbg_JP1 IN +40 Dbg_JP2 IN +41 Dbg_JP3 IN +42 Dbg_JP4 IN +53 7 Segment 0 OUT +54 7 Segment 1 OUT +55 7 Segment 2 OUT +56 7 Segment 3 OUT +*/ + +#define DB_78X60_AMC_GPP_OUT_ENA_LOW (~(BIT21 | BIT23 | BIT29 | BIT30)) +#define DB_78X60_AMC_GPP_OUT_ENA_MID (~(BIT21 | BIT22 | BIT23 | BIT24)) +#define DB_78X60_AMC_GPP_OUT_ENA_HIGH (~(0x0)) + +#define DB_78X60_AMC_GPP_OUT_VAL_LOW 0x0 +#define DB_78X60_AMC_GPP_OUT_VAL_MID 0x0 +#define DB_78X60_AMC_GPP_OUT_VAL_HIGH 0x0 + +#define DB_78X60_AMC_GPP_POL_LOW 0x0 +#define DB_78X60_AMC_GPP_POL_MID 0x0 +#define DB_78X60_AMC_GPP_POL_HIGH 0x0 + + + + +/*********************/ +/* DB-AXP-GP */ +/*********************/ + +#define RD_78460_GP_MPP0_7 0x00000000 +#define RD_78460_GP_MPP8_15 0x00000000 +#define RD_78460_GP_MPP16_23 0x33000000 +#define RD_78460_GP_MPP24_31 0x11000000 +#define RD_78460_GP_MPP32_39 0x11111111 +#define RD_78460_GP_MPP40_47 0x00221100 +#define RD_78460_GP_MPP48_55 0x00000003 +#define RD_78460_GP_MPP56_63 0x00000000 +#define RD_78460_GP_MPP64_67 0x00000000 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +21 SW_Reset_ OUT +25 Phy_Int# IN +28 SDI_WP IN +29 SDI_Status IN +54-61 On GPP Connector ? +62 Switch Interrupt IN +63-65 Reserved from SW Board ? +66 SW_BRD connected IN + +*/ +#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT21 | BIT20)) +#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT26 | BIT27)) +#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT21 | BIT20) +#define RD_78460_GP_GPP_OUT_VAL_MID (BIT26 | BIT27) +#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0 + +#define RD_78460_GP_GPP_POL_LOW 0x0 +#define RD_78460_GP_GPP_POL_MID 0x0 +#define RD_78460_GP_GPP_POL_HIGH 0x0 + + + + +/**********************/ +/* DB-AXP-CUSTOMER */ +/**********************/ + +#define RD_78460_CUSTOMER_MPP0_7 0x00000000 +#define RD_78460_CUSTOMER_MPP8_15 0x00000000 +#define RD_78460_CUSTOMER_MPP16_23 0x33000000 +#define RD_78460_CUSTOMER_MPP24_31 0x11000000 /* bits[27:24] = 0x5 to enable PMm for CPU0 */ +#define RD_78460_CUSTOMER_MPP32_39 0x11111111 +#define RD_78460_CUSTOMER_MPP40_47 0x00221100 /* bits[3:0] = 0x3 to enable PM for CPU1 */ +#define RD_78460_CUSTOMER_MPP48_55 0x00000003 +#define RD_78460_CUSTOMER_MPP56_63 0x00000000 /* bits[7:4] = 0x1 to enable PM for CPU2/3 */ +#define RD_78460_CUSTOMER_MPP64_67 0x00000000 + +/* GPPs +MPP# NAME IN/OUT +---------------------------------------------- +21 SW_Reset_ OUT +25 Phy_Int# IN +28 SDI_WP IN +29 SDI_Status IN +54-61 On GPP Connector ? +62 Switch Interrupt IN +63-65 Reserved from SW Board ? +66 SW_BRD connected IN + +*/ +#define RD_78460_CUSTOMER_GPP_OUT_ENA_LOW (~(BIT21)) +#define RD_78460_CUSTOMER_GPP_OUT_ENA_MID (~(0x0)) +#define RD_78460_CUSTOMER_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_CUSTOMER_GPP_OUT_VAL_LOW (BIT21) +#define RD_78460_CUSTOMER_GPP_OUT_VAL_MID 0x0 +#define RD_78460_CUSTOMER_GPP_OUT_VAL_HIGH 0x0 + +#define RD_78460_CUSTOMER_GPP_POL_LOW 0x0 +#define RD_78460_CUSTOMER_GPP_POL_MID 0x0 +#define RD_78460_CUSTOMER_GPP_POL_HIGH 0x0 + + + +#endif /* __INCmvBoardEnvSpech */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/cpu/mvCpu.c b/arch/arm/mach-armadaxp/armada_xp_family/cpu/mvCpu.c new file mode 100755 index 000000000..699062cca --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/cpu/mvCpu.c @@ -0,0 +1,323 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "boardEnv/mvBoardEnvLib.h" + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ + +/******************************************************************************* +* mvCpuPclkGet - Get the CPU pClk (pipe clock) +* +* DESCRIPTION: +* This routine extract the CPU core clock. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in MHertz. +* +*******************************************************************************/ +MV_U32 mvCpuPclkGet(MV_VOID) +{ + MV_U32 idx; + MV_U32 cpuClk[] = MV_CPU_CLK_TBL; + + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return MV_FPGA_CLK; /* FPGA is limited to 25Mhz */ + + idx = MSAR_CPU_CLK_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)), MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + return cpuClk[idx] * 1000000; +} + +/******************************************************************************* +* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU L2 clock. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvCpuL2ClkGet(MV_VOID) +{ + MV_U32 idx; + MV_U32 freqMhz, l2FreqMhz; + MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL; + + if (mvBoardIdGet() == FPGA_88F78XX0_ID) + return MV_FPGA_CLK; /* FPGA is limited to 25Mhz */ + + idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)), MV_REG_READ(MPP_SAMPLE_AT_RESET(1))); + + if (clockRatioTbl[idx].vco2cpu != 0) { + freqMhz = mvCpuPclkGet() / 1000000; /* CPU freq */ + freqMhz *= clockRatioTbl[idx].vco2cpu; /* VCO freq */ + l2FreqMhz = freqMhz / clockRatioTbl[idx].vco2l2c; + /* round up to integer MHz */ + if (((freqMhz % clockRatioTbl[idx].vco2l2c) * 10 / clockRatioTbl[idx].vco2l2c) >= 5) + l2FreqMhz++; + + return l2FreqMhz * 1000000; + } else + return (MV_U32)-1; +} + +/******************************************************************************* +* mvCpuNameGet - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +MV_VOID mvCpuNameGet(char *pNameBuff) +{ + MV_U32 cpuModel; + MV_U32 archType; + + cpuModel = mvOsCpuPartGet(); + archType = mvOsCpuThumbEEGet(); + /* The CPU module is indicated in the Processor Version Register (PVR) */ + switch (cpuModel & 0xfff) { + case CPU_PART_ARM_V6UP: + case CPU_PART_ARM_V7UP: + case CPU_PART_MRVLPJ4B_UP: + if (archType == 0x1) + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B (581) v7", mvOsCpuRevGet()); + else + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B (581) v6", mvOsCpuRevGet()); + break; + case CPU_PART_MRVLPJ4B_MP: + case CPU_PART_ARM_V6MP: + if (archType == 0x1) + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B (584) v7", mvOsCpuRevGet()); + else + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell PJ4B (584) v6", mvOsCpuRevGet()); + break; + default: + mvOsSPrintf(pNameBuff, "??? (0x%04x) (Rev %d)", cpuModel, mvOsCpuRevGet()); + break; + } /* switch */ + + return; +} + +#define MV_PROC_STR_SIZE 50 + +static void mvCpuIfGetL2EccMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_ECC_MASK) == CL2ACR_ECC_EN) + mvOsSPrintf(buf, "L2 ECC Enabled"); + else + mvOsSPrintf(buf, "L2 ECC Disabled"); +} + +static void mvCpuIfGetL2ParityMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_PARITY_MASK) == CL2ACR_PARITY_EN) + mvOsSPrintf(buf, "L2 Parity Enabled"); + else + mvOsSPrintf(buf, "L2 Parity Disabled"); +} + +static void mvCpuIfGetL2Mode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_CTRL_REG); + if (regVal & CL2CR_L2_EN_MASK) + mvOsSPrintf(buf, "L2 Enabled"); + else + mvOsSPrintf(buf, "L2 Disabled"); +} + +static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) +{ /* valid for PJ4B as well */ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_PFU_MASK) == CL2ACR_PFU_DIS) + mvOsSPrintf(buf, "L2 Prefetch Disabled"); + else + mvOsSPrintf(buf, "L2 Prefetch Enabled"); +} + +static void mvCpuIfGetWriteAllocMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + if ((regVal & CL2ACR_FORCE_WA_MASK) == CL2ACR_FORCE_NO_WA) + mvOsSPrintf(buf, "L2 Write Allocate Disabled"); + else + mvOsSPrintf(buf, "L2 Write Allocate Enabled"); +} + +static void mvCpuIfGetCpuStreamMode(MV_8 *buf) +{ /* valid for PJ4B as well */ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT29) + mvOsSPrintf(buf, "CPU Streaming Enabled"); + else + mvOsSPrintf(buf, "CPU Streaming Disabled"); +} + +static void mvCpuIfPrintCpuRegs(void) +{ + MV_U32 regVal = 0; + + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register0 */ + mvOsPrintf("Extra Features Reg[0] = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 1, %0, c15, c1, 1" : "=r" (regVal)); /* Read Marvell extra features register1 */ + mvOsPrintf("Extra Features Reg[1] = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ + mvOsPrintf("Control Reg = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read Main ID register */ + mvOsPrintf("Main ID Reg = 0x%x\n", regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ + mvOsPrintf("Cache Type Reg = 0x%x\n", regVal); + + regVal = MV_REG_READ(CPU_L2_CTRL_REG); + mvOsPrintf("L2 Control Reg = 0x%x\n", regVal); + + regVal = MV_REG_READ(CPU_L2_AUX_CTRL_REG); + mvOsPrintf("L2 Auxilary Control Reg = 0x%x\n", regVal); + +} + +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) +{ + MV_U32 count = 0; + + MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; + MV_8 L2_En_str[MV_PROC_STR_SIZE]; + MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; + MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; + MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; + MV_8 L2_Parity_str[MV_PROC_STR_SIZE]; + + mvCpuIfGetL2Mode(L2_En_str); + mvCpuIfGetL2EccMode(L2_ECC_str); + mvCpuIfGetL2ParityMode(L2_Parity_str); + mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); + mvCpuIfGetWriteAllocMode(Write_Alloc_str); + mvCpuIfGetCpuStreamMode(Cpu_Stream_str); + mvCpuIfPrintCpuRegs(); + + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Parity_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); + return count; +} + +/******************************************************************************* +* whoAmI - Get the CPU ID +* +* DESCRIPTION: +* This function returns CPU ID in multiprocessor system +* +* INPUT: +* None. +* +* OUTPUT: +* none. +* +* RETURN: +* CPU ID. +*******************************************************************************/ +unsigned int whoAmI(void) +{ + MV_U32 value; + + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 5 @ read CPUID reg\n" : "=r"(value) : : "memory"); + return (value & 0x7); +} diff --git a/arch/arm/mach-armadaxp/armada_xp_family/cpu/mvCpu.h b/arch/arm/mach-armadaxp/armada_xp_family/cpu/mvCpu.h new file mode 100755 index 000000000..c4e38d6bb --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/cpu/mvCpu.h @@ -0,0 +1,112 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuh +#define __INCmvCpuh + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#ifndef MV_ASMLANGUAGE +#include "mvOs.h" +#endif + +#define MASTER_CPU 0 +/* defines */ +#define CPU_PART_MRVL131 0x131 +#define CPU_PART_ARM926 0x926 +#define CPU_PART_ARM946 0x946 +#define CPU_PART_MRVL_A9 0xC09 +#define CPU_PART_MRVL571 0x571 +#define CPU_PART_MRVL521 0x521 + +#define CPU_PART_ARM_V6UP 0xb76 +#define CPU_PART_ARM_V7UP 0xc08 +#define CPU_PART_ARM_V6MP 0xb02 + +#define CPU_PART_MRVLPJ4B_UP 0x581 +#define CPU_PART_MRVLPJ4B_MP 0x584 + +#define MV_CPU_ARM_CLK_ELM_SIZE 12 +#define MV_CPU_ARM_CLK_RATIO_OFF 8 +#define MV_CPU_ARM_CLK_DDR_OFF 4 + +#ifndef MV_ASMLANGUAGE +typedef struct _mvCpuArmClkRatio { + MV_U32 vco2cpu; /* VCO:PCLK0(CPU) clock ratio */ + MV_U32 vco2l2c; /* VCO:NB(L2 cache) clock ratio */ + MV_U32 vco2hcl; /* VCO:HCLK(DDR controller) clock ratio */ + MV_U32 vco2ddr; /* VCO:DDR(DDR memory) clock ratio */ + +} MV_CPU_ARM_CLK_RATIO; + +MV_U32 mvCpuPclkGet(MV_VOID); +MV_VOID mvCpuNameGet(char *pNameBuff); +MV_U32 mvCpuL2ClkGet(MV_VOID); +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); +MV_U32 whoAmI(MV_VOID); + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvCpuh */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c new file mode 100755 index 000000000..8818c16e0 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.c @@ -0,0 +1,377 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCtrlEnvAddrDec.h - Marvell controller address decode library +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "sys/mvCpuIf.h" + +#undef MV_DEBUG + +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* Default Attributes array */ +MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; +extern MV_TARGET sampleAtResetTargetArray[]; + +/******************************************************************************* +* mvCtrlAttribGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib) +{ + targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; + targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; + + return MV_OK; +} +/*******************************************************************************/ +MV_STATUS mvCtrlAttribSet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib) +{ + mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib = targetAttrib->attrib; + mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId= targetAttrib->targetId; + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlGetAttrib - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS; target++) { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) { + /* found it */ + break; + } + } + + return target; +} + +/******************************************************************************* +* mvCtrlTargetByWinInfoGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetByWinInfoGet(MV_UNIT_WIN_INFO *unitWinInfo) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS; target++) { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == unitWinInfo->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == unitWinInfo->targetId)) { + /* found it */ + break; + } + } + + return target; +} + +/******************************************************************************* +* mvCtrlAddrWinMapBuild +* +* DESCRIPTION: +* Build the windows address decoding table, to be used for initializing +* the unit's address decoding windows. +* +* INPUT: +* pAddrWinMap: An array to hold the address decoding windows parameters. +* len: Number of entries in pAddrWinMap. +* +* OUTPUT: +* pAddrWinMap: Address window information. +* +* RETURN: +* MV_BAD_PARAM: input array is smaller than needed to store all window +* addresses. +* MV_ERROR: Otherwise. +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrWinMapBuild(MV_UNIT_WIN_INFO *pAddrWinMap, MV_U32 len) +{ + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 i, j; + MV_TARGET_ATTRIB targetAttrib; + MV_STATUS status; + MV_U64 startAddr, endAddr; + MV_UNIT_WIN_INFO ioDdrWin[MV_DRAM_MAX_CS]; + MV_U32 base; + MV_U64 size; + + /* Check size of CPU address win table */ + if (len <= MAX_TARGETS) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - Table size too small.\n"); + return MV_BAD_PARAM; + } + + /* Prepare an array of DRAM info */ + base = 0x0; + j = 0; + for (i = SDRAM_CS0; i <= SDRAM_CS3; i++) { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) { + if (status == MV_NO_SUCH) { + ioDdrWin[i].enable = MV_FALSE; + continue; + } else { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCpuIfTargetWinGet() failed.\n"); + return MV_ERROR; + } + } + + /* As all IO address decode windows support only 32-bit + ** addresses, limit the DRAM base / size to 4GB max. + */ + startAddr = (MV_U64)((((MV_U64)cpuAddrDecWin.addrWin.baseHigh << 32ll)) + + (MV_U64)cpuAddrDecWin.addrWin.baseLow); + endAddr = (MV_U64)(startAddr + (MV_U64)cpuAddrDecWin.addrWin.size) - 1; + if (endAddr > 0xFFFFFFFFll) { + if (startAddr <= 0xFFFFFFFFll) + cpuAddrDecWin.addrWin.size = (0x100000000ll - + cpuAddrDecWin.addrWin.baseLow); + else + cpuAddrDecWin.enable = MV_FALSE; + } + + if (cpuAddrDecWin.enable == MV_FALSE) + continue; + + /* If the endAddr passes minBase, then we need to split + ** this window to several windows up to minBase. + ** For example: minBase=0xE0000000, and CS0=2, CS1=2G, + ** Then we need to split the windwos as follows: + ** Win0: CS-0, 2GB (Base 0x0) + ** win1: CS-1, 1GB (Base 0x80000000) + ** Win2: CS-1, 0.5GB (Base 0xC0000000) + */ + if (endAddr > MV_DRAM_IO_RESERVE_BASE) + /* Need to cut down this CS to IO reserve base + ** address. + */ + size = MV_DRAM_IO_RESERVE_BASE - + cpuAddrDecWin.addrWin.baseLow; + else + size = cpuAddrDecWin.addrWin.size; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - " + "mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + /* Now, spread the last CS into several windows, and make sure + ** that each of has a power-of-2 size. + */ + while (size != 0) { + ioDdrWin[j].enable = MV_TRUE; + ioDdrWin[j].attrib = targetAttrib.attrib; + ioDdrWin[j].targetId = targetAttrib.targetId; + ioDdrWin[j].addrWin.baseHigh = 0; + if (MV_IS_POWER_OF_2(size)) + ioDdrWin[j].addrWin.size = size; + else + ioDdrWin[j].addrWin.size = (MV_U64)(1ll << (MV_U64)mvLog2(size)); + size -= ioDdrWin[j].addrWin.size; + ioDdrWin[j].addrWin.baseLow = base; + base += ioDdrWin[j].addrWin.size; + j++; + } + /* Support only up to 4 DRAM address decode windows in the + ** units. */ + if (j == MV_DRAM_MAX_CS) + break; + } + + for (; j < MV_DRAM_MAX_CS; j++) + ioDdrWin[j].enable = MV_FALSE; + + /* Fill in the pAddrWinMap fields */ + for (i = 0; i < MAX_TARGETS; i++) { + if (MV_TARGET_IS_DRAM(i)) { + pAddrWinMap[i].addrWin.baseLow = ioDdrWin[i].addrWin.baseLow; + pAddrWinMap[i].addrWin.baseHigh = ioDdrWin[i].addrWin.baseHigh; + pAddrWinMap[i].addrWin.size = ioDdrWin[i].addrWin.size; + pAddrWinMap[i].enable = ioDdrWin[i].enable; + pAddrWinMap[i].attrib = ioDdrWin[i].attrib; + pAddrWinMap[i].targetId = ioDdrWin[i].targetId; + } else { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) { + if (status == MV_NO_SUCH) { + pAddrWinMap[i].enable = MV_FALSE; + continue; + } else { + mvOsPrintf("mvCtrlAddrWinMapBuild()" + " - mvCpuIfTargetWinGet() failed.\n"); + return MV_ERROR; + } + } + + pAddrWinMap[i].addrWin.baseLow = + cpuAddrDecWin.addrWin.baseLow; + pAddrWinMap[i].addrWin.baseHigh = + cpuAddrDecWin.addrWin.baseHigh; + pAddrWinMap[i].addrWin.size = + cpuAddrDecWin.addrWin.size; + pAddrWinMap[i].enable = cpuAddrDecWin.enable; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - " + "mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + pAddrWinMap[i].attrib = targetAttrib.attrib; + pAddrWinMap[i].targetId = targetAttrib.targetId; + } + } + pAddrWinMap[i].addrWin.baseLow = TBL_TERM; + pAddrWinMap[i].addrWin.baseHigh = TBL_TERM; + pAddrWinMap[i].addrWin.size = TBL_TERM; + pAddrWinMap[i].enable = TBL_TERM; + pAddrWinMap[i].attrib = TBL_TERM; + pAddrWinMap[i].targetId = TBL_TERM; + + return MV_OK; +} + +MV_STATUS mvCtrlAddrWinInfoGet(MV_UNIT_WIN_INFO *pAddrWinInfo, MV_ULONG physAddr) +{ + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 i; + MV_TARGET_ATTRIB targetAttrib; + MV_STATUS status; + + for (i = 0; i < MAX_TARGETS; i++) { + status = mvCpuIfTargetWinGet(i, &cpuAddrDecWin); + if (status != MV_OK) + continue; + + if ((physAddr >= cpuAddrDecWin.addrWin.baseLow) && + (physAddr < cpuAddrDecWin.addrWin.baseLow + cpuAddrDecWin.addrWin.size)) { + /* Found */ + pAddrWinInfo->addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + pAddrWinInfo->addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + pAddrWinInfo->addrWin.size = cpuAddrDecWin.addrWin.size; + + if (mvCtrlAttribGet(i, &targetAttrib) != MV_OK) { + mvOsPrintf("mvCtrlAddrWinMapBuild() - mvCtrlAttribGet() failed.\n"); + return MV_ERROR; + } + pAddrWinInfo->attrib = targetAttrib.attrib; + pAddrWinInfo->targetId = targetAttrib.targetId; + return MV_OK; + } + } + /* not found */ + return MV_NOT_FOUND; +} diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h new file mode 100755 index 000000000..dcecd06d2 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAddrDec.h @@ -0,0 +1,194 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAddrDech +#define __INCmvCtrlEnvAddrDech + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + + +/* defines */ +/* DUnit attributes */ +#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 +#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 +#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) + +#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 +#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 +#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) + +#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 +#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 +#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) + +#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 +#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 +#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) + +/* RUnit (Device) attributes */ +#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 +#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 +#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 +#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 +#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 +#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 +#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) + +#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 +#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 +#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) + +/* LMaster (PCI) attributes */ +#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) + + +#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 +#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 +#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) + +#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 + +#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 +#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 +#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) +#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) + +#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 +#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 +#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 +#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 +#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +/* PEX Attributes */ +#define ATMWCR_WIN_PEX_TYPE_OFFS 3 +#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 +#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) +#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) + +/* typedefs */ + +/* Unsupported attributes for address decode: */ +/* 2) PCI0/1_REQ64n control */ + +typedef struct _mvTargetAttrib { + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ +} MV_TARGET_ATTRIB; + + +/* This structure describes address decode window */ +typedef struct _mvDecWin { + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ +} MV_DEC_WIN; + +typedef struct _mvDecWinParams { + MV_TARGET_ID targetId; /* Target ID field */ + MV_U8 attrib; /* Attribute field */ + MV_U32 baseAddr; /* Base address in register format */ + MV_U32 size; /* Size in register format */ +} MV_DEC_WIN_PARAMS; + + +/* mvCtrlEnvAddrDec API list */ + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib); +MV_STATUS mvCtrlAttribSet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib); + +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); +MV_TARGET mvCtrlTargetByWinInfoGet(MV_UNIT_WIN_INFO *unitWinInfo); + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, MV_DEC_WIN_PARAMS *pWinParam); + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, MV_DEC_WIN *pAddrDecWin); + +MV_STATUS mvCtrlAddrWinMapBuild(MV_UNIT_WIN_INFO *pAddrWinMap, MV_U32 len); + +MV_STATUS mvCtrlAddrWinInfoGet(MV_UNIT_WIN_INFO *pAddrWinInfo, MV_ULONG physAddr); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* __INCmvCtrlEnvAddrDech */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h new file mode 100755 index 000000000..1a14a79bb --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvAsm.h @@ -0,0 +1,97 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAsmh +#define __INCmvCtrlEnvAsmh +#include "pex/mvPexRegs.h" + +#define CHIP_BOND_REG 0x18238 +#define PCKG_OPT_MASK_AS #3 +#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK + +/* Read device ID into toReg bits 15:0 from 0xd0000000 */ +/* defines */ +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read device ID into toReg bits 15:0 from 0xf1000000*/ +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read Revision into toReg bits 7:0 0xd0000000*/ +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0, PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +/* Read Revision into toReg bits 7:0 0xf1000000*/ +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0, PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +#endif /* __INCmvCtrlEnvAsmh */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c new file mode 100755 index 000000000..44574b848 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.c @@ -0,0 +1,2107 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "gpp/mvGpp.h" +#include "gpp/mvGppRegs.h" +#include "mvSysEthConfig.h" + +#include "pex/mvPex.h" +#include "pex/mvPexRegs.h" + +#if defined(MV_INCLUDE_GIG_ETH) +#if defined(MV_ETH_LEGACY) +#include "eth/mvEth.h" +#else +#include "neta/gbe/mvNeta.h" +#endif /* MV_ETH_LEGACY or MV_ETH_NETA */ +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +#endif + +#if defined(MV_INCLUDE_SATA) +#include "sata/CoreDriver/mvSata.h" +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#endif + +#if defined(MV_INCLUDE_TDM) +#include "mvSysTdmConfig.h" +#endif + +#include "ddr2_3/mvDramIfRegs.h" + +/* defines */ +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif +MV_U32 dummyFlavour = 0; +MV_BIOS_MODE bios_modes[BIOS_MODES_NUM] = { +/*DBConf ConfID Code L2Size CPUFreq CpuFreqMode FabricFreq Altfabricfreq FabricFreqMode CPU1/2/3Enable cpuEndianess dramBusWidth BootSRC BootWidth */ +/* 0x4d/[1:0] 0x4d/[4:2] 0x4e[0] 0x4e/[4:1] 0x4f[0] 0x4f/[2:1] 0x4f/[3] */ +{"78230",0x13, 0x7823, 0x1, 0x3, 0x0, 0x1a, 0x5, 0x1, 0x1, 0x0, 0x1, 0x3, 0x1}, +{"78260",0x14, 0x7826, 0x1, 0x3, 0x0, 0x1a, 0x5, 0x1, 0x1, 0x0, 0x0, 0x3, 0x1}, +{"78460",0x15, 0x7846, 0x3, 0x3, 0x0, 0x1a, 0x5, 0x1, 0x3, 0x0, 0x0, 0x3, 0x1}, +{"78480",0x16, 0x7846, 0x3, 0x3, 0x0, 0x1a, 0x5, 0x1, 0x3, 0x0, 0x0, 0x3, 0x1} + +/* {"6710" ,0x11, 0x6710, 0x0, 0x3, 0x0, 0x5, 0x0, 0x0, 0x1, 0x0}, */ +}; + +MV_BIOS_MODE bios_modes_b0[BIOS_MODES_NUM] = { +/*DBConf ConfID Code L2Size CPUFreq CpuFreqMode FabricFreq Altfabricfreq FabricFreqMode CPUEna cpuEndianess dramBusWidth BootSRC BootWidth */ +/* 0x4d/[1:0] 0x4d/[4:2] 0x4e[0] 0x4e/[4:1] 0x4f[0] 0x4f/[2:1] 0x4f/[3] */ +{"78230",0x13, 0x7823, 0x1, 0x3, 0x0, 0x5, 0x5, 0x1, 0x1, 0x0, 0x1, 0x3, 0x1}, +{"78260",0x14, 0x7826, 0x1, 0x3, 0x0, 0x5, 0x5, 0x1, 0x1, 0x0, 0x0, 0x3, 0x1}, +{"78460",0x15, 0x7846, 0x3, 0x3, 0x0, 0x5, 0x5, 0x1, 0x3, 0x1, 0x0, 0x3, 0x1}, +{"78480",0x16, 0x7846, 0x3, 0x3, 0x0, 0x5, 0x5, 0x1, 0x3, 0x1, 0x0, 0x3, 0x1} +}; + +MV_U32 mvCtrlGetCpuNum(MV_VOID) +{ + return ((MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_CORE_MASK) >> SAR1_CPU_CORE_OFFSET); +} +MV_U32 mvCtrlGetQuadNum(MV_VOID) +{ + return ((MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_L2_SIZE_MASK) >> SAR0_L2_SIZE_OFFSET); +} +MV_BOOL mvCtrlIsValidSatR(MV_VOID) +{ + int i = 0; + MV_U32 tmpSocCores; + MV_U8 cpuEna = 0; + MV_U8 l2size; + MV_U8 cpuFreq; + MV_U8 fabricFreq; + MV_U8 cpuFreqMode; + MV_U8 fabricFreqMode; + MV_BIOS_MODE * pBbiosModes; + +#if defined(RD_88F78460_SERVER) || defined(DB_78X60_AMC) + MV_U32 confId = 0x15; +#else + MV_U32 confId = mvBoardConfIdGet(); +#endif + l2size = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_L2_SIZE_MASK) >> SAR0_L2_SIZE_OFFSET; + cpuFreq = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_CPU_FREQ_MASK) >> SAR0_CPU_FREQ_OFFSET; + fabricFreq = (MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET; + tmpSocCores = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_CORE_MASK) >> SAR1_CPU_CORE_OFFSET; + cpuFreqMode = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_CPU_MODE_MASK) >> SAR1_CPU_MODE_OFFSET; + fabricFreqMode = (MV_REG_READ(MPP_SAMPLE_AT_RESET(1)) & SAR1_FABRIC_MODE_MASK) >> SAR1_FABRIC_MODE_OFFSET; + /* Bug fix in HW, bit0 & bit1 are swapped */ + cpuEna |= (tmpSocCores & 0x2) >> 1; + cpuEna |= (tmpSocCores & 0x1) << 1; + if (mvCtrlRevGet() == 2) + pBbiosModes = bios_modes_b0; + else + pBbiosModes = bios_modes; + + /* Find out what is programmed in SAR and change device ID accordingly */ + for (i = 0; i < BIOS_MODES_NUM; i++) { + if (pBbiosModes->confId == confId) { + DB(mvOsPrintf("confId = 0x%x\n", confId)); + DB(mvOsPrintf("cpuFreq [0x%x] = 0x%x\n", cpuFreq, pBbiosModes->cpuFreq)); + DB(mvOsPrintf("fabricFreq [0x%x] = 0x%x\n", fabricFreq, pBbiosModes->fabricFreq)); + DB(mvOsPrintf("cpuEna [0x%x] = 0x%x\n", cpuEna, pBbiosModes->cpuEna)); + DB(mvOsPrintf("cpuFreqMode [0x%x] = 0x%x\n", cpuFreqMode, pBbiosModes->cpuFreqMode)); + DB(mvOsPrintf("fabricFreqMode [0x%x] = 0x%x\n", fabricFreqMode, pBbiosModes->fabricFreqMode)); + DB(mvOsPrintf("l2size [0x%x] = 0x%x\n", l2size, pBbiosModes->l2size)); + if ((cpuFreq == pBbiosModes->cpuFreq) && + (fabricFreq == pBbiosModes->fabricFreq) && + (cpuEna == pBbiosModes->cpuEna) && + (cpuFreqMode == pBbiosModes->cpuFreqMode) && + (fabricFreqMode == pBbiosModes->fabricFreqMode) && + (l2size == pBbiosModes->l2size)) { + return MV_TRUE; + } else { + return MV_FALSE; + } + } + pBbiosModes++; + } + return MV_FALSE; +} +/******************************************************************************* +* mvCtrlEnvInit - Initialize Marvell controller environment. +* +* DESCRIPTION: +* This function get environment information and initialize controller +* internal/external environment. For example +* 1) MPP settings according to board MPP macros. +* NOTE: It is the user responsibility to shut down all DMA channels +* in device and disable controller sub units interrupts during +* boot process. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCtrlEnvInit(MV_VOID) +{ + MV_U32 mppGroup; + MV_U32 mppVal; + MV_U32 i, gppMask; + + + /* Disable MBus Error Propagation */ + MV_REG_BIT_RESET(SOC_COHERENCY_FABRIC_CTRL_REG, BIT8); + + /* Use Background sync barrier (polling) for I/O cache coherency */ + MV_REG_BIT_SET(SOC_CIB_CTRL_CFG_REG, BIT8); + + /* MPP Init - scan which modeule is connected */ + mvBoardMppModulesScan(); + + /* Read MPP config values from board level and write MPP options to HW */ + for (mppGroup = 0; mppGroup < MV_MPP_MAX_GROUP; mppGroup++) { + mppVal = mvBoardMppGet(mppGroup); /* get pre-defined values */ + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + + /* disable all GPIO interrupts */ + for (i = 0; i < MV_GPP_MAX_GROUP; i++) { + MV_REG_WRITE(GPP_INT_MASK_REG(i), 0x0); + MV_REG_WRITE(GPP_INT_LVL_REG(i), 0x0); + } + + /* clear all int */ + for (i = 0; i < MV_GPP_MAX_GROUP; i++) + MV_REG_WRITE(GPP_INT_CAUSE_REG(i), 0x0); + + /* Set gpp interrupts as needed */ + for (i = 0; i < MV_GPP_MAX_GROUP; i++) { + gppMask = mvBoardGpioIntMaskGet(i); + mvGppTypeSet(i, gppMask , (MV_GPP_IN & gppMask)); + mvGppPolaritySet(i, gppMask , (MV_GPP_IN_INVERT & gppMask)); + } + + /* Scan for other modules (SERDES/LVDS/...) */ + mvBoardOtherModulesScan(); + + /* Update interfaces configuration based on above scan */ + if (MV_OK != mvCtrlSerdesPhyConfig()) + mvOsPrintf("mvCtrlEnvInit: Can't init some or all SERDES lanes\n"); + + MV_REG_BIT_SET(PUP_EN_REG,0x17); /* Enable GBE0, GBE1, LCD and NFC PUP */ + + mvOsDelay(100); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlMppRegGet - return reg address of mpp group +* +* DESCRIPTION: +* +* INPUT: +* mppGroup - MPP group. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - Register address. +* +*******************************************************************************/ +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) +{ + MV_U32 ret; + + if (mppGroup >= MV_MPP_MAX_GROUP) + mppGroup = 0; + + ret = MPP_CONTROL_REG(mppGroup); + + return ret; +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxIfGet(MV_VOID) +{ + switch (mvCtrlModelGet()) { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 7; + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_PEX_MAX_IF; + + default: + return 0; + } +} +#endif + +/******************************************************************************* +* mvCtrlPexMaxUnitGet - Get Marvell controller number of PEX units. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX units. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxUnitGet(MV_VOID) +{ + switch (mvCtrlModelGet()) { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 2; + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + return 3; + + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_PEX_MAX_UNIT; + + default: + return 0; + } +} + + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPciMaxIfGet(MV_VOID) +{ + switch (mvCtrlModelGet()) { + case MV_FPGA_DEV_ID: + return 1; + + default: + return 0; + } +} +#endif + +/******************************************************************************* +* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of etherent port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of etherent port. +* +*******************************************************************************/ +MV_U32 mvCtrlEthMaxPortGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + switch (devId) { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return MV_78130_ETH_MAX_PORT; + + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return MV_78460_ETH_MAX_PORT; + + default: + return 0; + } +} + +/******************************************************************************* +* mvCtrlEthMaxCPUsGet - Get Marvell controller number of CPUs. +* +* DESCRIPTION: +* This function returns Marvell controller number of CPUs. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of CPUs. +* +*******************************************************************************/ +MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + /* FIXME - assuming MV_78460_DEV_ID */ + devId = MV_78460_DEV_ID; + + switch (devId) { + case MV_78130_DEV_ID: + case MV_78230_DEV_ID: + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + return 4; + + default: + return 0; + } +} + + +#if defined(MV_INCLUDE_SATA) +/******************************************************************************* +* mvCtrlSataMaxPortGet - Get Marvell controller number of Sata ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of Sata ports. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of Sata ports. +* +*******************************************************************************/ +MV_U32 mvCtrlSataMaxPortGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_SATA_MAX_CHAN; + break; + } + return res; +} +#endif + +#if defined(MV_INCLUDE_IDMA) +/******************************************************************************* +* mvCtrlIdmaMaxChanGet - Get Marvell controller number of IDMA channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of IDMA channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of IDMA channels. +* +*******************************************************************************/ +MV_U32 mvCtrlIdmaMaxChanGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_IDMA_MAX_CHAN; + break; + } + return res; +} + +/******************************************************************************* +* mvCtrlIdmaMaxUnitGet - Get Marvell controller number of IDMA units. +* +* DESCRIPTION: +* This function returns Marvell controller number of IDMA units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of IDMA units. +* +*******************************************************************************/ +MV_U32 mvCtrlIdmaMaxUnitGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_IDMA_MAX_UNIT; + break; + } + return res; +} +#endif /* MV_INCLUDE_IDMA */ + +#if defined(MV_INCLUDE_XOR) +/******************************************************************************* +* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR channels. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxChanGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_XOR_MAX_CHAN; + break; + } + return res; +} + +/******************************************************************************* +* mvCtrlXorMaxUnitGet - Get Marvell controller number of XOR units. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR units. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR units. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxUnitGet(MV_VOID) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + default: + res = MV_XOR_MAX_UNIT; + break; + } + return res; +} + +#endif + +#if defined(MV_INCLUDE_USB) +/******************************************************************************* +* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns number of Marvell USB controllers. +* +*******************************************************************************/ +MV_U32 mvCtrlUsbMaxGet(void) +{ + MV_U32 devId; + MV_U32 res = 0; + + devId = mvCtrlModelGet(); + + switch (devId) { + case MV_FPGA_DEV_ID: + res = 0; + break; + + default: + res = ARMADA_XP_MAX_USB_PORTS; + break; + } + + return res; +} +#endif + +#if defined(MV_INCLUDE_LEGACY_NAND) +/******************************************************************************* +* mvCtrlNandSupport - Return if this controller has integrated NAND flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if NAND is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlNandSupport(MV_VOID) +{ + return ARMADA_XP_NAND; +} +#endif + +#if defined(MV_INCLUDE_SDIO) +/******************************************************************************* +* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if SDIO is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlSdioSupport(MV_VOID) +{ + return ARMADA_XP_SDIO; +} +#endif + +#if defined(MV_INCLUDE_TDM) +/******************************************************************************* +* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if TDM is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlTdmSupport(MV_VOID) +{ + return ARMADA_XP_TDM; +} + +/******************************************************************************* +* mvCtrlTdmMaxGet - Return the maximum number of TDM ports. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The number of TDM ports in device. +* +*******************************************************************************/ +MV_U32 mvCtrlTdmMaxGet(MV_VOID) +{ + return ARMADA_XP_MAX_TDM_PORTS; +} + +/******************************************************************************* +* mvCtrlTdmTypeGet +* +* DESCRIPTION: +* Return the TDM unit type being compiled in. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The TDM unit type. +* +*******************************************************************************/ +MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID) +{ + return TDM_UNIT_32CH; +} + +/******************************************************************************* +* mvCtrlTdmUnitIrqGet +* +* DESCRIPTION: +* Return the TDM unit IRQ number depending on the TDM unit compilation +* options. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +******************************************************************************/ +MV_U32 mvCtrlTdmUnitIrqGet(MV_VOID) +{ + return MV_TDM_IRQ_NUM; +} + +#endif /* if defined(MV_INCLUDE_TDM) */ + +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ +#if defined(CONFIG_SYNO_ARMADA_ARCH) + MV_U32 model = MV_78230_DEV_ID; +#else + MV_U32 devId; + MV_U16 model = 0; + MV_U32 reg, reg2; + + /* if PEX0 clocks are disabled - enabled it to read */ + reg = MV_REG_READ(POWER_MNG_CTRL_REG); + if ((reg & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) { + reg2 = ((reg & ~PMC_PEXSTOPCLOCK_MASK(0)) | PMC_PEXSTOPCLOCK_EN(0)); + MV_REG_WRITE(POWER_MNG_CTRL_REG, reg2); + } + + devId = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_DEVICE_AND_VENDOR_ID)); + + /* Reset the original value of the PEX0 clock */ + if ((reg & PMC_PEXSTOPCLOCK_MASK(0)) == PMC_PEXSTOPCLOCK_STOP(0)) + MV_REG_WRITE(POWER_MNG_CTRL_REG, reg); + + + model = (MV_U16) ((devId >> 16) & 0xFFFF); +#endif + return model; +} + +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller device revision number +* +* DESCRIPTION: +* This function returns 8bit describing the device revision as defined +* in PCI Express Class Code and Revision ID Register. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 8bit desscribing Marvell controller revision number +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + MV_U8 revNum; +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID, 0); + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +#endif + revNum = (MV_U8) MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PCI_CLASS_CODE_AND_REVISION_ID)); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); +#endif + return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); +} + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlNameGet(char *pNameBuff) +{ + if (mvCtrlModelGet() == 0x7800) + mvOsSPrintf(pNameBuff, "%s78XX", SOC_NAME_PREFIX); + else + mvOsSPrintf(pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, mvCtrlModelGet(), mvCtrlRevGet()); + return MV_OK; +} + +/******************************************************************************* +* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision +* +* DESCRIPTION: +* This function returns 32bit value describing both Device ID and Revision +* as defined in PCI Express Device and Vendor ID Register and device revision +* as defined in PCI Express Class Code and Revision ID Register. + +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing both controller device ID and revision number +* +*******************************************************************************/ +MV_U32 mvCtrlModelRevGet(MV_VOID) +{ + return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); +} + +/******************************************************************************* +* mvCtrlModelRevNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) +{ + switch (mvCtrlModelRevGet()) { + case MV_78130_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78130_Z1_NAME); + break; + + case MV_6710_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_6710_Z1_NAME); + break; + + case MV_78230_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78230_Z1_NAME); + break; + case MV_78160_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78160_Z1_NAME); + break; + case MV_78260_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78260_Z1_NAME); + break; + case MV_78460_Z1_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78460_Z1_NAME); + break; + + case MV_78130_A0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78130_A0_NAME); + break; + case MV_78230_A0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78230_A0_NAME); + break; + case MV_78160_A0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78160_A0_NAME); + break; + case MV_78260_A0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78260_A0_NAME); + break; + case MV_78460_A0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78460_A0_NAME); + break; + case MV_78130_B0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78130_B0_NAME); + break; + case MV_78230_B0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78230_B0_NAME); + break; + case MV_78160_B0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78160_B0_NAME); + break; + case MV_78260_B0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78260_B0_NAME); + break; + case MV_78460_B0_ID: + mvOsSPrintf(pNameBuff, "%s", MV_78460_B0_NAME); + break; + + default: + mvCtrlNameGet(pNameBuff); + break; + } + + return MV_OK; +} + +MV_U32 gDevId = -1; +/******************************************************************************* +* mvCtrlDevFamilyIdGet - Get Device ID +* +* DESCRIPTION: +* This function returns Device ID. +* +* INPUT: +* ctrlModel. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board Device ID number, '-1' if Device ID is undefined. +* +*******************************************************************************/ +MV_U32 mvCtrlDevFamilyIdGet(MV_U16 ctrlModel) +{ + if (gDevId == -1) + { + switch (ctrlModel) { + case MV_78130_DEV_ID: + case MV_78160_DEV_ID: + case MV_78230_DEV_ID: + case MV_78260_DEV_ID: + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + gDevId=MV_78XX0; + return gDevId; + break; + default: + return MV_ERROR; + } + } + else + return gDevId; +} + +static const char *cntrlName[] = TARGETS_NAME_ARRAY; + +/******************************************************************************* +* mvCtrlTargetNameGet - Get Marvell controller target name +* +* DESCRIPTION: +* This function convert the trget enumeration to string. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Target name (const MV_8 *) +*******************************************************************************/ +const MV_8 *mvCtrlTargetNameGet(MV_TARGET target) +{ + if (target >= MAX_TARGETS) + return "target unknown"; + + return cntrlName[target]; +} + +/******************************************************************************* +* mvCtrlPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvCtrlPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN win; + MV_U32 pexIf; + MV_U32 bar, winNum; + MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet(); + MV_U32 pexHWInf = 0; + + for (pexIf = 0; pexIf < boardPexInfo->boardPexIfNum; pexIf++) { + pexHWInf = boardPexInfo->pexMapping[pexIf]; + + + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexHWInf)) + continue; + mvOsOutput("\n"); + mvOsOutput("PEX%d:\n", pexHWInf); + mvOsOutput("-----\n"); + + mvOsOutput("\nPex Bars \n\n"); + + for (bar = 0; bar < PEX_MAX_BARS; bar++) { + memset(&pexBar, 0, sizeof(MV_PEX_BAR)); + + mvOsOutput("%s ", pexBarNameGet(bar)); + + if (mvPexBarGet(pexHWInf, bar, &pexBar) == MV_OK) { + if (pexBar.enable) { + mvOsOutput("base %08x, ", pexBar.addrWin.baseLow); + if (pexBar.addrWin.size == 0) + mvOsOutput("size %3dGB ", 4); + else + mvSizePrint(pexBar.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + mvOsOutput("\nPex Decode Windows\n\n"); + + for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) { + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvPexTargetWinRead(pexHWInf, winNum, &win) == MV_OK) { + if (win.winInfo.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(mvCtrlTargetByWinInfoGet(&win.winInfo)), + win.winInfo.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.winInfo.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("default win - "); + + if (mvPexTargetWinRead(pexHWInf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + memset(&win, 0, sizeof(MV_PEX_DEC_WIN)); + + mvOsOutput("Expansion ROM - "); + + if (mvPexTargetWinRead(pexHWInf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) { + mvOsOutput("%s ", mvCtrlTargetNameGet(win.target)); + mvOsOutput("\n"); + } + } +} + +/******************************************************************************* +* mvUnitAddrDecShow - Print the Unit's address decode map. +* +* DESCRIPTION: +* This is a generic function for printing the different unit's address +* decode map. +* +* INPUT: +* unit - The unit to print the address decode for. +* name - The unit's name. +* winGetFuncPtr - A pointer to the HAL's window get function. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void mvUnitAddrDecShow(MV_U8 numUnits, MV_UNIT_ID unitId, const char *name, MV_WIN_GET_FUNC_PTR winGetFuncPtr) +{ + MV_UNIT_WIN_INFO win; + MV_U32 unit, i; + + for (unit = 0; unit < numUnits; unit++) { + + if (MV_FALSE == mvCtrlPwrClckGet(unitId, unit)) + continue; + mvOsOutput("\n"); + mvOsOutput("%s %d:\n", name, unit); + mvOsOutput("----\n"); + + for (i = 0; i < 16; i++) { + memset(&win, 0, sizeof(MV_UNIT_WIN_INFO)); + + mvOsOutput("win%d - ", i); + + if (winGetFuncPtr(unit, i, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(mvCtrlTargetByWinInfoGet(&win)), + win.addrWin.baseLow); + mvOsOutput("...."); + if (win.addrWin.size == 0) + mvOsOutput("size %3dGB ", 4); + else + mvSizePrint(win.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } + } + return; +} + +/******************************************************************************* +* mvCtrlAddrDecShow - Print the Controller units address decode map. +* +* DESCRIPTION: +* This function the Controller units address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCtrlAddrDecShow(MV_VOID) +{ + mvCpuIfAddDecShow(); + mvAhbToMbusAddDecShow(); +#if defined(MV_INCLUDE_PEX) + mvCtrlPexAddrDecShow(); +#endif +#if defined(MV_INCLUDE_USB) + mvUnitAddrDecShow(mvCtrlUsbMaxGet(), USB_UNIT_ID, "USB", mvUsbWinRead); +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#if defined(MV_ETH_LEGACY) + mvUnitAddrDecShow(mvCtrlEthMaxPortGet(), ETH_GIG_UNIT_ID, "ETH", mvEthWinRead); +#else + mvUnitAddrDecShow(mvCtrlEthMaxPortGet(), ETH_GIG_UNIT_ID, "ETH", mvNetaWinRead); +#endif /* MV_ETH_LEGACY */ +#endif /* MV_INCLUDE_GIG_ETH */ + +#if defined(MV_INCLUDE_XOR) + mvUnitAddrDecShow(mvCtrlXorMaxChanGet(), XOR_UNIT_ID, "XOR", mvXorTargetWinRead); +#endif +#if defined(MV_INCLUDE_SATA) + mvUnitAddrDecShow(mvCtrlSataMaxPortGet(), SATA_UNIT_ID, "Sata", mvSataWinRead); +#endif +} + +/******************************************************************************* +* ctrlSizeToReg - Extract size value for register assignment. +* +* DESCRIPTION: +* Address decode size parameter must be programed from LSB to MSB as +* sequence of 1's followed by sequence of 0's. The number of 1's +* specifies the size of the window in 64 KB granularity (e.g. a +* value of 0x00ff specifies 256x64k = 16 MB). +* This function extract the size value from the size parameter according +* to given aligment paramter. For example for size 0x1000000 (16MB) and +* aligment 0x10000 (64KB) the function will return 0x00FF. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size register value correspond to size parameter. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) +{ + MV_U32 retVal; + + /* Check size parameter alignment */ + if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); + return -1; + } + + /* Take out the "alignment" portion out of the size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + /* and size is 0x1000000 (16MB) for example */ + while (alignment & 1) { /* Check that alignmet LSB is set */ + size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ + alignment = (alignment >> 1); + } + + /* If after the alignment first '0' was met we still have '1' in */ + /* it then aligment is invalid (not power of 2) */ + if (alignment) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", (MV_U32) alignment)); + return -1; + } + + /* Now the size is shifted right according to aligment: 0x0100 */ + size--; /* Now the size is a sequance of '1': 0x00ff */ + retVal = size; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + while (size & 1) /* Check that LSB is set */ + size = (size >> 1); /* If LSB is set, move one bit to the right */ + + if (size) { /* Sequance of 1's is over. Check that we have no other 1's */ + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", size)); + return -1; + } + return retVal; +} + +/******************************************************************************* +* ctrlRegToSize - Extract size value from register value. +* +* DESCRIPTION: +* This function extract a size value from the register size parameter +* according to given aligment paramter. For example for register size +* value 0xff and aligment 0x10000 the function will return 0x01000000. +* +* INPUT: +* regSize - Size as in register format. See ctrlSizeToReg. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) +{ + MV_U32 temp; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ + + while (temp & 1) /* Check that LSB is set */ + temp = (temp >> 1); /* If LSB is set, move one bit to the right */ + + if (temp) { /* Sequance of 1's is over. Check that we have no other 1's */ + DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", regSize)); + return -1; + } + + /* Check that aligment is a power of two */ + temp = alignment - 1; /* Now the alignmet is a sequance of '1' (0xffff) */ + + while (temp & 1) /* Check that alignmet LSB is set */ + temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ + + /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ + /* then 'temp' is invalid (not power of 2) */ + if (temp) { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", alignment)); + return -1; + } + + regSize++; /* Now the size is 0x0100 */ + + /* Add in the "alignment" portion to the register size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + + while (alignment & 1) { /* Check that alignmet LSB is set */ + regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ + alignment = (alignment >> 1); + } + + return regSize; +} + +/******************************************************************************* +* ctrlSizeRegRoundUp - Round up given size +* +* DESCRIPTION: +* This function round up a given size to a size that fits the +* restrictions of size format given an aligment parameter. +* to given aligment paramter. For example for size parameter 0xa1000 and +* aligment 0x1000 the function will return 0xFF000. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size value correspond to size in register. +*******************************************************************************/ +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) +{ + MV_U32 msbBit = 0; + MV_U32 retSize; + + /* Check if size parameter is already comply with restriction */ + if (!(-1 == ctrlSizeToReg(size, alignment))) + return size; + + while (size) { + size = (size >> 1); + msbBit++; + } + + retSize = (1 << msbBit); + + if (retSize < alignment) + return alignment; + else + return retSize; +} + +/******************************************************************************* +* mvCtrlIsBootFromNOR +* +* DESCRIPTION: +* Check if device is configured to boot from NOR flash according to the +* SAR registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from SPI. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromNOR(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if (satr == MSAR_BOOT_NOR) + return MV_TRUE; + else + return MV_FALSE; +} + +/******************************************************************************* +* mvCtrlIsBootFromSPI +* +* DESCRIPTION: +* Check if device is configured to boot from SPI flash according to the +* SAR registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from SPI. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if (satr == MSAR_BOOT_SPI) + return MV_TRUE; + else + return MV_FALSE; +} + +/******************************************************************************* +* mvCtrlIsBootFromNAND +* +* DESCRIPTION: +* Check if device is confiogured to boot from NAND flash according to the SAR +* registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if device boot from NAND. +*******************************************************************************/ +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) +{ + MV_U32 satr; + + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_BOOT_MODE_MASK; + + if ((satr == MSAR_BOOT_DOVE_NAND) || (satr == MSAR_BOOT_LEGACY_NAND)) + return MV_TRUE; + else + return MV_FALSE; +} + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +/******************************************************************************* +* mvCtrlPwrClckSet - Set Power State for specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + /* Clock gating is not supported on FPGA */ + if (mvCtrlModelGet() == MV_FPGA_DEV_ID) + return; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_CESASTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_CESASTOPCLOCK_MASK); + + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK(index)); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + + break; +#endif + case TDM_32CH_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + else + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + break; + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrClckGet - Get Power State of specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); + MV_BOOL state = MV_TRUE; + + /* Clock gating is not supported on FPGA */ + if (mvCtrlModelGet() == MV_FPGA_DEV_ID) + return MV_TRUE; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if ((reg & PMC_PEXSTOPCLOCK_MASK(index)) == PMC_PEXSTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if ((reg & PMC_CESASTOPCLOCK_MASK) == PMC_CESASTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if ((reg & PMC_USBSTOPCLOCK_MASK(index)) == PMC_USBSTOPCLOCK_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if ((reg & PMC_SDIOSTOPCLOCK_MASK) == PMC_SDIOSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_32CH_UNIT_ID: + if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + + return state; +} + +/******************************************************************************* +* mvCtrlPwrMemSet - Set Power State for memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX), PMC_PEXSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX), PMC_PEXSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE), PMC_GESTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE), PMC_GESTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA), PMC_SATASTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA), PMC_SATASTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA), PMC_CESASTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA), PMC_CESASTOPMEM_MASK); + + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB), PMC_USBSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB), PMC_USBSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR), PMC_XORSTOPMEM_STOP(index)); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR), PMC_XORSTOPMEM_MASK(index)); + + break; +#endif +#if defined(MV_INCLUDE_BM) + case BM_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM), PMC_BMSTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM), PMC_BMSTOPMEM_MASK); + + break; +#endif +#if defined(MV_INCLUDE_PNC) + case PNC_UNIT_ID: + if (enable == MV_FALSE) + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC), PMC_PNCSTOPMEM_STOP); + else + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC), PMC_PNCSTOPMEM_MASK); + + break; +#endif + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrMemGet - Get Power State of memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg; + MV_BOOL state = MV_TRUE; + + switch (unitId) { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PEX)); + if ((reg & PMC_PEXSTOPMEM_MASK(index)) == PMC_PEXSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_GE)); + if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_SATA)); + if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_CESA)); + if ((reg & PMC_CESASTOPMEM_MASK) == PMC_CESASTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_USB)); + if ((reg & PMC_USBSTOPMEM_MASK(index)) == PMC_USBSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_XOR)); + if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_BM) + case BM_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_BM)); + if ((reg & PMC_BMSTOPMEM_MASK) == PMC_BMSTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_PNC) + case PNC_UNIT_ID: + reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG(PMC_MCR_NUM_PNC)); + if ((reg & PMC_PNCSTOPMEM_MASK) == PMC_PNCSTOPMEM_STOP) + state = MV_FALSE; + else + state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + + return state; +} +#else +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + return; +} + +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + return MV_TRUE; +} +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +/******************************************************************************* +* mvCtrlSerdesMaxLinesGet - Get Marvell controller number of SERDES lines. +* +* DESCRIPTION: +* This function returns Marvell controller number of SERDES lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX units. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID) +{ + switch (mvCtrlModelGet()) { + case MV_78130_DEV_ID: + case MV_6710_DEV_ID: + case MV_78230_DEV_ID: + return 7; + case MV_78160_DEV_ID: + case MV_78260_DEV_ID: + return 12; + break; + case MV_78460_DEV_ID: + case MV_78000_DEV_ID: + return 16; + default: + return 0; + } +} + +MV_U32 mvCtrlDDRBudWidth(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(0x1400); + + return (reg & 0x8000) ? 64 : 32; +} +MV_BOOL mvCtrlDDRThruXbar(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(0x20184); + + return (reg & 0x1) ? MV_FALSE : MV_TRUE; +} + +MV_BOOL mvCtrlDDRECC(MV_VOID) +{ + MV_U32 reg; + reg = MV_REG_READ(REG_SDRAM_CONFIG_ADDR); + + return (reg & (0x1 << REG_SDRAM_CONFIG_ECC_OFFS)) ? MV_TRUE : MV_FALSE; +} + +static const MV_U8 serdesCfg[][8] = SERDES_CFG; + +/******************************************************************************* +* mvCtrlSerdesPhyConfig +* +* DESCRIPTION: +* Configure Serdes MUX and init PHYs connected to SERDES lines. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Status +* +*******************************************************************************/ +MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID) +{ + MV_U32 socCtrlReg, RegX4, serdesLine0_7; + MV_U32 serdesLineCfg; + MV_U8 serdesLineNum; + MV_U8 pexIf; + MV_U8 pexUnit; + MV_STATUS status = MV_OK; + MV_U32 pexIfNum = mvCtrlPexMaxIfGet(); + MV_U8 maxSerdesLines = mvCtrlSerdesMaxLinesGet(); + MV_BOARD_PEX_INFO *boardPexInfo = mvBoardPexInfoGet(); + +/* this is a mapping of the final power management clock gating control register value @ 0x18220.*/ + MV_U32 powermngmntctrlregmap = 0x0; + MV_U32 tmpcounter = 0; + + /* Check if no SERDESs available - FPGA */ + if (maxSerdesLines == 0) + return MV_OK; + + memset(boardPexInfo, 0, sizeof(MV_BOARD_PEX_INFO)); + socCtrlReg = MV_REG_READ(SOC_CTRL_REG); + RegX4 = MV_REG_READ(GEN_PURP_RES_2_REG); + boardPexInfo->pexUnitCfg[0].pexCfg = ((RegX4 & 0x0F) == 0x0F) ? PEX_BUS_MODE_X4: PEX_BUS_MODE_X1; + boardPexInfo->pexUnitCfg[1].pexCfg = ((RegX4 & 0x0F0) == 0x0F0) ? PEX_BUS_MODE_X4: PEX_BUS_MODE_X1; + boardPexInfo->pexUnitCfg[2].pexCfg = ((RegX4 & 0x0F00) == 0x0F00) ? PEX_BUS_MODE_X4: PEX_BUS_MODE_X1; + boardPexInfo->pexUnitCfg[3].pexCfg = ((RegX4 & 0x0F000) == 0x0F000) ? PEX_BUS_MODE_X4: PEX_BUS_MODE_X1; + + /* Prepare PHY parameters for each step according to MUX selection */ + for (pexIf = 0; pexIf < pexIfNum; pexIf++) { + /* for each serdes lane*/ + pexUnit = (pexIf<9)? (pexIf >> 2) : 3; + if ((socCtrlReg & (1<< pexUnit)) == 0){ + boardPexInfo->pexUnitCfg[pexUnit].pexCfg = PEX_BUS_DISABLED; + continue; + } + boardPexInfo->pexMapping[boardPexInfo->boardPexIfNum] = pexIf; + boardPexInfo->boardPexIfNum++; + boardPexInfo->pexUnitCfg[pexUnit].pexLaneStat[pexIf] = 0x1; + powermngmntctrlregmap = powermngmntctrlregmap | (0x1<<(pexIf+5)); + if (pexIf < 8) { + if (boardPexInfo->pexUnitCfg[pexUnit].pexCfg == PEX_BUS_MODE_X4){ + powermngmntctrlregmap |= (0xf<<(pexIf+5)); + pexIf += 3; + } + else + powermngmntctrlregmap |= (0x1<<(pexIf+5)); + } + else + powermngmntctrlregmap |= (0x1<<(18+pexIf)); + } + serdesLine0_7 = MV_REG_READ(SERDES_LINE_MUX_REG_0_7); + + for (serdesLineNum = 0; serdesLineNum < 8; serdesLineNum++) { + + serdesLineCfg =(serdesLine0_7 >> (serdesLineNum << 2)) & 0xF; + + if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SATA]) { + + if ((serdesLineNum == 4) || (serdesLineNum == 6)) + powermngmntctrlregmap |= PMC_SATASTOPCLOCK_MASK(0); + else if (serdesLineNum == 5) + powermngmntctrlregmap |= PMC_SATASTOPCLOCK_MASK(1); + else + goto err_cfg; + + } else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII0]) + powermngmntctrlregmap |= PMC_GESTOPCLOCK_MASK(0); + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII1]) + powermngmntctrlregmap |= PMC_GESTOPCLOCK_MASK(1); + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII2]) + powermngmntctrlregmap |= PMC_GESTOPCLOCK_MASK(2); + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_SGMII3]) + powermngmntctrlregmap |= PMC_GESTOPCLOCK_MASK(3); + else if (serdesLineCfg == serdesCfg[serdesLineNum][SERDES_UNIT_QSGMII]) + powermngmntctrlregmap |= PMC_GESTOPCLOCK_MASK(0) | PMC_GESTOPCLOCK_MASK(1) | PMC_GESTOPCLOCK_MASK(2) | PMC_GESTOPCLOCK_MASK(3); + } + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + powermngmntctrlregmap = powermngmntctrlregmap | BIT4; /* Enabling port GE0 always since we need SMI 0 to access other PHYs*/ + /*check if GE1 is not enabled via MPPs and not Serdes - if yes you have to enable the clock*/ + if (MV_TRUE == mvBoardIsGbEPortConnected(1)) + powermngmntctrlregmap = powermngmntctrlregmap | PMC_GESTOPCLOCK_MASK(1); + + + /* Hard core enable DDR, USB, SDIO, LCD, XOR, IDMA, CESA cause we don't support this at this momemt*/ + powermngmntctrlregmap = powermngmntctrlregmap | (BIT0 | BIT13 | (0x1FF<<16) | BIT24 | BIT25 | BIT28 | BIT31); + DB(mvOsPrintf("%s:Shutting down unused interfaces:\n", __func__)); + /*now report everything to the screen*/ + if (!(powermngmntctrlregmap & PMC_SATASTOPCLOCK_MASK(0))) { + DB(mvOsPrintf("%s: SATA0\n", __func__)); + mvCtrlPwrClckSet(SATA_UNIT_ID, 0, MV_FALSE); + } + if (!(powermngmntctrlregmap & PMC_SATASTOPCLOCK_MASK(1))) { + DB(mvOsPrintf("%s: SATA1\n", __func__)); + mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE); + } + for (tmpcounter = 0; tmpcounter < 4; tmpcounter++) { + if (!(powermngmntctrlregmap & (1 << (4 - tmpcounter)))) { + /*mvOsOutput(" GBE%d\n", tmpcounter );*/ + DB(mvOsPrintf("%s: GBE%d\n", __func__, tmpcounter)); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, tmpcounter, MV_FALSE); + } + } + for (tmpcounter = 0; tmpcounter < 8; tmpcounter++) { + if (!(powermngmntctrlregmap & (1 << (5 + tmpcounter)))) { + DB(mvOsPrintf("%s: PEX%d.%d\n", __func__, tmpcounter>>2, tmpcounter % 4)); + mvCtrlPwrClckSet(PEX_UNIT_ID, tmpcounter, MV_FALSE); + } + } + if (!(powermngmntctrlregmap & BIT26)) { + DB(mvOsPrintf("%s: PEX2\n", __func__)); + mvCtrlPwrClckSet(PEX_UNIT_ID, 8, MV_FALSE); + } + if (!(powermngmntctrlregmap & BIT27)) { + DB(mvOsPrintf("%s: PEX3\n", __func__)); + mvCtrlPwrClckSet(PEX_UNIT_ID, 9, MV_FALSE); + } + + +/*this code is valid for all devices after Z1*/ + if(!(powermngmntctrlregmap & BIT25)) { + DB(mvOsPrintf("%s: TDM\n", __func__)); + mvCtrlPwrClckSet(TDM_32CH_UNIT_ID, 0, MV_FALSE); + } + /*apply clock gatting*/ + MV_REG_WRITE(POWER_MNG_CTRL_REG, MV_REG_READ(POWER_MNG_CTRL_REG) & powermngmntctrlregmap); + /*the Sata driver doesn't support clock gating at this point so we enable the logic to the block*/ + MV_REG_WRITE(POWER_MNG_CTRL_REG, MV_REG_READ(POWER_MNG_CTRL_REG) | (BIT15 | BIT30)); +#endif /* defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + + + return status; +err_cfg: + DB(mvOsPrintf("%s: Wrong CFG (%#x) for SERDES line %d.\n", + __func__, serdesLineCfg, serdesLineNum)); + return MV_ERROR; + +} + + diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h new file mode 100755 index 000000000..f0b56f2cb --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvLib.h @@ -0,0 +1,278 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvLibh +#define __INCmvCtrlEnvLibh + +/* includes */ +#include "mvSysHwConfig.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +/*#include "boardEnv/mvBoardEnvLib.h"*/ + +/* 0 for Auto scan mode, 1 for manual. */ +#define MV_INTERNAL_SWITCH_SMI_SCAN_MODE 0 + +/* typedefs */ +typedef MV_STATUS(*MV_WIN_GET_FUNC_PTR)(MV_U32, MV_U32, MV_UNIT_WIN_INFO*); + +/* This enumerator describes the possible HW cache coherency policies the */ +/* controllers supports. */ +typedef enum _mvCachePolicy { + NO_COHERENCY, /* No HW cache coherency support */ + WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ + WB_COHERENCY /* HW cache coherency supported in Write Back policy */ +} MV_CACHE_POLICY; + + +/* The swapping is referred to a 64-bit words (as this is the controller */ +/* internal data path width). This enumerator describes the possible */ +/* data swap types. Below is an example of the data 0x0011223344556677 */ +typedef enum _mvSwapType { + MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ + MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ + MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ + MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ + SWAP_TYPE_MAX /* Delimiter for this enumerator */ +} MV_SWAP_TYPE; + +typedef enum { + SERDES_UNIT_UNCONNECTED = 0x0, + SERDES_UNIT_PEX = 0x1, + SERDES_UNIT_SATA = 0x2, + SERDES_UNIT_SGMII0 = 0x3, + SERDES_UNIT_SGMII1 = 0x4, + SERDES_UNIT_SGMII2 = 0x5, + SERDES_UNIT_SGMII3 = 0x6, + SERDES_UNIT_QSGMII = 0x7, + SERDES_UNIT_LAST +} MV_SERDES_UNIT_INDX; + +typedef enum { + PEX_BUS_DISABLED = 0, + PEX_BUS_MODE_X1 = 1, + PEX_BUS_MODE_X4 = 2, + PEX_BUS_MODE_X8 = 3 +} MV_PEX_UNIT_CFG; + +/* Configuration per SERDES line. + Each nibble is MV_SERDES_LINE_TYPE */ +typedef struct _boardSerdesConf { + MV_U32 enableSerdesConfiguration; /*This will determine if mvCtrlSerdesPhyConfig will configure the serdes*/ + MV_U32 serdesLine0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */ + MV_U32 serdesLine8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */ + MV_PEX_UNIT_CFG pex0Mod; + MV_PEX_UNIT_CFG pex1Mod; + MV_PEX_UNIT_CFG pex2Mod; + MV_PEX_UNIT_CFG pex3Mod; + MV_U32 busSpeed; /* Bus speed - one bit per SERDES line: + Low speed (0) High speed (1) + PEX 2.5 G (10 bit) 5 G (20 bit) + SATA 1.5 G 3 G + SGMII 1.25 Gbps 3.125 Gbps */ +} MV_SERDES_CFG; +/* Termal Sensor Registers */ +#define TSEN_STATUS_REG 0x184C4 +#define TSEN_STATUS_TEMP_OUT_OFFSET 1 +#define TSEN_STATUS_TEMP_OUT_MASK (0x1FF << TSEN_STATUS_TEMP_OUT_OFFSET) + +#define TSEN_CONF_REG 0x184D0 +#define TSEN_CONF_OTF_CALIB_MASK (0x1 << 30) +#define TSEN_CONF_REF_CAL_MASK (0x1FF << 11) +#define TSEN_CONF_SOFT_RESET_MASK (0x1 << 1) +#define TSEN_CONF_START_CALIB_MASK (0x1 << 25) + + +/* BIOS Modes related defines */ + +#define SAR0_BOOTWIDTH_OFFSET 3 +#define SAR0_BOOTWIDTH_MASK (0x3 << SAR0_BOOTWIDTH_OFFSET) +#define SAR0_BOOTSRC_OFFSET 5 +#define SAR0_BOOTSRC_MASK (0xF << SAR0_BOOTSRC_OFFSET) + +#define SAR0_L2_SIZE_OFFSET 19 +#define SAR0_L2_SIZE_MASK (0x3 << SAR0_L2_SIZE_OFFSET) +#define SAR0_CPU_FREQ_OFFSET 21 +#define SAR0_CPU_FREQ_MASK (0x7 << SAR0_CPU_FREQ_OFFSET) +#define SAR0_FABRIC_FREQ_OFFSET 24 +#define SAR0_FABRIC_FREQ_MASK (0xF << SAR0_FABRIC_FREQ_OFFSET) +#define SAR0_CPU0CORE_OFFSET 31 +#define SAR0_CPU0CORE_MASK (0x1 << SAR0_CPU0CORE_OFFSET) +#define SAR1_CPU0CORE_OFFSET 0 +#define SAR1_CPU0CORE_MASK (0x1 << SAR1_CPU0CORE_OFFSET) + +#define PEX_CLK_100MHZ_OFFSET 2 +#define PEX_CLK_100MHZ_MASK (0x1 << PEX_CLK_100MHZ_OFFSET) + +#define SAR1_CPU_CORE_OFFSET 3 +#define SAR1_CPU_CORE_MASK (0x3 << SAR1_CPU_CORE_OFFSET) +#define SAR1_FABRIC_MODE_OFFSET 19 +#define SAR1_FABRIC_MODE_MASK (0x1 << SAR1_FABRIC_MODE_OFFSET) +#define SAR1_CPU_MODE_OFFSET 20 +#define SAR1_CPU_MODE_MASK (0x1 << SAR1_CPU_MODE_OFFSET) + +#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) +#define BIOS_MODES_NUM 4 + +typedef struct { + char *name; + MV_U16 confId; + MV_U16 code; + MV_U8 l2size; + MV_U8 cpuFreq; + MV_U8 cpuFreqMode; + MV_U8 fabricFreq; + MV_U8 AltfabricFreq; + MV_U8 fabricFreqMode; + MV_U8 cpuEna; + MV_U8 cpuEndianess; + MV_U8 dramBusWidth; + MV_U8 bootSource; + MV_U8 bootWidth; +} MV_BIOS_MODE; + +extern MV_BIOS_MODE bios_modes[]; +extern MV_BIOS_MODE bios_modes_b0[]; + +/* mcspLib.h API list */ +MV_U32 mvCtrlGetCpuNum(MV_VOID); +MV_U32 mvCtrlGetQuadNum(MV_VOID); +MV_BOOL mvCtrlIsValidSatR(MV_VOID); + +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); + +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCtrlPexMaxIfGet(MV_VOID); +MV_U32 mvCtrlPexMaxUnitGet(MV_VOID); +#else +#define mvCtrlPexMaxIfGet() (0) +#endif + +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCtrlPciMaxIfGet(MV_VOID); +#else +#define mvCtrlPciIfMaxIfGet() (mvCtrlPexMaxIfGet()) +#endif + +MV_U32 mvCtrlEthMaxPortGet(MV_VOID); +MV_U8 mvCtrlEthMaxCPUsGet(MV_VOID); +#if defined(MV_INCLUDE_IDMA) +MV_U32 mvCtrlIdmaMaxUnitGet(MV_VOID); +MV_U32 mvCtrlIdmaMaxChanGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_XOR) +MV_U32 mvCtrlXorMaxChanGet(MV_VOID); +MV_U32 mvCtrlXorMaxUnitGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_USB) +MV_U32 mvCtrlUsbMaxGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_LEGACY_NAND) +MV_U32 mvCtrlNandSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_SDIO) +MV_U32 mvCtrlSdioSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_TDM) +MV_U32 mvCtrlTdmSupport(MV_VOID); +MV_U32 mvCtrlTdmMaxGet(MV_VOID); +MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID); +MV_U32 mvCtrlTdmUnitIrqGet(MV_VOID); +#endif +MV_U32 mvCtrlDevFamilyIdGet(MV_U16 ctrlModel); +MV_U16 mvCtrlModelGet(MV_VOID); +MV_U8 mvCtrlRevGet(MV_VOID); +MV_STATUS mvCtrlNameGet(char *pNameBuff); +MV_U32 mvCtrlModelRevGet(MV_VOID); +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); +MV_VOID mvCtrlAddrDecShow(MV_VOID); +const MV_8 *mvCtrlTargetNameGet(MV_TARGET target); +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); +MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlIsBootFromNOR(MV_VOID); +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); + +MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID); +MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID); +MV_U32 mvCtrlDDRBudWidth(MV_VOID); +MV_BOOL mvCtrlDDRThruXbar(MV_VOID); +MV_BOOL mvCtrlDDRECC(MV_VOID); + +#endif /* __INCmvCtrlEnvLibh */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h new file mode 100755 index 000000000..67dd2dea2 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvRegs.h @@ -0,0 +1,569 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvRegsh +#define __INCmvCtrlEnvRegsh + +#include "mvCtrlEnvSpec.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PEX0_MEM + +/* Controller revision info */ +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +/* Controler environment registers offsets */ +#define MV_TDM_IRQ_NUM 56 + + +/* Coherent Fabric Control and Status */ +#define MV_COHERENCY_FABRIC_CTRL_REG (MV_COHERENCY_FABRIC_OFFSET + 0x0) +#define MV_COHERENCY_FABRIC_CFG_REG (MV_COHERENCY_FABRIC_OFFSET + 0x4) + +/* CIB registers offsets */ +#define MV_CIB_CTRL_CFG_REG (MV_COHERENCY_FABRIC_OFFSET + 0x80) + +/* PMU_NFABRIC PMU_NFABRIC PMU_UNIT_SERVICE Units */ +#define MV_L2C_NFABRIC_PM_CTRL_CFG_REG (MV_PMU_NFABRIC_UNIT_SERV_OFFSET + 0x4) +#define MV_L2C_NFABRIC_PM_CTRL_CFG_PWR_DOWN (1 << 20) + +#define MV_L2C_NFABRIC_PWR_DOWN_FLOW_CTRL_REG (MV_PMU_NFABRIC_UNIT_SERV_OFFSET + 0x8) + +#define PM_CONTROL_AND_CONFIG_REG(cpu) (MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) + 0x4) +#define PM_CONTROL_AND_CONFIG_DFS_REQ (1 << 18) +#define PM_CONTROL_AND_CONFIG_PWDDN_REQ (1 << 16) +#define PM_CONTROL_AND_CONFIG_L2_PWDDN (1 << 20) + +#define PM_STATUS_AND_MASK_REG(cpu) (MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) + 0xc) +#define PM_STATUS_AND_MASK_CPU_IDLE_WAIT (1 << 16) +#define PM_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT (1 << 17) +#define PM_STATUS_AND_MASK_IRQ_WAKEUP (1 << 20) +#define PM_STATUS_AND_MASK_FIQ_WAKEUP (1 << 21) +#define PM_STATUS_AND_MASK_DBG_WAKEUP (1 << 22) +#define PM_STATUS_AND_MASK_IRQ_MASK (1 << 24) +#define PM_STATUS_AND_MASK_FIQ_MASK (1 << 25) + +#define PM_EVENT_STATUS_AND_MASK_REG(cpu) (MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) + 0x20) +#define PM_EVENT_STATUS_AND_MASK_DFS_DONE_OFFS 1 +#define PM_EVENT_STATUS_AND_MASK_DFS_DONE_MASK_OFFS 17 + +#define PM_CPU_BOOT_ADDR_REDIRECT(cpu) (MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) + 0x24) + +/* Power Management Memory Power Down Registers 1 - 6 */ +#define POWER_MNG_MEM_CTRL_REG(num) ((num) < 6 ? 0x1820C + (num) * 4 : 0x18228) +#define PMC_MCR_NUM_COMM 6 +#define PMC_MCR_NUM_PEX 2 +#define PMC_MCR_NUM_USB 4 +#define PMC_MCR_NUM_DUNIT 3 +#define PMC_MCR_NUM_DEVB 4 +#define PMC_MCR_NUM_NF 4 +#define PMC_MCR_NUM_XOR 4 +#define PMC_MCR_NUM_SATA 5 +#define PMC_MCR_NUM_CESA 4 +#define PMC_MCR_NUM_GE 5 +#define PMC_MCR_NUM_PNC 5 +#define PMC_MCR_NUM_BM 5 +#define PMC_MCR_NUM_PDMA 1 +#define PMC_MCR_NUM_NCS 3 +#define PMC_MCR_NUM_CFU 3 +#define PMC_MCR_NUM_L2 3 +#define PMC_MCR_NUM_CIB 3 +#define PMC_MCR_NUM_CPU 3 +#define PMC_MCR_NUM_IDMA 4 +#define PMC_MCR_NUM_LCD 4 +#define PMC_MCR_NUM_PMU 6 + +#define PMC_COMMSTOPMEM_OFFS 4 +#define PMC_COMMSTOPMEM_MASK (7 << PMC_COMMSTOPMEM_OFFS) +#define PMC_COMMSTOPMEM_EN (0 << PMC_COMMSTOPMEM_OFFS) +#define PMC_COMMSTOPMEM_STOP (1 << PMC_COMMSTOPMEM_OFFS) + +#define PMC_PEXSTOPMEM_OFFS(port) ((port) < 10 ? ((port) * 3) : 0) +#define PMC_PEXSTOPMEM_MASK(port) (7 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_EN(port) (0 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_STOP(port) (1 << PMC_PEXSTOPMEM_OFFS(port)) + +#define PMC_USBSTOPMEM_OFFS(port) ((port) < 3 ? (3 + (port) * 3) : 0) +#define PMC_USBSTOPMEM_MASK(port) (7 << PMC_USBSTOPMEM_OFFS(port)) +#define PMC_USBSTOPMEM_EN(port) (0 << PMC_USBSTOPMEM_OFFS(port)) +#define PMC_USBSTOPMEM_STOP(port) (1 << PMC_USBSTOPMEM_OFFS(port)) + +#define PMC_DUNITSTOPMEM_OFFS 12 +#define PMC_DUNITSTOPMEM_MASK (7 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) + +#define PMC_NFSTOPMEM_OFFS 27 +#define PMC_NFSTOPMEM_MASK (7 << PMC_NFSTOPMEM_OFFS) +#define PMC_NFSTOPMEM_EN (0 << PMC_NFSTOPMEM_OFFS) +#define PMC_NFSTOPMEM_STOP (1 << PMC_NFSTOPMEM_OFFS) + +#define PMC_DEVBSTOPMEM_OFFS 21 +#define PMC_DEVBSTOPMEM_MASK (7 << PMC_DEVBSTOPMEM_OFFS) +#define PMC_DEVBSTOPMEM_EN (0 << PMC_DEVBSTOPMEM_OFFS) +#define PMC_DEVBSTOPMEM_STOP (1 << PMC_DEVBSTOPMEM_OFFS) + +#define PMC_XORSTOPMEM_OFFS(port) ((port) == 0 ? 15 : 24) +#define PMC_XORSTOPMEM_MASK(port) (7 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) + +#define PMC_SATASTOPMEM_OFFS(port) ((port) == 0 ? 18 : 24) +#define PMC_SATASTOPMEM_MASK(port) (0x3F << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_STOP(port) (9 << PMC_SATASTOPMEM_OFFS(port)) + +#define PMC_CESASTOPMEM_OFFS 18 +#define PMC_CESASTOPMEM_MASK (7 << PMC_CESASTOPMEM_OFFS) +#define PMC_CESASTOPMEM_EN (0 << PMC_CESASTOPMEM_OFFS) +#define PMC_CESASTOPMEM_STOP (1 << PMC_CESASTOPMEM_OFFS) + +#define PMC_GESTOPMEM_OFFS(port) ((port) < 4 ? (9 - (port) * 3) : 0) +#define PMC_GESTOPMEM_MASK(port) (7 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) + +#define PMC_PNCSTOPMEM_OFFS 12 +#define PMC_PNCSTOPMEM_MASK (7 << PMC_PNCSTOPMEM_OFFS) +#define PMC_PNCSTOPMEM_EN (0 << PMC_PNCSTOPMEM_OFFS) +#define PMC_PNCSTOPMEM_STOP (1 << PMC_PNCSTOPMEM_OFFS) + +#define PMC_BMSTOPMEM_OFFS 15 +#define PMC_BMSTOPMEM_MASK (7 << PMC_BMSTOPMEM_OFFS) +#define PMC_BMSTOPMEM_EN (0 << PMC_BMSTOPMEM_OFFS) +#define PMC_BMSTOPMEM_STOP (1 << PMC_BMSTOPMEM_OFFS) + +#define PMC_PDMASTOPMEM_OFFS 0 +#define PMC_PDMATOPMEM_MASK (7 << PMC_PDMASTOPMEM_OFFS) +#define PMC_PDMASTOPMEM_EN (0 << PMC_PDMASTOPMEM_OFFS) +#define PMC_PDMASTOPMEM_STOP (1 << PMC_PDMASTOPMEM_OFFS) + +#define PMC_NCSSTOPMEM_OFFS 24 +#define PMC_NCSSTOPMEM_MASK (7 << PMC_NCSSTOPMEM_OFFS) +#define PMC_NCSSTOPMEM_EN (0 << PMC_NCSSTOPMEM_OFFS) +#define PMC_NCSSTOPMEM_STOP (1 << PMC_NCSSTOPMEM_OFFS) + +#define PMC_CFUSTOPMEM_OFFS 21 +#define PMC_CFUSTOPMEM_MASK (7 << PMC_CFUSTOPMEM_OFFS) +#define PMC_CFUSTOPMEM_EN (0 << PMC_CFUSTOPMEM_OFFS) +#define PMC_CFUSTOPMEM_STOP (1 << PMC_CFUSTOPMEM_OFFS) + +#define PMC_L2STOPMEM_OFFS 18 +#define PMC_L2STOPMEM_MASK (7 << PMC_L2STOPMEM_OFFS) +#define PMC_L2STOPMEM_EN (0 << PMC_L2STOPMEM_OFFS) +#define PMC_L2STOPMEM_STOP (1 << PMC_L2STOPMEM_OFFS) + +#define PMC_CIBSTOPMEM_OFFS 15 +#define PMC_CIBSTOPMEM_MASK (7 << PMC_CIBSTOPMEM_OFFS) +#define PMC_CIBSTOPMEM_EN (0 << PMC_CIBSTOPMEM_OFFS) +#define PMC_CIBSTOPMEM_STOP (1 << PMC_CIBSTOPMEM_OFFS) + +/* TODO - verify, the manual has no description */ +#define PMC_CPUSTOPMEM_OFFS(id) ((id) < 4 ? (id) * 3 : 0) +#define PMC_CPUSTOPMEM_MASK(id) (7 << PMC_CPUSTOPMEM_OFFS(id)) +#define PMC_CPUSTOPMEM_EN(id) (0 << PMC_CPUSTOPMEM_OFFS(id)) +#define PMC_CPUSTOPMEM_STOP(id) (1 << PMC_CPUSTOPMEM_OFFS(id)) + +#define PMC_IDMASTOPMEM_OFFS 12 +#define PMC_IDMASTOPMEM_MASK (7 << PMC_IDMASTOPMEM_OFFS) +#define PMC_IDMASTOPMEM_EN (0 << PMC_IDMASTOPMEM_OFFS) +#define PMC_IDMASTOPMEM_STOP (1 << PMC_IDMASTOPMEM_OFFS) + +#define PMC_LCDSTOPMEM_OFFS 0 +#define PMC_LCDSTOPMEM_MASK (7 << PMC_LCDSTOPMEM_OFFS) +#define PMC_LCDSTOPMEM_EN (0 << PMC_LCDSTOPMEM_OFFS) +#define PMC_LCDSTOPMEM_STOP (1 << PMC_LCDSTOPMEM_OFFS) + +#define PMC_PMUSTOPMEM_OFFS 0 +#define PMC_PMUSTOPMEM_MASK (7 << PMC_PMUSTOPMEM_OFFS) +#define PMC_PMUSTOPMEM_EN (0 << PMC_PMUSTOPMEM_OFFS) +#define PMC_PMUSTOPMEM_STOP (1 << PMC_PMUSTOPMEM_OFFS) + + +/* Power Management Clock Gating Control Register */ +#define POWER_MNG_CTRL_REG 0x18220 +#define L2C_MTCMOS_CONTROL_0_REG 0x22F00 +#define L2C_MTCMOS_CONTROL_1_REG 0x22F04 + +#define PMU_DFS_CTRL_REG(cpu) (MV_RUNIT_PMU_REGS_OFFSET + 0x54 + ((cpu) * 0x4)) +#define PMU_DFS_CTRL_INIT_RATIO_OFFS 24 +#define PMU_DFS_CTRL_INIT_RATIO_MASK 0x3F +#define PMU_DFS_CTRL_RATIO_OFFS 16 +#define PMU_DFS_CTRL_RATIO_MASK 0x3F + +#define PMC_TDMSTOPCLOCK_OFFS 25 +#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) + +#define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port))) +#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port)) + +#define PMC_USBSTOPCLOCK_OFFS(port) ((port) < 3 ? (18 + (port)) : 0) +#define PMC_USBSTOPCLOCK_MASK(port) (1 << PMC_USBSTOPCLOCK_OFFS(port)) +#define PMC_USBSTOPCLOCK_EN(port) (1 << PMC_USBSTOPCLOCK_OFFS(port)) +#define PMC_USBSTOPCLOCK_STOP(port) (0 << PMC_USBSTOPCLOCK_OFFS(port)) + +#define PMC_SDIOSTOPCLOCK_OFFS 17 +#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) + +#define PMC_RUNITSTOPCLOCK_OFFS 24 +#define PMC_RUNITSTOPCLOCK_MASK (1 << PMC_RUNITSTOPCLOCK_OFFS) +#define PMC_RUNITSTOPCLOCK_EN (1 << PMC_RUNITSTOPCLOCK_OFFS) +#define PMC_RUNITSTOPCLOCK_STOP (0 << PMC_RUNITSTOPCLOCK_OFFS) + +#define PMC_XORSTOPCLOCK_OFFS 22 +#define PMC_XORSTOPCLOCK_MASK (1 << PMC_XORSTOPCLOCK_OFFS) +#define PMC_XORSTOPCLOCK_EN (1 << PMC_XORSTOPCLOCK_OFFS) +#define PMC_XORSTOPCLOCK_STOP (0 << PMC_XORSTOPCLOCK_OFFS) + +#define PMC_SATASTOPCLOCK_OFFS(ch) (ch == 0 ? 14 : 29) +#define PMC_SATASTOPCLOCK_MASK(ch) (3 << PMC_SATASTOPCLOCK_OFFS(ch)) +#define PMC_SATASTOPCLOCK_EN(ch) (3 << PMC_SATASTOPCLOCK_OFFS(ch)) +#define PMC_SATASTOPCLOCK_STOP(ch) (0 << PMC_SATASTOPCLOCK_OFFS(ch)) + +#define PMC_CESASTOPCLOCK_OFFS 23 +#define PMC_CESASTOPCLOCK_MASK (1 << PMC_CESASTOPCLOCK_OFFS) +#define PMC_CESASTOPCLOCK_EN (1 << PMC_CESASTOPCLOCK_OFFS) +#define PMC_CESASTOPCLOCK_STOP (0 << PMC_CESASTOPCLOCK_OFFS) + +#define PMC_GESTOPCLOCK_OFFS(port) ((port) < 4 ? (4 - (port)) : 0) +#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) + +#define PMC_NETASTOPCLOCK_OFFS 13 +#define PMC_NETASTOPCLOCK_MASK (1 << PMC_NETASTOPCLOCK_OFFS) +#define PMC_NETASTOPCLOCK_EN (1 << PMC_NETASTOPCLOCK_OFFS) +#define PMC_NETASTOPCLOCK_STOP (0 << PMC_NETASTOPCLOCK_OFFS) + +#define PMC_LCDSTOPCLOCK_OFFS 16 +#define PMC_LCDSTOPCLOCK_MASK (1 << PMC_LCDSTOPCLOCK_OFFS) +#define PMC_LCDSTOPCLOCK_EN (1 << PMC_LCDSTOPCLOCK_OFFS) +#define PMC_LCDSTOPCLOCK_STOP (0 << PMC_LCDSTOPCLOCK_OFFS) + +#define PMC_IDMASTOPCLOCK_OFFS 21 +#define PMC_IDMASTOPCLOCK_MASK (1 << PMC_IDMASTOPCLOCK_OFFS) +#define PMC_IDMASTOPCLOCK_EN (1 << PMC_IDMASTOPCLOCK_OFFS) +#define PMC_IDMASTOPCLOCK_STOP (0 << PMC_IDMASTOPCLOCK_OFFS) + +#define PMC_DDRSTOPCLOCK_OFFS 28 +#define PMC_DDRSTOPCLOCK_MASK (1 << PMC_DDRSTOPCLOCK_OFFS) +#define PMC_DDRSTOPCLOCK_EN (1 << PMC_DDRSTOPCLOCK_OFFS) +#define PMC_DDRSTOPCLOCK_STOP (0 << PMC_DDRSTOPCLOCK_OFFS) + +#define SATA_IMP_TX_SSC_CTRL_REG(port) (0xA2810 + (port)*0x2000) +#define SATA_GEN_1_SET_0_REG(port) (0xA2834 + (port)*0x2000) +#define SATA_GEN_1_SET_1_REG(port) (0xA2838 + (port)*0x2000) +#define SATA_GEN_2_SET_0_REG(port) (0xA283C + (port)*0x2000) +#define SATA_GEN_2_SET_1_REG(port) (0xA2840 + (port)*0x2000) + +#define SATA_PWR_PLL_CTRL_REG(port) (0xA2804 + (port)*0x2000) +#define SATA_DIG_LP_ENA_REG(port) (0xA288C + (port)*0x2000) +#define SATA_REF_CLK_SEL_REG(port) (0xA2918 + (port)*0x2000) +#define SATA_COMPHY_CTRL_REG(port) (0xA2920 + (port)*0x2000) +#define SATA_LP_PHY_EXT_CTRL_REG(port) (0xA2058 + (port)*0x2000) +#define SATA_LP_PHY_EXT_STAT_REG(port) (0xA205C + (port)*0x2000) + +#define SGMII_PWR_PLL_CTRL_REG(port) (0x72E04 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_DIG_LP_ENA_REG(port) (0x72E8C + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_REF_CLK_SEL_REG(port) (0x72F18 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_SERDES_CFG_REG(port) (0x724A0 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_SERDES_STAT_REG(port) (0x724A4 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define SGMII_COMPHY_CTRL_REG(port) (0x72F20 + ((port)%2)*0x4000 - ((port)/2)*0x40000) +#define QSGMII_GEN_1_SETTING_REG(port) (0x72E38 + ((port)%2)*0x4000 - ((port)/2)*0x40000) + +#define SERDES_LINE_MUX_REG_0_7 0x18270 +#define SERDES_LINE_MUX_REG_8_15 0x18274 +#define QSGMII_CONTROL_1_REG 0x18404 +/* Controler environment registers offsets */ +#define GEN_PURP_RES_1_REG 0x182F4 +#define GEN_PURP_RES_2_REG 0x182F8 + +#define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) + +/* Sample at Reset */ +#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4)) + +/* SYSRSTn Length Counter */ +#define SYSRST_LENGTH_COUNTER_REG 0x18250 +#define SLCR_COUNT_OFFS 0 +#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) +#define SLCR_CLR_OFFS 31 +#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) + +/* Device ID */ +#define CHIP_BOND_REG 0x18238 +#define PCKG_OPT_MASK 0x3 + +#define MPP_OUTPUT_DRIVE_REG 0x184E4 +#define MPP_GE_A_OUTPUT_DRIVE_OFFS 6 +#define MPP_GE_A_1_8_OUTPUT_DRIVE (0x1 << MPP_GE_A_OUTPUT_DRIVE_OFFS) +#define MPP_GE_A_2_5_OUTPUT_DRIVE (0x2 << MPP_GE_A_OUTPUT_DRIVE_OFFS) +#define MPP_GE_B_OUTPUT_DRIVE_OFFS 14 +#define MPP_GE_B_1_8_OUTPUT_DRIVE (0x1 << MPP_GE_B_OUTPUT_DRIVE_OFFS) +#define MPP_GE_B_2_5_OUTPUT_DRIVE (0x2 << MPP_GE_B_OUTPUT_DRIVE_OFFS) + +#define MSAR_BOOT_MODE_OFFS 5 +#define MSAR_BOOT_MODE_MASK (0xF << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_NOR (0x0 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_SPI (0x3 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_DOVE_NAND (0x1 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_LEGACY_NAND (0x6 << MSAR_BOOT_MODE_OFFS) + +#define MSAR_TCLK_OFFS 28 +#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS) + +/*****************/ +/* PUP registers */ +/*****************/ +#define PUP_EN_REG 0x1864C + +/* Extract CPU, L2, DDR clocks SAR value from +** SAR bits 24-27 +*/ +#define MSAR_CPU_CLK_IDX(sar0, sar1) ((((sar0) >> 21) & 0x7) + ((((sar1) >> 20) & 1) << 3)) +#define MSAR_CPU_CLK_TWSI(sar0, sar1) ((((sar0) >> 2) & 0x7) + (((sar1) & 1) << 3)) +#define MSAR_DDR_L2_CLK_RATIO_IDX(sar0, sar1) ((((sar0) >> 24) & 0xF) + ((((sar1) >> 19) & 1) << 4)) +#define MSAR_DDR_L2_CLK_RATIO_TWSI(sar0) (((sar0) >> 1) & 0xF) + +#ifndef MV_ASMLANGUAGE + +#define MV_CPU_CLK_TBL { 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000,\ + 600, 667, 800, 1600, 2133, 2200, 2400, 0 } + +/* cpu l2c hclk ddr */ +#define MV_DDR_L2_CLK_RATIO_TBL { \ +/*00*/ { 1, 1, 4, 2 },\ +/*01*/ { 1, 2, 2, 2 },\ +/*02*/ { 2, 2, 6, 3 },\ +/*03*/ { 2, 2, 3, 3 },\ +/*04*/ { 1, 2, 3, 3 },\ +/*05*/ { 1, 2, 4, 2 },\ +/*06*/ { 1, 1, 2, 2 },\ +/*07*/ { 2, 3, 6, 6 },\ +/*08*/ { 2, 3, 5, 5 },\ +/*09*/ { 1, 2, 6, 3 },\ +/*10*/ { 2, 4, 10, 5 },\ +/*11*/ { 1, 3, 6, 6 },\ +/*12*/ { 1, 2, 4, 4 },\ +/*13*/ { 1, 3, 6, 3 },\ +/*14*/ { 1, 2, 5, 5 },\ +/*15*/ { 2, 2, 5, 5 },\ +/*16*/ { 1, 1, 3, 3 },\ +/*17*/ { 2, 5, 10, 10 },\ +/*18*/ { 1, 3, 8, 4 },\ +/*19*/ { 1, 1, 2, 1 },\ +/*20*/ { 2, 3, 6, 3 },\ +/*21*/ { 1, 2, 8, 4 },\ +/*22*/ { 2, 5, 10, 5 } \ +} + +/* These macros help units to identify a target Mport Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) +#define MV_TARGET_IS_PEX1(target) \ + ((target >= PEX1_MEM) && (target <= PEX1_IO)) +#define MV_TARGET_IS_PEX2(target) \ + ((target >= PEX2_MEM) && (target <= PEX2_IO)) +#define MV_TARGET_IS_PEX3(target) \ + ((target >= PEX3_MEM) && (target <= PEX3_IO)) +#define MV_TARGET_IS_PEX4(target) \ + ((target >= PEX4_MEM) && (target <= PEX4_IO)) +#define MV_TARGET_IS_PEX5(target) \ + ((target >= PEX5_MEM) && (target <= PEX5_IO)) +#define MV_TARGET_IS_PEX6(target) \ + ((target >= PEX6_MEM) && (target <= PEX6_IO)) +#define MV_TARGET_IS_PEX7(target) \ + ((target >= PEX7_MEM) && (target <= PEX7_IO)) +#define MV_TARGET_IS_PEX8(target) \ + ((target >= PEX8_MEM) && (target <= PEX8_IO)) +#define MV_TARGET_IS_PEX9(target) \ + ((target >= PEX9_MEM) && (target <= PEX9_IO)) + +#define MV_TARGET_IS_PEX(target) ((target >= PEX0_MEM) && (target <= PEX9_IO)) + +#define MV_TARGET_IS_DEVICE(target) ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_CHANGE_BOOT_CS(target) target + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ + + +#define BOOT_TARGETS_NAME_ARRAY { \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + BOOT_ROM_CS \ +} + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + START_DEV_CS) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +/* This enumerator defines the Marvell controller target ID (see Address map) */ +typedef enum _mvTargetId { + DRAM_TARGET_ID = 0, /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> Device port, BootROM, SPI */ + PEX0_2_TARGET_ID = 4, /* Port 4 -> PCI Express 0 and 2 */ + PEX1_3_TARGET_ID = 8, /* Port 4 -> PCI Express 1 and 3 */ + CRYPT_TARGET_ID = 9, /* Port 9 --> Crypto Engine SRAM */ + PNC_BM_TARGET_ID = 12, /* Port 12 -> PNC + BM Unit */ + MAX_TARGETS_ID +} MV_TARGET_ID; + +/* +typedef enum { + SERDES_UNIT_UNCONNECTED = 0x0, + SERDES_UNIT_PEX = 0x1, + SERDES_UNIT_SATA = 0x2, + SERDES_UNIT_SGMII0 = 0x3, + SERDES_UNIT_SGMII1 = 0x4, + SERDES_UNIT_SGMII2 = 0x5, + SERDES_UNIT_SGMII3 = 0x6, + SERDES_UNIT_QSGMII = 0x7 +} MV_SERDES_UNIT_INDX; +*/ + +/* + This structure refrect registers: + Serdes 0-7 selectors 0x18270 + and Serdes 8-15 selectors 0x18274 +*/ + +#define SERDES_CFG { \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 0 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 1 */ \ + {0, 1, -1 , 2, -1, -1, -1, -1}, /* Lane 2 */ \ + {0, 1, -1 , -1, 2, -1, -1, 3}, /* Lane 3 */ \ + {0, 1, 2 , -1, -1, 3, -1, -1}, /* Lane 4 */ \ + {0, 1, 2 , -1, 3, -1, -1, 4}, /* Lane 5 */ \ + {0, 1, 2 , 4, -1, 3, -1, -1}, /* Lane 6 */ \ + {0, 1, -1 , 2, -1, -1, 3, -1}, /* Lane 7*/ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 8 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 9 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 10 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 11 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 12 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 13 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1}, /* Lane 14 */ \ + {0, 1, -1 , -1, -1, -1, -1, -1} /* Lane 15 */ \ +} + + +/* + This enum should reflect the units numbers in register + space which we will need when accessing the HW +*/ + +typedef enum { + PEX0_0x4 = 0, + PEX0_1x4 = 1, + PEX0_2x4 = 2, + PEX0_3x4 = 3, + PEX1_0x4 = 4, + PEX1_1x4 = 5, + PEX1_2x4 = 6, + PEX1_3x4 = 7, + PEX2_0x4 = 8, + PEX3_0x4 = 9, + PEXIF_MAX = 10 +} MV_PEXIF_INDX; + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h new file mode 100755 index 000000000..36b87bbb4 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvCtrlEnvSpec.h @@ -0,0 +1,497 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvSpech +#define __INCmvCtrlEnvSpech + +#include "mvDeviceId.h" +#include "mvSysHwConfig.h" + +#include "ctrlEnv/sys/mvCpuIfRegs.h" + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +/* + * Armada-XP Units Address decoding + */ +#define MV_DRAM_REGS_OFFSET (0x0) +#define MV_AURORA_L2_REGS_OFFSET (0x8000) +#define MV_RTC_REGS_OFFSET (0x10300) +#ifdef CONFIG_SYNO_ARMADA +#define MV_RTC_EXTERNAL_ALARM_OFFSET (0x10320) +#endif +#define MV_DEV_BUS_REGS_OFFSET (0x10400) +#define MV_SPI_REGS_OFFSET(unit) (0x10600 + (unit * 0x80)) +#define MV_TWSI_SLAVE_REGS_OFFSET(chanNum) (0x11000 + (chanNum * 0x100)) +#define MV_UART_REGS_OFFSET(chanNum) (0x12000 + (chanNum * 0x100)) +#define MV_RUNIT_PMU_REGS_OFFSET (0x1C000) +#define MV_MPP_REGS_OFFSET (0x18000) +#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40)) +#define MV_MISC_REGS_OFFSET (0x18200) +#define MV_CLK_CMPLX_REGS_OFFSET (0x18700) +#define MV_MBUS_REGS_OFFSET (0x20000) +#define MV_COHERENCY_FABRIC_OFFSET (0x20200) +#define MV_CIB_CTRL_STATUS_OFFSET (0x20280) +#define MV_CNTMR_REGS_OFFSET (0x20300) +#define MV_CPUIF_LOCAL_REGS_OFFSET (0x21000) +#define MV_CPUIF_REGS_OFFSET(cpu) (0x21800 + (cpu) * 0x100) +#define MV_PMU_NFABRIC_UNIT_SERV_OFFSET (0x22000) +#define MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) (0x22100 + (cpu) * 0x100) +#define MV_CPU_HW_SEM_OFFSET (0x20500) + +#if defined(MV_ETH_LEGACY) + #define MV_ETH_BASE_ADDR (0x72000) +#else + #define MV_ETH_BASE_ADDR (0x70000) +#endif +#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * 0x40000 + ((port) % 2) * 0x4000) +#define MV_PEX_IF_REGS_OFFSET(pexIf) (pexIf < 8 ? (0x40000 + ((pexIf) / 4) * 0x40000 + ((pexIf) % 4) * 0x4000) \ + : (0x42000 + ((pexIf) % 8) * 0x40000)) +#define MV_USB_REGS_OFFSET(dev) (0x50000 + (dev * 0x1000)) +#define MV_XOR_REGS_OFFSET(unit) (unit ? 0xF0900 : 0x60900) +#if defined(MV_INCLUDE_IDMA) +#define MV_IDMA_REGS_OFFSET (0x60800) +#endif +#define MV_CESA_TDMA_REGS_OFFSET(chanNum) (0x90000 + (chanNum * 0x2000)) +#define MV_CESA_REGS_OFFSET(chanNum) (0x9D000 + (chanNum * 0x2000)) +#define MV_SATA_REGS_OFFSET (0xA0000) +#define MV_COMM_UNIT_REGS_OFFSET (0xB0000) +#define MV_NFC_REGS_OFFSET (0xD0000) +#define MV_BM_REGS_OFFSET (0xC0000) +#define MV_PNC_REGS_OFFSET (0xC8000) +#define MV_SDMMC_REGS_OFFSET (0xD4000) + + +#ifdef CONFIG_ARMADA_XP_ERRATA_SMI_1 + #define MV_ETH_SMI_PORT 1 +#else + #define MV_ETH_SMI_PORT 0 +#endif + +#define MV_SERDES_NUM_TO_PEX_NUM(sernum) ((sernum < 8) ? (sernum) : (8 + (sernum/12))) +/* + * Miscellanuous Controller Configurations + */ + +#define AVS_CONTROL2_REG 0x20868 +#define AVS_LOW_VDD_LIMIT 0x20860 + +#define INTER_REGS_SIZE _1M + +/* This define describes the TWSI interrupt bit and location */ +#define TWSI_CPU_MAIN_INT_CAUSE_REG(cpu) CPU_MAIN_INT_CAUSE_REG(1, (cpu)) +#define TWSI0_CPU_MAIN_INT_BIT(ch) ((ch) + 3) +#define TWSI_SPEED 100000 + +#define MV_GPP_MAX_PINS 68 +#define MV_GPP_MAX_GROUP 3 /* group == configuration register? */ +#define MV_CNTMR_MAX_COUNTER 8 /* 4 global + 1 global WD + 2 current private CPU + 1 private CPU WD*/ + +/* + MV88F78X60_Z1 MV88F78X60_A0 + ------------------------------- ------------------------------- + Global Counters 0-3 : 0-3 Global Counters 0-3 : 0-3 + Global WD : 4 Global WD : 4 + + CPU 0 Counter 0-1 : 5-6 Private CPU Counter 0-1 : 5-6 + CPU 0 WD : 7 Private CPU WD : 7 + CPU 1 Counter 0-1 : 8-9 + CPU 1 WD : 10 + CPU 2 Counter 0-1 : 11-12 + CPU 2 WD : 13 + CPU 3 Counter 0-1 : 14-15 + CPU 3 WD : 16 +*/ + +#define MV_UART_MAX_CHAN 4 + +#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ +#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ +#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ + +#if defined(MV_INCLUDE_IDMA) +#define MV_IDMA_MAX_UNIT 1 /* IDMA unit == IDMA engine */ +#define MV_IDMA_MAX_CHAN 4 /* total channels for all units together */ +#endif + +#define MV_SATA_MAX_CHAN 2 + +#define MV_MPP_MAX_GROUP 9 + +#define MV_DRAM_MAX_CS 4 +#define MV_SPI_MAX_CS 8 +/* This define describes the maximum number of supported PCI\PCIX Interfaces */ +#ifdef MV_INCLUDE_PCI + #define MV_PCI_MAX_IF 1 + #define MV_PCI_START_IF 0 + #define PCI_HOST_BUS_NUM(pciIf) (pciIf) + #define PCI_HOST_DEV_NUM(pciIf) 0 +#else + #define MV_PCI_MAX_IF 0 + #define MV_PCI_START_IF 0 +#endif + +/* This define describes the maximum number of supported PEX Interfaces */ +#define MV_PEX_MAX_IF 10 +#define MV_PEX_MAX_UNIT 4 +#ifdef MV_INCLUDE_PEX +#define MV_INCLUDE_PEX0 +#define MV_DISABLE_PEX_DEVICE_BAR + +#define MV_PEX_START_IF MV_PCI_MAX_IF + #define PEX_HOST_BUS_NUM(pciIf) (pciIf) + #define PEX_HOST_DEV_NUM(pciIf) 0 +#else + #undef MV_INCLUDE_PEX0 +#endif + +#define PCI_IO(pciIf) (PEX0_IO + 2 * (pciIf)) +#define PCI_MEM(pciIf, memNum) (PEX0_MEM0 + 2 * (pciIf)) +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_IDMA_MAX_CHAN 4 +#define ARMADA_XP_MAX_USB_PORTS 3 +#define ARMADA_XP_NAND 1 +#define ARMADA_XP_SDIO 1 +#define ARMADA_XP_MAX_TDM_PORTS 32 +#define ARMADA_XP_TDM 1 +#define MV_DEVICE_MAX_CS 4 + +#ifndef MV_USB_MAX_PORTS +#define MV_USB_MAX_PORTS (ARMADA_XP_MAX_USB_PORTS) +#endif + + +/* CESA version #3: One channel, 2KB SRAM, TDMA, CHAIN Mode support */ +#define MV_CESA_VERSION 3 /*TODO verify */ +#define MV_CESA_SRAM_SIZE (2 * 1024) + + +/* This define describes the maximum number of supported Ethernet ports */ +/* TODO - verify all these numbers */ +#define MV_ETH_VERSION 4 /* for Legacy mode */ +#define MV_NETA_VERSION 1 /* for NETA mode */ +#define MV_ETH_MAX_PORTS 4 +#define MV_ETH_MAX_RXQ 8 +#define MV_ETH_MAX_TXQ 8 +#define MV_ETH_TX_CSUM_MAX_SIZE 9800 +#define MV_PNC_TCAM_LINES 1024 /* TCAM num of entries */ + +/* New GMAC module is used */ +#define MV_ETH_GMAC_NEW +/* New WRR/EJP module is used */ +#define MV_ETH_WRR_NEW +/* IPv6 parsing support for Legacy parser */ +#define MV_ETH_LEGACY_PARSER_IPV6 +/* New PNC module - extra fields */ +#define MV_ETH_PNC_NEW +/* PNC Load Balancing support */ +#define MV_ETH_PNC_LB + +#define MV_78130_ETH_MAX_PORT 3 +#define MV_78460_ETH_MAX_PORT 4 + +/* This define describes the the support of USB */ +#define MV_USB_VERSION 1 + +#define MV_SPI_VERSION 2 + +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 + +#ifndef MV_ASMLANGUAGE + +#define TBL_UNUSED 0 /* Used to mark unused entry */ + +typedef enum { + TDM_UNIT_32CH +} MV_TDM_UNIT_TYPE; + +/* This enumerator defines the Marvell Units ID */ +typedef enum _mvUnitId { + DRAM_UNIT_ID, + PEX_UNIT_ID, + ETH_GIG_UNIT_ID, + USB_UNIT_ID, + IDMA_UNIT_ID, + XOR_UNIT_ID, + SATA_UNIT_ID, + TDM_32CH_UNIT_ID, + UART_UNIT_ID, + CESA_UNIT_ID, + SPI_UNIT_ID, + SDIO_UNIT_ID, + BM_UNIT_ID, + PNC_UNIT_ID, + MAX_UNITS_ID +} MV_UNIT_ID; + +/* This enumerator describes the Marvell controller possible devices that */ +/* can be connected to its device interface. */ +typedef enum _mvDevice { +#if defined(MV_INCLUDE_DEVICE_CS0) + DEV_CS0 = 0, /* Device connected to dev CS[0] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEV_CS1 = 1, /* Device connected to dev CS[1] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEV_CS2 = 2, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEV_CS3 = 3, /* Device connected to dev CS[2] */ +#endif + BOOT_CS, /* Device connected to BOOT dev */ + MV_DEV_MAX_CS = MV_DEVICE_MAX_CS +} MV_DEVICE; + +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget { + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /*0 SDRAM chip select 0 */ + SDRAM_CS1, /*1 SDRAM chip select 1 */ + SDRAM_CS2, /*2 SDRAM chip select 2 */ + SDRAM_CS3, /*3 SDRAM chip select 3 */ + DEVICE_CS0, /*4 Device chip select 0 */ + DEVICE_CS1, /*5 Device chip select 1 */ + DEVICE_CS2, /*6 Device chip select 2 */ + DEVICE_CS3, /*7 Device chip select 3 */ + PEX0_MEM, /*8 PCI Express 0 Memory */ + PEX0_IO, /*9 PCI Express 0 IO */ + PEX1_MEM, /*10 PCI Express 1 Memory */ + PEX1_IO, /*11 PCI Express 1 IO */ + PEX2_MEM, /*12 PCI Express 2 Memory */ + PEX2_IO, /*13 PCI Express 2 IO */ + PEX3_MEM, /*14 PCI Express 3 Memory */ + PEX3_IO, /*15 PCI Express 3 IO */ + PEX4_MEM, /*16 PCI Express 4 Memory */ + PEX4_IO, /*17 PCI Express 4 IO */ + PEX5_MEM, /*18 PCI Express 5 Memory */ + PEX5_IO, /*19 PCI Express 5 IO */ + PEX6_MEM, /*20 PCI Express 6 Memory */ + PEX6_IO, /*21 PCI Express 6 IO */ + PEX7_MEM, /*22 PCI Express 7 Memory */ + PEX7_IO, /*23 PCI Express 7 IO */ + PEX8_MEM, /*24 PCI Express 8 Memory */ + PEX8_IO, /*25 PCI Express 8 IO */ + PEX9_MEM, /*26 PCI Express 9 Memory */ + PEX9_IO, /*27 PCI Express 9 IO */ + INTER_REGS, /*28 Internal registers */ + DMA_UART, /*29 DMA based UART request */ + SPI_CS0, /*30 SPI_CS0 */ + SPI_CS1, /*31 SPI_CS1 */ + SPI_CS2, /*32 SPI_CS2 */ + SPI_CS3, /*33 SPI_CS3 */ + SPI_CS4, /*34 SPI_CS4 */ + SPI_CS5, /*35 SPI_CS5 */ + SPI_CS6, /*36 SPI_CS6 */ + SPI_CS7, /*37 SPI_CS7 */ + BOOT_ROM_CS, /*38 BOOT_ROM_CS */ + DEV_BOOCS, /*39 DEV_BOOCS */ + PMU_SCRATCHPAD, /*40 PMU Scratchpad */ + CRYPT0_ENG, /* 41 Crypto0 Engine */ + CRYPT1_ENG, /* 42 Crypto1 Engine */ + PNC_BM, /* 43 PNC + BM */ + MAX_TARGETS +} MV_TARGET; + +#ifdef AURORA_IO_CACHE_COHERENCY +#define DRAM_CS0_ATTR 0x1E +#define DRAM_CS1_ATTR 0x1D +#define DRAM_CS2_ATTR 0x1B +#define DRAM_CS3_ATTR 0x17 +#else +#define DRAM_CS0_ATTR 0x0E +#define DRAM_CS1_ATTR 0x0D +#define DRAM_CS2_ATTR 0x0B +#define DRAM_CS3_ATTR 0x07 +#endif + +#ifdef CONFIG_MACH_ARMADA_XP_FPGA + #define MAIN_BOOT_ATTR 0x2F /* Boot Device CS - NOR */ + #define SEC_BOOT_ATTR 0x1D /* BootROM - Dummy */ +#else + #define MAIN_BOOT_ATTR 0x1D /* BootROM */ + #define SEC_BOOT_ATTR 0x2F /* Boot Device CS */ +#endif + +#define TARGETS_DEF_ARRAY { \ + {DRAM_CS0_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {DRAM_CS1_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {DRAM_CS2_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {DRAM_CS3_ATTR, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {0x3E, DEV_TARGET_ID }, /* DEVICE_CS0 */ \ + {0x3D, DEV_TARGET_ID }, /* DEVICE_CS1 */ \ + {0x3B, DEV_TARGET_ID }, /* DEVICE_CS2 */ \ + {0x37, DEV_TARGET_ID }, /* DEVICE_CS3 */ \ + {0xE8, PEX0_2_TARGET_ID }, /* PEX0_LANE0_MEM */ \ + {0xE0, PEX0_2_TARGET_ID }, /* PEX0_LANE0_IO */ \ + {0xD8, PEX0_2_TARGET_ID }, /* PEX0_LANE1_MEM */ \ + {0xD0, PEX0_2_TARGET_ID }, /* PEX0_LANE1_IO */ \ + {0xB8, PEX0_2_TARGET_ID }, /* PEX0_LANE2_MEM */ \ + {0xB0, PEX0_2_TARGET_ID }, /* PEX0_LANE2_IO */ \ + {0x78, PEX0_2_TARGET_ID }, /* PEX0_LANE3_MEM */ \ + {0x70, PEX0_2_TARGET_ID }, /* PEX0_LANE3_IO */ \ + {0xE8, PEX1_3_TARGET_ID }, /* PEX1_LANE0_MEM */ \ + {0xE0, PEX1_3_TARGET_ID }, /* PEX1_LANE0_IO */ \ + {0xD8, PEX1_3_TARGET_ID }, /* PEX1_LANE1_MEM */ \ + {0xD0, PEX1_3_TARGET_ID }, /* PEX1_LANE1_IO */ \ + {0xB8, PEX1_3_TARGET_ID }, /* PEX1_LANE2_MEM */ \ + {0xB0, PEX1_3_TARGET_ID }, /* PEX1_LANE2_IO */ \ + {0x78, PEX1_3_TARGET_ID }, /* PEX1_LANE3_MEM */ \ + {0x70, PEX1_3_TARGET_ID }, /* PEX1_LANE3_IO */ \ + {0xF8, PEX0_2_TARGET_ID }, /* PEX2_LANE0_MEM */ \ + {0xF0, PEX0_2_TARGET_ID }, /* PEX2_LANE0_IO */ \ + {0xF8, PEX1_3_TARGET_ID }, /* PEX3_LANE0_MEM */ \ + {0xF0, PEX1_3_TARGET_ID }, /* PEX3_LANE0_IO */ \ + {0xFF, 0xFF }, /* INTER_REGS */ \ + {0x01, DEV_TARGET_ID }, /* DMA_UART */ \ + {0x1E, DEV_TARGET_ID }, /* SPI_CS0 */ \ + {0x5E, DEV_TARGET_ID }, /* SPI_CS1 */ \ + {0x9E, DEV_TARGET_ID }, /* SPI_CS2 */ \ + {0xDE, DEV_TARGET_ID }, /* SPI_CS3 */ \ + {0x1F, DEV_TARGET_ID }, /* SPI_CS4 */ \ + {0x5F, DEV_TARGET_ID }, /* SPI_CS5 */ \ + {0x9F, DEV_TARGET_ID }, /* SPI_CS6 */ \ + {0xDF, DEV_TARGET_ID }, /* SPI_CS7 */ \ + {MAIN_BOOT_ATTR, DEV_TARGET_ID }, /* Main Boot device */ \ + {SEC_BOOT_ATTR, DEV_TARGET_ID }, /* Secondary Boot device, */ \ + {0x2D, DEV_TARGET_ID }, /* PMU_SCRATCHPAD */ \ + {0x01, CRYPT_TARGET_ID }, /* CRYPT_ENG0 */ \ + {0x05, CRYPT_TARGET_ID }, /* CRYPT_ENG1 */ \ + {0x00, PNC_BM_TARGET_ID }, /* PNC_BM */ \ +} + +#define CESA_TARGET_NAME_DEF ("CRYPT_ENG0", "CRYPT_ENG1") +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS1 */ \ + "SDRAM_CS3", /* SDRAM_CS1 */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEVICE_CS3", /* DEVICE_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PEX1_MEM", /* PEX1_MEM */ \ + "PEX1_IO", /* PEX1_IO */ \ + "PEX2_MEM", /* PEX2_MEM */ \ + "PEX2_IO", /* PEX2_IO */ \ + "PEX3_MEM", /* PEX3_MEM */ \ + "PEX3_IO", /* PEX3_IO */ \ + "PEX4_MEM", /* PEX4_MEM */ \ + "PEX4_IO", /* PEX4_IO */ \ + "PEX5_MEM", /* PEX5_MEM */ \ + "PEX5_IO", /* PEX5_IO */ \ + "PEX6_MEM", /* PEX6_MEM */ \ + "PEX6_IO", /* PEX6_IO */ \ + "PEX7_MEM", /* PEX7_MEM */ \ + "PEX7_IO", /* PEX7_IO */ \ + "PEX8_MEM", /* PEX8_MEM */ \ + "PEX8_IO", /* PEX8_IO */ \ + "PEX9_MEM", /* PEX9_MEM */ \ + "PEX9_IO", /* PEX9_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DMA_UART", /* DMA_UART */ \ + "SPI_CS0", /* SPI_CS0 */ \ + "SPI_CS1", /* SPI_CS1 */ \ + "SPI_CS2", /* SPI_CS2 */ \ + "SPI_CS3", /* SPI_CS3 */ \ + "SPI_CS4", /* SPI_CS4 */ \ + "SPI_CS5", /* SPI_CS5 */ \ + "SPI_CS6", /* SPI_CS6 */ \ + "SPI_CS7", /* SPI_CS7 */ \ + "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "PMU_SCRATCHPAD",/* PMU_SCRATCHPAD */ \ + "CRYPT1_ENG", /* CRYPT1_ENG */ \ + "CRYPT2_ENG", /* CRYPT2_ENG */ \ + "PNC_BM" /* PNC_BM */ \ +} + + + + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCtrlEnvSpech */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvSemaphore.c b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvSemaphore.c new file mode 100755 index 000000000..d71df4e0c --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvSemaphore.c @@ -0,0 +1,124 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvSemaphore.h" + + +MV_BOOL mvSemaLock(MV_32 num) +{ + MV_U32 tmp; + MV_U32 cpuId; + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + cpuId = whoAmI(); + do + { + tmp = MV_REG_BYTE_READ(MV_SEMA_REG_BASE+num); + } while ((tmp & 0xFF) != cpuId); + return MV_TRUE; +} + +MV_BOOL mvSemaTryLock(MV_32 num) +{ + MV_U32 tmp; + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + tmp = MV_REG_BYTE_READ(MV_SEMA_REG_BASE+num); + if ((tmp & 0xFF) != whoAmI()) + { + return MV_FALSE; + } + else + return MV_TRUE; +} + +MV_BOOL mvSemaUnlock(MV_32 num) +{ + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + MV_REG_BYTE_WRITE(MV_SEMA_REG_BASE+(num), 0xFF); + return MV_TRUE; +} + +MV_32 mvReadAmpReg(int regId) +{ + return MV_REG_READ(MV_AMP_GLOBAL_REG(regId)); +} + +MV_32 mvWriteAmpReg(int regId, MV_32 value) +{ + return MV_REG_WRITE(MV_AMP_GLOBAL_REG(regId), value); +} diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvSemaphore.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvSemaphore.h new file mode 100755 index 000000000..a5a94d368 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvSemaphore.h @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef mvsemaphore_h +#define mvsemaphore_h + +#ifdef MV_VXWORKS +#include "common/mvTypes.h" +#include "config.h" +#endif + +#define MV_AMP_GLOBAL_REG(x) (0x20980 + (4*x)) +#define ADR_WIN_EN_REG 0 + +#define MV_SEMA_REG_BASE (0x20500) +#define MV_MAX_SEMA 128 +#define MV_SEMA_SMI 50 +#define MV_SEMA_RTC 51 +#define MV_SEMA_NOR_FLASH 0 +#define MV_SEMA_BOOT 1 +#define MV_SEMA_PEX0 2 +#define MV_SEMA_BRIDGE 3 +#define MV_SEMA_IRQ 4 +#define MV_SEMA_CLOCK 5 +#define MV_SEMA_L2 6 +#define MV_SEMA_TWSI 7 +#define MV_SEMA_ADR_WIN 8 + +#define MV_SEMA_BARRIER(cpu) (50 + cpu) + + +MV_BOOL mvSemaLock(MV_32 num); +MV_BOOL mvSemaTryLock(MV_32 num); +MV_BOOL mvSemaUnlock(MV_32 num); +MV_32 mvReadAmpReg(int regId); +MV_32 mvWriteAmpReg(int regId, MV_32 value); + +/* Turn on HW semapores only if AMP is enabled */ +#ifndef CONFIG_MV_AMP_ENABLE +#define mvSemaLock +#define mvSemaTryLock +#define mvSemaUnlock +#define mvHwBarrier +#endif /* CONFIG_MV_AMP_ENABLE */ + +#endif /* mvsemaphore_h */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvUnitMap.c b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvUnitMap.c new file mode 100755 index 000000000..a2436d153 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvUnitMap.c @@ -0,0 +1,266 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvUnitMap.h" + +static MV_BOOL mv_rsrc_limited = MV_FALSE; +static MV_RES_MAP mv_res_table[] = { + /* Dividable units */ + {0, "uart0"}, + {0, "uart1"}, + {0, "pex0"}, + {0, "pex1"}, + {0, "pex2"}, + {0, "pex3"}, + {0, "eth0"}, + {0, "eth1"}, + {0, "eth2"}, + {0, "eth3"}, + {0, "xor0"}, + {0, "xor1"}, + {0, "usb0"}, + {0, "usb1"}, + {0, "usb2"}, + {0, "i2c0"}, + {0, "i2c1"}, + /* Single Allocation units */ + {0, "sata"}, + {0, "cesa"}, + {0, "nor"}, + {0, "nand"}, + {0, "spi"}, + {0, "tdm"}, + {0, "sdio"}, + {0, "lcd"}, + {0, "hwmon"}, + {0, "rtc"}, + {0, "gpio"}, + {0, "mstr"}, + {-1, "last"} +}; + +MV_BOOL mvUnitMapIsRsrcLimited(void) +{ + return mv_rsrc_limited; +} + +MV_VOID mvUnitMapSetRsrcLimited(MV_BOOL isLimited) +{ + mv_rsrc_limited = isLimited; +} + +MV_BOOL mvUnitMapIsMine(MV_SOC_UNIT unitIdx) +{ + return mv_res_table[unitIdx].isMine; +} + +MV_BOOL mvUnitMapIsPexMine(int pciIf) +{ + MV_SOC_UNIT unitIdx; + + /* Map line Number to PEX unit number */ + /* This is compatible to mvCtrlSerdesPhyConfig in BoardEnvLib.c */ + if(pciIf < PEX1_0x4) + unitIdx = PEX0; + else if(pciIf < PEX2_0x4) + unitIdx = PEX1; + else if(pciIf < PEX3_0x4) + unitIdx = PEX2; + else + unitIdx = PEX3; + + return mv_res_table[unitIdx].isMine; +} + +MV_VOID mvUnitMapSetMine(MV_SOC_UNIT unitIdx) +{ + if (MV_TRUE == mv_res_table[unitIdx].isMine) + return; + + mv_res_table[unitIdx].isMine = 1; +} + +MV_BOOL mvUnitMapSetup(char* cmdLine, STRSTR_FUNCPTR strstr_func) +{ + int unitIdx; + char* match; + + for (unitIdx = 0; mv_res_table[unitIdx].isMine != (-1); unitIdx++) { + char *unitName = mv_res_table[unitIdx].unitName; + int len; + match = strstr_func(cmdLine, unitName); + if (!match) continue; + /*Look for start delimiter*/ + if (match > cmdLine) { + if (match[-1] != ' ' && match[-1] != ':') { + continue; + } + } + /* Calc string length without using strlen() */ + while (*unitName++ != '\0'); + len = unitName - mv_res_table[unitIdx].unitName - 1; + /*Look for end delimiter*/ + if (match[len] != ' ' && match[len] != ':' && match[len] != '\0') { + continue; + } + mvUnitMapSetMine(unitIdx); + } + return MV_TRUE; +} + +/*MV_BOOL mvSocUnitMapFillTableFormBitMap(MV_U32 flag) +{ + int i,bit,cpuId; + for (i = 0; mv_res_table[i].cpuId != -1; i++) + { + switch (i) + { + case UART0: bit=UART0_T0_CPU1; break; + case UART1: bit=UART1_TO_CPU1; break; + case PEX00: bit=PEX0_TO_CPU1; break; + case PEX10: bit=PEX1_TO_CPU1; break; + case GIGA0: bit=GIGA0_TO_CPU1; break; + case GIGA1: bit=GIGA1_TO_CPU1; break; + case GIGA2: bit=GIGA2_TO_CPU1; break; + case GIGA3: bit=GIGA3_TO_CPU1; break; + case SATA: bit=SATA_TO_CPU1; break; + case XOR: bit=XOR_TO_CPU1; break; + case IDMA: bit=IDMA_TO_CPU1; break; + case USB0: bit=USB0_TO_CPU1; break; + case USB1: bit=USB1_TO_CPU1; break; + case USB2: bit=USB2_TO_CPU1; break; + case CESA: bit=CESA_TO_CPU1; break; + case NOR_FLASH: bit=NOR_TO_CPU1; break; + case NAND_FLASH: bit=NAND_TO_CPU1; break; + case SPI_FLASH:bit=SPI_TO_CPU1; break; + case TDM: bit=TDM_TO_CPU1; break; + default: bit=0; + break; + } + //cpuId = (flag & bit) ? SLAVE_CPU:MASTER_CPU; + mvSocUnitMapSet(i, cpuId); + } + return MV_TRUE; +} + +MV_U32 mvSocUnitMapFillFlagFormTable(void) +{ + int i; + MV_U32 flag = 0; + for (i = 0; mv_res_table[i].cpuId != -1; i++) + { + if (mvSocUnitMapGet(i) == 0)//SLAVE_CPU) + { + switch (i) + { + case UART0: flag |= UART0_T0_CPU1; break; + case UART1: flag |= UART1_TO_CPU1; break; + case PEX00: flag |= PEX0_TO_CPU1; break; + case PEX10: flag |= PEX1_TO_CPU1; break; + case GIGA0: flag |= GIGA0_TO_CPU1; break; + case GIGA1: flag |= GIGA1_TO_CPU1; break; + case GIGA2: flag |= GIGA2_TO_CPU1; break; + case GIGA3: flag |= GIGA3_TO_CPU1; break; + case SATA: flag |= SATA_TO_CPU1; break; + case XOR: flag |= XOR_TO_CPU1; break; + case IDMA: flag |= IDMA_TO_CPU1; break; + case USB0: flag |= USB0_TO_CPU1; break; + case USB1: flag |= USB1_TO_CPU1; break; + case USB2: flag |= USB2_TO_CPU1; break; + case CESA: flag |= CESA_TO_CPU1; break; + case NOR_FLASH: flag |= NOR_TO_CPU1; break; + case NAND_FLASH: flag |= NAND_TO_CPU1; break; + case SPI_FLASH: flag |= SPI_TO_CPU1; break; + case TDM: flag |= TDM_TO_CPU1; break; + default: + break; + } + } + } + + return flag; +}*/ +MV_VOID mvUnitMapSetAllMine() +{ + int unitIdx; + for (unitIdx = 0; mv_res_table[unitIdx].isMine != (-1); unitIdx++) { + mvUnitMapSetMine(unitIdx); + } +} + +MV_VOID mvUnitMapPrint() +{ + int unitIdx; + mvOsPrintf(" AMP: Resources "); + for (unitIdx = 0; mv_res_table[unitIdx].isMine != -1; unitIdx++) { + if (mv_res_table[unitIdx].isMine) { + mvOsPrintf("- %s ", mv_res_table[unitIdx].unitName); + } + } + mvOsPrintf("\n"); +} diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvUnitMap.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvUnitMap.h new file mode 100755 index 000000000..0321d7b59 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/mvUnitMap.h @@ -0,0 +1,158 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef mvUnitMap_h +#define mvUnitMap_h + +#ifdef MV_VXWORKS +#include "common/mvTypes.h" +#include "config.h" +#endif + +typedef enum +{ + UART0=0, + UART1, + PEX0, + PEX1, + PEX2, + PEX3, + ETH0, + ETH1, + ETH2, + ETH3, + XOR0, + XOR1, + USB0, + USB1, + USB2, + I2C0, + I2C1, + SATA, + CESA, + NOR, + NAND, + SPI, + TDM, + SDIO, + LCD, + HWMON, + RTC, + GPIO, + MSTR, + MAX_UNITS +} MV_SOC_UNIT; + +/* binary flags for mvSocUnitMapFillTableFormBitMap */ +/*#define UART0_T0_CPU1 0x0001 +#define UART1_TO_CPU1 0x0002 +#define PEX0_TO_CPU1 0x0004 +#define PEX1_TO_CPU1 0x0008 +#define GIGA0_TO_CPU1 0x0010 +#define GIGA1_TO_CPU1 0x0020 +#define GIGA2_TO_CPU1 0x0040 +#define GIGA3_TO_CPU1 0x0080 +#define SATA_TO_CPU1 0x0100 +#define XOR_TO_CPU1 0x0200 +#define IDMA_TO_CPU1 0x0400 +#define USB0_TO_CPU1 0x0800 +#define USB1_TO_CPU1 0x1000 +#define USB2_TO_CPU1 0x2000 +#define CESA_TO_CPU1 0x4000 +#define NOR_TO_CPU1 0x8000 +#define NAND_TO_CPU1 0x10000 +#define SPI_TO_CPU1 0x20000 +#define TDM_TO_CPU1 0x40000 + +#define CPU1_DEFAULT_INTERFACE (UART1_TO_CPU1 | PEX1_TO_CPU1 | GIGA2_TO_CPU1 | GIGA3_TO_CPU1 | IDMA_TO_CPU1 | USB1_TO_CPU1)*/ + +typedef struct __MV_RES_MAP +{ + int isMine; + char* unitName; +} MV_RES_MAP; + +typedef char *(*STRSTR_FUNCPTR)(const char *s1, const char *s2); + +#ifdef CONFIG_MV_AMP_ENABLE + +MV_BOOL mvUnitMapIsMine(MV_SOC_UNIT unitIdx); +MV_BOOL mvUnitMapIsPexMine(int pciIf); +MV_VOID mvUnitMapSetMine(MV_SOC_UNIT unitIdx); +MV_BOOL mvUnitMapSetup(char* p, STRSTR_FUNCPTR strstr_func); +MV_VOID mvUnitMapSetAllMine(void); +MV_VOID mvUnitMapPrint(void); +MV_BOOL mvUnitMapIsRsrcLimited(void); +MV_VOID mvUnitMapSetRsrcLimited(MV_BOOL isLimited); +#else /* CONFIG_MV_AMP_ENABLE */ +#define mvUnitMapIsMine(rsrc) MV_TRUE +#define mvUnitMapIsPexMine(pciIf) MV_TRUE +#define mvUnitMapIsRsrcLimited MV_TRUE +#define mvUnitMapSetRsrcLimited(limit) +#define mvUnitMapSetMine(rsrc) +#define mvUnitMapSetAllMine +#define mvUnitMapPrint +#define mvUnitMapSetup(str, strstr_func) MV_TRUE +#endif /* CONFIG_MV_AMP_ENABLE */ + +#endif /* mvUnitMap_h */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c new file mode 100755 index 000000000..1cc1aa333 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.c @@ -0,0 +1,750 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "mvCpuIfRegs.h" + +#undef MV_DEBUG +/* defines */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* typedefs */ + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _ahbToMbusRemapRegOffs { + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +} AHB_TO_MBUS_REMAP_REG_OFFS; + +/* locals */ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); + +/******************************************************************************* +* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK laways. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusInit(void) +{ + return MV_OK; + +} + +/******************************************************************************* +* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* This function sets +* address window, also known as address decode window. +* A new address decode window is set for specified winNum address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the winNum window, allowing CPU to access +* the winNum window. +* +* INPUT: +* winNum - Windows number. +* pAddrDecWin - CPU winNum window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU winNum window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + MV_U32 sizeToReg; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) { + mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to " + "target %s.\nAddress 0x%08x is unaligned to size 0x%llx.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* Size parameter validity check. */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.size, ATMWCR_WIN_SIZE_ALIGNMENT)) { + mvOsPrintf("mvAhbToMbusWinSet: Failed, size not aligned to 0x%x.\n", ATMWCR_WIN_SIZE_ALIGNMENT); + return MV_BAD_PARAM; + } + + /* Write to address decode Base Address Register */ + decRegs.baseReg = (pAddrDecWin->addrWin.baseLow & ATMWBR_BASE_MASK); + + /* Get size register value according to window size */ + sizeToReg = (pAddrDecWin->addrWin.size / ATMWCR_WIN_SIZE_ALIGNMENT) - 1; + + /* set size */ + decRegs.ctrlReg = (sizeToReg << ATMWCR_WIN_SIZE_OFFS); + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + decRegs.ctrlReg |= ATMWCR_WIN_ENABLE; + else + decRegs.ctrlReg &= ~ATMWCR_WIN_ENABLE; + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.ctrlReg &= ~ATMWCR_WIN_ATTR_MASK; + decRegs.ctrlReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.ctrlReg &= ~ATMWCR_WIN_TARGET_MASK; + decRegs.ctrlReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; + +#if !defined(MV_RUN_FROM_FLASH) + /* To be on the safe side we disable the window before writing the */ + /* new values. */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + mvAhbToMbusWinEnable(winNum, MV_FALSE); +#endif + + /* 3) Write to address decode Base Address Register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); + else + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); + + + /* Internal register space have no size */ + /* register. Do not perform size register assigment for those targets */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) { + /* Write to address decode Size Register */ + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.ctrlReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* Get the CPU peripheral winNum address window. +* +* INPUT: +* winNum - Peripheral winNum enumerator +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_OK if winNum exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 sizeRegVal; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal register space size have no size register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + decRegs.ctrlReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + else + decRegs.ctrlReg = 0; + + /* Read base and size */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + else + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + + pAddrDecWin->addrWin.baseHigh = 0; + pAddrDecWin->addrWin.baseLow = decRegs.baseReg & ATMWBR_BASE_MASK; + sizeRegVal = (decRegs.ctrlReg & ATMWCR_WIN_SIZE_MASK) >> ATMWCR_WIN_SIZE_OFFS; + pAddrDecWin->addrWin.size = (sizeRegVal + 1) * ATMWCR_WIN_SIZE_ALIGNMENT; + + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) { + pAddrDecWin->addrWin.size = INTER_REGS_SIZE; + pAddrDecWin->target = INTER_REGS; + pAddrDecWin->enable = MV_TRUE; + + return MV_OK; + } + + if (decRegs.ctrlReg & ATMWCR_WIN_ENABLE) + pAddrDecWin->enable = MV_TRUE; + else + pAddrDecWin->enable = MV_FALSE; + + if (-1 == pAddrDecWin->addrWin.size) + return MV_ERROR; + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.ctrlReg & ATMWCR_WIN_ATTR_MASK) >> ATMWCR_WIN_ATTR_OFFS; + targetAttrib.targetId = (decRegs.ctrlReg & ATMWCR_WIN_TARGET_MASK) >> ATMWCR_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is illegal\n", target); + return 0xffffffff; + } + + if (INTER_REGS == target) + return MV_AHB_TO_MBUS_INTREG_WIN; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_TRUE) { + if (decWin.target == target) + return winNum; + } + } + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvAhbToMbusWinAvailGet - Get First Available window number. +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_FALSE) + return winNum; + } + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Peripheral winNum enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other winNum window. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) +{ + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal registers bar can't be disable or enabled */ + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + return (enable ? MV_OK : MV_ERROR); + + + if (enable == MV_TRUE) { + /* enable the window */ + MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } else { + /* Disable address decode winNum window */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* After a CPU address hits one of PCI address decode windows there is an +* option to remap the address to a different one. For example, CPU +* executes a read from PCI winNum window address 0x1200.0000. This +* can be modified so the address on the PCI bus would be 0x1400.0000 +* Using the PCI address remap mechanism. +* +* INPUT: +* winNum - Peripheral winNum enumerator. Must be a PCI winNum. +* pAddrDecWin - CPU winNum window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddr; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + MV_U32 effectiveBaseAddress = 0, baseAddrValue = 0, windowSizeValue = 0; + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) + return 0xffffffff; + + /* 1) Set address remap low */ + baseAddr = pAddrWin->baseLow; + + /* Check base address aligment */ + /* + if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) + { + mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", + baseAddr); + return MV_ERROR; + } + */ + + /* BaseLow[31:16] => base register [31:16] */ + baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; + + MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); + MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); + + baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + + baseAddrValue &= ATMWBR_BASE_MASK; + windowSizeValue &= ATMWCR_WIN_SIZE_MASK; + + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue; + + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + + if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) { + mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); + return 0xffffffff; + } + + return effectiveBaseAddress; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets +* +* DESCRIPTION: +* +* INPUT: +* target1 - CPU Interface target 1 +* target2 - CPU Interface target 2 +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if targets are illigal, or if one of the targets is not +* associated to a valid window . +* MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1, MV_TARGET target2) +{ + MV_U32 winNum1, winNum2; + MV_AHB_TO_MBUS_DEC_WIN winDec1, winDec2, winDecTemp; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1, remapRegs2; + MV_U32 remapBaseLow1 = 0, remapBaseLow2 = 0; + MV_U32 remapBaseHigh1 = 0, remapBaseHigh2 = 0; + + /* Check parameters */ + if (target1 >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is illegal\n", target1); + return MV_ERROR; + } + + if (target2 >= MAX_TARGETS) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is illegal\n", target1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum1 = mvAhbToMbusWinTargetGet(target1); + + if (winNum1 == 0xffffffff) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", target1, winNum1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum2 = mvAhbToMbusWinTargetGet(target2); + if (winNum2 == 0xffffffff) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", target2, winNum2); + return MV_ERROR; + } + + /* now Get original values of both Windows */ + if (MV_OK != mvAhbToMbusWinGet(winNum1, &winDec1)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinGet(winNum2, &winDec2)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", winNum2); + return MV_ERROR; + } + + /* disable both windows */ + if (MV_OK != mvAhbToMbusWinEnable(winNum1, MV_FALSE)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinEnable(winNum2, MV_FALSE)) { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", winNum2); + return MV_ERROR; + } + + /* now swap targets */ + + /* first save winDec2 values */ + winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; + winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; + winDecTemp.addrWin.size = winDec2.addrWin.size; + winDecTemp.enable = winDec2.enable; + winDecTemp.target = winDec2.target; + + /* winDec2 = winDec1 */ + winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; + winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; + winDec2.addrWin.size = winDec1.addrWin.size; + winDec2.enable = winDec1.enable; + winDec2.target = winDec1.target; + + /* winDec1 = winDecTemp */ + winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; + winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; + winDec1.addrWin.size = winDecTemp.addrWin.size; + winDec1.enable = winDecTemp.enable; + winDec1.target = winDecTemp.target; + + /* now set the new values */ + mvAhbToMbusWinSet(winNum1, &winDec1); + mvAhbToMbusWinSet(winNum2, &winDec2); + + /* now we will treat the remap windows if exist */ + + /* now check if one or both windows has a remap window + as well after the swap ! */ + + /* if a window had a remap value differnt than the base value + before the swap , then after the swap the remap value will be + equal to the base value unless both windows has a remap windows */ + + /* first get old values */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1, &remapRegs1)) { + remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); + remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); + } + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); + remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); + } + + /* now do the swap */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1, &remapRegs1)) { + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + /* Two windows has a remap !!! so swap */ + + MV_REG_WRITE(remapRegs2.highRegOffs, remapBaseHigh1); + MV_REG_WRITE(remapRegs2.lowRegOffs, remapBaseLow1); + + MV_REG_WRITE(remapRegs1.highRegOffs, remapBaseHigh2); + MV_REG_WRITE(remapRegs1.lowRegOffs, remapBaseLow2); + } else { + /* remap == base */ + MV_REG_WRITE(remapRegs1.highRegOffs, winDec1.addrWin.baseHigh); + MV_REG_WRITE(remapRegs1.lowRegOffs, winDec1.addrWin.baseLow); + } + } else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2, &remapRegs2)) { + /* remap == base */ + MV_REG_WRITE(remapRegs2.highRegOffs, winDec2.addrWin.baseHigh); + MV_REG_WRITE(remapRegs2.lowRegOffs, winDec2.addrWin.baseLow); + } + + return MV_OK; +} + +/******************************************************************************* +* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets +* +* DESCRIPTION: +* CPU to PCI address remap registers offsets are inconsecutive. +* This function returns PCI address remap registers offsets. +* +* INPUT: +* winNum - Address decode window number. See MV_U32 enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one. +* +*******************************************************************************/ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) +{ + switch (winNum) { + case 0: + case 1: + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + case 2: + case 3: + if ((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID) || + (mvCtrlModelGet() == MV_6710_DEV_ID) || + (mvCtrlModelGet() == MV_78130_DEV_ID) || + (mvCtrlModelGet() == MV_78160_DEV_ID) || + (mvCtrlModelGet() == MV_78230_DEV_ID) || + (mvCtrlModelGet() == MV_78260_DEV_ID) || + (mvCtrlModelGet() == MV_78460_DEV_ID) || + (mvCtrlModelGet() == MV_78000_DEV_ID)) { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } else { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + break; + case 4: + case 5: + case 6: + case 7: + if ((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID) || + (mvCtrlModelGet() == MV_6710_DEV_ID) || + (mvCtrlModelGet() == MV_78130_DEV_ID) || + (mvCtrlModelGet() == MV_78160_DEV_ID) || + (mvCtrlModelGet() == MV_78230_DEV_ID) || + (mvCtrlModelGet() == MV_78260_DEV_ID) || + (mvCtrlModelGet() == MV_78460_DEV_ID) || + (mvCtrlModelGet() == MV_78000_DEV_ID)) { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } else { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + break; + default: + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", winNum)); + return MV_NO_SUCH; + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAhbToMbusAddDecShow(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN win; + MV_U32 winNum; + mvOsOutput("\n"); + mvOsOutput("AHB To MBUS Bridge:\n"); + mvOsOutput("-------------------\n"); + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++) { + memset(&win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN)); + + mvOsOutput("win%d - ", winNum); + + if (mvAhbToMbusWinGet(winNum, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("%s base %08x, ", mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput("...."); + mvSizePrint(win.addrWin.size); + + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } + } +} diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h new file mode 100755 index 000000000..f91ee5911 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbus.h @@ -0,0 +1,96 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbush +#define __INCmvAhbToMbush + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* defines */ + +typedef struct _mvAhbtoMbusDecWin { + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_AHB_TO_MBUS_DEC_WIN; + +/* mvAhbToMbus.h API list */ + +MV_STATUS mvAhbToMbusInit(MV_VOID); +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable); +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1, MV_TARGET target2); + +MV_VOID mvAhbToMbusAddDecShow(MV_VOID); + +#endif /* __INCmvAhbToMbush */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h new file mode 100755 index 000000000..50fd8161c --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvAhbToMbusRegs.h @@ -0,0 +1,143 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusRegsh +#define __INCmvAhbToMbusRegsh + +#define MAX_AHB_TO_MBUS_WINS 21 +#define MAX_AHB_TO_MBUS_REMAP_WINS 8 +#define MV_AHB_TO_MBUS_INTREG_WIN 20 + +/***********************/ +/* AHB TO MBUS WINDOWS */ +/***********************/ +/* Window-X Control Registers */ +#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS) ? \ + (MV_MBUS_REGS_OFFSET + winNum * 0x10) : \ + (MV_MBUS_REGS_OFFSET + 0x90 + (winNum-8)*0x08)) +#define ATMWCR_WIN_ENABLE BIT0 +#define ATMWCR_WIN_TARGET_OFFS 4 +#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) +#define ATMWCR_WIN_ATTR_OFFS 8 +#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) +#define ATMWCR_WIN_SIZE_OFFS 16 +#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) +#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 + +/* Window-X Base Register */ +#define AHB_TO_MBUS_WIN_BASE_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS) ? \ + (MV_MBUS_REGS_OFFSET + 0x4 + winNum*0x10) : \ + (MV_MBUS_REGS_OFFSET + 0x94 + (winNum-8)*0x08)) +#define ATMWBR_BASE_OFFS 16 +#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) +#define ATMWBR_BASE_ALIGNMENT 0x10000 + +/* Window-X Remap Low Register */ +#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS) ? \ + (MV_MBUS_REGS_OFFSET + 0x8 + winNum*0x10) : \ + (0)) +#define ATMWRLR_REMAP_LOW_OFFS 16 +#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) +#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 + +/* Window-X Remap Hi Register */ +#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) ((winNum < MAX_AHB_TO_MBUS_REMAP_WINS) ? \ + (MV_MBUS_REGS_OFFSET + 0xC + winNum*0x10) : \ + (0)) +#define ATMWRHR_REMAP_HIGH_OFFS 0 +#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) + +/*****************************/ +/* INTERNAL REGISTERS WINDOW */ +/*****************************/ +/* Internal Registers Base Address in set to be window 20 */ +#define AHB_TO_MBUS_WIN_INTEREG_REG (MV_MBUS_REGS_OFFSET + 0x80) + +/************************/ +/* SDRAM DECODE WINDOWS */ +/************************/ +/* All DRAM Window definitions are declared under the ddr2_3 HAL */ + +/****************************/ +/* SRAM (L2) DECODE WINDOWS */ +/****************************/ +#define SRAM_WIN_CTRL_REG(winNum) (MV_MBUS_REGS_OFFSET + 0x240 + winNum * 0x4) +#define SRAMWCR_ENABLE BIT0 +#define SRAMWCR_SIZE_OFFS 8 +#define SRAMWCR_SIZE_MASK (0x7 << SRAMWCR_SIZE_OFFS) +#define SRAMWCR_BASE_OFFS 16 +#define SRAMWCR_BASE_MASK (0xFFFF << SRAMWCR_BASE_OFFS) + +/**********************/ +/* MBUS BRIDGE WINDOW */ +/**********************/ +#define MBUS_BRIDGE_WIN_CTRL_REG (MV_MBUS_REGS_OFFSET + 0x250) +#define BRIDGWCR_ENABLE BIT0 +#define BRIDGWCR_SIZE_OFFS 16 +#define BRIDGWCR_SIZE_MASK (0xFFFF << BRIDGWCR_SIZE_OFFS) +#define MBUS_BRIDGE_WIN_BASE_REG (MV_MBUS_REGS_OFFSET + 0x254) + +#endif /* __INCmvAhbToMbusRegsh */ + diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c new file mode 100755 index 000000000..dbd355b06 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIf.c @@ -0,0 +1,966 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +/*#include "cpu/mvCpu.h" *//* whoAmI() */ +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "ddr2_3/mvDramIf.h" +#include "ddr2_3/mvDramIfRegs.h" +#include "pex/mvPexRegs.h" + +/*#define MV_DEBUG*/ +/* defines */ + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ +/* static functions */ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +MV_TARGET sampleAtResetTargetArray[] = BOOT_TARGETS_NAME_ARRAY; +MV_STATUS mvCpuIfVerify(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + MV_32 diff; + + for (target = 0; target < MAX_TARGETS; target++) { + memset(&win, 0, sizeof(MV_CPU_DEC_WIN)); + + if(win.enable == cpuAddrWinMap->enable) + { + if(win.enable) + { + diff = (win.addrWin.baseLow - cpuAddrWinMap->addrWin.baseLow); + diff |= (win.addrWin.baseHigh - cpuAddrWinMap->addrWin.baseHigh); + diff |= (win.addrWin.size - cpuAddrWinMap->addrWin.size); + /*TODO - Need to compare the window attributes as well */ + + if(diff) + { + mvOsOutput("mvCpuIfVerify: Mismatched window size in target %d\n", target); + return MV_ERROR; + } + } + } + else + { + mvOsOutput("mvCpuIfVerify: Mismatched enable field in target %d\n", target); + return MV_ERROR; + } + } + return MV_OK; +} +/******************************************************************************* +* mvCpuIfInitForCpu - Initialize Controller CPU interface +* +* DESCRIPTION: +* This function initialize Controller CPU interface: +* 1. Set CPU interface configuration registers. +* 2. Set CPU master Pizza arbiter control according to static +* configuration described in configuration file. +* 3. Opens CPU address decode windows. DRAM windows are assumed to be +* already set (auto detection). +* +* INPUT: +* cpu - CPU id. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfInitForCpu(MV_U32 cpu, MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_U32 regVal, i; + MV_TARGET target; + MV_ADDR_WIN addrWin; + MV_U32 minBase = 0xFFFFFFFF; + MV_U32 minSize; + + if (cpuAddrWinMap == NULL) { + DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); + return MV_ERROR; + } + + /* Set IO Bypass base address and size according to the cpuAddrWinMap */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + if ((MV_TARGET_IS_DRAM(target)) || (DIS == cpuAddrWinMap[target].enable) || + (target == INTER_REGS)) + continue; + if (cpuAddrWinMap[target].addrWin.baseLow == 0) + continue; + if (cpuAddrWinMap[target].addrWin.baseLow < minBase) + minBase = cpuAddrWinMap[target].addrWin.baseLow; + } + if (minBase != 0x0) { + minSize = 0xFFFFFFFF - minBase + 1; + if (!MV_IS_POWER_OF_2(minSize)) { + /* Round up to next power of 2. */ + minSize = (1 << (mvLog2(minSize) + 1)); + minBase = 0xFFFFFFFF - minSize + 1; + } + + /* Now write the base and size */ + MV_REG_WRITE(MBUS_BRIDGE_WIN_BASE_REG, minBase); + /* Align window size to 64KB */ + regVal = (minSize / SDRAMWBR_BASE_ALIGNMENT) - 1; + regVal = (regVal << 16) | 0x1; + MV_REG_WRITE(MBUS_BRIDGE_WIN_CTRL_REG, regVal); + } + + /* Set CPU Configuration register */ + regVal = MV_REG_READ(CPU_CONFIG_REG(cpu)); + regVal &= ~CPU_CONFIG_DEFAULT_MASK; + regVal |= CPU_CONFIG_DEFAULT; + MV_REG_WRITE(CPU_CONFIG_REG(cpu), regVal); + + for (i = 0; i < MAX_AHB_TO_MBUS_WINS-2; i++) + mvAhbToMbusWinEnable(i, MV_FALSE); + + /* Disable all SRAM windows */ + mvCpuIfSramWinDisable(); + + /* First disable all CPU target windows */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + if ((MV_TARGET_IS_DRAM(target)) || (target == INTER_REGS)) + continue; +#ifdef CONFIG_MV_AMP_ENABLE + if(target == BOOT_ROM_CS) + continue; +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + continue; +#endif +#if defined(MV_RUN_FROM_FLASH) + /* Don't disable the boot device. */ + if (target == DEV_BOOCS) + continue; +#endif /* MV_RUN_FROM_FLASH */ + mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target), MV_FALSE); + } + +#if defined(MV_RUN_FROM_FLASH) + /* Resize the bootcs windows before other windows, because this */ + /* window is enabled and will cause an overlap if not resized. */ + target = DEV_BOOCS; + + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum, &addrWin)) { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } +#endif /* MV_RUN_FROM_FLASH */ + + /* Go through all targets in user table until table terminator */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) { + +#if defined(MV_RUN_FROM_FLASH) + if (target == DEV_BOOCS) + continue; +#endif /* MV_RUN_FROM_FLASH */ + + /* if DRAM auto sizing is used do not initialized DRAM target windows, */ + /* assuming this already has been done earlier. */ +#ifdef MV_DRAM_AUTO_SIZE + if (MV_TARGET_IS_DRAM(target)) + continue; +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + continue; +#endif + if ((0 == cpuAddrWinMap[target].addrWin.size) || (DIS == cpuAddrWinMap[target].enable)) + continue; + else { + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum, &addrWin)) { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + } + } + return MV_OK; +} + +/*******************************************************************************/ +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + return mvCpuIfInitForCpu(whoAmI(), cpuAddrWinMap); +} + + +/******************************************************************************* +* mvCpuIfDramInit - Initialize Controller DRAM Fastpath windows +* +* DESCRIPTION: +* This function initialize Controller DRAM Fastpath windows +* It takes the CS size information from the 0x1500 scratch registers +* and sets the correct windows sizes and base addresses accordingly +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfDramInit() +{ + MV_U64 base = 0; + MV_U32 size, cs, temp; + + for (cs = 0; cs < SDRAM_MAX_CS; cs++) { + size = MV_REG_READ(SDRAM_SIZE_REG(cs)) & SDRAM_ADDR_MASK; +/* if (size > 0 && base < SDRAM_MAX_ADDR) { */ + if (size != 0) { + size |= ~(SDRAM_ADDR_MASK); + + /* Set Base Address */ + temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); + MV_REG_WRITE(SDRAM_WIN_BASE_REG(cs), temp); + + /* Check if out of max window size and resize the window */ +#if 0 + if (base+size > SDRAM_MAX_ADDR) { + size = SDRAM_MAX_ADDR - base - 1; + MV_REG_WRITE(SDRAM_SIZE_REG(cs), 0); + } +#endif + temp = (MV_REG_READ(SDRAM_WIN_CTRL_REG(cs)) & ~(SDRAM_ADDR_MASK)) | (1<= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinSet: target %d is illegal\n", target); + return MV_ERROR; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); + return MV_BAD_PARAM; + } + + if (MV_TARGET_IS_DRAM(target)) { + /* copy relevant data to MV_DRAM_DEC_WIN structure */ + addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; + addrDecWin.enable = pAddrDecWin->enable; + + if (mvDramIfWinSet(target, &addrDecWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); + return MV_ERROR; + } + } else { + /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ + decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + decWin.addrWin.size = pAddrDecWin->addrWin.size; + decWin.enable = pAddrDecWin->enable; + decWin.target = target; + + existingWinNum = mvAhbToMbusWinTargetGet(target); + + /* check if there is already another Window configured + for this target */ + if ((existingWinNum < MAX_AHB_TO_MBUS_WINS) && (existingWinNum != pAddrDecWin->winNum)) { + /* if we want to enable the new window number + passed by the user , then the old one should + be disabled */ + if (MV_TRUE == pAddrDecWin->enable) { + /* be sure it is disabled */ + mvAhbToMbusWinEnable(existingWinNum, MV_FALSE); + } + } + + if (mvAhbToMbusWinSet(pAddrDecWin->winNum, &decWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_U32 winNum = 0xffffffff; + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinGet: target %d is illegal\n", target); + return MV_ERROR; + } + + if (MV_TARGET_IS_DRAM(target)) { + if (mvDramIfWinGet(target, &addrDecWin) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", target); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = (MV_U64)addrDecWin.addrWin.size; + pAddrDecWin->enable = addrDecWin.enable; + pAddrDecWin->winNum = target; + } else { + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(target); + if (winNum >= MAX_AHB_TO_MBUS_WINS) + return MV_NO_SUCH; + + if (mvAhbToMbusWinGet(winNum, &decWin) != MV_OK) { + mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", __func__, winNum); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = decWin.addrWin.size; + pAddrDecWin->enable = decWin.enable; + pAddrDecWin->winNum = winNum; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* target - Peripheral target enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other target window. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_U32 winNum, temp; + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinEnable: target %d is illegal\n", target); + return MV_ERROR; + } + + /* get the window and check if it exist */ + temp = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == temp) { + return (enable ? MV_ERROR : MV_OK); + } else if (MV_OK != temp) { + mvOsPrintf("%s: ERR. Getting target %d failed.\n", __func__, target); + return MV_ERROR; + } + + /* check overlap */ + if (MV_TRUE == enable) { + if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) { + DB(mvOsPrintf("%s: ERR. Target %d overlap\n", __func__, target)); + return MV_ERROR; + } + } + + if (MV_TARGET_IS_DRAM(target)) { + if (mvDramIfWinEnable(target, enable) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); + return MV_ERROR; + } + } else { + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(target); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + return (enable ? MV_ERROR : MV_OK); + + if (mvAhbToMbusWinEnable(winNum, enable) != MV_OK) { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", winNum); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinSizeGet - Get CPU target address window size +* +* DESCRIPTION: +* Get the size of CPU-to-peripheral target window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit size. Function also returns '0' if window is closed. +* Function returns 0xFFFFFFFF in case of an error. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is illegal\n", target); + return 0; + } + + /* Get the winNum window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", target); + return 0; + } + + /* Check if window is enabled */ + if (addrDecWin.enable == MV_TRUE) + return (addrDecWin.addrWin.size); + else + return 0; /* Window disabled. return 0 */ +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target low base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit low base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is illegal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + return 0xffffffff; + + return (addrDecWin.addrWin.baseLow); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target high base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit high base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is illegal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + return 0; + + return (addrDecWin.addrWin.baseHigh); +} + + +/******************************************************************************* +* mvCpuIfSramWinDisable +* +* DESCRIPTION: +* Disable the SRAM windows. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success. +* +*******************************************************************************/ +MV_STATUS mvCpuIfSramWinDisable(MV_VOID) +{ + MV_U32 i; + + for (i = 0; i < 4; i++) + MV_REG_WRITE(SRAM_WIN_CTRL_REG(i), SRAM_WIN_CTRL_DEFAULT_VAL); + + return MV_OK; +} + + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfPexRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pexTarget - Peripheral target enumerator. Must be a PEX target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PEX one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + if (mvCtrlPexMaxIfGet() > 1) { + if ((!MV_TARGET_IS_PEX0(pexTarget)) && + (!MV_TARGET_IS_PEX1(pexTarget)) && + (!MV_TARGET_IS_PEX2(pexTarget)) && + (!MV_TARGET_IS_PEX3(pexTarget)) && + (!MV_TARGET_IS_PEX4(pexTarget)) && + (!MV_TARGET_IS_PEX5(pexTarget)) && + (!MV_TARGET_IS_PEX6(pexTarget)) && + (!MV_TARGET_IS_PEX7(pexTarget)) && + (!MV_TARGET_IS_PEX8(pexTarget)) && + (!MV_TARGET_IS_PEX9(pexTarget))) { + mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget); + return 0xffffffff; + } + } else { + if (!MV_TARGET_IS_PEX0(pexTarget)) { + mvOsPrintf("mvCpuIfPexRemap: target %d is illegal\n", pexTarget); + return 0xffffffff; + } + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pexTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + } + + return mvAhbToMbusWinRemap(winNum, pAddrDecWin); +} +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCpuIfPciRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pciIfTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + } + + return mvAhbToMbusWinRemap(winNum, pAddrDecWin); +} +#endif + +/******************************************************************************* +* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address +* +* DESCRIPTION: +* +* INPUT: +* baseAddress - base address to be checked +* +* OUTPUT: +* None. +* +* RETURN: +* the target number that baseAddress belongs to or MAX_TARGETS is not +* found +* +*******************************************************************************/ +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + for (target = 0; target < MAX_TARGETS; target++) { + if (mvCpuIfTargetWinGet(target, &win) == MV_OK) { + if (win.enable) { + if ((baseAddress >= win.addrWin.baseLow) && + (baseAddress < win.addrWin.baseLow + win.addrWin.size)) + break; + } + } else + return MAX_TARGETS; + } + + return target; +} + +/******************************************************************************* +* cpuTargetWinOverlap - Detect CPU address decode windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case CPU address decode +* windows overlapps. +* This function detects CPU address decode windows overlapping of a +* specified target. The function does not check the target itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 targetNum; + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS status; + + for (targetNum = 0; targetNum < MAX_TARGETS; targetNum++) { + /* don't check our target or illegal targets */ + if (targetNum == target) + continue; + + /* Get window parameters */ + status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); + if (MV_NO_SUCH == status) + continue; + + if (MV_OK != status) { + DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); + return MV_TRUE; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + continue; + + if (MV_TRUE == mvWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) { + DB(mvOsPrintf("cpuTargetWinOverlap: Required target %d overlap current %d\n", + target, targetNum)); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvCpuIfAddDecShow - Print the CPU address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfAddDecShow(MV_VOID) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + mvOsOutput("\n"); + mvOsOutput("CPU Interface\n"); + mvOsOutput("-------------\n"); + + for (target = 0; target < MAX_TARGETS; target++) { + memset(&win, 0, sizeof(MV_CPU_DEC_WIN)); + + mvOsOutput("%s ", mvCtrlTargetNameGet(target)); + mvOsOutput("...."); + + if (mvCpuIfTargetWinGet(target, &win) == MV_OK) { + if (win.enable) { + mvOsOutput("base %01x%08x, ", win.addrWin.baseHigh, win.addrWin.baseLow); + mvSizePrint(win.addrWin.size); + mvOsOutput("\n"); + } else + mvOsOutput("disable\n"); + } else if (mvCpuIfTargetWinGet(target, &win) == MV_NO_SUCH) { + mvOsOutput("no such\n"); + } + } +} + +/******************************************************************************* +* mvCpuIfLvdsPadsEnable +* +* DESCRIPTION: +* Enable / Disable the LVDS pads. +* +* INPUT: +* enable - MV_TRUE to enable the pads, MV_FALSE to disable. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success. +* +*******************************************************************************/ +MV_STATUS mvCpuIfLvdsPadsEnable(MV_BOOL enable) +{ + MV_U32 reg; + MV_U32 i; + + reg = MV_REG_READ(LVDS_PADS_CTRL_REG); + + for (i = 0; i < 5; i++) { + reg &= ~LVDS_PADS_CONF_PD_MASK(i); + reg |= LVDS_PADS_CONF_PD_EN(i, enable); + } + + MV_REG_WRITE(LVDS_PADS_CTRL_REG, reg); + + return MV_OK; +} diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h new file mode 100755 index 000000000..f5ed71f25 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIf.h @@ -0,0 +1,122 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfh +#define __INCmvCpuIfh + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/sys/mvAhbToMbus.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ + +/* typedefs */ +/* This structure describes CPU interface address decode window */ +typedef struct _mvCpuIfDecWin { + MV_ADDR_WIN addrWin; /* An address window */ + MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +} MV_CPU_DEC_WIN; + + +/* mvCpuIfLib.h API list */ + +/* mvCpuIfLib.h API list */ + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); +MV_STATUS mvCpuIfVerify(MV_CPU_DEC_WIN *cpuAddrWinMap); +MV_STATUS mvCpuIfDramInit(MV_VOID); +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target, MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); +MV_STATUS mvCpuIfSramWinDisable(MV_VOID); +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +MV_VOID mvCpuIfAddDecShow(MV_VOID); + +MV_STATUS mvCpuIfLvdsPadsEnable(MV_BOOL enable); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCpuIfh */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S new file mode 100755 index 000000000..655d01bab --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIfInit.S @@ -0,0 +1,167 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvCommon.h" +#include "mvOsAsm.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvDeviceId.h" +#include "mvCtrlEnvRegs.h" +#include "mvCpuIfRegs.h" +#include "mvCtrlEnvAsm.h" + + +/******************************************************************************* +* mvCpuIfPreInit - Make early initialization of CPU interface. +* +* DESCRIPTION: +* The function will initialize the CPU interface parameters that must +* be initialize before any BUS activity towards the DDR interface, +* which means it must be executed from ROM. Because of that, the function +* is implemented in assembly code. +* The function configure the following CPU config register parameters: +* 1) CPU2MbusLTickDrv +* 2) CPU2MbusLTickSample. +* NOTE: This function must be called AFTER the internal register +* base is modified to INTER_REGS_BASE. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* r11 holds return function address. +*******************************************************************************/ +#define MV88F6281_PCKG_OPT 2 +#define MV88F6192_PCKG_OPT 1 +#define MV88F6180_PCKG_OPT 0 + + .globl _mvCpuIfPreInit +_mvCpuIfPreInit: + + mov r11, LR /* Save link register */ + b done +#if 0 + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* goto calcConfigReg if device is 6281/6282 */ + ldr r5, =MV88F6281_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* goto calcConfigReg if device is 6192/6190 */ + ldr r5, =MV88F6192_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* Else 6180 */ + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_CPUCLCK_MASK_6180 + and r5, r4, r5 + mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3_1 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4_1 + beq setConfigReg + b setConfigReg + +calcConfigReg: + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_DDRCLCK_RTIO_MASK + and r5, r4, r5 + mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4 + beq setConfigReg + + /* Else */ + ldr r4, =0 + +setConfigReg: + /* Read CPU Config register */ + MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) + ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) + and r7, r7, r5 /* Clear register fields */ + orr r7, r7, r4 /* Set the values according to the findings */ + MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) +#endif + +done: + mov PC, r11 /* r11 is saved link register */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h new file mode 100755 index 000000000..76362d207 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/ctrlEnv/sys/mvCpuIfRegs.h @@ -0,0 +1,362 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfRegsh +#define __INCmvCpuIfRegsh + +/****************************************/ +/* ARM Control and Status Registers Map */ +/****************************************/ +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + +#define MV_CPUIF_REGS_BASE(cpu) (MV_CPUIF_REGS_OFFSET(cpu)) +#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET) +#define MV_CLK_CMPLX_REGS_BASE (MV_CLK_CMPLX_REGS_OFFSET) +#define MV_L2C_REGS_BASE (MV_AURORA_L2_REGS_OFFSET) +#define MV_CPUIF_SHARED_REGS_BASE (MV_MBUS_REGS_OFFSET) +#define MV_COHERENCY_FABRIC_REGS_BASE (MV_COHERENCY_FABRIC_OFFSET) + +#define CPU_CONFIG_REG(cpu) (MV_CPUIF_REGS_BASE(cpu)) +#define CPU_CTRL_STAT_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x8) +#define CPU_RESUME_ADDR_REG(cpu) (MV_CPUIF_SHARED_REGS_BASE + (0x2124) + (cpu)*0x100) +#define CPU_RESET_REG(cpu) (MV_CPUIF_SHARED_REGS_BASE + (0x800+(cpu)*8)) +#define CPU_RESUME_CTRL_REG (MV_CPUIF_SHARED_REGS_BASE + (0x988)) +#define CPU_RSTOUTN_MASK_REG (MV_MISC_REGS_BASE + 0x60) +#define CPU_SYS_SOFT_RST_REG (MV_MISC_REGS_BASE + 0x64) +#define CPU_L2_CTRL_REG (MV_L2C_REGS_BASE + 0x100) +#define CPU_L2_AUX_CTRL_REG (MV_L2C_REGS_BASE + 0x104) +#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) +#define LVDS_PADS_CTRL_REG (MV_MISC_REGS_BASE + 0xF0) +#define SOC_COHERENCY_FABRIC_CTRL_REG (MV_COHERENCY_FABRIC_REGS_BASE) +#define SOC_COHERENCY_FABRIC_CFG_REG (MV_COHERENCY_FABRIC_REGS_BASE + 0x4) +#define SOC_CIB_CTRL_CFG_REG (MV_COHERENCY_FABRIC_REGS_BASE + 0x80) + +#define Fabric_Units_Priority_Control_REG (MV_MBUS_REGS_OFFSET + 0x424) +#define Fabric_Units_Prefetch_Control_REG (MV_MBUS_REGS_OFFSET + 0x42c) +#define CPUs_Data_PFen (0xf << 8) +#define CPUs_Data_PFen_MASK (0xf << 8) +#define CPU_PRIO_HIGH 0x2 +#define CPUs_PRIO_MASK 0xff +#define CPU0_PRIO_HIGH (CPU_PRIO_HIGH << 0) +#define CPU1_PRIO_HIGH (CPU_PRIO_HIGH << 2) +#define CPU2_PRIO_HIGH (CPU_PRIO_HIGH << 4) +#define CPU3_PRIO_HIGH (CPU_PRIO_HIGH << 6) +/* SoC Control Register bits */ +#define PCIE0_QUADX1_EN (1<<7) +#define PCIE1_QUADX1_EN (1<<8) + +/* ARM Configuration register */ +/* CPU_CONFIG_REG (CCR) */ + +/* Reset vector location */ +#define CCR_VEC_INIT_LOC_OFFS 1 +#define CCR_VEC_INIT_LOC_MASK (1 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0x00000000 */ +#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0xFFFF0000 */ +#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) + +#define CCR_ENDIAN_INIT_OFFS 3 +#define CCR_ENDIAN_INIT_MASK (1 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) + +#define CCR_ARM_ID_SEL_OFFS 4 +#define CCR_CPU_ID_SEL_MASK (1 << CCR_ARM_ID_SEL_OFFS) +#define CCR_CPU_ID_SEL_ARM (0 << CCR_ARM_ID_SEL_OFFS) +#define CCR_CPU_ID_SEL_MRVL (1 << CCR_ARM_ID_SEL_OFFS) + +#define CCR_TE_INIT_OFFS 5 +#define CCR_TE_INIT_MASK (1 << CCR_NCB_BLOCKING_OFFS) +#define CCR_TE_INIT_ARM (0 << CCR_NCB_BLOCKING_OFFS) +#define CCR_TE_INIT_THUMB (1 << CCR_NCB_BLOCKING_OFFS) + +#define CCR_NFMI_EN_OFFS 6 +#define CCR_NFMI_EN_MASK (1 << CCR_NFMI_EN_OFFS) +#define CCR_NFMI_EN_DIS (0 << CCR_NFMI_EN_OFFS) +#define CCR_NFMI_EN_EN (1 << CCR_NFMI_EN_OFFS) + +#define CCR_CORE_MODE_OFFS 9 +#define CCR_CORE_MODE_MASK (3 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_ARM1176 (0 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_CORTEX_A8 (1 << CCR_CORE_MODE_OFFS) +#define CCR_CORE_MODE_ARM11_MPC (2 << CCR_CORE_MODE_OFFS) + +#define CCR_UBIT_INIT_OFFS 11 +#define CCR_UBIT_INIT_MASK (1 << CCR_UBIT_INIT_OFFS) +#define CCR_UBIT_INIT_DIS (0 << CCR_UBIT_INIT_OFFS) +#define CCR_UBIT_INIT_EN (1 << CCR_UBIT_INIT_OFFS) + +#define CCR_PCLK_WFI_OFFS 15 +#define CCR_PCLK_WFI_MASK (1 << CCR_PCLK_WFI_OFFS) +#define CCR_PCLK_WFI_DIS (0 << CCR_PCLK_WFI_OFFS) +#define CCR_PCLK_WFI_EN (1 << CCR_PCLK_WFI_OFFS) + +#define CCR_SHARED_L2_OFFS 16 +#define CCR_SHARED_L2_MASK (1 << CCR_SHARED_L2_OFFS) +#define CCR_SHARED_L2_DIS (0 << CCR_SHARED_L2_OFFS) +#define CCR_SHARED_L2_EN (1 << CCR_SHARED_L2_OFFS) + +#define CCR_SP_IN_MP_OFFS 17 +#define CCR_SP_IN_MP_MASK (1 << CCR_SP_IN_MP_OFFS) +#define CCR_SP_IN_MP_DIS (0 << CCR_SP_IN_MP_OFFS) +#define CCR_SP_IN_MP_EN (1 << CCR_SP_IN_MP_OFFS) + +#define CCR_SRAM_LOW_LEAK_OFFS 19 +#define CCR_SRAM_LOW_LEAK_MASK (1 << CCR_SRAM_LOW_LEAK_OFFS) +#define CCR_SRAM_LOW_LEAK_EN (0 << CCR_SRAM_LOW_LEAK_OFFS) +#define CCR_SRAM_LOW_LEAK_DIS (1 << CCR_SRAM_LOW_LEAK_OFFS) + +#define CCR_CLUSTER_ID_OFFS 24 +#define CCR_CLUSTER_ID_MASK (0xF << CCR_SRAM_LOW_LEAK_OFFS) + + +/* ARM Control and Status register */ +/* CPU_CTRL_STAT_REG (CCSR) */ + +#define CCSR_SMP_N_AMP_OFFS 0 +#define CCSR_SMP_N_AMP_MASK (1 << CCSR_SMP_N_AMP_OFFS) + +#define CCSR_ENDIAN_STATUS_OFFS 15 +#define CCSR_ENDIAN_STATUS_MASK (1 << CCSR_ENDIAN_STATUS_OFFS) +#define CCSR_ENDIAN_STATUS_LITTLE (0 << CCSR_ENDIAN_STATUS_OFFS) +#define CCSR_ENDIAN_STATUS_BIG (1 << CCSR_ENDIAN_STATUS_OFFS) + + +/* RSTOUTn Mask Register */ +/* CPU_RSTOUTN_MASK_REG (CRMR) */ + +#define CRMR_SOFT_RST_OUT_OFFS 0 +#define CRMR_SOFT_RST_OUT_MASK (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_DISABLE (0 << CRMR_SOFT_RST_OUT_OFFS) + +#define CRMR_PEX_SYSRST_OUT_OFFS(bus) (1 + ((bus) & 0x3)) +#define CRMR_PEX_SYSRST_OUT_MASK(bus) (1 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) +#define CRMR_PEX_SYSRST_OUT_ENABLE(bus) (1 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) +#define CRMR_PEX_SYSRST_OUT_DISABLE(bus) (0 << CRMR_PEX_SYSRST_OUT_OFFS(bus)) + +#define CRMR_PEX_TRST_OUT_OFFS(bus) (5 + ((bus) & 0x3)) +#define CRMR_PEX_TRST_OUT_MASK(bus) (1 << CRMR_PEX_TRST_OUT_OFFS(bus)) +#define CRMR_PEX_TRST_OUT_ENABLE(bus) (1 << CRMR_PEX_TRST_OUT_OFFS(bus)) +#define CRMR_PEX_TRST_OUT_DISABLE(bus) (0 << CRMR_PEX_TRST_OUT_OFFS(bus)) + + +/* System Software Reset Register */ +/* CPU_SYS_SOFT_RST_REG (CSSRR) */ + +#define CSSRR_SYSTEM_SOFT_RST BIT0 + + +/* CPU_L2_CTRL_REG fields */ + +#define CL2CR_L2_EN_OFFS 0 +#define CL2CR_L2_EN_MASK (1 << CL2CR_L2_EN_OFFS) + +/* CPU_L2_AUX_CTRL_REG fields */ + +#define CL2ACR_WB_WT_ATTR_OFFS 0 +#define CL2ACR_WB_WT_ATTR_MASK (3 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_PAGE (0 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_WB (1 << CL2ACR_WB_WT_ATTR_OFFS) +#define CL2ACR_WB_WT_ATTR_WT (2 << CL2ACR_WB_WT_ATTR_OFFS) + +#define CL2ACR_PFU_OFFS 2 +#define CL2ACR_PFU_MASK (1 << CL2ACR_PFU_OFFS) +#define CL2ACR_PFU_EN (1 << CL2ACR_PFU_OFFS) +#define CL2ACR_PFU_DIS (0 << CL2ACR_PFU_OFFS) + +#define CL2ACR_L2_SIZE_OFFS 10 +#define CL2ACR_L2_SIZE_MASK (3 << CL2ACR_L2_SIZE_OFFS) +#define CL2ACR_L2_SIZE_KB(reg) ((((((reg) & 0x3) & CL2ACR_L2_SIZE_MASK) \ + >> CL2ACR_PFU_OFFS) + 1) * _512K) + +#define CL2ACR_ASSOC_OFFS 13 +#define CL2ACR_ASSOC_MASK (0xF << CL2ACR_ASSOC_OFFS) + +#define CL2ACR_L2_WAY_SZ_OFFS 17 +#define CL2ACR_L2_WAY_SZ_MASK (7 << CL2ACR_L2_WAY_SZ_OFFS) +#define CL2ACR_L2_WAY_SZ_KB(reg) (_16K << (((((reg) & 0x7) & CL2ACR_L2_SIZE_MASK) \ + >> CL2ACR_L2_WAY_SZ_OFFS))) + +#define CL2ACR_ECC_OFFS 20 +#define CL2ACR_ECC_MASK (1 << CL2ACR_ECC_OFFS) +#define CL2ACR_ECC_EN (1 << CL2ACR_ECC_OFFS) +#define CL2ACR_ECC_DIS (0 << CL2ACR_ECC_OFFS) + +#define CL2ACR_PARITY_OFFS 21 +#define CL2ACR_PARITY_MASK (1 << CL2ACR_PARITY_OFFS) +#define CL2ACR_PARITY_EN (1 << CL2ACR_PARITY_OFFS) +#define CL2ACR_PARITY_DIS (0 << CL2ACR_PARITY_OFFS) + +#define CL2ACR_INVAL_UCE_OFFS 22 +#define CL2ACR_INVAL_UCE_MASK (1 << CL2ACR_INVAL_UCE_OFFS) +#define CL2ACR_INVAL_UCE_EN (1 << CL2ACR_INVAL_UCE_OFFS) +#define CL2ACR_INVAL_UCE_DIS (0 << CL2ACR_INVAL_UCE_OFFS) + +#define CL2ACR_FORCE_WA_OFFS 23 +#define CL2ACR_FORCE_WA_MASK (3 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_WA_DISABLE (0 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_NO_WA (1 << CL2ACR_FORCE_WA_OFFS) +#define CL2ACR_FORCE_WA (2 << CL2ACR_FORCE_WA_OFFS) + +#define CL2ACR_REP_STRGY_OFFS 27 +#define CL2ACR_REP_STRGY_MASK (3 << CL2ACR_REP_STRGY_OFFS) + +#define CL2ACR_REP_STRGY_LFSR_MASK (0x1 << CL2ACR_REP_STRGY_OFFS) +#define CL2ACR_REP_STRGY_semiPLRU_MASK (0x2 << CL2ACR_REP_STRGY_OFFS) +#define CL2ACR_REP_STRGY_semiPLRU_WA_MASK (0x3 << CL2ACR_REP_STRGY_OFFS) +#define CL2_DUAL_EVICTION (0x1 << 4) +#define CL2_PARITY_ENABLE (0x1 << 21) +#define CL2_InvalEvicLineUCErr (0x1 << 22) + +/* SOC_CTRL_REG fields */ +#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3) +#define SCR_PEX_ENA_MASK(pex) (1 << pex) + +#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7) +#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex)) + +#define SCR_PEX0_4BY1_OFFS 7 +#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS) + +#define SCR_PEX1_4BY1_OFFS 8 +#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS) + +#define PCIE1_CLK_OUT_EN_OFF 5 +#define PCIE1_CLK_OUT_EN_MASK (1 << PCIE1_CLK_OUT_EN_OFF) + +#define PCIE0_CLK_OUT_EN_OFF 4 +#define PCIE0_CLK_OUT_EN_MASK (1 << PCIE0_CLK_OUT_EN_OFF) + +/* LVDS_PADS_CTRL_REG fields */ +#define LVDS_PADS_CONF_PD_OFFS(idx) (16 + idx) +#define LVDS_PADS_CONF_PD_MASK(idx) (1 << (16 + idx)) +#define LVDS_PADS_CONF_PD_EN(idx, en) ((en ? 0 : 1) << LVDS_PADS_CONF_PD_OFFS(idx)) + + +/*******************************************/ +/* Main Interrupt Controller Registers Map */ +/*******************************************/ + +#define CPU_MAIN_INT_CAUSE_REG(vec, cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x80 + (vec * 0x4)) +#define CPU_MAIN_INT_TWSI_OFFS(i) (2 + i) +#define CPU_MAIN_INT_CAUSE_TWSI(i) (31 + i) + +#define CPU_CF_LOCAL_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0xc4) +#define CPU_CF_LOCAL_MASK_PMU_MASK_OFFS 18 +#define CPU_INT_SOURCE_CONTROL_REG(i) (MV_CPUIF_SHARED_REGS_BASE + 0xB00 + (i * 0x4)) + +#define CPU_INT_SOURCE_CONTROL_IRQ_OFFS 28 +#define CPU_INT_SOURCE_CONTROL_IRQ_MASK (1 << CPU_INT_SOURCE_CONTROL_IRQ_OFFS ) + +#define CPU_INT_SET_ENABLE_REG (MV_CPUIF_SHARED_REGS_BASE + 0xA30) +#define CPU_INT_CLEAR_ENABLE_REG (MV_CPUIF_SHARED_REGS_BASE + 0xA34) + +#define CPU_INT_SET_MASK_OFFS (0xB8) +#define CPU_INT_CLEAR_MASK_OFFS (0xBC) + +#define CPU_INT_SET_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + CPU_INT_SET_MASK_OFFS) +#define CPU_INT_CLEAR_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + CPU_INT_CLEAR_MASK_OFFS) + +#define CPU_INT_SET_MASK_LOCAL_REG (MV_CPUIF_LOCAL_REGS_OFFSET + CPU_INT_SET_MASK_OFFS) +#define CPU_INT_CLEAR_MASK_LOCAL_REG (MV_CPUIF_LOCAL_REGS_OFFSET + CPU_INT_CLEAR_MASK_OFFS) + +#define CPU_SNOOP_FILTER_CTRL_REG (MV_CPUIF_LOCAL_REGS_OFFSET + 0x20) + +#define MV_IRQ_NR 116 + + +/*******************************************/ +/* ARM Doorbell Registers Map */ +/*******************************************/ +#define CPU_SW_TRIG_IRQ (MV_MBUS_REGS_OFFSET + 0xA04) +#define CPU_DOORBELL_IN_REG (MV_CPUIF_LOCAL_REGS_OFFSET + 0x78) +#define CPU_DOORBELL_IN_MASK_REG (MV_CPUIF_LOCAL_REGS_OFFSET + 0x7C) +#define CPU_HOST_TO_ARM_DRBL_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x78) +#define CPU_HOST_TO_ARM_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x7C) +#define CPU_ARM_TO_HOST_DRBL_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x70) +#define CPU_ARM_TO_HOST_MASK_REG(cpu) (MV_CPUIF_REGS_BASE(cpu) + 0x74) + +/*******************************************/ +/* CLOCK Complex Registers Map */ +/*******************************************/ + +#define CPU_DIV_CLK_CTRL0_REG (MV_CLK_CMPLX_REGS_OFFSET) +#define CPU_DIV_CLK_CTRL0_RESET_MASK_OFFS 8 +#define CPU_DIV_CLK_CTRL2_RATIO_FULL0_REG (MV_CLK_CMPLX_REGS_OFFSET + 0x8) +#define CPU_DIV_CLK_CTRL2_NB_RATIO_OFFS 16 +#define CPU_DIV_CLK_CTRL3_RATIO_FULL1_REG (MV_CLK_CMPLX_REGS_OFFSET + 0xC) +#define CPU_DIV_CLK_CTRL3_CPU_RATIO_OFFS 8 + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK) +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) + + +#endif /* __INCmvCpuIfRegsh */ + diff --git a/arch/arm/mach-armadaxp/armada_xp_family/device/mvDevice.c b/arch/arm/mach-armadaxp/armada_xp_family/device/mvDevice.c new file mode 100755 index 000000000..74c7f27dd --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/device/mvDevice.c @@ -0,0 +1,291 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "device/mvDevice.h" + +/* defines */ +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/******************************************************************************* +* mvDevPramSet - Set device interface bank parameters +* +* DESCRIPTION: +* This function sets a device bank parameters to a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* *pDevParams - Device bank parameter struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + } + if (pDevParams->turnOff > MAX_DBP_TURNOFF) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->turnOff out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2First > MAX_DBP_ACC2FIRST) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2First out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2Next > MAX_DBP_ACC2NEXT) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2Next out of range\n")); + return MV_ERROR; + } + if (pDevParams->ale2Wr > MAX_DBP_ALE2WR) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrLow > MAX_DBP_WRLOW) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrHigh > MAX_DBP_WRHIGH) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if ((pDevParams->badrSkew << DBP_BADRSKEW_OFFS) > DBP_BADRSKEW_2CYCLE) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->badrSkew out of range\n")); + return MV_ERROR; + } + if ((pDevParams->deviceWidth != 8) && (pDevParams->deviceWidth != 16) && (pDevParams->deviceWidth != 32)) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth out of range\n")); + return MV_ERROR; + } + + /* devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); */ + /* setting values */ + devParam |= DBP_TURNOFF_SET(pDevParams->turnOff); + devParam |= DBP_ACC2FIRST_SET(pDevParams->acc2First); + devParam |= DBP_ACC2NEXT_SET(pDevParams->acc2Next); + devParam |= ((pDevParams->badrSkew & DBP_BADRSKEW_MASK) << DBP_BADRSKEW_OFFS); + + switch (pDevParams->deviceWidth) { + case 8: + devParam |= DBP_DEVWIDTH_8BIT; + break; + case 16: + devParam |= DBP_DEVWIDTH_16BIT; + break; + case 32: + devParam |= DBP_DEVWIDTH_32BIT; + break; + default: + return MV_ERROR; + } + + MV_REG_WRITE(DEV_BANK_PARAM_REG(device), devParam); + + devParam = 0; + devParam |= DBP_ALE2WR_SET(pDevParams->ale2Wr); + devParam |= DBP_WRLOW_SET(pDevParams->wrLow); + devParam |= DBP_WRHIGH_SET(pDevParams->wrHigh); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(device), devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevPramget - Get device interface bank parameters +* +* DESCRIPTION: +* This function retrieves a device bank parameter settings. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* *pDevParams - Device bank parameter struct. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + pDevParams->turnOff = DBP_TURNOFF_GET(devParam); + pDevParams->acc2First = DBP_ACC2FIRST_GET(devParam); + pDevParams->acc2Next = DBP_ACC2NEXT_GET(devParam); + pDevParams->badrSkew = (devParam & DBP_BADRSKEW_MASK) >> DBP_BADRSKEW_OFFS; + + switch (devParam & DBP_DEVWIDTH_MASK) { + case DBP_DEVWIDTH_8BIT: + pDevParams->deviceWidth = 8; + break; + case DBP_DEVWIDTH_16BIT: + pDevParams->deviceWidth = 16; + break; + case DBP_DEVWIDTH_32BIT: + pDevParams->deviceWidth = 32; + break; + default: + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth non valid value\n")); + return MV_ERROR; + break; + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG_WR(device)); + pDevParams->ale2Wr = DBP_ALE2WR_GET(devParam); + pDevParams->wrLow = DBP_WRLOW_GET(devParam); + pDevParams->wrHigh = DBP_WRHIGH_GET(devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevWidthGet - Get device width parameter +* +* DESCRIPTION: +* This function gets width parameter of a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* Device width in bits (8,16,32...). +* +*******************************************************************************/ +MV_U32 mvDevWidthGet(MV_DEVICE device) +{ + MV_U32 devParam; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + devParam = (devParam & DBP_DEVWIDTH_MASK) >> DBP_DEVWIDTH_OFFS; + + return (MV_U32) (0x8 << devParam); + +} + +/******************************************************************************* +* mvDevNandDevCsSet - Set NAND chip-select, care mode and init sequence +* +* DESCRIPTION: +* This function set the NAND flash controller registers with NAND +* device chip-select. +* +* INPUT: +* devNum - Device number. See MV_DEVICE enumerator. +* careMode - NAND device care mode (0 = Don't care, '1' = care). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode) +{ + MV_U32 nfCtrlReg; /* NAND Flash Control Register */ + + /* Set chip select */ + nfCtrlReg = MV_REG_READ(DEV_NAND_CTRL_REG); + + nfCtrlReg |= (DINFCR_NF_CS_MASK(device)); + + if (careMode) + nfCtrlReg |= (DINFCR_NF_ACT_CE_MASK(device)); + else + nfCtrlReg &= ~(DINFCR_NF_ACT_CE_MASK(device)); + + MV_REG_WRITE(DEV_NAND_CTRL_REG, nfCtrlReg); +} diff --git a/arch/arm/mach-armadaxp/armada_xp_family/device/mvDevice.h b/arch/arm/mach-armadaxp/armada_xp_family/device/mvDevice.h new file mode 100755 index 000000000..2f7d33f12 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/device/mvDevice.h @@ -0,0 +1,99 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceH +#define __INCmvDeviceH + +#include "device/mvDeviceRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* This structure describes device interface parameters to be assigned to */ +/* device bank parameter */ +typedef struct _mvDeviceParam { + /* boundary values */ + MV_U32 turnOff; /* 0x0 - 0xf */ + MV_U32 acc2First; /* 0x0 - 0x1f */ + MV_U32 acc2Next; /* 0x0 - 0x1f */ + MV_U32 ale2Wr; /* 0x0 - 0xf */ + MV_U32 wrLow; /* 0x0 - 0xf */ + MV_U32 wrHigh; /* 0x0 - 0xf */ + MV_U32 badrSkew; /* 0x0 - 0x2 */ + MV_U32 deviceWidth; /* in Bytes */ +} MV_DEVICE_PARAM; + + +/* mvDevPramSet - Set device interface bank parameters */ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevPramget - Get device interface bank parameters */ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevWidthGet - Get device width parameter*/ +MV_U32 mvDevWidthGet(MV_DEVICE device); + +/* mvDevNandDevCsSet - Set the NAND flash control registers with NAND device- */ +/* select and care mode */ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode); + +#endif /* #ifndef __INCmvDeviceH */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/device/mvDeviceRegs.h b/arch/arm/mach-armadaxp/armada_xp_family/device/mvDeviceRegs.h new file mode 100755 index 000000000..25fea91a5 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/device/mvDeviceRegs.h @@ -0,0 +1,270 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceRegsH +#define __INCmvDeviceRegsH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_DEVICE_MAX_XBAR_TIMEOUT 0x0FFF +/* TODO - usage of DEV_BANK_PARAM_REG_DV is unclear */ +/* #define DEV_BANK_PARAM_REG_DV 0x80000000 */ +/* registers offsets */ + +static INLINE MV_U32 DEV_BANK_PARAM_REG(int num) +{ + switch (num) { + case (DEV_BOOCS): + return MV_DEV_BUS_REGS_OFFSET + 0x00; + case (DEVICE_CS0): + return MV_DEV_BUS_REGS_OFFSET + 0x08; + case (DEVICE_CS1): + return MV_DEV_BUS_REGS_OFFSET + 0x10; +#ifdef MV_INCLUDE_DEVICE_CS2 + case (DEVICE_CS2): + return MV_DEV_BUS_REGS_OFFSET + 0x18; +#endif +#ifdef MV_INCLUDE_DEVICE_CS3 + case (DEVICE_CS3): + return MV_DEV_BUS_REGS_OFFSET + 0x20; +#endif + default: + return 0xFFFFFFFF; + } +} + +#define DEV_BANK_PARAM_REG_WR(num) (DEV_BANK_PARAM_REG(num)+0x4) +#define DEV_NAND_CTRL_REG (MV_DEV_BUS_REGS_OFFSET + 0x0470) +#define DEV_BUS_SYNC_CTRL (MV_DEV_BUS_REGS_OFFSET + 0xC8) + +/* Device Bank Parameters register fields (DBP_REG)*/ +/* Boot Device Bank Parameters (DBP) register fields (DEV_BOOT_BANK_PARAM_REG)*/ +/* DBP_XXX_MASK_HIGH is the offset of the extend bit from the msb of the input value */ + +#define DBP_TURNOFF_OFFS_LOW 0 +#define DBP_TURNOFF_MASK_LOW 0x3F +#define MAX_DBP_TURNOFF 0xf + + +#define DBP_TURNOFF_SET(value) \ +((value & DBP_TURNOFF_MASK_LOW) << DBP_TURNOFF_OFFS_LOW) + +#define DBP_TURNOFF_GET(value) \ +((value >> DBP_TURNOFF_OFFS_LOW) & DBP_TURNOFF_MASK_LOW) + +#define DBP_ACC2FIRST_OFFS_LOW 6 +#define DBP_ACC2FIRST_MASK_LOW 0x3f +#define MAX_DBP_ACC2FIRST 0x3f + +#define DBP_ACC2FIRST_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2FIRST_GET(value) \ +((value >> DBP_ACC2FIRST_OFFS_LOW) & DBP_ACC2FIRST_MASK_LOW) + +#define DBP_ACC2NEXT_OFFS_LOW 17 +#define DBP_ACC2NEXT_MASK_LOW 0x3f +#define MAX_DBP_ACC2NEXT 0x3f + +#define DBP_ACC2NEXT_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2NEXT_GET(value) \ +((value >> DBP_ACC2NEXT_OFFS_LOW) & DBP_ACC2NEXT_MASK_LOW) + +#define DBP_DEVWIDTH_OFFS 30 /* Device Width */ +#define DBP_DEVWIDTH_MASK (0x3 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_8BIT (0x0 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_16BIT (0x1 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_32BIT (0x2 << DBP_DEVWIDTH_OFFS) + +#define DBP_BADRSKEW_OFFS 28 +#define DBP_BADRSKEW_MASK (0x3 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_NOGAP (0x0 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_1CYCLE (0x1 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_2CYCLE (0x2 << DBP_BADRSKEW_OFFS) + + +#define DBP_ALE2WR_OFFS_LOW 0 +#define DBP_ALE2WR_MASK_LOW 0x3f +#define MAX_DBP_ALE2WR 0x3F + +#define DBP_ALE2WR_SET(value) \ +((value & DBP_ALE2WR_MASK_LOW) << DBP_ALE2WR_OFFS_LOW) + +#define DBP_ALE2WR_GET(value) \ +((value >> DBP_ALE2WR_OFFS_LOW) & DBP_ALE2WR_MASK_LOW) + +#define DBP_WRLOW_OFFS_LOW 8 +#define DBP_WRLOW_MASK_LOW 0x3F +#define MAX_DBP_WRLOW 0x3F + +#define DBP_WRLOW_SET(value) \ +((value & DBP_WRLOW_MASK_LOW) << DBP_WRLOW_OFFS_LOW) + +#define DBP_WRLOW_GET(value) \ +((value >> DBP_WRLOW_OFFS_LOW) & DBP_WRLOW_MASK_LOW) + +#define DBP_WRHIGH_OFFS_LOW 16 +#define DBP_WRHIGH_MASK_LOW 0x3F +#define MAX_DBP_WRHIGH 0x3F + +#define DBP_WRHIGH_SET(value) \ +((value & DBP_WRHIGH_MASK_LOW) << DBP_WRHIGH_OFFS_LOW) + +#define DBP_WRHIGH_GET(value) \ +((value >> DBP_WRHIGH_OFFS_LOW) & DBP_WRHIGH_MASK_LOW) + + +/* Device Interface Control register fields (DIC) (DIC_REG)*/ +#define DIC_TIMEOUT_OFFS 0 /* Timeout Timer Preset Value. */ +#define DIC_TIMEOUT_MASK (0xffff << DIC_TIMEOUT_OFFS) +#define MAX_DIC_TIMEOUT 0xffff + +/* NAND Flash Control register fields (NF) (NF_REG)*/ +#define NF_BOOTCS_OFFS 0 /* Define if BOOTCS is connected to NAND Flash */ +#define NF_BOOT_MASK (1 << NF_BOOTCS_OFFS) +#define NF_BOOT_NC (0 << NF_BOOTCS_OFFS) +#define NF_BOOT_C (1 << NF_BOOTCS_OFFS) + +#define NF_BOOTCS_CE_ACT_OFFS 1 /* Define if NAND Flash on BOOTCS is CE care or CE don't care */ +#define NF_BOOTCS_CE_ACT_MASK (1 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_NCARE (0 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_CARE (1 << NF_BOOTCS_CE_ACT_OFFS) + +#define NF_CS0_OFFS 2 /* Define if CS0 is connected to NAND Flash */ +#define NF_CS0_MASK (1 << NF_CS0_OFFS) +#define NF_CS0_NC (0 << NF_CS0_OFFS) +#define NF_CS0_C (1 << NF_CS0_OFFS) + +#define NF_CS0_CE_ACT_OFFS 3 /* Define if NAND Flash on CS0 is CE care or CE don't care */ +#define NF_CS0_CE_ACT_MASK (1 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_NCARE (0 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_CARE (1 << NF_CS0_CE_ACT_OFFS) + +#define NF_CS1_OFFS 4 /* Define if CS1 is connected to NAND Flash */ +#define NF_CS1_MASK (1 << NF_CS1_OFFS) +#define NF_CS1_NC (0 << NF_CS1_OFFS) +#define NF_CS1_C (1 << NF_CS1_OFFS) + +#define NF_CS1_CE_ACT_OFFS 5 /* Define if NAND Flash on CS1 is CE care or CE don't care */ +#define NF_CS1_CE_ACT_MASK (1 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_NCARE (0 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_CARE (1 << NF_CS1_CE_ACT_OFFS) + +#define NF_CS2_OFFS 6 /* Define if CS2 is connected to NAND Flash */ +#define NF_CS2_MASK (1 << NF_CS2_OFFS) +#define NF_CS2_NC (0 << NF_CS2_OFFS) +#define NF_CS2_C (1 << NF_CS2_OFFS) + +#define NF_CS2_CE_ACT_OFFS 7 /* Define if NAND Flash on CS2 is CE care or CE don't care */ +#define NF_CS2_CE_ACT_MASK (1 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_NCARE (0 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_CARE (1 << NF_CS2_CE_ACT_OFFS) + +#define NF_INIT_SEQ_OFFS 8 /* NAND Flash initialization sequence */ +#define NF_INIT_SEQ_MASK (1 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_EN (0 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_DIS (1 << NF_INIT_SEQ_OFFS) + +#define NF_OE_HIGHW_OFFS 9 /* NAND Flash OE high width in core clocks units (value + 1) */ +#define NF_OE_HIGHW_MASK (0x1f << NF_OE_HIGHW_OFFS) +#define MAX_OE_HIGHW (0x1f << NF_OE_HIGHW_OFFS) + +#define NF_TREADY_OFFS 14 /* NAND Flash time ready in core clocks units (value + 1) */ +#define NF_TREADY_MASK (0x1f << NF_TREADY_OFFS) +#define MAX_TREADY (0x1f << NF_TREADY_OFFS) + +#define NF_OE_TCTRL_OFFS 19 /* NAND Flash OE toggle control */ +#define NF_OE_TCTRL_MASK (1 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_1_CYC_AFT (0 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_SAME_CYC (1 << NF_OE_TCTRL_OFFS) + +#define NF_CS3_OFFS 20 /* Define if CS3 is connected to NAND Flash */ +#define NF_CS3_MASK (1 << NF_CS3_OFFS) +#define NF_CS3_NC (0 << NF_CS3_OFFS) +#define NF_CS3_C (1 << NF_CS3_OFFS) + +#define NF_CS3_CE_ACT_OFFS 21 /* Define if NAND Flash on CS3 is CE care or CE don't care */ +#define NF_CS3_CE_ACT_MASK (1 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_NCARE (0 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_CARE (1 << NF_CS3_CE_ACT_OFFS) + + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) \ +(csNum == BOOT_CS) ? 0x1 : ((csNum == DEV_CS3) ? (0x1 << 20) : (0x1 << (((csNum+1) % MV_DEV_MAX_CS) * 2))) + + +#define DINFCR_NF_ACT_CE_MASK(csNum) \ +(csNum == DEV_CS3) ? (0x2 << 20) : (0x2 << (((csNum+1) % MV_DEV_MAX_CS) * 2)) + +#define NAND_ACTCEBOOT_BIT BIT1 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #ifndef __INCmvDeviceRegsH */ diff --git a/arch/arm/mach-armadaxp/armada_xp_family/version.txt b/arch/arm/mach-armadaxp/armada_xp_family/version.txt new file mode 100755 index 000000000..0a33871d1 --- /dev/null +++ b/arch/arm/mach-armadaxp/armada_xp_family/version.txt @@ -0,0 +1 @@ +2013_Q1.0 diff --git a/arch/arm/mach-armadaxp/btns_dev.h b/arch/arm/mach-armadaxp/btns_dev.h new file mode 100755 index 000000000..a4d325c7f --- /dev/null +++ b/arch/arm/mach-armadaxp/btns_dev.h @@ -0,0 +1,27 @@ +/******************************************************************************* +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ + +#ifndef _BTNS_DEV_H_ +#define _BTNS_DEV_H_ + +#define TEST_GPP 41 + +struct btns_platform_data { + unsigned int btns_num; + struct btn_data *btns_data_arr; +}; + +#endif /* _BTNS_DEV_H_ */ diff --git a/arch/arm/mach-armadaxp/btns_device.c b/arch/arm/mach-armadaxp/btns_device.c new file mode 100755 index 000000000..3d6d2f59b --- /dev/null +++ b/arch/arm/mach-armadaxp/btns_device.c @@ -0,0 +1,93 @@ +/****************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ +#include +#include +#include "../plat-armada/mv_drivers_lsp/mv_btns/btns_driver.h" +#include "btns_dev.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* + * common debug for all + */ +#undef DEBUG + +#ifdef DEBUG +#define dprintk printk +#else +#define dprintk(a...) +#endif + +static struct btns_platform_data btns_data; +static struct btn_data btn_data_db[] = { + [0] = { + .gpp_id = TEST_GPP, + .default_gpp_val = 0x0, + .btn_op = BTN_PUSH, + .btn_name = "TEST", + } +}; + +static struct platform_device btns_device = { + .name = MV_BTNS_NAME, + .id = 0, + .num_resources = 0, + .dev = { + .platform_data = &btns_data, + }, +}; + +static int btns_init_data(struct platform_device *pdev) +{ + dprintk("%s - ArmadaXP board\n", __func__); + btns_data.btns_data_arr = btn_data_db; + btns_data.btns_num = (btns_data.btns_data_arr == NULL) ? + 0 : ARRAY_SIZE(btn_data_db); + + if (btns_data.btns_num) + dprintk("%s - Number of configured buttons: %d\n", + __func__, btns_data.btns_num); + + return 0; +} + +static int __init mv_btns_init(void) +{ + int status; + + printk(KERN_NOTICE "MV Buttons Device Load\n"); + + /* Initialize btns related structures and data*/ + status = btns_init_data(&btns_device); + if (status) { + printk(KERN_WARNING + "Can't initialize Marvell Buttons Data, status=%d\n", + status); + return status; + } + + /* register device */ + status = platform_device_register(&btns_device); + if (status) { + printk(KERN_WARNING + "Can't register Marvell Buttons Device, status=%d\n", + status); + return status; + } + + return 0; +} + +subsys_initcall(mv_btns_init); diff --git a/arch/arm/mach-armadaxp/clcd.c b/arch/arm/mach-armadaxp/clcd.c new file mode 100755 index 000000000..dac86ceb3 --- /dev/null +++ b/arch/arm/mach-armadaxp/clcd.c @@ -0,0 +1,557 @@ +/* + * linux/arch/arm/mach-dove/clcd.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* HZ */ +#include + +#include +#include +#include +#include +#include +#include