/*

* Copyright (C) 2013 Cisco Systems, Inc. All rights reserved.

* Copyright (C) 2009-2011 STMicroelectronics. All rights reserved.

* Copyright (C) 2008 Apple Inc. All rights reserved.

*

* Redistribution and use in source and binary forms, with or without

* modification, are permitted provided that the following conditions

* are met:

* 1. Redistributions of source code must retain the above copyright

* notice, this list of conditions and the following disclaimer.

* 2. Redistributions in binary form must reproduce the above copyright

* notice, this list of conditions and the following disclaimer in the

* documentation and/or other materials provided with the distribution.

*

* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR

* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*/

#ifndef MacroAssemblerSH4_h

#define MacroAssemblerSH4_h

#if ENABLE(ASSEMBLER) && CPU(SH4)

#include "SH4Assembler.h"

#include "AbstractMacroAssembler.h"

#include <wtf/Assertions.h>

namespace JSC {

class MacroAssemblerSH4 : public AbstractMacroAssembler<SH4Assembler> {

public:

typedef SH4Assembler::FPRegisterID FPRegisterID;

static const Scale ScalePtr = TimesFour;

static const FPRegisterID fscratch = SH4Registers::dr10;

static const RegisterID stackPointerRegister = SH4Registers::sp;

static const RegisterID framePointerRegister = SH4Registers::fp;

static const RegisterID linkRegister = SH4Registers::pr;

static const RegisterID scratchReg3 = SH4Registers::r13;

static const int MaximumCompactPtrAlignedAddressOffset = 60;

static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)

{

return (value >= 0) && (value <= MaximumCompactPtrAlignedAddressOffset) && (!(value & 3));

}

enum RelationalCondition {

Equal = SH4Assembler::EQ,

NotEqual = SH4Assembler::NE,

Above = SH4Assembler::HI,

AboveOrEqual = SH4Assembler::HS,

Below = SH4Assembler::LI,

BelowOrEqual = SH4Assembler::LS,

GreaterThan = SH4Assembler::GT,

GreaterThanOrEqual = SH4Assembler::GE,

LessThan = SH4Assembler::LT,

LessThanOrEqual = SH4Assembler::LE

};

enum ResultCondition {

Overflow = SH4Assembler::OF,

Signed = SH4Assembler::SI,

PositiveOrZero = SH4Assembler::NS,

Zero = SH4Assembler::EQ,

NonZero = SH4Assembler::NE

};

enum DoubleCondition {

// These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.

DoubleEqual = SH4Assembler::EQ,

DoubleNotEqual = SH4Assembler::NE,

DoubleGreaterThan = SH4Assembler::GT,

DoubleGreaterThanOrEqual = SH4Assembler::GE,

DoubleLessThan = SH4Assembler::LT,

DoubleLessThanOrEqual = SH4Assembler::LE,

// If either operand is NaN, these conditions always evaluate to true.

DoubleEqualOrUnordered = SH4Assembler::EQU,

DoubleNotEqualOrUnordered = SH4Assembler::NEU,

DoubleGreaterThanOrUnordered = SH4Assembler::GTU,

DoubleGreaterThanOrEqualOrUnordered = SH4Assembler::GEU,

DoubleLessThanOrUnordered = SH4Assembler::LTU,

DoubleLessThanOrEqualOrUnordered = SH4Assembler::LEU,

};

RegisterID claimScratch()

{

return m_assembler.claimScratch();

}

void releaseScratch(RegisterID reg)

{

m_assembler.releaseScratch(reg);

}

static RelationalCondition invert(RelationalCondition cond)

{

switch (cond) {

case Equal:

return NotEqual;

case NotEqual:

return Equal;

case Above:

return BelowOrEqual;

case AboveOrEqual:

return Below;

case Below:

return AboveOrEqual;

case BelowOrEqual:

return Above;

case GreaterThan:

return LessThanOrEqual;

case GreaterThanOrEqual:

return LessThan;

case LessThan:

return GreaterThanOrEqual;

case LessThanOrEqual:

return GreaterThan;

default:

RELEASE_ASSERT_NOT_REACHED();

}

}

// Integer arithmetic operations

void add32(RegisterID src, RegisterID dest)

{

m_assembler.addlRegReg(src, dest);

}

void add32(RegisterID src1, RegisterID src2, RegisterID dest)

{

if (src1 == dest)

add32(src2, dest);

else {

move(src2, dest);

add32(src1, dest);

}

}

void add32(TrustedImm32 imm, RegisterID dest)

{

if (!imm.m_value)

return;

if (m_assembler.isImmediate(imm.m_value)) {

m_assembler.addlImm8r(imm.m_value, dest);

return;

}

RegisterID scr = claimScratch();

m_assembler.loadConstant(imm.m_value, scr);

m_assembler.addlRegReg(scr, dest);

releaseScratch(scr);

}

void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

move(src, dest);

add32(imm, dest);

}

void add32(TrustedImm32 imm, Address address)

{

if (!imm.m_value)

return;

RegisterID scr = claimScratch();

load32(address, scr);

add32(imm, scr);

store32(scr, address);

releaseScratch(scr);

}

void add32(Address src, RegisterID dest)

{

RegisterID scr = claimScratch();

load32(src, scr);

m_assembler.addlRegReg(scr, dest);

releaseScratch(scr);

}

void add32(AbsoluteAddress src, RegisterID dest)

{

RegisterID scr = claimScratch();

load32(src.m_ptr, scr);

m_assembler.addlRegReg(scr, dest);

releaseScratch(scr);

}

void and32(RegisterID src, RegisterID dest)

{

m_assembler.andlRegReg(src, dest);

}

void and32(RegisterID src1, RegisterID src2, RegisterID dest)

{

if (src1 == dest)

and32(src2, dest);

else {

move(src2, dest);

and32(src1, dest);

}

}

void and32(Address src, RegisterID dest)

{

RegisterID scr = claimScratch();

load32(src, scr);

and32(scr, dest);

releaseScratch(scr);

}

void and32(TrustedImm32 imm, RegisterID dest)

{

if (!imm.m_value) {

m_assembler.movImm8(0, dest);

return;

}

if ((imm.m_value <= 255) && (imm.m_value >= 0) && (dest == SH4Registers::r0)) {

m_assembler.andlImm8r(imm.m_value, dest);

return;

}

RegisterID scr = claimScratch();

m_assembler.loadConstant(imm.m_value, scr);

m_assembler.andlRegReg(scr, dest);

releaseScratch(scr);

}

void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

if (src != dest) {

move(imm, dest);

and32(src, dest);

return;

}

and32(imm, dest);

}

void lshift32(RegisterID shiftamount, RegisterID dest)

{

RegisterID shiftTmp = claimScratch();

m_assembler.loadConstant(0x1f, shiftTmp);

m_assembler.andlRegReg(shiftamount, shiftTmp);

m_assembler.shldRegReg(dest, shiftTmp);

releaseScratch(shiftTmp);

}

void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)

{

move(src, dest);

lshift32(shiftAmount, dest);

}

void lshift32(TrustedImm32 imm, RegisterID dest)

{

int immMasked = imm.m_value & 0x1f;

if (!immMasked)

return;

if ((immMasked == 1) || (immMasked == 2) || (immMasked == 8) || (immMasked == 16)) {

m_assembler.shllImm8r(immMasked, dest);

return;

}

RegisterID shiftTmp = claimScratch();

m_assembler.loadConstant(immMasked, shiftTmp);

m_assembler.shldRegReg(dest, shiftTmp);

releaseScratch(shiftTmp);

}

void lshift32(RegisterID src, TrustedImm32 shiftamount, RegisterID dest)

{

move(src, dest);

lshift32(shiftamount, dest);

}

void mul32(RegisterID src, RegisterID dest)

{

mul32(src, dest, dest);

}

void mul32(RegisterID src1, RegisterID src2, RegisterID dest)

{

m_assembler.imullRegReg(src1, src2);

m_assembler.stsmacl(dest);

}

void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

if (src == dest) {

RegisterID immval = claimScratch();

move(imm, immval);

mul32(immval, dest);

releaseScratch(immval);

} else {

move(imm, dest);

mul32(src, dest);

}

}

void or32(RegisterID src, RegisterID dest)

{

m_assembler.orlRegReg(src, dest);

}

void or32(TrustedImm32 imm, RegisterID dest)

{

if ((imm.m_value <= 255) && (imm.m_value >= 0) && (dest == SH4Registers::r0)) {

m_assembler.orlImm8r(imm.m_value, dest);

return;

}

RegisterID scr = claimScratch();

m_assembler.loadConstant(imm.m_value, scr);

m_assembler.orlRegReg(scr, dest);

releaseScratch(scr);

}

void or32(RegisterID op1, RegisterID op2, RegisterID dest)

{

if (op1 == op2)

move(op1, dest);

else if (op1 == dest)

or32(op2, dest);

else {

move(op2, dest);

or32(op1, dest);

}

}

void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

if (src != dest) {

move(imm, dest);

or32(src, dest);

return;

}

or32(imm, dest);

}

void or32(RegisterID src, AbsoluteAddress address)

{

RegisterID destptr = claimScratch();

move(TrustedImmPtr(address.m_ptr), destptr);

RegisterID destval = claimScratch();

m_assembler.movlMemReg(destptr, destval);

m_assembler.orlRegReg(src, destval);

m_assembler.movlRegMem(destval, destptr);

releaseScratch(destval);

releaseScratch(destptr);

}

void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

if (src != dest) {

move(imm, dest);

xor32(src, dest);

return;

}

xor32(imm, dest);

}

void rshift32(RegisterID shiftamount, RegisterID dest)

{

RegisterID shiftTmp = claimScratch();

m_assembler.loadConstant(0x1f, shiftTmp);

m_assembler.andlRegReg(shiftamount, shiftTmp);

m_assembler.neg(shiftTmp, shiftTmp);

m_assembler.shadRegReg(dest, shiftTmp);

releaseScratch(shiftTmp);

}

void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)

{

move(src, dest);

rshift32(shiftAmount, dest);

}

void rshift32(TrustedImm32 imm, RegisterID dest)

{

int immMasked = imm.m_value & 0x1f;

if (!immMasked)

return;

if (immMasked == 1) {

m_assembler.sharImm8r(immMasked, dest);

return;

}

RegisterID shiftTmp = claimScratch();

m_assembler.loadConstant(-immMasked, shiftTmp);

m_assembler.shadRegReg(dest, shiftTmp);

releaseScratch(shiftTmp);

}

void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)

{

move(src, dest);

rshift32(imm, dest);

}

void sub32(RegisterID src, RegisterID dest)

{

m_assembler.sublRegReg(src, dest);

}

void sub32(TrustedImm32 imm, AbsoluteAddress address)

{

if (!imm.m_value)

return;

RegisterID result = claimScratch();

RegisterID scratchReg = claimScratch();

move(TrustedImmPtr(address.m_ptr), scratchReg);

m_assembler.movlMemReg(scratchReg, result);

if (m_assembler.isImmediate(-imm.m_value))

m_assembler.addlImm8r(-imm.m_value, result);

else {

m_assembler.loadConstant(imm.m_value, scratchReg3);

m_assembler.sublRegReg(scratchReg3, result);

}

store32(result, scratchReg);

releaseScratch(result);

releaseScratch(scratchReg);

}

void sub32(TrustedImm32 imm, Address address)

{

add32(TrustedImm32(-imm.m_value), address);

}

void add32(TrustedImm32 imm, AbsoluteAddress address)

{

if (!imm.m_value)

return;

RegisterID result = claimScratch();

RegisterID scratchReg = claimScratch();

move(TrustedImmPtr(address.m_ptr), scratchReg);

m_assembler.movlMemReg(scratchReg, result);

if (m_assembler.isImmediate(imm.m_value))

m_assembler.addlImm8r(imm.m_value, result);

else {

m_assembler.loadConstant(imm.m_value, scratchReg3);

m_assembler.addlRegReg(scratchReg3, result);

}

store32(result, scratchReg);

releaseScratch(result);

releaseScratch(scratchReg);

}

void add64(TrustedImm32 imm, AbsoluteAddress address)

{

RegisterID scr1 = claimScratch();

RegisterID scr2 = claimScratch();

// Add 32-bit LSB first.

move(TrustedImmPtr(address.m_ptr), scratchReg3);

m_assembler.movlMemReg(scratchReg3, scr1); // scr1 = 32-bit LSB of int64 @ address

m_assembler.loadConstant(imm.m_value, scr2);

m_assembler.clrt();

m_assembler.addclRegReg(scr1, scr2);

m_assembler.movlRegMem(scr2, scratchReg3); // Update address with 32-bit LSB result.

// Then add 32-bit MSB.

m_assembler.addlImm8r(4, scratchReg3);

m_assembler.movlMemReg(scratchReg3, scr1); // scr1 = 32-bit MSB of int64 @ address

m_assembler.movt(scr2);

if (imm.m_value < 0)

m_assembler.addlImm8r(-1, scr2); // Sign extend imm value if needed.

m_assembler.addvlRegReg(scr2, scr1);

m_assembler.movlRegMem(scr1, scratchReg3); // Update (address + 4) with 32-bit MSB result.

releaseScratch(scr2);

releaseScratch(scr1);

}

void sub32(TrustedImm32 imm, RegisterID dest)

{

if (!imm.m_value)

return;

if (m_assembler.isImmediate(-imm.m_value)) {

m_assembler.addlImm8r(-imm.m_value, dest);

return;

}

RegisterID scr = claimScratch();

m_assembler.loadConstant(imm.m_value, scr);

m_assembler.sublRegReg(scr, dest);

releaseScratch(scr);

}

void sub32(Address src, RegisterID dest)

{

RegisterID scr = claimScratch();

load32(src, scr);

m_assembler.sublRegReg(scr, dest);

releaseScratch(scr);

}

void xor32(RegisterID src, RegisterID dest)

{

m_assembler.xorlRegReg(src, dest);

}

void xor32(RegisterID src1, RegisterID src2, RegisterID dest)

{

if (src1 == dest)

xor32(src2, dest);

else {

move(src2, dest);

xor32(src1, dest);

}

}

void xor32(TrustedImm32 imm, RegisterID srcDest)

{

if (imm.m_value == -1) {

m_assembler.notlReg(srcDest, srcDest);

return;

}

if ((srcDest != SH4Registers::r0) || (imm.m_value > 255) || (imm.m_value < 0)) {

RegisterID scr = claimScratch();

m_assembler.loadConstant(imm.m_value, scr);

m_assembler.xorlRegReg(scr, srcDest);

releaseScratch(scr);

return;

}

m_assembler.xorlImm8r(imm.m_value, srcDest);

}

void compare32(int imm, RegisterID dst, RelationalCondition cond)

{

if (((cond == Equal) || (cond == NotEqual)) && (dst == SH4Registers::r0) && m_assembler.isImmediate(imm)) {

m_assembler.cmpEqImmR0(imm, dst);

return;

}

if (((cond == Equal) || (cond == NotEqual)) && !imm) {

m_assembler.testlRegReg(dst, dst);

return;

}

RegisterID scr = claimScratch();

m_assembler.loadConstant(imm, scr);

m_assembler.cmplRegReg(scr, dst, SH4Condition(cond));

releaseScratch(scr);

}

void compare32(int offset, RegisterID base, RegisterID left, RelationalCondition cond)

{

RegisterID scr = claimScratch();

if (!offset) {

m_assembler.movlMemReg(base, scr);

m_assembler.cmplRegReg(scr, left, SH4Condition(cond));

releaseScratch(scr);

return;

}

if ((offset < 0) || (offset >= 64)) {

m_assembler.loadConstant(offset, scr);

m_assembler.addlRegReg(base, scr);

m_assembler.movlMemReg(scr, scr);

m_assembler.cmplRegReg(scr, left, SH4Condition(cond));

releaseScratch(scr);

return;

}

m_assembler.movlMemReg(offset >> 2, base, scr);

m_assembler.cmplRegReg(scr, left, SH4Condition(cond));

releaseScratch(scr);

}

void testImm(int imm, int offset, RegisterID base)

{

RegisterID scr = claimScratch();

load32(base, offset, scr);

RegisterID scr1 = claimScratch();

move(TrustedImm32(imm), scr1);

m_assembler.testlRegReg(scr, scr1);

releaseScratch(scr);

releaseScratch(scr1);

}

void testlImm(int imm, RegisterID dst)

{

if ((dst == SH4Registers::r0) && (imm <= 255) && (imm >= 0)) {

m_assembler.testlImm8r(imm, dst);

return;

}

RegisterID scr = claimScratch();

m_assembler.loadConstant(imm, scr);

m_assembler.testlRegReg(scr, dst);

releaseScratch(scr);

}

void compare32(RegisterID right, int offset, RegisterID base, RelationalCondition cond)

{

if (!offset) {

RegisterID scr = claimScratch();

m_assembler.movlMemReg(base, scr);

m_assembler.cmplRegReg(right, scr, SH4Condition(cond));

releaseScratch(scr);

return;

}

if ((offset < 0) || (offset >= 64)) {

RegisterID scr = claimScratch();

m_assembler.loadConstant(offset, scr);

m_assembler.addlRegReg(base, scr);

m_assembler.movlMemReg(scr, scr);

m_assembler.cmplRegReg(right, scr, SH4Condition(cond));

releaseScratch(scr);

return;

}

RegisterID scr = claimScratch();

m_assembler.movlMemReg(offset >> 2, base, scr);

m_assembler.cmplRegReg(right, scr, SH4Condition(cond));

releaseScratch(scr);

}

void compare32(int imm, int offset, RegisterID base, RelationalCondition cond)

{

RegisterID scr = claimScratch();

load32(base, offset, scr);

RegisterID scr1 = claimScratch();

move(TrustedImm32(imm), scr1);

m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));

releaseScratch(scr1);

releaseScratch(scr);

}

// Memory access operation

ALWAYS_INLINE void loadEffectiveAddress(BaseIndex address, RegisterID dest, int extraoffset = 0)

{

if (dest == address.base) {

RegisterID scaledIndex = claimScratch();

move(address.index, scaledIndex);

lshift32(TrustedImm32(address.scale), scaledIndex);

add32(scaledIndex, dest);

releaseScratch(scaledIndex);

} else {

move(address.index, dest);

lshift32(TrustedImm32(address.scale), dest);

add32(address.base, dest);

}

add32(TrustedImm32(address.offset + extraoffset), dest);

}

void load32(ImplicitAddress address, RegisterID dest)

{

load32(address.base, address.offset, dest);

}

void load8(ImplicitAddress address, RegisterID dest)

{

load8(address.base, address.offset, dest);

}

void load8(BaseIndex address, RegisterID dest)

{

RegisterID scr = claimScratch();

move(address.index, scr);

lshift32(TrustedImm32(address.scale), scr);

add32(address.base, scr);

load8(scr, address.offset, dest);

releaseScratch(scr);

}

void load8(AbsoluteAddress address, RegisterID dest)

{

move(TrustedImmPtr(address.m_ptr), dest);

m_assembler.movbMemReg(dest, dest);

m_assembler.extub(dest, dest);

}

void load8(const void* address, RegisterID dest)

{

load8(AbsoluteAddress(address), dest);

}

void load8PostInc(RegisterID base, RegisterID dest)

{

m_assembler.movbMemRegIn(base, dest);

m_assembler.extub(dest, dest);

}

void load8Signed(BaseIndex address, RegisterID dest)

{

RegisterID scr = claimScratch();

move(address.index, scr);

lshift32(TrustedImm32(address.scale), scr);

add32(address.base, scr);

load8Signed(scr, address.offset, dest);

releaseScratch(scr);

}

void load32(BaseIndex address, RegisterID dest)

{

RegisterID scr = claimScratch();

move(address.index, scr);

lshift32(TrustedImm32(address.scale), scr);

add32(address.base, scr);

load32(scr, address.offset, dest);

releaseScratch(scr);

}

void load32(const void* address, RegisterID dest)

{

move(TrustedImmPtr(address), dest);

m_assembler.movlMemReg(dest, dest);

}

void load32(RegisterID base, int offset, RegisterID dest)

{

if (!offset) {

m_assembler.movlMemReg(base, dest);

return;

}

if ((offset >= 0) && (offset < 64)) {

m_assembler.movlMemReg(offset >> 2, base, dest);

return;

}

RegisterID scr = (dest == base) ? claimScratch() : dest;

m_assembler.loadConstant(offset, scr);

if (base == SH4Registers::r0)

m_assembler.movlR0mr(scr, dest);

else {

m_assembler.addlRegReg(base, scr);

m_assembler.movlMemReg(scr, dest);

}

if (dest == base)

releaseScratch(scr);

}

void load8Signed(RegisterID base, int offset, RegisterID dest)

{

if (!offset) {

m_assembler.movbMemReg(base, dest);

return;

}

if ((offset > 0) && (offset <= 15) && (dest == SH4Registers::r0)) {

m_assembler.movbMemReg(offset, base, dest);

return;

}

RegisterID scr = (dest == base) ? claimScratch() : dest;

m_assembler.loadConstant(offset, scr);

if (base == SH4Registers::r0)

m_assembler.movbR0mr(scr, dest);

else {

m_assembler.addlRegReg(base, scr);

m_assembler.movbMemReg(scr, dest);

}

if (dest == base)

releaseScratch(scr);

}

void load8(RegisterID base, int offset, RegisterID dest)

{

load8Signed(base, offset, dest);

m_assembler.extub(dest, dest);

}

void load32(RegisterID src, RegisterID dst)

{

m_assembler.movlMemReg(src, dst);

}

void load16(ImplicitAddress address, RegisterID dest)

{

if (!address.offset) {

m_assembler.movwMemReg(address.base, dest);

m_assembler.extuw(dest, dest);

return;

}

if ((address.offset > 0) && (address.offset <= 30) && (dest == SH4Registers::r0)) {

m_assembler.movwMemReg(address.offset >> 1, address.base, dest);

m_assembler.extuw(dest, dest);

return;

}

RegisterID scr = (dest == address.base) ? claimScratch() : dest;

m_assembler.loadConstant(address.offset, scr);

if (address.base == SH4Registers::r0)

m_assembler.movwR0mr(scr, dest);

else {

m_assembler.addlRegReg(address.base, scr);

m_assembler.movwMemReg(scr, dest);

}

m_assembler.extuw(dest, dest);

if (dest == address.base)

releaseScratch(scr);

}

void load16Unaligned(BaseIndex address, RegisterID dest)

{

RegisterID scr = claimScratch();

loadEffectiveAddress(address, scr);

RegisterID scr1 = claimScratch();

load8PostInc(scr, scr1);

load8(scr, dest);

m_assembler.shllImm8r(8, dest);

or32(scr1, dest);

releaseScratch(scr);

releaseScratch(scr1);

}

void load16(RegisterID src, RegisterID dest)

{

m_assembler.movwMemReg(src, dest);

m_assembler.extuw(dest, dest);

}

void load16Signed(RegisterID src, RegisterID dest)

{

m_assembler.movwMemReg(src, dest);

}

void load16(BaseIndex address, RegisterID dest)

{

load16Signed(address, dest);

m_assembler.extuw(dest, dest);

}

void load16PostInc(RegisterID base, RegisterID dest)

{

m_assembler.movwMemRegIn(base, dest);

m_assembler.extuw(dest, dest);

}

void load16Signed(BaseIndex address, RegisterID dest)

{

RegisterID scr = claimScratch();

move(address.index, scr);

lshift32(TrustedImm32(address.scale), scr);

add32(TrustedImm32(address.offset), scr);

if (address.base == SH4Registers::r0)

m_assembler.movwR0mr(scr, dest);

else {

add32(address.base, scr);

load16Signed(scr, dest);

}

releaseScratch(scr);

}

void store8(RegisterID src, BaseIndex address)

{

RegisterID scr = claimScratch();

move(address.index, scr);

lshift32(TrustedImm32(address.scale), scr);

add32(TrustedImm32(address.offset), scr);

if (address.base == SH4Registers::r0)

m_assembler.movbRegMemr0(src, scr);

else {

add32(address.base, scr);

m_assembler.movbRegMem(src, scr);

}

releaseScratch(scr);

}

void store8(RegisterID src, void* address)

{

RegisterID destptr = claimScratch();

move(TrustedImmPtr(address), destptr);

m_assembler.movbRegMem(src, destptr);

releaseScratch(destptr);

}

void store8(TrustedImm32 imm, void* address)

{

ASSERT((imm.m_value >= -128) && (imm.m_value <= 127));

RegisterID dstptr = claimScratch();

move(TrustedImmPtr(address), dstptr);

RegisterID srcval = claimScratch();

move(imm, srcval);

m_assembler.movbRegMem(srcval, dstptr);

releaseScratch(dstptr);

releaseScratch(srcval);

}

void store16(RegisterID src, BaseIndex address)

{

RegisterID scr = claimScratch();

move(address.index, scr);

lshift32(TrustedImm32(address.scale), scr);

add32(TrustedImm32(address.offset), scr);

if (address.base == SH4Registers::r0)

m_assembler.movwRegMemr0(src, scr);

else {

add32(address.base, scr);

m_assembler.movwRegMem(src, scr);

}

releaseScratch(scr);

}

void store32(RegisterID src, ImplicitAddress address)

{

if (!address.offset) {

m_assembler.movlRegMem(src, address.base);

return;

}

if ((address.offset >= 0) && (address.offset < 64)) {

m_assembler.movlRegMem(src, address.offset >> 2, address.base);

return;

}

RegisterID scr = claimScratch();

m_assembler.loadConstant(address.offset, scr);

if (address.base == SH4Registers::r0)

m_assembler.movlRegMemr0(src, scr);

else {

m_assembler.addlRegReg(address.base, scr);

m_assembler.movlRegMem(src, scr);

}

releaseScratch(scr);

}

void store32(RegisterID src, RegisterID dst)

{

m_assembler.movlRegMem(src, dst);

}

void store32(TrustedImm32 imm, ImplicitAddress address)

{

RegisterID scr = claimScratch();

m_assembler.loadConstant(imm.m_value, scr);

store32(scr, address);

releaseScratch(scr);

}

void store32(RegisterID src, BaseIndex address)

{

RegisterID scr = claimScratch();

move(address.index, scr);

lshift32(TrustedImm32(address.scale), scr);

add32(address.base, scr);

store32(src, Address(scr, address.offset));

releaseScratch(scr);

}

void store32(TrustedImm32 imm, void* address)