/*

* Copyright (C) 2008, 2012, 2013 Apple Inc. All rights reserved.

*

* Redistribution and use in source and binary forms, with or without

* modification, are permitted provided that the following conditions

* are met:

* 1. Redistributions of source code must retain the above copyright

* notice, this list of conditions and the following disclaimer.

* 2. Redistributions in binary form must reproduce the above copyright

* notice, this list of conditions and the following disclaimer in the

* documentation and/or other materials provided with the distribution.

*

* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR

* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*/

#ifndef X86Assembler_h

#define X86Assembler_h

#if ENABLE(ASSEMBLER) && (CPU(X86) || CPU(X86_64))

#include "AssemblerBuffer.h"

#include "JITCompilationEffort.h"

#include <limits.h>

#include <stdint.h>

#include <wtf/Assertions.h>

#include <wtf/Vector.h>

#if USE(MASM_PROBE)

#include <xmmintrin.h>

#endif

namespace JSC {

inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(signed char)value; }

namespace X86Registers {

typedef enum {

eax,

ecx,

edx,

ebx,

esp,

ebp,

esi,

edi,

#if CPU(X86_64)

r8,

r9,

r10,

r11,

r12,

r13,

r14,

r15,

#endif

} RegisterID;

typedef enum {

xmm0,

xmm1,

xmm2,

xmm3,

xmm4,

xmm5,

xmm6,

xmm7,

#if CPU(X86_64)

xmm8,

xmm9,

xmm10,

xmm11,

xmm12,

xmm13,

xmm14,

xmm15,

#endif

} XMMRegisterID;

#if USE(MASM_PROBE)

#define FOR_EACH_CPU_REGISTER(V) \

FOR_EACH_CPU_GPREGISTER(V) \

FOR_EACH_CPU_SPECIAL_REGISTER(V) \

FOR_EACH_CPU_FPREGISTER(V)

#define FOR_EACH_CPU_GPREGISTER(V) \

V(void*, eax) \

V(void*, ebx) \

V(void*, ecx) \

V(void*, edx) \

V(void*, esi) \

V(void*, edi) \

V(void*, ebp) \

V(void*, esp) \

FOR_EACH_X86_64_CPU_GPREGISTER(V)

#define FOR_EACH_CPU_SPECIAL_REGISTER(V) \

V(void*, eip) \

V(void*, eflags) \

#define FOR_EACH_CPU_FPREGISTER(V) \

V(__m128, xmm0) \

V(__m128, xmm1) \

V(__m128, xmm2) \

V(__m128, xmm3) \

V(__m128, xmm4) \

V(__m128, xmm5) \

V(__m128, xmm6) \

V(__m128, xmm7)

#if CPU(X86)

#define FOR_EACH_X86_64_CPU_GPREGISTER(V) // Nothing to add.

#elif CPU(X86_64)

#define FOR_EACH_X86_64_CPU_GPREGISTER(V) \

V(void*, r8) \

V(void*, r9) \

V(void*, r10) \

V(void*, r11) \

V(void*, r12) \

V(void*, r13) \

V(void*, r14) \

V(void*, r15)

#endif // CPU(X86_64)

#endif // USE(MASM_PROBE)

}

class X86Assembler {

public:

typedef X86Registers::RegisterID RegisterID;

static RegisterID firstRegister() { return X86Registers::eax; }

static RegisterID lastRegister()

{

#if CPU(X86_64)

return X86Registers::r15;

#else

return X86Registers::edi;

#endif

}

typedef X86Registers::XMMRegisterID XMMRegisterID;

typedef XMMRegisterID FPRegisterID;

static FPRegisterID firstFPRegister() { return X86Registers::xmm0; }

static FPRegisterID lastFPRegister()

{

#if CPU(X86_64)

return X86Registers::xmm15;

#else

return X86Registers::xmm7;

#endif

}

typedef enum {

ConditionO,

ConditionNO,

ConditionB,

ConditionAE,

ConditionE,

ConditionNE,

ConditionBE,

ConditionA,

ConditionS,

ConditionNS,

ConditionP,

ConditionNP,

ConditionL,

ConditionGE,

ConditionLE,

ConditionG,

ConditionC = ConditionB,

ConditionNC = ConditionAE,

} Condition;

private:

typedef enum {

OP_ADD_EvGv = 0x01,

OP_ADD_GvEv = 0x03,

OP_OR_EvGv = 0x09,

OP_OR_GvEv = 0x0B,

OP_2BYTE_ESCAPE = 0x0F,

OP_AND_EvGv = 0x21,

OP_AND_GvEv = 0x23,

OP_SUB_EvGv = 0x29,

OP_SUB_GvEv = 0x2B,

PRE_PREDICT_BRANCH_NOT_TAKEN = 0x2E,

OP_XOR_EvGv = 0x31,

OP_XOR_GvEv = 0x33,

OP_CMP_EvGv = 0x39,

OP_CMP_GvEv = 0x3B,

#if CPU(X86_64)

PRE_REX = 0x40,

#endif

OP_PUSH_EAX = 0x50,

OP_POP_EAX = 0x58,

#if CPU(X86_64)

OP_MOVSXD_GvEv = 0x63,

#endif

PRE_OPERAND_SIZE = 0x66,

PRE_SSE_66 = 0x66,

OP_PUSH_Iz = 0x68,

OP_IMUL_GvEvIz = 0x69,

OP_GROUP1_EbIb = 0x80,

OP_GROUP1_EvIz = 0x81,

OP_GROUP1_EvIb = 0x83,

OP_TEST_EbGb = 0x84,

OP_TEST_EvGv = 0x85,

OP_XCHG_EvGv = 0x87,

OP_MOV_EbGb = 0x88,

OP_MOV_EvGv = 0x89,

OP_MOV_GvEv = 0x8B,

OP_LEA = 0x8D,

OP_GROUP1A_Ev = 0x8F,

OP_NOP = 0x90,

OP_CDQ = 0x99,

OP_MOV_EAXOv = 0xA1,

OP_MOV_OvEAX = 0xA3,

OP_MOV_EAXIv = 0xB8,

OP_GROUP2_EvIb = 0xC1,

OP_RET = 0xC3,

OP_GROUP11_EvIb = 0xC6,

OP_GROUP11_EvIz = 0xC7,

OP_INT3 = 0xCC,

OP_GROUP2_Ev1 = 0xD1,

OP_GROUP2_EvCL = 0xD3,

OP_ESCAPE_DD = 0xDD,

OP_CALL_rel32 = 0xE8,

OP_JMP_rel32 = 0xE9,

PRE_SSE_F2 = 0xF2,

PRE_SSE_F3 = 0xF3,

OP_HLT = 0xF4,

OP_GROUP3_EbIb = 0xF6,

OP_GROUP3_Ev = 0xF7,

OP_GROUP3_EvIz = 0xF7, // OP_GROUP3_Ev has an immediate, when instruction is a test.

OP_GROUP5_Ev = 0xFF,

} OneByteOpcodeID;

typedef enum {

OP2_MOVSD_VsdWsd = 0x10,

OP2_MOVSD_WsdVsd = 0x11,

OP2_MOVSS_VsdWsd = 0x10,

OP2_MOVSS_WsdVsd = 0x11,

OP2_CVTSI2SD_VsdEd = 0x2A,

OP2_CVTTSD2SI_GdWsd = 0x2C,

OP2_UCOMISD_VsdWsd = 0x2E,

OP2_ADDSD_VsdWsd = 0x58,

OP2_MULSD_VsdWsd = 0x59,

OP2_CVTSD2SS_VsdWsd = 0x5A,

OP2_CVTSS2SD_VsdWsd = 0x5A,

OP2_SUBSD_VsdWsd = 0x5C,

OP2_DIVSD_VsdWsd = 0x5E,

OP2_SQRTSD_VsdWsd = 0x51,

OP2_ANDNPD_VpdWpd = 0x55,

OP2_XORPD_VpdWpd = 0x57,

OP2_MOVD_VdEd = 0x6E,

OP2_MOVD_EdVd = 0x7E,

OP2_JCC_rel32 = 0x80,

OP_SETCC = 0x90,

OP2_3BYTE_ESCAPE = 0xAE,

OP2_IMUL_GvEv = 0xAF,

OP2_MOVZX_GvEb = 0xB6,

OP2_MOVSX_GvEb = 0xBE,

OP2_MOVZX_GvEw = 0xB7,

OP2_MOVSX_GvEw = 0xBF,

OP2_PEXTRW_GdUdIb = 0xC5,

OP2_PSLLQ_UdqIb = 0x73,

OP2_PSRLQ_UdqIb = 0x73,

OP2_POR_VdqWdq = 0XEB,

} TwoByteOpcodeID;

typedef enum {

OP3_MFENCE = 0xF0,

} ThreeByteOpcodeID;

TwoByteOpcodeID jccRel32(Condition cond)

{

return (TwoByteOpcodeID)(OP2_JCC_rel32 + cond);

}

TwoByteOpcodeID setccOpcode(Condition cond)

{

return (TwoByteOpcodeID)(OP_SETCC + cond);

}

typedef enum {

GROUP1_OP_ADD = 0,

GROUP1_OP_OR = 1,

GROUP1_OP_ADC = 2,

GROUP1_OP_AND = 4,

GROUP1_OP_SUB = 5,

GROUP1_OP_XOR = 6,

GROUP1_OP_CMP = 7,

GROUP1A_OP_POP = 0,

GROUP2_OP_ROL = 0,

GROUP2_OP_ROR = 1,

GROUP2_OP_RCL = 2,

GROUP2_OP_RCR = 3,

GROUP2_OP_SHL = 4,

GROUP2_OP_SHR = 5,

GROUP2_OP_SAR = 7,

GROUP3_OP_TEST = 0,

GROUP3_OP_NOT = 2,

GROUP3_OP_NEG = 3,

GROUP3_OP_IDIV = 7,

GROUP5_OP_CALLN = 2,

GROUP5_OP_JMPN = 4,

GROUP5_OP_PUSH = 6,

GROUP11_MOV = 0,

GROUP14_OP_PSLLQ = 6,

GROUP14_OP_PSRLQ = 2,

ESCAPE_DD_FSTP_doubleReal = 3,

} GroupOpcodeID;

class X86InstructionFormatter;

public:

X86Assembler()

: m_indexOfLastWatchpoint(INT_MIN)

, m_indexOfTailOfLastWatchpoint(INT_MIN)

{

}

AssemblerBuffer& buffer() { return m_formatter.m_buffer; }

// Stack operations:

void push_r(RegisterID reg)

{

m_formatter.oneByteOp(OP_PUSH_EAX, reg);

}

void pop_r(RegisterID reg)

{

m_formatter.oneByteOp(OP_POP_EAX, reg);

}

void push_i32(int imm)

{

m_formatter.oneByteOp(OP_PUSH_Iz);

m_formatter.immediate32(imm);

}

void push_m(int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_PUSH, base, offset);

}

void pop_m(int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_GROUP1A_Ev, GROUP1A_OP_POP, base, offset);

}

// Arithmetic operations:

#if !CPU(X86_64)

void adcl_im(int imm, const void* addr)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADC, addr);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADC, addr);

m_formatter.immediate32(imm);

}

}

#endif

void addl_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp(OP_ADD_EvGv, src, dst);

}

void addl_mr(int offset, RegisterID base, RegisterID dst)

{

m_formatter.oneByteOp(OP_ADD_GvEv, dst, base, offset);

}

#if !CPU(X86_64)

void addl_mr(const void* addr, RegisterID dst)

{

m_formatter.oneByteOp(OP_ADD_GvEv, dst, addr);

}

#endif

void addl_rm(RegisterID src, int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_ADD_EvGv, src, base, offset);

}

void addl_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);

m_formatter.immediate32(imm);

}

}

void addl_im(int imm, int offset, RegisterID base)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);

m_formatter.immediate32(imm);

}

}

#if CPU(X86_64)

void addq_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp64(OP_ADD_EvGv, src, dst);

}

void addq_mr(int offset, RegisterID base, RegisterID dst)

{

m_formatter.oneByteOp64(OP_ADD_GvEv, dst, base, offset);

}

void addq_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);

m_formatter.immediate32(imm);

}

}

void addq_im(int imm, int offset, RegisterID base)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);

m_formatter.immediate32(imm);

}

}

#else

void addl_im(int imm, const void* addr)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, addr);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, addr);

m_formatter.immediate32(imm);

}

}

#endif

void andl_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp(OP_AND_EvGv, src, dst);

}

void andl_mr(int offset, RegisterID base, RegisterID dst)

{

m_formatter.oneByteOp(OP_AND_GvEv, dst, base, offset);

}

void andl_rm(RegisterID src, int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_AND_EvGv, src, base, offset);

}

void andl_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, dst);

m_formatter.immediate32(imm);

}

}

void andl_im(int imm, int offset, RegisterID base)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, base, offset);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, base, offset);

m_formatter.immediate32(imm);

}

}

#if CPU(X86_64)

void andq_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp64(OP_AND_EvGv, src, dst);

}

void andq_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_AND, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_AND, dst);

m_formatter.immediate32(imm);

}

}

#else

void andl_im(int imm, const void* addr)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, addr);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, addr);

m_formatter.immediate32(imm);

}

}

#endif

void dec_r(RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP1_OP_OR, dst);

}

#if CPU(X86_64)

void decq_r(RegisterID dst)

{

m_formatter.oneByteOp64(OP_GROUP5_Ev, GROUP1_OP_OR, dst);

}

#endif // CPU(X86_64)

void inc_r(RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP1_OP_ADD, dst);

}

#if CPU(X86_64)

void incq_r(RegisterID dst)

{

m_formatter.oneByteOp64(OP_GROUP5_Ev, GROUP1_OP_ADD, dst);

}

#endif // CPU(X86_64)

void negl_r(RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NEG, dst);

}

#if CPU(X86_64)

void negq_r(RegisterID dst)

{

m_formatter.oneByteOp64(OP_GROUP3_Ev, GROUP3_OP_NEG, dst);

}

#endif

void negl_m(int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NEG, base, offset);

}

void notl_r(RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NOT, dst);

}

void notl_m(int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NOT, base, offset);

}

void orl_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp(OP_OR_EvGv, src, dst);

}

void orl_mr(int offset, RegisterID base, RegisterID dst)

{

m_formatter.oneByteOp(OP_OR_GvEv, dst, base, offset);

}

void orl_rm(RegisterID src, int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_OR_EvGv, src, base, offset);

}

void orl_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_OR, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_OR, dst);

m_formatter.immediate32(imm);

}

}

void orl_im(int imm, int offset, RegisterID base)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_OR, base, offset);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_OR, base, offset);

m_formatter.immediate32(imm);

}

}

#if CPU(X86_64)

void orq_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp64(OP_OR_EvGv, src, dst);

}

void orq_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_OR, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_OR, dst);

m_formatter.immediate32(imm);

}

}

#else

void orl_im(int imm, const void* addr)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_OR, addr);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_OR, addr);

m_formatter.immediate32(imm);

}

}

void orl_rm(RegisterID src, const void* addr)

{

m_formatter.oneByteOp(OP_OR_EvGv, src, addr);

}

#endif

void subl_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp(OP_SUB_EvGv, src, dst);

}

void subl_mr(int offset, RegisterID base, RegisterID dst)

{

m_formatter.oneByteOp(OP_SUB_GvEv, dst, base, offset);

}

void subl_rm(RegisterID src, int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_SUB_EvGv, src, base, offset);

}

void subl_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_SUB, dst);

m_formatter.immediate32(imm);

}

}

void subl_im(int imm, int offset, RegisterID base)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, base, offset);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_SUB, base, offset);

m_formatter.immediate32(imm);

}

}

#if CPU(X86_64)

void subq_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp64(OP_SUB_EvGv, src, dst);

}

void subq_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_SUB, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_SUB, dst);

m_formatter.immediate32(imm);

}

}

#else

void subl_im(int imm, const void* addr)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, addr);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_SUB, addr);

m_formatter.immediate32(imm);

}

}

#endif

void xorl_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp(OP_XOR_EvGv, src, dst);

}

void xorl_mr(int offset, RegisterID base, RegisterID dst)

{

m_formatter.oneByteOp(OP_XOR_GvEv, dst, base, offset);

}

void xorl_rm(RegisterID src, int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_XOR_EvGv, src, base, offset);

}

void xorl_im(int imm, int offset, RegisterID base)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_XOR, base, offset);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_XOR, base, offset);

m_formatter.immediate32(imm);

}

}

void xorl_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_XOR, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_XOR, dst);

m_formatter.immediate32(imm);

}

}

#if CPU(X86_64)

void xorq_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp64(OP_XOR_EvGv, src, dst);

}

void xorq_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_XOR, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_XOR, dst);

m_formatter.immediate32(imm);

}

}

void xorq_rm(RegisterID src, int offset, RegisterID base)

{

m_formatter.oneByteOp64(OP_XOR_EvGv, src, base, offset);

}

void rorq_i8r(int imm, RegisterID dst)

{

if (imm == 1)

m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_ROR, dst);

else {

m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_ROR, dst);

m_formatter.immediate8(imm);

}

}

#endif

void sarl_i8r(int imm, RegisterID dst)

{

if (imm == 1)

m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SAR, dst);

else {

m_formatter.oneByteOp(OP_GROUP2_EvIb, GROUP2_OP_SAR, dst);

m_formatter.immediate8(imm);

}

}

void sarl_CLr(RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SAR, dst);

}

void shrl_i8r(int imm, RegisterID dst)

{

if (imm == 1)

m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SHR, dst);

else {

m_formatter.oneByteOp(OP_GROUP2_EvIb, GROUP2_OP_SHR, dst);

m_formatter.immediate8(imm);

}

}

void shrl_CLr(RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SHR, dst);

}

void shll_i8r(int imm, RegisterID dst)

{

if (imm == 1)

m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SHL, dst);

else {

m_formatter.oneByteOp(OP_GROUP2_EvIb, GROUP2_OP_SHL, dst);

m_formatter.immediate8(imm);

}

}

void shll_CLr(RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SHL, dst);

}

#if CPU(X86_64)

void sarq_CLr(RegisterID dst)

{

m_formatter.oneByteOp64(OP_GROUP2_EvCL, GROUP2_OP_SAR, dst);

}

void sarq_i8r(int imm, RegisterID dst)

{

if (imm == 1)

m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SAR, dst);

else {

m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_SAR, dst);

m_formatter.immediate8(imm);

}

}

void shlq_i8r(int imm, RegisterID dst)

{

if (imm == 1)

m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SHL, dst);

else {

m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_SHL, dst);

m_formatter.immediate8(imm);

}

}

#endif // CPU(X86_64)

void imull_rr(RegisterID src, RegisterID dst)

{

m_formatter.twoByteOp(OP2_IMUL_GvEv, dst, src);

}

#if CPU(X86_64)

void imulq_rr(RegisterID src, RegisterID dst)

{

m_formatter.twoByteOp64(OP2_IMUL_GvEv, dst, src);

}

#endif // CPU(X86_64)

void imull_mr(int offset, RegisterID base, RegisterID dst)

{

m_formatter.twoByteOp(OP2_IMUL_GvEv, dst, base, offset);

}

void imull_i32r(RegisterID src, int32_t value, RegisterID dst)

{

m_formatter.oneByteOp(OP_IMUL_GvEvIz, dst, src);

m_formatter.immediate32(value);

}

void idivl_r(RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_IDIV, dst);

}

// Comparisons:

void cmpl_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp(OP_CMP_EvGv, src, dst);

}

void cmpl_rm(RegisterID src, int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_CMP_EvGv, src, base, offset);

}

void cmpl_mr(int offset, RegisterID base, RegisterID src)

{

m_formatter.oneByteOp(OP_CMP_GvEv, src, base, offset);

}

void cmpl_ir(int imm, RegisterID dst)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, dst);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);

m_formatter.immediate32(imm);

}

}

void cmpl_ir_force32(int imm, RegisterID dst)

{

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);

m_formatter.immediate32(imm);

}

void cmpl_im(int imm, int offset, RegisterID base)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, offset);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, offset);

m_formatter.immediate32(imm);

}

}

void cmpb_im(int imm, int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_GROUP1_EbIb, GROUP1_OP_CMP, base, offset);

m_formatter.immediate8(imm);

}

void cmpb_im(int imm, int offset, RegisterID base, RegisterID index, int scale)

{

m_formatter.oneByteOp(OP_GROUP1_EbIb, GROUP1_OP_CMP, base, index, scale, offset);

m_formatter.immediate8(imm);

}

#if CPU(X86)

void cmpb_im(int imm, const void* addr)

{

m_formatter.oneByteOp(OP_GROUP1_EbIb, GROUP1_OP_CMP, addr);

m_formatter.immediate8(imm);

}

#endif

void cmpl_im(int imm, int offset, RegisterID base, RegisterID index, int scale)

{

if (CAN_SIGN_EXTEND_8_32(imm)) {

m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, index, scale, offset);

m_formatter.immediate8(imm);

} else {

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, index, scale, offset);

m_formatter.immediate32(imm);

}

}

void cmpl_im_force32(int imm, int offset, RegisterID base)

{

m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, offset);

m_formatter.immediate32(imm);

}

#if CPU(X86_64)

void cmpq_rr(RegisterID src, RegisterID dst)

{

m_formatter.oneByteOp64(OP_CMP_EvGv, src, dst);

}

void cmpq_rm(RegisterID src, int offset, RegisterID base)

{

m_formatter.oneByteOp64(OP_CMP_EvGv, src, base, offset);

}

void cmpq_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)

{

m_formatter.oneByteOp64(OP_CMP_EvGv, src, base, index, scale, offset);

}

void cmpq_mr(int offset, RegisterID base, RegisterID src)