/*

* Copyright (C) 2008, 2012, 2013 Apple Inc. All rights reserved.

*

* Redistribution and use in source and binary forms, with or without

* modification, are permitted provided that the following conditions

* are met:

* 1. Redistributions of source code must retain the above copyright

* notice, this list of conditions and the following disclaimer.

* 2. Redistributions in binary form must reproduce the above copyright

* notice, this list of conditions and the following disclaimer in the

* documentation and/or other materials provided with the distribution.

*

* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR

* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*/

#ifndef MacroAssembler_h

#define MacroAssembler_h

#include <wtf/Platform.h>

#if ENABLE(ASSEMBLER)

#if CPU(ARM_THUMB2)

#include "MacroAssemblerARMv7.h"

namespace JSC { typedef MacroAssemblerARMv7 MacroAssemblerBase; };

#elif CPU(ARM64)

#include "MacroAssemblerARM64.h"

namespace JSC { typedef MacroAssemblerARM64 MacroAssemblerBase; };

#elif CPU(ARM_TRADITIONAL)

#include "MacroAssemblerARM.h"

namespace JSC { typedef MacroAssemblerARM MacroAssemblerBase; };

#elif CPU(MIPS)

#include "MacroAssemblerMIPS.h"

namespace JSC {

typedef MacroAssemblerMIPS MacroAssemblerBase;

};

#elif CPU(X86)

#include "MacroAssemblerX86.h"

namespace JSC { typedef MacroAssemblerX86 MacroAssemblerBase; };

#elif CPU(X86_64)

#include "MacroAssemblerX86_64.h"

namespace JSC { typedef MacroAssemblerX86_64 MacroAssemblerBase; };

#elif CPU(SH4)

#include "MacroAssemblerSH4.h"

namespace JSC {

typedef MacroAssemblerSH4 MacroAssemblerBase;

};

#else

#error "The MacroAssembler is not supported on this platform."

#endif

namespace JSC {

class MacroAssembler : public MacroAssemblerBase {

public:

static bool isStackRelated(RegisterID reg)

{

return reg == stackPointerRegister || reg == framePointerRegister;

}

static RegisterID firstRealRegister()

{

RegisterID firstRegister = MacroAssembler::firstRegister();

while (MacroAssembler::isStackRelated(firstRegister))

firstRegister = static_cast<RegisterID>(firstRegister + 1);

return firstRegister;

}

static RegisterID nextRegister(RegisterID reg)

{

RegisterID result = static_cast<RegisterID>(reg + 1);

while (MacroAssembler::isStackRelated(result))

result = static_cast<RegisterID>(result + 1);

return result;

}

static RegisterID secondRealRegister()

{

return nextRegister(firstRealRegister());

}

static FPRegisterID nextFPRegister(FPRegisterID reg)

{

return static_cast<FPRegisterID>(reg + 1);

}

static unsigned numberOfRegisters()

{

return lastRegister() - firstRegister() + 1;

}

static unsigned registerIndex(RegisterID reg)

{

return reg - firstRegister();

}

static unsigned numberOfFPRegisters()

{

return lastFPRegister() - firstFPRegister() + 1;

}

static unsigned fpRegisterIndex(FPRegisterID reg)

{

return reg - firstFPRegister();

}

static unsigned registerIndex(FPRegisterID reg)

{

return fpRegisterIndex(reg) + numberOfRegisters();

}

static unsigned totalNumberOfRegisters()

{

return numberOfRegisters() + numberOfFPRegisters();

}

using MacroAssemblerBase::pop;

using MacroAssemblerBase::jump;

using MacroAssemblerBase::branch32;

using MacroAssemblerBase::move;

using MacroAssemblerBase::add32;

using MacroAssemblerBase::and32;

using MacroAssemblerBase::branchAdd32;

using MacroAssemblerBase::branchMul32;

#if CPU(X86_64)

using MacroAssemblerBase::branchPtr;

#endif // CPU(X86_64)

using MacroAssemblerBase::branchSub32;

using MacroAssemblerBase::lshift32;

using MacroAssemblerBase::or32;

using MacroAssemblerBase::rshift32;

using MacroAssemblerBase::store32;

using MacroAssemblerBase::sub32;

using MacroAssemblerBase::urshift32;

using MacroAssemblerBase::xor32;

static bool isPtrAlignedAddressOffset(ptrdiff_t value)

{

return value == static_cast<int32_t>(value);

}

static const double twoToThe32; // This is super useful for some double code.

// Utilities used by the DFG JIT.

#if ENABLE(DFG_JIT)

using MacroAssemblerBase::invert;

static DoubleCondition invert(DoubleCondition cond)

{

switch (cond) {

case DoubleEqual:

return DoubleNotEqualOrUnordered;

case DoubleNotEqual:

return DoubleEqualOrUnordered;

case DoubleGreaterThan:

return DoubleLessThanOrEqualOrUnordered;

case DoubleGreaterThanOrEqual:

return DoubleLessThanOrUnordered;

case DoubleLessThan:

return DoubleGreaterThanOrEqualOrUnordered;

case DoubleLessThanOrEqual:

return DoubleGreaterThanOrUnordered;

case DoubleEqualOrUnordered:

return DoubleNotEqual;

case DoubleNotEqualOrUnordered:

return DoubleEqual;

case DoubleGreaterThanOrUnordered:

return DoubleLessThanOrEqual;

case DoubleGreaterThanOrEqualOrUnordered:

return DoubleLessThan;

case DoubleLessThanOrUnordered:

return DoubleGreaterThanOrEqual;

case DoubleLessThanOrEqualOrUnordered:

return DoubleGreaterThan;

default:

RELEASE_ASSERT_NOT_REACHED();

return DoubleEqual; // make compiler happy

}

}

static bool isInvertible(ResultCondition cond)

{

switch (cond) {

case Zero:

case NonZero:

return true;

default:

return false;

}

}

static ResultCondition invert(ResultCondition cond)

{

switch (cond) {

case Zero:

return NonZero;

case NonZero:

return Zero;

default:

RELEASE_ASSERT_NOT_REACHED();

return Zero; // Make compiler happy for release builds.

}

}

#endif

// Platform agnostic onvenience functions,

// described in terms of other macro assembly methods.

void pop()

{

addPtr(TrustedImm32(sizeof(void*)), stackPointerRegister);

}

void peek(RegisterID dest, int index = 0)

{

loadPtr(Address(stackPointerRegister, (index * sizeof(void*))), dest);

}

Address addressForPoke(int index)

{

return Address(stackPointerRegister, (index * sizeof(void*)));

}

void poke(RegisterID src, int index = 0)

{

storePtr(src, addressForPoke(index));

}

void poke(TrustedImm32 value, int index = 0)

{

store32(value, addressForPoke(index));

}

void poke(TrustedImmPtr imm, int index = 0)

{

storePtr(imm, addressForPoke(index));

}

#if !CPU(ARM64)

void pushToSave(RegisterID src)

{

push(src);

}

void popToRestore(RegisterID dest)

{

pop(dest);

}

void pushToSave(FPRegisterID src)

{

subPtr(TrustedImm32(sizeof(double)), stackPointerRegister);

storeDouble(src, stackPointerRegister);

}

void popToRestore(FPRegisterID dest)

{

loadDouble(stackPointerRegister, dest);

addPtr(TrustedImm32(sizeof(double)), stackPointerRegister);

}

#endif // !CPU(ARM64)

#if CPU(X86_64) || CPU(ARM64)

void peek64(RegisterID dest, int index = 0)

{

load64(Address(stackPointerRegister, (index * sizeof(void*))), dest);

}

void poke(TrustedImm64 value, int index = 0)

{

store64(value, addressForPoke(index));

}

void poke64(RegisterID src, int index = 0)

{

store64(src, addressForPoke(index));

}

#endif

#if CPU(MIPS)

void poke(FPRegisterID src, int index = 0)

{

ASSERT(!(index & 1));

storeDouble(src, addressForPoke(index));

}

#endif

// Immediate shifts only have 5 controllable bits

// so we'll consider them safe for now.

TrustedImm32 trustedImm32ForShift(Imm32 imm)

{

return TrustedImm32(imm.asTrustedImm32().m_value & 31);

}

// Backwards banches, these are currently all implemented using existing forwards branch mechanisms.

void branchPtr(RelationalCondition cond, RegisterID op1, TrustedImmPtr imm, Label target)

{

branchPtr(cond, op1, imm).linkTo(target, this);

}

void branchPtr(RelationalCondition cond, RegisterID op1, ImmPtr imm, Label target)

{

branchPtr(cond, op1, imm).linkTo(target, this);

}

void branch32(RelationalCondition cond, RegisterID op1, RegisterID op2, Label target)

{

branch32(cond, op1, op2).linkTo(target, this);

}

void branch32(RelationalCondition cond, RegisterID op1, TrustedImm32 imm, Label target)

{

branch32(cond, op1, imm).linkTo(target, this);

}

void branch32(RelationalCondition cond, RegisterID op1, Imm32 imm, Label target)

{

branch32(cond, op1, imm).linkTo(target, this);

}

void branch32(RelationalCondition cond, RegisterID left, Address right, Label target)

{

branch32(cond, left, right).linkTo(target, this);

}

Jump branch32(RelationalCondition cond, TrustedImm32 left, RegisterID right)

{

return branch32(commute(cond), right, left);

}

Jump branch32(RelationalCondition cond, Imm32 left, RegisterID right)

{

return branch32(commute(cond), right, left);

}

void branchTestPtr(ResultCondition cond, RegisterID reg, Label target)

{

branchTestPtr(cond, reg).linkTo(target, this);

}

#if !CPU(ARM_THUMB2) && !CPU(ARM64)

PatchableJump patchableBranchPtr(RelationalCondition cond, Address left, TrustedImmPtr right = TrustedImmPtr(0))

{

return PatchableJump(branchPtr(cond, left, right));

}

PatchableJump patchableBranchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))

{

return PatchableJump(branchPtrWithPatch(cond, left, dataLabel, initialRightValue));

}

#if !CPU(ARM_TRADITIONAL)

PatchableJump patchableJump()

{

return PatchableJump(jump());

}

PatchableJump patchableBranchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))

{

return PatchableJump(branchTest32(cond, reg, mask));

}

PatchableJump patchableBranch32(RelationalCondition cond, RegisterID reg, TrustedImm32 imm)

{

return PatchableJump(branch32(cond, reg, imm));

}

#endif

#endif

void jump(Label target)

{

jump().linkTo(target, this);

}

// Commute a relational condition, returns a new condition that will produce

// the same results given the same inputs but with their positions exchanged.

static RelationalCondition commute(RelationalCondition condition)

{

switch (condition) {

case Above:

return Below;

case AboveOrEqual:

return BelowOrEqual;

case Below:

return Above;

case BelowOrEqual:

return AboveOrEqual;

case GreaterThan:

return LessThan;

case GreaterThanOrEqual:

return LessThanOrEqual;

case LessThan:

return GreaterThan;

case LessThanOrEqual:

return GreaterThanOrEqual;

default:

break;

}

ASSERT(condition == Equal || condition == NotEqual);

return condition;

}

static const unsigned BlindingModulus = 64;

bool shouldConsiderBlinding()

{

return !(random() & (BlindingModulus - 1));

}

// Ptr methods

// On 32-bit platforms (i.e. x86), these methods directly map onto their 32-bit equivalents.

// FIXME: should this use a test for 32-bitness instead of this specific exception?

#if !CPU(X86_64) && !CPU(ARM64)

void addPtr(Address src, RegisterID dest)

{

add32(src, dest);

}

void addPtr(AbsoluteAddress src, RegisterID dest)

{

add32(src, dest);

}

void addPtr(RegisterID src, RegisterID dest)

{

add32(src, dest);

}

void addPtr(TrustedImm32 imm, RegisterID srcDest)

{

add32(imm, srcDest);

}

void addPtr(TrustedImmPtr imm, RegisterID dest)

{

add32(TrustedImm32(imm), dest);

}

void addPtr(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

add32(imm, src, dest);

}

void addPtr(TrustedImm32 imm, AbsoluteAddress address)

{

add32(imm, address);

}

void andPtr(RegisterID src, RegisterID dest)

{

and32(src, dest);

}

void andPtr(TrustedImm32 imm, RegisterID srcDest)

{

and32(imm, srcDest);

}

void andPtr(TrustedImmPtr imm, RegisterID srcDest)

{

and32(TrustedImm32(imm), srcDest);

}

void negPtr(RegisterID dest)

{

neg32(dest);

}

void orPtr(RegisterID src, RegisterID dest)

{

or32(src, dest);

}

void orPtr(RegisterID op1, RegisterID op2, RegisterID dest)

{

or32(op1, op2, dest);

}

void orPtr(TrustedImmPtr imm, RegisterID dest)

{

or32(TrustedImm32(imm), dest);

}

void orPtr(TrustedImm32 imm, RegisterID dest)

{

or32(imm, dest);

}

void subPtr(RegisterID src, RegisterID dest)

{

sub32(src, dest);

}

void subPtr(TrustedImm32 imm, RegisterID dest)

{

sub32(imm, dest);

}

void subPtr(TrustedImmPtr imm, RegisterID dest)

{

sub32(TrustedImm32(imm), dest);

}

void xorPtr(RegisterID src, RegisterID dest)

{

xor32(src, dest);

}

void xorPtr(TrustedImm32 imm, RegisterID srcDest)

{

xor32(imm, srcDest);

}

void loadPtr(ImplicitAddress address, RegisterID dest)

{

load32(address, dest);

}

void loadPtr(BaseIndex address, RegisterID dest)

{

load32(address, dest);

}

void loadPtr(const void* address, RegisterID dest)

{

load32(address, dest);

}

DataLabel32 loadPtrWithAddressOffsetPatch(Address address, RegisterID dest)

{

return load32WithAddressOffsetPatch(address, dest);

}

DataLabelCompact loadPtrWithCompactAddressOffsetPatch(Address address, RegisterID dest)

{

return load32WithCompactAddressOffsetPatch(address, dest);

}

void move(ImmPtr imm, RegisterID dest)

{

move(Imm32(imm.asTrustedImmPtr()), dest);

}

void comparePtr(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)

{

compare32(cond, left, right, dest);

}

void comparePtr(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)

{

compare32(cond, left, right, dest);

}

void storePtr(RegisterID src, ImplicitAddress address)

{

store32(src, address);

}

void storePtr(RegisterID src, BaseIndex address)

{

store32(src, address);

}

void storePtr(RegisterID src, void* address)

{

store32(src, address);

}

void storePtr(TrustedImmPtr imm, ImplicitAddress address)

{

store32(TrustedImm32(imm), address);

}

void storePtr(ImmPtr imm, Address address)

{

store32(Imm32(imm.asTrustedImmPtr()), address);

}

void storePtr(TrustedImmPtr imm, void* address)

{

store32(TrustedImm32(imm), address);

}

void storePtr(TrustedImmPtr imm, BaseIndex address)

{

store32(TrustedImm32(imm), address);

}

DataLabel32 storePtrWithAddressOffsetPatch(RegisterID src, Address address)

{

return store32WithAddressOffsetPatch(src, address);

}

Jump branchPtr(RelationalCondition cond, RegisterID left, RegisterID right)

{

return branch32(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, RegisterID left, TrustedImmPtr right)

{

return branch32(cond, left, TrustedImm32(right));

}

Jump branchPtr(RelationalCondition cond, RegisterID left, ImmPtr right)

{

return branch32(cond, left, Imm32(right.asTrustedImmPtr()));

}

Jump branchPtr(RelationalCondition cond, RegisterID left, Address right)

{

return branch32(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, Address left, RegisterID right)

{

return branch32(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, AbsoluteAddress left, RegisterID right)

{

return branch32(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, Address left, TrustedImmPtr right)

{

return branch32(cond, left, TrustedImm32(right));

}

Jump branchPtr(RelationalCondition cond, AbsoluteAddress left, TrustedImmPtr right)

{

return branch32(cond, left, TrustedImm32(right));

}

Jump branchSubPtr(ResultCondition cond, RegisterID src, RegisterID dest)

{

return branchSub32(cond, src, dest);

}

Jump branchTestPtr(ResultCondition cond, RegisterID reg, RegisterID mask)

{

return branchTest32(cond, reg, mask);

}

Jump branchTestPtr(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest32(cond, reg, mask);

}

Jump branchTestPtr(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest32(cond, address, mask);

}

Jump branchTestPtr(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest32(cond, address, mask);

}

Jump branchAddPtr(ResultCondition cond, RegisterID src, RegisterID dest)

{

return branchAdd32(cond, src, dest);

}

Jump branchSubPtr(ResultCondition cond, TrustedImm32 imm, RegisterID dest)

{

return branchSub32(cond, imm, dest);

}

using MacroAssemblerBase::branchTest8;

Jump branchTest8(ResultCondition cond, ExtendedAddress address, TrustedImm32 mask = TrustedImm32(-1))

{

return MacroAssemblerBase::branchTest8(cond, Address(address.base, address.offset), mask);

}

#else // !CPU(X86_64)

void addPtr(RegisterID src, RegisterID dest)

{

add64(src, dest);

}

void addPtr(Address src, RegisterID dest)

{

add64(src, dest);

}

void addPtr(TrustedImm32 imm, RegisterID srcDest)

{

add64(imm, srcDest);

}

void addPtr(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

add64(imm, src, dest);

}

void addPtr(TrustedImm32 imm, Address address)

{

add64(imm, address);

}

void addPtr(AbsoluteAddress src, RegisterID dest)

{

add64(src, dest);

}

void addPtr(TrustedImmPtr imm, RegisterID dest)

{

add64(TrustedImm64(imm), dest);

}

void addPtr(TrustedImm32 imm, AbsoluteAddress address)

{

add64(imm, address);

}

void andPtr(RegisterID src, RegisterID dest)

{

and64(src, dest);

}

void andPtr(TrustedImm32 imm, RegisterID srcDest)

{

and64(imm, srcDest);

}

void andPtr(TrustedImmPtr imm, RegisterID srcDest)

{

and64(imm, srcDest);

}

void lshiftPtr(Imm32 imm, RegisterID srcDest)

{

lshift64(trustedImm32ForShift(imm), srcDest);

}

void negPtr(RegisterID dest)

{

neg64(dest);

}

void orPtr(RegisterID src, RegisterID dest)

{

or64(src, dest);

}

void orPtr(TrustedImm32 imm, RegisterID dest)

{

or64(imm, dest);

}

void orPtr(TrustedImmPtr imm, RegisterID dest)

{

or64(TrustedImm64(imm), dest);

}

void orPtr(RegisterID op1, RegisterID op2, RegisterID dest)

{

or64(op1, op2, dest);

}

void orPtr(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

or64(imm, src, dest);

}

void rotateRightPtr(TrustedImm32 imm, RegisterID srcDst)

{

rotateRight64(imm, srcDst);

}

void subPtr(RegisterID src, RegisterID dest)

{

sub64(src, dest);

}

void subPtr(TrustedImm32 imm, RegisterID dest)

{

sub64(imm, dest);

}

void subPtr(TrustedImmPtr imm, RegisterID dest)

{

sub64(TrustedImm64(imm), dest);

}

void xorPtr(RegisterID src, RegisterID dest)

{

xor64(src, dest);

}

void xorPtr(RegisterID src, Address dest)

{

xor64(src, dest);

}

void xorPtr(TrustedImm32 imm, RegisterID srcDest)

{

xor64(imm, srcDest);

}

void loadPtr(ImplicitAddress address, RegisterID dest)

{

load64(address, dest);

}

void loadPtr(BaseIndex address, RegisterID dest)

{

load64(address, dest);

}

void loadPtr(const void* address, RegisterID dest)

{

load64(address, dest);

}

DataLabel32 loadPtrWithAddressOffsetPatch(Address address, RegisterID dest)

{

return load64WithAddressOffsetPatch(address, dest);

}

DataLabelCompact loadPtrWithCompactAddressOffsetPatch(Address address, RegisterID dest)

{

return load64WithCompactAddressOffsetPatch(address, dest);

}

void storePtr(RegisterID src, ImplicitAddress address)

{

store64(src, address);

}

void storePtr(RegisterID src, BaseIndex address)

{

store64(src, address);

}

void storePtr(RegisterID src, void* address)

{

store64(src, address);

}

void storePtr(TrustedImmPtr imm, ImplicitAddress address)

{

store64(TrustedImm64(imm), address);

}

void storePtr(TrustedImmPtr imm, BaseIndex address)

{

store64(TrustedImm64(imm), address);

}

DataLabel32 storePtrWithAddressOffsetPatch(RegisterID src, Address address)

{

return store64WithAddressOffsetPatch(src, address);

}

void comparePtr(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)

{

compare64(cond, left, right, dest);

}

void comparePtr(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)

{

compare64(cond, left, right, dest);

}

void testPtr(ResultCondition cond, RegisterID reg, TrustedImm32 mask, RegisterID dest)

{

test64(cond, reg, mask, dest);

}

void testPtr(ResultCondition cond, RegisterID reg, RegisterID mask, RegisterID dest)

{

test64(cond, reg, mask, dest);

}

Jump branchPtr(RelationalCondition cond, RegisterID left, RegisterID right)

{

return branch64(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, RegisterID left, TrustedImmPtr right)

{

return branch64(cond, left, TrustedImm64(right));

}

Jump branchPtr(RelationalCondition cond, RegisterID left, Address right)

{

return branch64(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, Address left, RegisterID right)

{

return branch64(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, AbsoluteAddress left, RegisterID right)

{

return branch64(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, Address left, TrustedImmPtr right)

{

return branch64(cond, left, TrustedImm64(right));

}

Jump branchTestPtr(ResultCondition cond, RegisterID reg, RegisterID mask)

{

return branchTest64(cond, reg, mask);

}

Jump branchTestPtr(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest64(cond, reg, mask);

}

Jump branchTestPtr(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest64(cond, address, mask);

}

Jump branchTestPtr(ResultCondition cond, Address address, RegisterID reg)

{

return branchTest64(cond, address, reg);

}

Jump branchTestPtr(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest64(cond, address, mask);

}

Jump branchTestPtr(ResultCondition cond, AbsoluteAddress address, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest64(cond, address, mask);

}

Jump branchAddPtr(ResultCondition cond, TrustedImm32 imm, RegisterID dest)

{

return branchAdd64(cond, imm, dest);

}

Jump branchAddPtr(ResultCondition cond, RegisterID src, RegisterID dest)

{

return branchAdd64(cond, src, dest);

}

Jump branchSubPtr(ResultCondition cond, TrustedImm32 imm, RegisterID dest)

{

return branchSub64(cond, imm, dest);

}

Jump branchSubPtr(ResultCondition cond, RegisterID src, RegisterID dest)

{

return branchSub64(cond, src, dest);

}

Jump branchSubPtr(ResultCondition cond, RegisterID src1, TrustedImm32 src2, RegisterID dest)

{

return branchSub64(cond, src1, src2, dest);

}

using MacroAssemblerBase::and64;

using MacroAssemblerBase::convertInt32ToDouble;

using MacroAssemblerBase::store64;

bool shouldBlindDouble(double value)

{

// Don't trust NaN or +/-Infinity

if (!std::isfinite(value))

return shouldConsiderBlinding();

// Try to force normalisation, and check that there's no change

// in the bit pattern

if (bitwise_cast<uint64_t>(value * 1.0) != bitwise_cast<uint64_t>(value))

return shouldConsiderBlinding();

value = fabs(value);

// Only allow a limited set of fractional components

double scaledValue = value * 8;

if (scaledValue / 8 != value)

return shouldConsiderBlinding();

double frac = scaledValue - floor(scaledValue);

if (frac != 0.0)

return shouldConsiderBlinding();

return value > 0xff;

}