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base repository: Minres/DBT-RISE-RISCV
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base: main
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head repository: Minres/DBT-RISE-RISCV
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compare: bugfix/reset
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  • 2 commits
  • 17 files changed
  • 1 contributor

Commits on Aug 18, 2026

  1. new generation of asmjit changed order of includes

    @EAlexJ
    EAlexJ committed Aug 18, 2026
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    4bae3b8 View commit details
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  2. reset now correctly zeroes out all registers 

    The solution before could lead to UB as it zeroed out NUM_REGS registers of reg_t, even if the other registers were smaller
    @EAlexJ
    EAlexJ committed Aug 18, 2026
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    145547c View commit details
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