# Copyright (C) 2021 Igalia S.L.

#

# Redistribution and use in source and binary forms, with or without

# modification, are permitted provided that the following conditions

# are met:

# 1. Redistributions of source code must retain the above copyright

# notice, this list of conditions and the following disclaimer.

# 2. Redistributions in binary form must reproduce the above copyright

# notice, this list of conditions and the following disclaimer in the

# documentation and/or other materials provided with the distribution.

#

# THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS''

# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS

# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF

# THE POSSIBILITY OF SUCH DAMAGE.

# Naming conventions

#

# x<number> => GPR, used to operate with 32-bit and 64-bit integer values

# f<number> => FPR, used to operate with 32-bit and 64-bit floating-point values

#

# GPR conventions, to match the baseline JIT:

#

# x0 => not used (except where needed for operations) (RISC-V hard-wired zero register)

# x1 => la (through alias ra) (RISC-V return address register)

# x2 => sp (through alias sp) (RISC-V stack pointer register)

# x3 => not used (RISC-V global pointer register)

# x4 => not used (RISC-V thread pointer register)

# x5 => not used

# x6 => ws0

# x7 => ws1

# x8 => cfr (thought alias fp) (RISC-V frame pointer register)

# x9 => csr0

# x10 => t0, a0, wa0, r0

# x11 => t1, a1, wa1, r1

# x12 => t2, a2, wa2

# x13 => t3, a3, wa3

# x14 => t4, a4, wa4

# x15 => t5, a5, wa5

# x16 => t6, a6, wa6

# x17 => t7, a7, wa7

# x18 => csr1

# x19 => csr2

# x20 => csr3

# x21 => csr4

# x22 => csr5

# x23 => csr6 (metadataTable)

# x24 => csr7 (PB)

# x25 => csr8 (numberTag)

# x26 => csr9 (notCellMask)

# x27 => csr10

# x28 => not used

# x29 => not used

# x30 => scratch register

# x31 => scratch register

#

# FPR conventions, to match the baseline JIT:

#

# f0 => ft0

# f1 => ft1

# f2 => ft2

# f3 => ft3

# f4 => ft4

# f5 => ft5

# f6 => not used

# f7 => not used

# f8 => csfr0

# f9 => csfr1

# f10 => fa0, wfa0

# f11 => fa1, wfa1

# f12 => fa2, wfa2

# f13 => fa3, wfa3

# f14 => fa4, wfa4

# f15 => fa5, wfa5

# f16 => fa6, wfa6

# f17 => fa7, wfa7

# f18 => csfr2

# f19 => csfr3

# f20 => csfr4

# f21 => csfr5

# f22 => csfr6

# f23 => csfr7

# f24 => csfr8

# f25 => csfr9

# f26 => csfr10

# f27 => csfr11

# f28 => not used

# f29 => not used

# f30 => not used

# f31 => not used

def riscv64OperandTypes(operands)

return operands.map {

|op|

op.class

}

end

def riscv64RaiseMismatchedOperands(operands)

raise "Unable to match operands #{riscv64OperandTypes(operands)}"

end

def riscv64RaiseUnsupported

raise "Not supported for RISCV64"

end

def riscv64LoadInstruction(size)

case size

when :b

"lb"

when :bu

"lbu"

when :h

"lh"

when :hu

"lhu"

when :w

"lw"

when :wu

"lwu"

when :d

"ld"

else

raise "Unsupported size #{size}"

end

end

def riscv64ZeroExtendedLoadInstruction(size)

case size

when :b

riscv64LoadInstruction(:bu)

when :h

riscv64LoadInstruction(:hu)

when :w

riscv64LoadInstruction(:wu)

when :d

riscv64LoadInstruction(:d)

else

raise "Unsupported size #{size}"

end

end

def riscv64StoreInstruction(size)

case size

when :b

"sb"

when :h

"sh"

when :w

"sw"

when :d

"sd"

else

raise "Unsupported size #{size}"

end

end

def riscv64EmitRegisterMask(target, size)

case size

when :w

$asm.puts "li x31, 0xffffffff"

$asm.puts "and #{target.riscv64Operand}, #{target.riscv64Operand}, x31"

when :d

else

raise "Unsupported size"

end

end

def riscv64ConditionalBranchInstruction(condition)

case condition

when :eq

"beq"

when :neq

"bne"

when :a

"bgtu"

when :aeq

"bgeu"

when :b

"bltu"

when :beq

"bleu"

when :gt

"bgt"

when :gteq

"bge"

when :lt

"blt"

when :lteq

"ble"

else

raise "Unsupported condition #{condition}"

end

end

def riscv64EmitLoad(operands, type, mask)

instruction = riscv64LoadInstruction(type)

case riscv64OperandTypes(operands)

when [Address, RegisterID]

if operands[0].riscv64RequiresLoad

operands[0].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{instruction} #{operands[1].riscv64Operand}, 0(x31)"

else

$asm.puts "#{instruction} #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"

end

when [BaseIndex, RegisterID]

operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)

$asm.puts "#{instruction} #{operands[1].riscv64Operand}, 0(x31)"

else

riscv64RaiseMismatchedOperands(operands)

end

case mask

when :w

riscv64EmitRegisterMask(operands[1], :w)

when :none

else

raise "Unsupported mask type"

end

end

def riscv64EmitStore(operands, type)

instruction = riscv64StoreInstruction(type)

case riscv64OperandTypes(operands)

when [RegisterID, Address]

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{instruction} #{operands[0].riscv64Operand}, 0(x31)"

else

$asm.puts "#{instruction} #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

end

when [RegisterID, BaseIndex]

operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)

$asm.puts "#{instruction} #{operands[0].riscv64Operand}, 0(x31)"

when [Immediate, Address]

$asm.puts "li x30, #{operands[0].riscv64Operand}"

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{instruction} x30, 0(x31)"

else

$asm.puts "#{instruction} x30, #{operands[1].riscv64Operand}"

end

when [Immediate, BaseIndex]

operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)

$asm.puts "li x30, #{operands[0].riscv64Operand}"

$asm.puts "#{instruction} x30, 0(x31)"

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitAdditionOperation(operands, size, operation)

raise "Unsupported size" unless [:w, :d].include? size

def additionInstruction(size, operation)

case operation

when :add

size == :w ? "addw" : "add"

when :sub

size == :w ? "subw" : "sub"

else

raise "Unsupported arithmetic operation"

end

end

instruction = additionInstruction(size, operation)

loadInstruction = riscv64LoadInstruction(size)

storeInstruction = riscv64StoreInstruction(size)

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID]

operands = [operands[1], operands[0], operands[1]]

when [Immediate, RegisterID]

operands = [operands[1], operands[0], operands[1]]

when [Address, RegisterID]

operands = [operands[1], operands[0], operands[1]]

end

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, RegisterID]

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

riscv64EmitRegisterMask(operands[2], size)

when [RegisterID, Immediate, RegisterID]

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, x31"

riscv64EmitRegisterMask(operands[2], size)

when [Immediate, RegisterID, RegisterID]

operands[0].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, x31, #{operands[1].riscv64Operand}"

riscv64EmitRegisterMask(operands[2], size)

when [RegisterID, Address, RegisterID]

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{loadInstruction} x31, 0(x31)"

else

$asm.puts "#{loadInstruction} x31, #{operands[1].riscv64Operand}"

end

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, x31"

riscv64EmitRegisterMask(operands[2], size)

when [Immediate, Address]

$asm.puts "li x30, #{operands[0].riscv64Operand}"

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{loadInstruction} x31, 0(x31)"

else

$asm.puts "#{loadInstruction} x31, #{operands[1].riscv64Operand}"

end

$asm.puts "#{instruction} x30, x30, x31"

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{storeInstruction} x30, 0(x31)"

else

$asm.puts "#{storeInstruction} x30, #{operands[1].riscv64Operand}"

end

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitMulDivArithmetic(operands, size, operation)

raise "Unsupported size" unless [:w, :d].include? size

def arithmeticInstruction(size, operation)

case operation

when :mul

size == :w ? "mulw" : "mul"

when :div

size == :w ? "divuw" : "divu"

else

raise "Unsupported arithmetic operation"

end

end

instruction = arithmeticInstruction(size, operation)

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID]

operands = [operands[0], operands[1], operands[1]]

when [Immediate, RegisterID]

operands = [operands[1], operands[0], operands[1]]

end

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, RegisterID]

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

when [RegisterID, Immediate, RegisterID]

$asm.puts "li x31, #{operands[1].riscv64Operand}"

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, x31"

when [Immediate, RegisterID, RegisterID]

$asm.puts "li x31, #{operands[0].riscv64Operand}"

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, x31, #{operands[1].riscv64Operand}"

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitConditionalBranch(operands, size, condition)

instruction = riscv64ConditionalBranchInstruction(condition)

def signExtendForSize(register, target, size)

case size

when :b

$asm.puts "slli #{target}, #{register.riscv64Operand}, 24"

$asm.puts "sext.w #{target}, #{target}"

$asm.puts "srai #{target}, #{target}, 24"

when :w

$asm.puts "sext.w #{target}, #{register.riscv64Operand}"

when :d

$asm.puts "mv #{target}, #{register.riscv64Operand}"

end

end

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, LocalLabelReference]

signExtendForSize(operands[0], 'x30', size)

signExtendForSize(operands[1], 'x31', size)

$asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"

when [RegisterID, Immediate, LocalLabelReference]

signExtendForSize(operands[0], 'x30', size)

$asm.puts "li x31, #{operands[1].riscv64Operand}"

$asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"

when [RegisterID, Address, LocalLabelReference]

signExtendForSize(operands[0], 'x30', size)

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{riscv64LoadInstruction(size)} x31, 0(x31)"

else

$asm.puts "#{riscv64LoadInstruction(size)} x31, #{operands[1].riscv64Operand}"

end

$asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"

when [RegisterID, BaseIndex, LocalLabelReference]

operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)

$asm.puts "#{riscv64LoadInstruction(size)} x31, 0(x31)"

signExtendForSize(operands[0], 'x30', size)

$asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"

when [Address, RegisterID, LocalLabelReference]

if operands[0].riscv64RequiresLoad

operands[0].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{riscv64LoadInstruction(size)} x30, 0(x31)"

else

$asm.puts "#{riscv64LoadInstruction(size)} x30, #{operands[0].riscv64Operand}"

end

signExtendForSize(operands[1], 'x31', size)

$asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"

when [Address, Immediate, LocalLabelReference]

if operands[0].riscv64RequiresLoad

operands[0].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{riscv64LoadInstruction(size)} x30, 0(x31)"

else

$asm.puts "#{riscv64LoadInstruction(size)} x30, #{operands[0].riscv64Operand}"

end

$asm.puts "li x31, #{operands[1].riscv64Operand}"

$asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitConditionalBranchForTest(operands, size, test)

def branchInstruction(test)

case test

when :z

"beqz"

when :nz

"bnez"

when :s

"bltz"

else

end

end

def signExtendForSize(target, size)

case size

when :b

$asm.puts "slli #{target}, #{target}, 24"

$asm.puts "sext.w #{target}, #{target}"

$asm.puts "srai #{target}, #{target}, 24"

when :h

$asm.puts "slli #{target}, #{target}, 16"

$asm.puts "sext.w #{target}, #{target}"

$asm.puts "srai #{target}, #{target}, 16"

when :w

$asm.puts "sext.w #{target}, #{target}"

when :d

return

end

end

bInstruction = branchInstruction(test)

loadInstruction = riscv64LoadInstruction(size)

case riscv64OperandTypes(operands)

when [RegisterID, LocalLabelReference]

case test

when :s

$asm.puts "mv x31, #{operands[0].riscv64Operand}"

signExtendForSize('x31', size)

$asm.puts "#{bInstruction} x31, #{operands[1].asmLabel}"

else

$asm.puts "#{bInstruction} #{operands[0].riscv64Operand}, #{operands[1].asmLabel}"

end

when [RegisterID, RegisterID, LocalLabelReference]

$asm.puts "and x31, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

signExtendForSize('x31', size)

$asm.puts "#{bInstruction} x31, #{operands[2].asmLabel}"

when [RegisterID, Immediate, LocalLabelReference]

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "and x31, #{operands[0].riscv64Operand}, x31"

else

$asm.puts "andi x31, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

end

signExtendForSize('x31', size)

$asm.puts "#{bInstruction} x31, #{operands[2].asmLabel}"

when [Address, LocalLabelReference]

if operands[0].riscv64RequiresLoad

operands[0].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{loadInstruction} x31, 0(x31)"

else

$asm.puts "#{loadInstruction} x31, #{operands[0].riscv64Operand}"

end

$asm.puts "#{bInstruction} x31, #{operands[1].asmLabel}"

when [Address, Immediate, LocalLabelReference]

if operands[0].riscv64RequiresLoad

operands[0].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{loadInstruction} x30, 0(x31)"

else

$asm.puts "#{loadInstruction} x30, #{operands[0].riscv64Operand}"

end

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "and x31, x30, x31"

else

$asm.puts "andi x31, x30, #{operands[1].riscv64Operand}"

end

signExtendForSize('x31', size)

$asm.puts "#{bInstruction} x31, #{operands[2].asmLabel}"

when [BaseIndex, LocalLabelReference]

operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)

$asm.puts "#{loadInstruction} x31, 0(x31)"

$asm.puts "#{bInstruction} x31, #{operands[1].asmLabel}"

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitConditionalBranchForAdditionOperation(operands, size, operation, test)

def additionInstruction(size, operation)

case operation

when :add

size == :w ? "addw" : "add"

when :sub

size == :w ? "subw" : "sub"

else

raise "Unsupported arithmetic operation"

end

end

def emitBranchForTest(test, target, label)

case test

when :z

$asm.puts "beqz #{target.riscv64Operand}, #{label.asmLabel}"

when :nz

$asm.puts "bnez #{target.riscv64Operand}, #{label.asmLabel}"

when :s

$asm.puts "bltz #{target.riscv64Operand}, #{label.asmLabel}"

else

raise "Unsupported test"

end

end

instruction = additionInstruction(size, operation)

loadInstruction = riscv64LoadInstruction(size)

storeInstruction = riscv64StoreInstruction(size)

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, LocalLabelReference]

operands = [operands[1], operands[0], operands[1], operands[2]]

when [Immediate, RegisterID, LocalLabelReference]

operands = [operands[1], operands[0], operands[1], operands[2]]

end

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, RegisterID, LocalLabelReference]

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

$asm.puts "mv x30, #{operands[2].riscv64Operand}"

riscv64EmitRegisterMask(operands[2], size)

emitBranchForTest(test, RISCV64ScratchRegister.x30, operands[3])

when [RegisterID, Immediate, RegisterID, LocalLabelReference]

$asm.puts "li x31, #{operands[1].riscv64Operand}"

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, x31"

$asm.puts "mv x30, #{operands[2].riscv64Operand}"

riscv64EmitRegisterMask(operands[2], size)

emitBranchForTest(test, RISCV64ScratchRegister.x30, operands[3])

when [Immediate, Address, LocalLabelReference]

$asm.puts "li x30, #{operands[0].riscv64Operand}"

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{loadInstruction} x31, 0(x31)"

else

$asm.puts "#{loadInstruction} x31, #{operands[1].riscv64Operand}"

end

$asm.puts "#{instruction} x30, x30, x31"

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{storeInstruction} x30, 0(x31)"

else

$asm.puts "#{storeInstruction} x30, #{operands[1].riscv64Operand}"

end

emitBranchForTest(test, RISCV64ScratchRegister.x30, operands[2])

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitConditionalBranchForMultiplicationOperation(operands, size, test)

raise "Unsupported size" unless size == :w

def emitMultiplication(lhs, rhs)

$asm.puts "sext.w x30, #{lhs.riscv64Operand}"

$asm.puts "sext.w x31, #{rhs.riscv64Operand}"

$asm.puts "mul x30, x30, x31"

end

def emitBranchForTest(test, label)

case test

when :z

$asm.puts "beqz x30, #{label.asmLabel}"

when :nz

$asm.puts "bnez x30, #{label.asmLabel}"

when :s

$asm.puts "bltz x30, #{label.asmLabel}"

else

raise "Unsupported test"

end

end

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, LocalLabelReference]

emitMultiplication(operands[0], operands[1])

$asm.puts "mv #{operands[1].riscv64Operand}, x30"

riscv64EmitRegisterMask(operands[1], size)

emitBranchForTest(test, operands[2])

when [Immediate, RegisterID, LocalLabelReference]

$asm.puts "li x30, #{operands[0].riscv64Operand}"

emitMultiplication(RISCV64ScratchRegister.x30, operands[1])

$asm.puts "mv #{operands[1].riscv64Operand}, x30"

riscv64EmitRegisterMask(operands[1], size)

emitBranchForTest(test, operands[2])

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitOverflowBranchForOperation(operands, size, operation)

raise "Unsupported size" unless size == :w

def operationInstruction(operation)

case operation

when :add

"add"

when :sub

"sub"

when :mul

"mul"

else

raise "Unsupported operation"

end

end

instruction = operationInstruction(operation)

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, LocalLabelReference]

operands = [operands[1], operands[0], operands[1], operands[2]]

when [Immediate, RegisterID, LocalLabelReference]

operands = [operands[1], operands[0], operands[1], operands[2]]

end

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, RegisterID, LocalLabelReference]

$asm.puts "sext.w x30, #{operands[0].riscv64Operand}"

$asm.puts "sext.w x31, #{operands[1].riscv64Operand}"

$asm.puts "#{instruction} x30, x30, x31"

$asm.puts "mv #{operands[2].riscv64Operand}, x30"

riscv64EmitRegisterMask(operands[2], size)

$asm.puts "sext.w x31, x30"

$asm.puts "bne x30, x31, #{operands[3].asmLabel}"

when [RegisterID, Immediate, RegisterID, LocalLabelReference]

$asm.puts "sext.w x30, #{operands[0].riscv64Operand}"

$asm.puts "li x31, #{operands[1].riscv64Operand}"

$asm.puts "sext.w x31, x31"

$asm.puts "#{instruction} x30, x30, x31"

$asm.puts "mv #{operands[2].riscv64Operand}, x30"

riscv64EmitRegisterMask(operands[2], size)

$asm.puts "sext.w x31, x30"

$asm.puts "bne x30, x31, #{operands[3].asmLabel}"

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitCompare(operands, size, condition)

def signExtendRegisterForSize(register, target, size)

case size

when :b

$asm.puts "slli #{target}, #{register.riscv64Operand}, 24"

$asm.puts "sext.w #{target}, #{target}"

$asm.puts "srai #{target}, #{target}, 24"

when :w

$asm.puts "sext.w #{target}, #{register.riscv64Operand}"

when :d

$asm.puts "mv #{target}, #{register.riscv64Operand}"

else

raise "Unsupported size"

end

end

def signExtendImmediateForSize(immediate, target, size)

$asm.puts "li #{target}, #{immediate.riscv64Operand}"

case size

when :b

$asm.puts "slli #{target}, #{target}, 24"

$asm.puts "sext.w #{target}, #{target}"

$asm.puts "srai #{target}, #{target}, 24"

when :w

$asm.puts "sext.w #{target}, #{target}"

when :d

else

raise "Unsupported size"

end

end

def loadAndSignExtendAddressForSize(address, target, size)

if address.riscv64RequiresLoad

address.riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{riscv64LoadInstruction(size)} #{target}, 0(x31)"

else

$asm.puts "#{riscv64LoadInstruction(size)} #{target}, #{address.riscv64Operand}"

end

end

def setForCondition(lhs, rhs, target, condition)

case condition

when :eq

$asm.puts "sub x31, #{lhs}, #{rhs}"

$asm.puts "seqz #{operands[2].riscv64Operand}, x31"

when :neq

$asm.puts "sub x31, #{lhs}, #{rhs}"

$asm.puts "snez #{operands[2].riscv64Operand}, x31"

when :a

$asm.puts "sltu #{operands[2].riscv64Operand}, #{rhs}, #{lhs}"

when :aeq

$asm.puts "sltu #{operands[2].riscv64Operand}, #{lhs}, #{rhs}"

$asm.puts "xori #{operands[2].riscv64Operand}, #{operands[2].riscv64Operand}, 1"

when :b

$asm.puts "sltu #{operands[2].riscv64Operand}, #{lhs}, #{rhs}"

when :beq

$asm.puts "sltu #{operands[2].riscv64Operand}, #{rhs}, #{lhs}"

$asm.puts "xori #{operands[2].riscv64Operand}, #{operands[2].riscv64Operand}, 1"

when :lt

$asm.puts "slt #{target.riscv64Operand}, #{lhs}, #{rhs}"

when :lteq

$asm.puts "slt #{target.riscv64Operand}, #{rhs}, #{lhs}"

$asm.puts "xori #{target.riscv64Operand}, #{target.riscv64Operand}, 1"

when :gt

$asm.puts "slt #{target.riscv64Operand}, #{rhs}, #{lhs}"

when :gteq

$asm.puts "slt #{target.riscv64Operand}, #{lhs}, #{rhs}"

$asm.puts "xori #{target.riscv64Operand}, #{target.riscv64Operand}, 1"

else

raise "Unsupported condition"

end

end

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, RegisterID]

signExtendRegisterForSize(operands[0], 'x30', size)

signExtendRegisterForSize(operands[1], 'x31', size)

setForCondition('x30', 'x31', operands[2], condition)

when [RegisterID, Immediate, RegisterID]

signExtendRegisterForSize(operands[0], 'x30', size)

signExtendImmediateForSize(operands[1], 'x31', size)

setForCondition('x30', 'x31', operands[2], condition)

when [Address, RegisterID, RegisterID]

loadAndSignExtendAddressForSize(operands[0], 'x30', size)

signExtendRegisterForSize(operands[1], 'x31', size)

setForCondition('x30', 'x31', operands[2], condition)

when [Address, Immediate, RegisterID]

loadAndSignExtendAddressForSize(operands[0], 'x30', size)

signExtendImmediateForSize(operands[1], 'x31', size)

setForCondition('x30', 'x31', operands[2], condition)

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitTest(operands, size, test)

def testInstruction(test)

case test

when :z

"seqz"

when :nz

"snez"

else

raise "Unknown test type"

end

end

instruction = testInstruction(test)

loadInstruction = riscv64ZeroExtendedLoadInstruction(size)

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID, RegisterID]

$asm.puts "and x31, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, x31"

when [RegisterID, Immediate, RegisterID]

if operands[1].riscv64RequiresLoad

$asm.puts "li x31, #{operands[1].riscv64Operand}"

$asm.puts "and x31, #{operands[0].riscv64Operand}, x31"

else

$asm.puts "andi x31, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

end

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, x31"

when [Address, Immediate, RegisterID]

if operands[0].riscv64RequiresLoad

operands[0].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{loadInstruction} x31, 0(x31)"

else

$asm.puts "#{loadInstruction} x31, #{operands[0].riscv64Operand}"

end

if operands[1].riscv64RequiresLoad

$asm.puts "li x30, #{operands[1].riscv64Operand}"

$asm.puts "and x31, x30, x31"

else

$asm.puts "andi x31, x31, #{operands[1].riscv64Operand}"

end

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, x31"

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitLogicalOperation(operands, size, operation)

def opInstruction(operation)

case operation

when :and

"and"

when :or

"or"

when :xor

"xor"

else

raise "Unsupported logical operation"

end

end

instruction = opInstruction(operation)

loadInstruction = riscv64ZeroExtendedLoadInstruction(size)

storeInstruction = riscv64StoreInstruction(size)

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID]

$asm.puts "#{instruction} #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

riscv64EmitRegisterMask(operands[1], size)

when [RegisterID, RegisterID, RegisterID]

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

riscv64EmitRegisterMask(operands[2], size)

when [RegisterID, Immediate, RegisterID]

if operands[1].riscv64RequiresLoad

$asm.puts "li x31, #{operands[1].riscv64Operand}"

$asm.puts "#{instruction} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, x31"

else

$asm.puts "#{instruction}i #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

end

riscv64EmitRegisterMask(operands[2], size)

when [Immediate, RegisterID]

if operands[0].riscv64RequiresLoad

$asm.puts "li x31, #{operands[0].riscv64Operand}"

$asm.puts "#{instruction} #{operands[1].riscv64Operand}, x31, #{operands[1].riscv64Operand}"

else

$asm.puts "#{instruction}i #{operands[1].riscv64Operand}, #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"

end

riscv64EmitRegisterMask(operands[1], size)

when [Immediate, Address]

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{loadInstruction} x30, 0(x31)"

else

$asm.puts "#{loadInstruction} x30, #{operands[1].riscv64Operand}"

end

$asm.puts "li x31, #{operands[0].riscv64Operand}"

$asm.puts "#{instruction} x30, x31, x30"

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{storeInstruction} x30, 0(x31)"

else

$asm.puts "#{storeInstruction} x30, #{operands[1].riscv64Operand}"

end

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitComplementOperation(operands, size, operation)

def complementInstruction(size, operation)

case operation

when :not

"not"

when :neg

size == :w ? "negw" : "neg"

else

raise "Unsupported complement operation"

end

end

instruction = complementInstruction(size, operation)

case riscv64OperandTypes(operands)

when [RegisterID]

$asm.puts "#{instruction} #{operands[0].riscv64Operand}, #{operands[0].riscv64Operand}"

riscv64EmitRegisterMask(operands[0], size)

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitShift(operands, size, shift)

raise "Unsupported size" unless [:w, :d].include? size

def shiftInstruction(size, shift)

case shift

when :lleft

size == :w ? "sllw" : "sll"

when :lright

size == :w ? "srlw" : "srl"

when :aright

size == :w ? "sraw" : "sra"

else

raise "Unsupported shift type"

end

end

case riscv64OperandTypes(operands)

when [RegisterID, RegisterID]

$asm.puts "#{shiftInstruction(size, shift)} #{operands[1].riscv64Operand}, #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"

riscv64EmitRegisterMask(operands[1], size)

when [Immediate, RegisterID]

$asm.puts "li x31, #{operands[0].riscv64Operand}"

$asm.puts "#{shiftInstruction(size, shift)} #{operands[1].riscv64Operand}, #{operands[1].riscv64Operand}, x31"

riscv64EmitRegisterMask(operands[1], size)

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitBitExtension(operands, fromSize, toSize, extensionType)

raise "Unsupported operand types" unless riscv64OperandTypes(operands) == [RegisterID, RegisterID]

def emitShifts(operands, shiftCount)

$asm.puts "slli #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}, #{shiftCount}"

$asm.puts "sext.w #{operands[1].riscv64Operand}, #{operands[1].riscv64Operand}"

$asm.puts "srai #{operands[1].riscv64Operand}, #{operands[1].riscv64Operand}, #{shiftCount}"

end

case [fromSize, toSize, extensionType]

when [:b, :w, :sign], [:b, :d, :sign]

emitShifts(operands, 24)

riscv64EmitRegisterMask(operands[1], toSize)

when [:h, :w, :sign], [:h, :d, :sign]

emitShifts(operands, 16)

riscv64EmitRegisterMask(operands[1], toSize)

when [:w, :d, :sign]

$asm.puts "sext.w #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"

when [:w, :d, :zero]

$asm.puts "slli #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}, 32"

$asm.puts "srli #{operands[1].riscv64Operand}, #{operands[1].riscv64Operand}, 32"

else

raise "Unsupported bit-extension operation"

end

end

def riscv64EmitFPLoad(operands, loadInstruction)

case riscv64OperandTypes(operands)

when [Address, FPRegisterID]

if operands[0].riscv64RequiresLoad

operands[0].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{loadInstruction} #{operands[1].riscv64Operand}, 0(x31)"

else

$asm.puts "#{loadInstruction} #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"

end

when [BaseIndex, FPRegisterID]

operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)

$asm.puts "#{loadInstruction} #{operands[1].riscv64Operand}, 0(x31)"

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitFPStore(operands, storeInstruction)

case riscv64OperandTypes(operands)

when [FPRegisterID, Address]

if operands[1].riscv64RequiresLoad

operands[1].riscv64Load(RISCV64ScratchRegister.x31)

$asm.puts "#{storeInstruction} #{operands[0].riscv64Operand}, 0(x31)"

else

$asm.puts "#{storeInstruction} #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

end

when [FPRegisterID, BaseIndex]

operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)

$asm.puts "#{storeInstruction} #{operands[0].riscv64Operand}, 0(x31)"

else

riscv64RaiseMismatchedOperands(operands)

end

end

def riscv64EmitFPOperation(operands, operation)

case riscv64OperandTypes(operands)

when [FPRegisterID, FPRegisterID, FPRegisterID]

$asm.puts "#{operation} #{operands[2].riscv64Operand}, #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"

when [FPRegisterID, FPRegisterID]

$asm.puts "#{operation} #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"

else