diff --git a/Benchy_Sump_LogicAnalyzer_Standalone/circuit/PSL_Papilio_DUO_LX9.xise b/Benchy_Sump_LogicAnalyzer_Standalone/circuit/PSL_Papilio_DUO_LX9.xise index 38dda02..dde92d6 100644 --- a/Benchy_Sump_LogicAnalyzer_Standalone/circuit/PSL_Papilio_DUO_LX9.xise +++ b/Benchy_Sump_LogicAnalyzer_Standalone/circuit/PSL_Papilio_DUO_LX9.xise @@ -1194,12 +1194,12 @@ - - + + diff --git a/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.sym b/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.sym new file mode 100644 index 0000000..93f1188 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.sym @@ -0,0 +1,19 @@ + + + BLOCK + 2016-1-22T17:22:29 + + + + + + + + + + + + + + + diff --git a/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd b/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd new file mode 100644 index 0000000..1609a98 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd @@ -0,0 +1,193 @@ +---------------------------------------------------------------------------------- +-- Papilio_Logic.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Logic Analyzer top level module. It connects the core with the hardware +-- dependent IO modules and defines all la_inputs and outputs that represent +-- phyisical pins of the fpga. +-- +-- It defines two constants FREQ and RATE. The first is the clock frequency +-- used for receiver and transmitter for generating the proper baud rate. +-- The second defines the speed at which to operate the serial port. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity BENCHY_wb_SumpBlaze_LogicAnalyzer32 is + port( + wishbone_in : in std_logic_vector(100 downto 0); + wishbone_out : out std_logic_vector(100 downto 0); + wishbone_slot_video_in : out std_logic_vector(100 downto 0); + wishbone_slot_video_out : in std_logic_vector(100 downto 0); + la : in std_logic_vector(31 downto 0) + ); +end BENCHY_wb_SumpBlaze_LogicAnalyzer32; + +architecture behavioral of BENCHY_wb_SumpBlaze_LogicAnalyzer32 is + + signal core_reset: std_logic; +--signals for unpacking the wishbone array + signal wb_clk_i: std_logic; -- Wishbone clock + signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) + signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) + signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) + signal wb_we_i: std_logic; -- Wishbone write enable signal + signal wb_cyc_i: std_logic; -- Wishbone cycle signal + signal wb_stb_i: std_logic; -- Wishbone strobe signal + + signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) + signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal + signal wb_inta_o: std_logic; + signal id: std_logic_vector(15 downto 0); -- ZPUino Wishbone id +--end signals for unpacking the wishbone array + +--signals for unpacking DMA array + signal mi_wb_dat_i: std_logic_vector(31 downto 0); + signal mi_wb_dat_o: std_logic_vector(31 downto 0); + signal mi_wb_adr_o: std_logic_vector(27 downto 0); + signal mi_wb_sel_o: std_logic_vector(3 downto 0); + signal mi_wb_cti_o: std_logic_vector(2 downto 0); + signal mi_wb_we_o: std_logic; + signal mi_wb_cyc_o: std_logic; + signal mi_wb_stb_o: std_logic; + signal mi_wb_ack_i: std_logic; + signal mi_wb_stall_i: std_logic; +--end signals for unpacking DMA array + + signal cmd : std_logic_vector (39 downto 0); + signal memoryIn, memoryOut : std_logic_vector (35 downto 0); + signal output, la_input : std_logic_vector (31 downto 0); + signal clock : std_logic; + signal read, write, execute, send, busy, resetInternal, reset, run : std_logic; + signal tx_bytes : integer range 0 to 4; + signal extClockIn, extTriggerIn : std_logic; + signal armed: std_logic_vector(3 downto 0); + + begin +-- Unpack the wishbone array into signals so the modules code is not confusing. + wb_clk_i <= wishbone_in(61); + wb_rst_i <= wishbone_in(60); + wb_dat_i <= wishbone_in(59 downto 28); + wb_adr_i <= wishbone_in(27 downto 3); + wb_we_i <= wishbone_in(2); + wb_cyc_i <= wishbone_in(1); + wb_stb_i <= wishbone_in(0); + + wishbone_out(49 downto 34) <= id; + wishbone_out(33 downto 2) <= wb_dat_o; + wishbone_out(1) <= wb_ack_o; + wishbone_out(0) <= wb_inta_o; +-- End unpacking Wishbone array + +--Unpack DMA array + wishbone_slot_video_in(31 downto 0) <= mi_wb_dat_o; + wishbone_slot_video_in(77 downto 50) <= mi_wb_adr_o; + wishbone_slot_video_in(100) <= mi_wb_we_o; + wishbone_slot_video_in(99) <= mi_wb_cyc_o; + wishbone_slot_video_in(98) <= mi_wb_stb_o; + + mi_wb_dat_i <= wishbone_slot_video_out(31 downto 0); + mi_wb_ack_i <= wishbone_slot_video_out(100); + mi_wb_stall_i <= wishbone_slot_video_out(99); +--End upack DMA array + + --la_input <= (others => '0'); + la_input <= la; + +-- adc_cs_n <= '1'; --Disables ADC + + extClockIn <= '0'; --External clock disabled + extTriggerIn <= '0'; --External trigger disabled + + clock <= wb_clk_i; + + id <= x"08" & x"22"; -- Vendor: ZPUIno Product: Sump Logic Analyzer + + Inst_core: entity work.core + port map( + clock => clock, + cmd => cmd, + execute => execute, + la_input => la_input, + la_inputClock => extClockIn, + output => output, + outputSend => send, + outputBusy => '1', + memoryIn => memoryIn, + memoryOut => memoryOut, + memoryRead => read, + memoryWrite => write, + run => run, + armed => armed, + extTriggerIn => extTriggerIn, + extTriggerOut => open, + extClockOut => open, + armLED => open, + triggerLED => open, +-- resetInternal => resetInternal, + reset => core_reset, + tx_bytes => tx_bytes + ); + + SumpWb_Inst: entity work.sump_wishbone + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + -- Main wishbone signals + wb_dat_i => wb_dat_i, + wb_adr_i => wb_adr_i, + wb_we_i => wb_we_i, + wb_cyc_i => wb_cyc_i, + wb_stb_i => wb_stb_i, + + wb_dat_o => wb_dat_o, + wb_ack_o => wb_ack_o, + + -- Signals to/from core + -- clock => clock, -- not used. + reset => core_reset, + write => write, + memoryOut => memoryOut(31 downto 0), + run => run, + send => send, + cmd => cmd, + armed => armed, + execute => execute, + -- DMA + mi_wb_dat_i => mi_wb_dat_i, + mi_wb_dat_o => mi_wb_dat_o, + mi_wb_adr_o => mi_wb_adr_o, + mi_wb_sel_o => mi_wb_sel_o, + mi_wb_cti_o => mi_wb_cti_o, + mi_wb_we_o => mi_wb_we_o, + mi_wb_cyc_o => mi_wb_cyc_o, + mi_wb_stb_o => mi_wb_stb_o, + mi_wb_ack_i => mi_wb_ack_i, + mi_wb_stall_i => mi_wb_stall_i + ); + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/BRAM6k36bit.vhd b/libraries/Wishbone_Sump_LA/BRAM6k36bit.vhd new file mode 100644 index 0000000..8b2acac --- /dev/null +++ b/libraries/Wishbone_Sump_LA/BRAM6k36bit.vhd @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------------- +-- BRAM8k32bit.vhd +-- +-- Copyright (C) 2007 Jonas Diemer +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Single Ported RAM, 32bit wide, 8k deep. +-- +-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are +-- concatenated to form a 32bit wide, 8k deep RAM. +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity BRAM6k36bit is + Port ( CLK : in STD_LOGIC; + ADDR : in STD_LOGIC_VECTOR (12 downto 0); + WE : in STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR (35 downto 0); + DIN : in STD_LOGIC_VECTOR (35 downto 0)); +end BRAM6k36bit; + +architecture Behavioral of BRAM6k36bit is + + type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range); + signal RAMBlDOut : RAMBlDOut_Type; + + --signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0); + signal WEB : std_logic_vector(11 downto 0); +begin + + +-- BlockRAMS: for i in 0 to 11 generate +-- RAMB16_S2_inst : RAMB16_S2 +-- generic map ( +-- INIT => X"0", -- Value of output RAM registers at startup +-- SRVAL => X"0", -- Ouput value upon SSR assertion +-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE +-- ) +-- port map ( +-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output +-- ADDR => ADDR, -- 13-bit Address Input +-- CLK => CLK, -- Clock +-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input +-- EN => '1', -- RAM Enable Input +-- SSR => '0', -- Synchronous Set/Reset Input +-- WE => WE -- Write Enable Input +-- ); +-- end generate; + + BlockRAMS: for i in 0 to 11 generate + RAMB16_S36_inst : RAMB16_S36 + generic map ( + INIT => X"0", -- Value of output RAM registers at startup + SRVAL => X"0", -- Ouput value upon SSR assertion + WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + port map ( + DO => RAMBlDOut(i)(31 downto 0), + DOP => RAMBlDOut(i)(35 downto 32), + ADDR => ADDR(8 downto 0), -- 8-bit Address Input + CLK => CLK, -- Clock + DI => DIN(31 downto 0), + DIP => DIN(35 downto 32), + EN => '1', -- RAM Enable Input + SSR => '0', -- Synchronous Set/Reset Input + WE => WEB(i) -- Write Enable Input + ); + end generate; + +WEB_Dcd:for i in WEB'range generate + WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0'; +end generate ; + +dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9))); + +end Behavioral; + diff --git a/libraries/Wishbone_Sump_LA/BRAM8k36bit.vhd b/libraries/Wishbone_Sump_LA/BRAM8k36bit.vhd new file mode 100644 index 0000000..d912994 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/BRAM8k36bit.vhd @@ -0,0 +1,78 @@ +-- +-- Generic dual-port RAM (symmetric) +-- +-- Copyright 2011 Alvaro Lopes +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity BRAM8k36bit is + generic ( + address_bits: integer := 13; + data_bits: integer := 36 + ); + port ( + clka: in std_logic; +-- ena: in std_logic; + wea: in std_logic; + addra: in std_logic_vector(address_bits-1 downto 0); + dina: in std_logic_vector(data_bits-1 downto 0); + douta: out std_logic_vector(data_bits-1 downto 0) + ); + +end entity BRAM8k36bit; + +architecture behave of BRAM8k36bit is + + + subtype RAM_WORD is STD_LOGIC_VECTOR (data_bits-1 downto 0); + + type RAM_TABLE is array (0 to (2**address_bits) - 1) of RAM_WORD; + shared variable RAM: RAM_TABLE; + signal ena : std_logic; + +begin + ena <= '1'; + process (clka) + begin + if rising_edge(clka) then + if ena='1' then + if wea='1' then + RAM( conv_integer(addra) ) := dina; + end if; + douta <= RAM(conv_integer(addra)) ; + end if; + end if; + end process; + +end behave; diff --git a/libraries/Wishbone_Sump_LA/Chip_Designer.xise b/libraries/Wishbone_Sump_LA/Chip_Designer.xise new file mode 100644 index 0000000..8f1e0ad --- /dev/null +++ b/libraries/Wishbone_Sump_LA/Chip_Designer.xise @@ -0,0 +1,1081 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/libraries/Wishbone_Sump_LA/Chip_Designer/Default.wcfg b/libraries/Wishbone_Sump_LA/Chip_Designer/Default.wcfg new file mode 100644 index 0000000..598e08c --- /dev/null +++ b/libraries/Wishbone_Sump_LA/Chip_Designer/Default.wcfg @@ -0,0 +1,371 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Wishbone Bus + label + + + Decoder + label + + + Top Level + label + + + Core + label + + + Trigger + label + + + Memory + label + + + armed[3:0] + armed[3:0] + + + wishbone_in[100:0] + wishbone_in[100:0] + + + wishbone_out[100:0] + wishbone_out[100:0] + + + wishbone_slot_video_in[100:0] + wishbone_slot_video_in[100:0] + + + wishbone_slot_video_out[100:0] + wishbone_slot_video_out[100:0] + + + la[31:0] + la[31:0] + + + core_reset + core_reset + + + wb_clk_i + wb_clk_i + + + wb_rst_i + wb_rst_i + + + wb_dat_i[31:0] + wb_dat_i[31:0] + + + wb_adr_i[26:2] + wb_adr_i[26:2] + + + wb_we_i + wb_we_i + + + wb_cyc_i + wb_cyc_i + + + wb_stb_i + wb_stb_i + + + wb_dat_o[31:0] + wb_dat_o[31:0] + + + wb_ack_o + wb_ack_o + + + wb_inta_o + wb_inta_o + + + id[15:0] + id[15:0] + + + mi_wb_dat_i[31:0] + mi_wb_dat_i[31:0] + + + mi_wb_dat_o[31:0] + mi_wb_dat_o[31:0] + + + mi_wb_adr_o[27:0] + mi_wb_adr_o[27:0] + + + mi_wb_sel_o[3:0] + mi_wb_sel_o[3:0] + + + mi_wb_cti_o[2:0] + mi_wb_cti_o[2:0] + + + mi_wb_we_o + mi_wb_we_o + + + mi_wb_cyc_o + mi_wb_cyc_o + + + mi_wb_stb_o + mi_wb_stb_o + + + mi_wb_ack_i + mi_wb_ack_i + + + mi_wb_stall_i + mi_wb_stall_i + + + cmd[39:0] + cmd[39:0] + HEXRADIX + + + memoryin[35:0] + memoryin[35:0] + + + memoryout[35:0] + memoryout[35:0] + HEXRADIX + + + output[31:0] + output[31:0] + + + la_input[31:0] + la_input[31:0] + + + clock + clock + + + read + read + + + write + write + + + execute + execute + + + send + send + + + busy + busy + + + resetinternal + resetinternal + + + reset + reset + + + run + run + + + tx_bytes + tx_bytes + + + extclockin + extclockin + + + exttriggerin + exttriggerin + + + armed[3:0] + armed[3:0] + + + Decoder + label + + opcode[7:0] + opcode[7:0] + + + execute + execute + + + clock + clock + + + wrtrigmask[3:0] + wrtrigmask[3:0] + + + wrtrigval[3:0] + wrtrigval[3:0] + + + wrtrigcfg[3:0] + wrtrigcfg[3:0] + + + wrspeed + wrspeed + + + wrsize + wrsize + + + wrflags + wrflags + + + arm + arm + + + reset + reset + + + abort + abort + + + ident + ident + + + meta + meta + + + exe + exe + + + exereg + exereg + + + + trigger + label + + la_input[31:0] + la_input[31:0] + + + la_inputready + la_inputready + + + data[31:0] + data[31:0] + + + clock + clock + + + reset + reset + + + wrmask[3:0] + wrmask[3:0] + + + wrvalue[3:0] + wrvalue[3:0] + + + wrconfig[3:0] + wrconfig[3:0] + + + arm + arm + + + demuxed + demuxed + + + run + run + + + armed[3:0] + armed[3:0] + + + exttriggerin + exttriggerin + + + stagematch[3:0] + stagematch[3:0] + + + stagerun[4:0] + stagerun[4:0] + + + levelreg[1:0] + levelreg[1:0] + + + diff --git a/libraries/Wishbone_Sump_LA/Chip_Designer/Papilio_DUO_LX9.ut b/libraries/Wishbone_Sump_LA/Chip_Designer/Papilio_DUO_LX9.ut new file mode 100644 index 0000000..d1824d0 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/Chip_Designer/Papilio_DUO_LX9.ut @@ -0,0 +1,30 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g Reset_on_err:No +-g ConfigRate:2 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:1 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:Yes +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 diff --git a/libraries/Wishbone_Sump_LA/Chip_Designer/Simulate_Your_Chip_Design.vhd b/libraries/Wishbone_Sump_LA/Chip_Designer/Simulate_Your_Chip_Design.vhd new file mode 100644 index 0000000..b544642 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/Chip_Designer/Simulate_Your_Chip_Design.vhd @@ -0,0 +1,211 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity Simulate_Your_CCL_Design is +end entity; + + +architecture sim of Simulate_Your_CCL_Design is + + constant period: time := 10 ns; + + signal clk: std_logic := '1'; + signal rst: std_logic := '0'; + + COMPONENT BENCHY_wb_SumpBlaze_LogicAnalyzer32 + PORT( + clk_32Mhz : IN std_logic; + wishbone_in : IN std_logic_vector(100 downto 0); + la : IN std_logic_vector(31 downto 0); + wishbone_out : OUT std_logic_vector(100 downto 0); + wishbone_slot_video_in : out std_logic_vector(100 downto 0); + wishbone_slot_video_out : in std_logic_vector(100 downto 0); + reset : IN std_logic; + tx : OUT std_logic + ); + END COMPONENT; + + signal wb_dat_o: std_logic_vector(31 downto 0); + signal wb_dat_i: std_logic_vector(31 downto 0); + signal wb_adr_i: std_logic_vector(31 downto 0); + signal wb_we_i: std_logic := '0'; + signal wb_cyc_i: std_logic := '0'; + signal wb_stb_i: std_logic := '0'; + signal wb_ack_o: std_logic; + + signal wb_in: std_logic_vector(100 downto 0); + signal wb_out: std_logic_vector(100 downto 0); + + signal wb_v_out: std_logic_vector(100 downto 0); + signal wb_v_in: std_logic_vector(100 downto 0); + + signal wb_dat_o_dly: std_logic_vector(31 downto 0); + + --Define your Register addresses here + constant REGISTER0_ADDR: std_logic_vector(31 downto 0) := x"00000000"; + constant REGISTER1_ADDR: std_logic_vector(31 downto 0) := x"00000001"; + constant REGISTER2_ADDR: std_logic_vector(31 downto 0) := x"00000002"; + + --Define your external connections here + signal count : std_logic_vector(31 downto 0); + signal count_en : std_logic; + +begin + + clk <= not clk after period/2; + + -- Reset + process + begin + wait for 5 ns; + rst <= '1'; + wait for 20 ns; + rst <= '0'; + wait; + end process; + + process(clk, rst) + begin + if rst = '1' then + count <= X"00000000"; + elsif rising_edge(clk) then + if count_en = '1' then + count <= count + 1; + end if; + end if; + end process; + + Inst_BENCHY_wb_SumpBlaze_LogicAnalyzer32: BENCHY_wb_SumpBlaze_LogicAnalyzer32 PORT MAP( + clk_32Mhz => clk, + wishbone_in => wb_in, + wishbone_out => wb_out, + wishbone_slot_video_in => wb_v_in, + wishbone_slot_video_out => wb_v_out, +-- la => "10101010101010101010101010101010", + la => count, + reset => rst, + tx => OPEN + ); + + wb_in(61) <= clk; + wb_in(60) <= rst; + wb_in(59 downto 28) <= wb_dat_i; + wb_in(27 downto 3) <= wb_adr_i(24 downto 0); + wb_in(2) <= wb_we_i; + wb_in(1) <= wb_cyc_i; + wb_in(0) <= wb_stb_i; + wb_dat_o <= wb_out(33 downto 2); + wb_ack_o <= wb_out(1); + --wb_inta_o <= wb_out(0); + + -- Delayed read + wb_dat_o_dly<=transport wb_dat_o after 1 ps; + + process + procedure wbwrite(a: in std_logic_vector(31 downto 0); d: in std_logic_vector(31 downto 0) ) is + begin + wb_cyc_i<='1'; + wb_stb_i<='1'; + wb_we_i<='1'; + wb_dat_i<=d; + wb_adr_i<=a; + wait until rising_edge(clk); + if wb_ack_o /= '1' then + wait until wb_ack_o='1'; + end if; + wait until rising_edge(clk); + wb_cyc_i<='0'; + wb_stb_i<='0'; + wb_we_i <='0'; + end procedure; + + procedure wbread( a: in std_logic_vector(31 downto 0); d: out std_logic_vector(31 downto 0)) is + begin + wb_cyc_i<='1'; + wb_stb_i<='1'; + wb_we_i<='0'; + wb_adr_i<=a; + wait until rising_edge(clk); + if wb_ack_o /= '1' then + wait until wb_ack_o='1'; + end if; + wait until rising_edge(clk); + d := wb_dat_o_dly; + wb_cyc_i<='0'; + wb_stb_i<='0'; + wb_we_i <='0'; + end procedure; + + + variable r : std_logic_vector(31 downto 0); + + begin + + wait until rst='1'; + wait until rst='0'; + count_en <= '1'; + wait until rising_edge(clk); + + + -- This is where you should start providing your stimulus to test your design. + + -- Test register R/W + -- Read and write to the Wishbone Bus + -- Write a reset + wbwrite( REGISTER1_ADDR, x"00000000"); + -- Execute + wbwrite( REGISTER0_ADDR, x"00000001"); + wbwrite( REGISTER0_ADDR, x"00000000"); + wait for 100 ns; + -- Init all settings + + -- Trigger Masks + wbwrite( REGISTER1_ADDR, x"000000C0"); + wbwrite( REGISTER2_ADDR, x"00000000"); + -- Execute + wbwrite( REGISTER0_ADDR, x"00000001"); + wbwrite( REGISTER0_ADDR, x"00000000"); + -- Trigger Values + wbwrite( REGISTER1_ADDR, x"000000C1"); + wbwrite( REGISTER2_ADDR, x"00000000"); + -- Execute + wbwrite( REGISTER0_ADDR, x"00000001"); + wbwrite( REGISTER0_ADDR, x"00000000"); + -- Trigger Configuration + wbwrite( REGISTER1_ADDR, x"000000C2"); + wbwrite( REGISTER2_ADDR, x"08000000"); + -- Execute + wbwrite( REGISTER0_ADDR, x"00000001"); + wbwrite( REGISTER0_ADDR, x"00000000"); + -- Set Divider + wbwrite( REGISTER1_ADDR, x"00000080"); + wbwrite( REGISTER2_ADDR, x"00000000"); + -- Execute + wbwrite( REGISTER0_ADDR, x"00000001"); + wbwrite( REGISTER0_ADDR, x"00000000"); + -- Set Read and Delay Count + wbwrite( REGISTER1_ADDR, x"00000081"); + wbwrite( REGISTER2_ADDR, x"01ff01ff"); + -- Execute + wbwrite( REGISTER0_ADDR, x"00000001"); + wbwrite( REGISTER0_ADDR, x"00000000"); + -- Set Flags + wbwrite( REGISTER1_ADDR, x"00000082"); + wbwrite( REGISTER2_ADDR, x"00000002"); + -- Execute + wbwrite( REGISTER0_ADDR, x"00000001"); + wbwrite( REGISTER0_ADDR, x"00000000"); + -- Arm the trigger + wbwrite( REGISTER1_ADDR, x"00000001"); + -- Execute + wbwrite( REGISTER0_ADDR, x"00000001"); + wbwrite( REGISTER0_ADDR, x"00000000"); + + wait for 80 us; + report "Finsihed" severity failure; + end process; + + +end sim; diff --git a/libraries/Wishbone_Sump_LA/Chip_Designer/Wishbone_to_Registers.vhd b/libraries/Wishbone_Sump_LA/Chip_Designer/Wishbone_to_Registers.vhd new file mode 100644 index 0000000..92a8bdb --- /dev/null +++ b/libraries/Wishbone_Sump_LA/Chip_Designer/Wishbone_to_Registers.vhd @@ -0,0 +1,146 @@ +---------------------------------------------------------------------------------- +-- Company: Gadget Factory +-- Engineer: Alvaro Lopes +-- +-- Create Date: 13:56:50 12/10/2013 +-- Design Name: +-- Module Name: Wishbone_Symbol_Example - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- This is an example template to use for your own Wishbone Peripherals. +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- This example uses asynchronous outputs. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity Wishbone_to_Registers is + port ( + wishbone_in : in std_logic_vector(61 downto 0); + wishbone_out : out std_logic_vector(33 downto 0); + + --Registers + register0_in : in std_logic_vector(31 downto 0); -- Register 0 (32 bits) + register0_out : out std_logic_vector(31 downto 0); -- Register 0 (32 bits) + register1_in : in std_logic_vector(31 downto 0); -- Register 0 (32 bits) + register1_out : out std_logic_vector(31 downto 0); -- Register 0 (32 bits) + register2_in : in std_logic_vector(31 downto 0); -- Register 0 (32 bits) + register2_out : out std_logic_vector(31 downto 0) -- Register 0 (32 bits) + ); +end entity Wishbone_to_Registers; + + + +architecture rtl of Wishbone_to_Registers is + +--Define your registers here +-- signal register0: std_logic_vector(31 downto 0); -- Register 0 (32 bits) +-- signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) +-- signal register2: std_logic_vector(7 downto 0); -- Register 2 (8 bits) + +--Wishbone signals - Don't touch. + signal wb_clk_i: std_logic; -- Wishbone clock + signal wb_rst_i: std_logic; -- Wishbone reset (synchronous) + signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) + signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) + signal wb_we_i: std_logic; -- Wishbone write enable signal + signal wb_cyc_i: std_logic; -- Wishbone cycle signal + signal wb_stb_i: std_logic; -- Wishbone strobe signal + + signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) + signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal + signal wb_inta_o: std_logic; +begin +-- Unpack the wishbone array into signals so the modules code is not confusing. - Don't touch. + wb_clk_i <= wishbone_in(61); + wb_rst_i <= wishbone_in(60); + wb_dat_i <= wishbone_in(59 downto 28); + wb_adr_i <= wishbone_in(27 downto 3); + wb_we_i <= wishbone_in(2); + wb_cyc_i <= wishbone_in(1); + wb_stb_i <= wishbone_in(0); + + wishbone_out(33 downto 2) <= wb_dat_o; + wishbone_out(1) <= wb_ack_o; + wishbone_out(0) <= wb_inta_o; +-- End unpacking Wishbone signals + + -- Asynchronous acknowledge + + wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0'; + + -- Multiplex the data output (asynchronous) + + --This is for a Wishbone read + process(register0_in,register1_in,register2_in, wb_adr_i) + begin + + -- Multiplex the read depending on the address. Use only the 2 lowest bits of addr + + case wb_adr_i(3 downto 2) is + when "00" => + wb_dat_o <= register0_in; -- Output register0 + when "01" => + wb_dat_o <= register1_in; -- Output register1 + when "10" => + wb_dat_o <= register2_in; -- Output register1 + --wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero + --wb_dat_o(7 downto 0) <= register2; -- since register2 only has 8 bits + when others => + wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses + end case; + + end process; + + + --This is for a Wishbone write + process(wb_clk_i) + begin + + if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock + + if wb_rst_i='1' then + -- Reset request, put register1 and register2 with zeroes, + -- put register 3 with binary 10101010b + +-- register0 <= (others => '0'); +-- register1 <= (others => '0'); +-- register2 <= "10101010"; + + else -- Not reset + + -- Check if someone is writing + if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then + -- Yes, it's a write. See for which register based on address + case wb_adr_i(3 downto 2) is + when "00" => + register0_out <= wb_dat_i; -- Set register0 + when "01" => + register1_out <= wb_dat_i; -- Set register1 + when "10" => + register2_out <= wb_dat_i; -- Only lower 8 bits for register2 + when others => + null; -- Nothing to do for other addresses + end case; + + end if; + + end if; + + end if; + + end process; + +end rtl; + diff --git a/libraries/Wishbone_Sump_LA/Edit_Your_Chip_Design.sch b/libraries/Wishbone_Sump_LA/Edit_Your_Chip_Design.sch new file mode 100644 index 0000000..655e60b --- /dev/null +++ b/libraries/Wishbone_Sump_LA/Edit_Your_Chip_Design.sch @@ -0,0 +1,34 @@ + + + + + + + + + + 2016-1-18T23:38:12 + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/Mem_Gen_36bit.vhd b/libraries/Wishbone_Sump_LA/Mem_Gen_36bit.vhd new file mode 100644 index 0000000..844bb7f --- /dev/null +++ b/libraries/Wishbone_Sump_LA/Mem_Gen_36bit.vhd @@ -0,0 +1,87 @@ +---------------------------------------------------------------------------------- +-- Mem_Gen_36bit.vhd +-- +-- Copyright (C) 2013 Jack Gassett +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://papilio.cc +-- +-- Single Ported RAM, 36bit wide, depth is configurable. +-- +-- Set the depth by setting the brams generic variable. +-- Depth will be 512 x brams so 12 brams will be 6K depth. +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity Mem_Gen_36bit is + generic ( + brams: integer := 12 + ); + Port ( CLK : in STD_LOGIC; + ADDR : in STD_LOGIC_VECTOR (13 downto 0); + WE : in STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR (35 downto 0); + DIN : in STD_LOGIC_VECTOR (35 downto 0)); +end Mem_Gen_36bit; + +architecture Behavioral of Mem_Gen_36bit is + + --type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range); + type RAMBlDOut_Type is array(31 downto 0) of std_logic_vector(dout'range); + signal RAMBlDOut : RAMBlDOut_Type; + signal WEB : std_logic_vector((brams-1) downto 0); + +begin + BlockRAMS: for i in 0 to (brams-1) generate + RAMB16_S36_inst : RAMB16_S36 + generic map ( + INIT => X"0", -- Value of output RAM registers at startup + SRVAL => X"0", -- Ouput value upon SSR assertion + WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + port map ( + DO => RAMBlDOut(i)(31 downto 0), + DOP => RAMBlDOut(i)(35 downto 32), + ADDR => ADDR(8 downto 0), -- 8-bit Address Input + CLK => CLK, -- Clock + DI => DIN(31 downto 0), + DIP => DIN(35 downto 32), + EN => '1', -- RAM Enable Input + SSR => '0', -- Synchronous Set/Reset Input + WE => WEB(i) -- Write Enable Input + ); + end generate; + +WEB_Dcd:for i in WEB'range generate + WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0'; +end generate ; + +dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9))); + +end Behavioral; + diff --git a/libraries/Wishbone_Sump_LA/async_fifo.vhd b/libraries/Wishbone_Sump_LA/async_fifo.vhd new file mode 100644 index 0000000..62529b8 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/async_fifo.vhd @@ -0,0 +1,205 @@ +-- +-- General-purpose Async FIFO for ZPUINO +-- +-- Copyright 2013 Alvaro Lopes +-- +-- Version: 1.0 +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use IEEE.std_logic_unsigned.all; + + +entity async_fifo is + generic ( + address_bits: integer := 11; + data_bits: integer := 8; + threshold: integer + ); + port ( + clk_r: in std_logic; + clk_w: in std_logic; + arst: in std_logic; + + wr: in std_logic; + rd: in std_logic; + + write: in std_logic_vector(data_bits-1 downto 0); + read : out std_logic_vector(data_bits-1 downto 0); + + almost_full: out std_logic; + empty: out std_logic + ); +end entity async_fifo; + + +architecture behave of async_fifo is + + component generic_dp_ram is + generic ( + address_bits: integer := 8; + data_bits: integer := 32 + ); + port ( + clka: in std_logic; + ena: in std_logic; + wea: in std_logic; + addra: in std_logic_vector(address_bits-1 downto 0); + dia: in std_logic_vector(data_bits-1 downto 0); + doa: out std_logic_vector(data_bits-1 downto 0); + clkb: in std_logic; + enb: in std_logic; + web: in std_logic; + addrb: in std_logic_vector(address_bits-1 downto 0); + dib: in std_logic_vector(data_bits-1 downto 0); + dob: out std_logic_vector(data_bits-1 downto 0) + ); + end component; + + signal rdptr: unsigned(address_bits-1 downto 0); + signal wrptr: unsigned(address_bits-1 downto 0); + signal rdptr_in_clkw_1: unsigned(address_bits-1 downto 0); + signal rdptr_in_clkw_2: unsigned(address_bits-1 downto 0); + + signal wrptr_in_clkr_1: unsigned(address_bits-1 downto 0); + signal wrptr_in_clkr_2: unsigned(address_bits-1 downto 0); + + constant nothing: std_logic_vector(data_bits-1 downto 0) := (others => 'X'); + constant threshcmp: unsigned(address_bits-1 downto 0) := to_unsigned( threshold, address_bits); + signal rst_w, rst_w_1, rst_r, rst_r_1: std_logic; + +begin + + process(arst,clk_r,clk_w) + begin + if arst='1' then + rst_w_1<='1'; + rst_w <='1'; + rst_r_1<='1'; + rst_r <='1'; + else + if rising_edge(clk_r) then + rst_r_1<='0'; + rst_r<=rst_r_1; + end if; + if rising_edge(clk_w) then + rst_w_1<='0'; + rst_w<=rst_w_1; + end if; + end if; + end process; + + process(rdptr_in_clkw_2, wrptr, rst_r) + variable delta: unsigned(address_bits-1 downto 0); + begin + delta := wrptr - rdptr_in_clkw_2; + if (delta>threshcmp) then + almost_full <= '1'; + else + almost_full <= '0'; + end if; + if rst_r='1' then + almost_full <= '0'; + end if; + end process; + + + process(clk_w, rst_w) + begin + if rst_w='1' then + rdptr_in_clkw_2 <= ( others => '0'); + rdptr_in_clkw_1 <= ( others => '0'); + elsif rising_edge(clk_w) then + rdptr_in_clkw_2 <= rdptr_in_clkw_1; + rdptr_in_clkw_1 <= rdptr; + end if; + end process; + + process(clk_r) + begin + if rst_r='1' then + wrptr_in_clkr_2 <= ( others => '0'); + wrptr_in_clkr_1 <= ( others => '0'); + elsif rising_edge(clk_r) then + wrptr_in_clkr_2 <= wrptr_in_clkr_1; + wrptr_in_clkr_1 <= wrptr; + end if; + end process; + + empty <= '1' when wrptr_in_clkr_2=rdptr or rst_r='1' else '0'; + + mem: generic_dp_ram + generic map ( + address_bits => address_bits, + data_bits => data_bits + ) + port map ( + clka => clk_r, + ena => rd, + doa => read, + wea => '0', + dia => nothing, + addra => std_logic_vector(rdptr), + + clkb => clk_w, + enb => wr, + web => wr, + dib => write, + dob => open, + addrb => std_logic_vector(wrptr) + ); + + -- Write process + process(clk_w, rst_w) + begin + if rst_w='1' then + wrptr <= (others => '0'); + elsif rising_edge(clk_w) then + if wr='1' then + wrptr <= wrptr + 1; + end if; + end if; + end process; + + -- Read process + process(clk_r, rst_r) + begin + if rst_r='1' then + rdptr <= (others => '0'); + elsif rising_edge(clk_r) then + if rd='1' then + rdptr <= rdptr + 1; + end if; + end if; + end process; + + +end behave; diff --git a/libraries/Wishbone_Sump_LA/bscan_spi_spartan6.vhd b/libraries/Wishbone_Sump_LA/bscan_spi_spartan6.vhd new file mode 100644 index 0000000..9d2b9c1 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/bscan_spi_spartan6.vhd @@ -0,0 +1,169 @@ +---------------------------------------------------------------------------------- +-- Company: - +-- Engineer: Jochem Govers +-- +-- Create Date: 13:00:21 05/13/2010 +-- Design Name: +-- Module Name: bscan_spi - Behavioral +-- Project Name: +-- Target Devices: Spartan 3e 100/250/500 VQ100 +-- Tool versions: ISE 11.4 +-- Description: a simple implementation of the BSCAN_SPARTAN3E module to access +-- external SPI Flash via JTAG. +-- +-- Dependencies: None +-- +-- Revision: +-- Revision 0.01 - File Created +-- Revision 0.02 - Added header recognation of header and TDO alignment (requires +-- 4 bytes of preamble and 1 byte post). Based on design +-- of xc3sprog (changes made to CS handling and header length). +-- Additional Comments: tested on Butterfly One with xc3s250e +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity bscan_spi is + Port ( SPI_MISO : in STD_LOGIC; + SPI_MOSI : inout STD_LOGIC; + SPI_CS : inout STD_LOGIC; + SPI_SCK : inout STD_LOGIC); +end bscan_spi; + +architecture Behavioral of bscan_spi is +--component BSCAN_SPARTAN6 +-- port (CAPTURE : out STD_ULOGIC; +-- DRCK1 : out STD_ULOGIC; +-- DRCK2 : out STD_ULOGIC; +-- RESET : out STD_ULOGIC; +-- SEL1 : out STD_ULOGIC; +-- SEL2 : out STD_ULOGIC; +-- SHIFT : out STD_ULOGIC; +-- TDI : out STD_ULOGIC; +-- UPDATE : out STD_ULOGIC; +-- TDO1 : in STD_ULOGIC; +-- TDO2 : in STD_ULOGIC); +-- end component; + + signal user_CAPTURE : std_ulogic; + signal user_DRCK1 : std_ulogic; + signal user_DRCK2 : std_ulogic; + signal user_RESET : std_ulogic; + signal user_SEL1 : std_ulogic; + signal user_SEL2 : std_ulogic; + signal user_SHIFT : std_ulogic; + signal user_TDI : std_ulogic; + signal user_UPDATE : std_ulogic; + signal user_TDO1 : std_ulogic; + signal user_TDO2 : std_ulogic; + + signal tdi_mem : std_logic_vector(31 downto 0); + signal tdo_mem : std_logic_vector(7 downto 0); + signal len : std_logic_vector(15 downto 0); + signal CS_GO_PREP : std_logic; + signal CS_GO : std_logic; + signal CS_STOP_PREP : std_logic; + signal CS_STOP : std_logic; + signal reset : std_logic; + signal have_header : std_logic; +begin + +reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); + +BS : BSCAN_SPARTAN6 + port map ( + CAPTURE => user_CAPTURE, + DRCK => user_DRCK1, + --DRCK2 => user_DRCK2, + RESET => user_RESET, + SEL => user_SEL1, + --SEL2 => user_SEL2, + SHIFT => user_SHIFT, + TDI => user_TDI, + UPDATE => user_UPDATE, + TDO => user_TDO1 + --TDO2 => user_TDO2 + ); + + +process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) +begin + -- default assignments (put outputs in High-Z state if not in USER1) + --user_TDO1<=SPI_MISO; + user_TDO1<=tdo_mem(tdo_mem'high); + SPI_MOSI<='Z'; + SPI_SCK<='Z'; + SPI_CS<='Z'; + + if (user_SEL1='1') then + SPI_MOSI<='0'; + SPI_SCK<='1'; + --SPI_CS<='1'; + SPI_CS<=not(CS_GO and not(CS_STOP)); + + if(user_SHIFT='1') then + SPI_SCK<=user_DRCK1; + --SPI_CS<='0'; + SPI_MOSI<=user_TDI; + end if; + end if; +end process; + + +process(user_DRCK1) +variable i : integer; +begin + if(reset = '1')then + have_header<='0'; + CS_GO<='0'; + elsif(falling_edge(user_DRCK1))then + if ( have_header='0') then + if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then + len <= tdi_mem(15 downto 0); + have_header <= '1'; + if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then + CS_GO <= '1'; + end if; + end if; + elsif (len /= 0) then + len <= len - 1; + end if; + end if; +end process; + +process(user_DRCK1) +variable i : integer; +variable j : integer; +begin + if(reset ='1') then + tdo_mem<=(others => '0'); + tdi_mem<=(others => '0'); + CS_STOP<='0'; + elsif(rising_edge(user_DRCK1))then + tdi_mem(0)<=user_TDI; + for j in 1 to tdi_mem'high loop + tdi_mem(j)<=tdi_mem(j-1); + end loop; + + tdo_mem(0)<=SPI_MISO; + for i in 1 to tdo_mem'high loop + tdo_mem(i)<=tdo_mem(i-1); + end loop; + + if(CS_GO='1' and len=0)then + CS_STOP<='1'; + end if; + end if; +end process; + +end Behavioral; + diff --git a/libraries/Wishbone_Sump_LA/circuit/250K/Papilio_One_250K.ut b/libraries/Wishbone_Sump_LA/circuit/250K/Papilio_One_250K.ut new file mode 100644 index 0000000..1c9e99e --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/250K/Papilio_One_250K.ut @@ -0,0 +1,22 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:1 +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:Yes +-g DriveDone:No diff --git a/libraries/Wishbone_Sump_LA/circuit/250K/papilio_one_250k.bit b/libraries/Wishbone_Sump_LA/circuit/250K/papilio_one_250k.bit new file mode 100644 index 0000000..82c566b Binary files /dev/null and b/libraries/Wishbone_Sump_LA/circuit/250K/papilio_one_250k.bit differ diff --git a/libraries/Wishbone_Sump_LA/circuit/500K/Papilio_One_500K.ut b/libraries/Wishbone_Sump_LA/circuit/500K/Papilio_One_500K.ut new file mode 100644 index 0000000..1c9e99e --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/500K/Papilio_One_500K.ut @@ -0,0 +1,22 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:1 +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:Yes +-g DriveDone:No diff --git a/libraries/Wishbone_Sump_LA/circuit/500K/papilio_one_500k.bit b/libraries/Wishbone_Sump_LA/circuit/500K/papilio_one_500k.bit new file mode 100644 index 0000000..dec9d53 Binary files /dev/null and b/libraries/Wishbone_Sump_LA/circuit/500K/papilio_one_500k.bit differ diff --git a/libraries/Wishbone_Sump_LA/circuit/DUO_LX9/Papilio_DUO_LX9.ut b/libraries/Wishbone_Sump_LA/circuit/DUO_LX9/Papilio_DUO_LX9.ut new file mode 100644 index 0000000..d1824d0 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/DUO_LX9/Papilio_DUO_LX9.ut @@ -0,0 +1,30 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g Reset_on_err:No +-g ConfigRate:2 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:1 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:Yes +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 diff --git a/libraries/Wishbone_Sump_LA/circuit/DUO_LX9/papilio_duo_lx9.bit b/libraries/Wishbone_Sump_LA/circuit/DUO_LX9/papilio_duo_lx9.bit new file mode 100644 index 0000000..8822810 Binary files /dev/null and b/libraries/Wishbone_Sump_LA/circuit/DUO_LX9/papilio_duo_lx9.bit differ diff --git a/libraries/Wishbone_Sump_LA/circuit/LX9/Papilio_Pro.ut b/libraries/Wishbone_Sump_LA/circuit/LX9/Papilio_Pro.ut new file mode 100644 index 0000000..d1824d0 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/LX9/Papilio_Pro.ut @@ -0,0 +1,30 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g Reset_on_err:No +-g ConfigRate:2 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:1 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:Yes +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 diff --git a/libraries/Wishbone_Sump_LA/circuit/LX9/papilio_pro.bit b/libraries/Wishbone_Sump_LA/circuit/LX9/papilio_pro.bit new file mode 100644 index 0000000..412bca4 Binary files /dev/null and b/libraries/Wishbone_Sump_LA/circuit/LX9/papilio_pro.bit differ diff --git a/libraries/Wishbone_Sump_LA/circuit/PSL_Papilio_DUO_LX9.xise b/libraries/Wishbone_Sump_LA/circuit/PSL_Papilio_DUO_LX9.xise new file mode 100644 index 0000000..ccddd14 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/PSL_Papilio_DUO_LX9.xise @@ -0,0 +1,2260 @@ + + + +
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disable the ATmega32U4 chip when this circuit is loaded. + + Papilio DUO Reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/circuit/Papilio_One_250K.sch b/libraries/Wishbone_Sump_LA/circuit/Papilio_One_250K.sch new file mode 100644 index 0000000..7775743 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/Papilio_One_250K.sch @@ -0,0 +1,687 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2014-10-31T16:12:30 + + + + + + + + 2014-11-10T23:27:39 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2014-11-10T23:27:39 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + 2014-11-10T23:27:39 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Version: 1.0 + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/circuit/Papilio_Pro.sch b/libraries/Wishbone_Sump_LA/circuit/Papilio_Pro.sch new file mode 100644 index 0000000..a00c3d6 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/Papilio_Pro.sch @@ -0,0 +1,605 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2014-10-31T16:12:30 + + + + + + + + 2014-11-10T23:27:39 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2015-2-12T19:27:37 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2016-1-22T17:22:29 + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Version: 1.0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/circuit/build_all.bat b/libraries/Wishbone_Sump_LA/circuit/build_all.bat new file mode 100644 index 0000000..477e286 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/build_all.bat @@ -0,0 +1,18 @@ +mkdir 250K\xst\projnav.tmp +mkdir 500K\xst\projnav.tmp +mkdir LX9\xst\projnav.tmp +mkdir DUO_LX9\xst\projnav.tmp +cd DUO_LX9 +start Papilio_DUO_LX9.cmd +cd LX9 +start Papilio_Pro.cmd +REM clean.bat +REM mkdir xst\projnav.tmp +cd ..\500K +start Papilio_One_500K.cmd +REM clean.bat +REM mkdir xst\projnav.tmp +cd ..\250K +start Papilio_One_250K.cmd +pause +clean.bat \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/circuit/clean.bat b/libraries/Wishbone_Sump_LA/circuit/clean.bat new file mode 100644 index 0000000..33e6f58 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/circuit/clean.bat @@ -0,0 +1,47 @@ + @setlocal enableextensions enabledelayedexpansion + set startdir=%cd% + set temp=%startdir% + set folder= +:loop + if not "x%temp:~-1%"=="x\" ( + set folder=!temp:~-1!!folder! + set temp=!temp:~0,-1! + goto :loop + ) + echo.startdir = %startdir% + echo.folder = %folder% + endlocal && set folder=%folder% + +REM Deletes all unnecessary files +for /f %%F in ('dir /b /a-d ^| findstr /vile ".sch .xise .bit .bat .sym .vhd .pdf .ino .cmd_log .cmd .xst .prj .vhf .ut .h .cpp .xtcl keywords.txt"') do del "%%F" +REM for /f %%F in ('dir /b ^| findstr /vile "Sketch saved_bitfiles rebuild LX9 500K 250K smallfs ols-0.9.7 Libraries ym_converter"') do rmdir /q /s "%%F" +rmdir /q /s iseconfig + +if exist LX9 ( + cd LX9 + move Papilio_Pro.cmd_log Papilio_Pro.cmd + for /f %%F in ('dir /b /a-d ^| findstr /vile ".sch .xise .bit .bat .sym .vhd .pdf .ino .cmd_log .cmd .xst .prj .vhf .ut .html .wcfg"') do del "%%F" + for /f %%F in ('dir /b ^| findstr /vile "Sketch saved_bitfiles rebuild LX9 500K 250K"') do rmdir /q /s "%%F" + cd .. +) +if exist 250K ( + cd 250K + move Papilio_One_250K.cmd_log Papilio_One_250K.cmd + for /f %%F in ('dir /b /a-d ^| findstr /vile ".sch .xise .bit .bat .sym .vhd .pdf .ino .cmd_log .cmd .xst .prj .vhf .ut .html .wcfg"') do del "%%F" + for /f %%F in ('dir /b ^| findstr /vile "Sketch saved_bitfiles rebuild LX9 500K 250K"') do rmdir /q /s "%%F" + cd .. +) +if exist 500K ( + cd 500K + move Papilio_One_500K.cmd_log Papilio_One_500K.cmd + for /f %%F in ('dir /b /a-d ^| findstr /vile ".sch .xise .bit .bat .sym .vhd .pdf .ino .cmd_log .cmd .xst .prj .vhf .ut .html .wcfg"') do del "%%F" + for /f %%F in ('dir /b ^| findstr /vile "Sketch saved_bitfiles rebuild LX9 500K 250K"') do rmdir /q /s "%%F" + cd .. +) +if exist DUO_LX9 ( + cd DUO_LX9 + move Papilio_DUO_LX9.cmd_log Papilio_DUO_LX9.cmd + for /f %%F in ('dir /b /a-d ^| findstr /vile ".sch .xise .bit .bat .sym .vhd .pdf .ino .cmd_log .cmd .xst .prj .vhf .ut .html .wcfg"') do del "%%F" + for /f %%F in ('dir /b ^| findstr /vile "Sketch saved_bitfiles rebuild LX9 500K 250K"') do rmdir /q /s "%%F" + cd .. +) \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_DUO.pdf b/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_DUO.pdf new file mode 100644 index 0000000..23a05ae Binary files /dev/null and b/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_DUO.pdf differ diff --git a/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_one_250k.pdf b/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_one_250k.pdf new file mode 100644 index 0000000..4a8e7dc Binary files /dev/null and b/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_one_250k.pdf differ diff --git a/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_one_500k.pdf b/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_one_500k.pdf new file mode 100644 index 0000000..6083c3f Binary files /dev/null and b/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_one_500k.pdf differ diff --git a/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_pro.pdf b/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_pro.pdf new file mode 100644 index 0000000..5a5f2e2 Binary files /dev/null and b/libraries/Wishbone_Sump_LA/circuit/schematic_papilio_pro.pdf differ diff --git a/libraries/Wishbone_Sump_LA/clean.bat b/libraries/Wishbone_Sump_LA/clean.bat new file mode 100644 index 0000000..8a48128 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/clean.bat @@ -0,0 +1,50 @@ + @setlocal enableextensions enabledelayedexpansion + set startdir=%cd% + set temp=%startdir% + set folder= +:loop + if not "x%temp:~-1%"=="x\" ( + set folder=!temp:~-1!!folder! + set temp=!temp:~0,-1! + goto :loop + ) + echo.startdir = %startdir% + echo.folder = %folder% + endlocal && set folder=%folder% + +if exist papilio_pro.bit ( + mkdir saved_bitfiles + copy papilio_pro.bit saved_bitfiles\%folder%-papilio-pro.bit + move Papilio_Pro_summary.html saved_bitfiles\%folder%-papilio-pro-summary.html +) else ( + echo "No File" +) + +if exist papilio_one_500k.bit ( + mkdir saved_bitfiles + copy papilio_one_500k.bit saved_bitfiles\%folder%-papilio-one_500K.bit + move papilio_one_500k_summary.html saved_bitfiles\%folder%-papilio-one-500K-summary.html +) else ( + echo "No File" +) + +if exist papilio_one_250k.bit ( + mkdir saved_bitfiles + copy papilio_one_250k.bit saved_bitfiles\%folder%-papilio-one_250K.bit + move papilio_one_250k_summary.html saved_bitfiles\%folder%-papilio-one-250K-summary.html +) else ( + echo "No File" +) + +REM Deletes all unnecessary files +for /f %%F in ('dir /b /a-d ^| findstr /vile ".sch .xise .bit .bat .sym .vhd .pdf .ino .cmd_log .cmd .xst .prj .vhf .ut .h .cpp .xtcl keywords.txt"') do del "%%F" +REM for /f %%F in ('dir /b ^| findstr /vile "Sketch saved_bitfiles rebuild LX9 500K 250K smallfs ols-0.9.7 Libraries ym_converter"') do rmdir /q /s "%%F" +rmdir /q /s iseconfig + +if exist Chip_Designer ( + cd Chip_Designer + REM move Papilio_DUO_LX9.cmd_log Papilio_DUO_LX9.cmd + for /f %%F in ('dir /b /a-d ^| findstr /vile ".sch .xise .bit .bat .sym .vhd .pdf .ino .cmd_log .cmd .xst .prj .vhf .ut .html .wcfg .ngc"') do del "%%F" + for /f %%F in ('dir /b ^| findstr /vile "Sketch saved_bitfiles rebuild LX9 500K 250K"') do rmdir /q /s "%%F" + cd .. +) diff --git a/libraries/Wishbone_Sump_LA/clockman_papilio.vhd b/libraries/Wishbone_Sump_LA/clockman_papilio.vhd new file mode 100644 index 0000000..f32f2f7 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/clockman_papilio.vhd @@ -0,0 +1,85 @@ +---------------------------------------------------------------------------------- +-- clockman.vhd +-- +-- Author: Michael "Mr. Sump" Poppitz +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- This is only a wrapper for Xilinx' DCM component so it doesn't +-- have to go in the main code and can be replaced more easily. +-- +-- Creates clk0 with 100MHz. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +entity clockman is + port( + clkin : in std_logic; -- clock input + clk0 : out std_logic -- double clock rate output + ); +end clockman; + +architecture behavioral of clockman is + + signal clkin1, clkfb, clkfbbuf, realclk0 : std_logic; + +begin + -- DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E + -- Xilinx HDL Language Template version 8.1i + + clkin2_inst: BUFG + port map ( + I => clkin, + O => clkin1 + ); + + DCM_baseClock : DCM + generic map( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 8, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 25, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 31.25, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"C080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => TRUE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + ) + port map( + CLKIN => clkin1, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => '0', -- Dynamic phase adjust clock input + PSEN => '0', -- Dynamic phase adjust enable input + PSINCDEC => '0', -- Dynamic phase adjust increment/decrement + RST => '0', -- DCM asynchronous reset input + CLK2X => open, + CLKFX => realclk0, + CLK0 => clkfb, + CLKFB => clkfbbuf + ); + + -- clkfb is run through a BUFG only to shut up ISE 8.1 + BUFG_clkfb : BUFG + port map( + O => clkfbbuf, -- Clock buffer output + I => clkfb -- Clock buffer input + ); + + clk0 <= realclk0; + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/controller.vhd b/libraries/Wishbone_Sump_LA/controller.vhd new file mode 100644 index 0000000..5cab4ba --- /dev/null +++ b/libraries/Wishbone_Sump_LA/controller.vhd @@ -0,0 +1,253 @@ +---------------------------------------------------------------------------------- +-- controller.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Controls the capturing & readback operation. +-- +-- If no other operation has been activated, the controller samples data +-- into the memory. When the run signal is received, it continues to do so +-- for fwd * 4 samples and then sends bwd * 4 samples to the transmitter. +-- This allows to capture data from before the trigger match which is a nice +-- feature. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity controller is + port( + clock : in std_logic; + reset : in std_logic; + la_input : in std_logic_vector (32 downto 0); + la_inputReady : in std_logic; + run : in std_logic; + wrSize : in std_logic; + data : in std_logic_vector (31 downto 0); + busy : in std_logic; + send : out std_logic; + output : out std_logic_vector (31 downto 0); + memoryIn : in std_logic_vector (31 downto 0); + memoryOut : out std_logic_vector (32 downto 0); + memoryRead : out std_logic; + memoryWrite : out std_logic; + rle_busy : in std_logic; + rle_read : out std_logic; + rle_mode : in std_logic; + rdstate : out std_logic; + data_ready : in std_logic; + trig_delay : in std_logic_vector(1 downto 0); + abort : in std_logic + ); +end controller; + +architecture behavioral of controller is + + type CONTROLLER_STATES is (SAMPLE, DELAY, READ, DATAWAIT, READWAIT, RLE_POSTSCRIPT); + + signal fwd, bwd : std_logic_vector (15 downto 0); + signal ncounter, counter, ctr_delay : std_logic_vector (17 downto 0); + signal nstate, state : CONTROLLER_STATES; + signal sendReg, memoryWrite_i, memoryRead_i, rle_read_i, send_i : std_logic; + signal output_i : std_logic_vector (31 downto 0); + +begin + + rdstate <= '1' when state /= SAMPLE and state /= DELAY else '0'; + + ctr_delay <= + "00" & x"0000" when trig_delay = "01" else + "11" & x"fffe" when trig_delay = "10" else + "11" & x"fffd"; + + -- synchronization and reset logic + process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + state <= SAMPLE; + else + state <= nstate; + counter <= ncounter; + end if; + -- register outputs + output <= output_i; + memoryOut <= la_input; + memoryWrite <= memoryWrite_i; + memoryRead <= memoryRead_i; + send_i <= sendReg; + send <= sendReg; + rle_read <= rle_read_i; + end if; + end process; + + -- FSM to control the controller action + process(state, run, counter, fwd, la_inputReady, bwd, busy, rle_busy, + data_ready, send_i, ctr_delay, abort, rle_mode, memoryIn) + begin + case state is + -- default mode: sample data from la_input to memory + when SAMPLE => + if run = '1' then + nstate <= DELAY; + else + nstate <= state; + end if; + ncounter <= ctr_delay; + memoryWrite_i <= la_inputReady; + memoryRead_i <= '0'; + sendReg <= '0'; + rle_read_i <= '0'; + output_i <= memoryIn; + + -- keep sampling for 4 * fwd + 4 samples after run condition + when DELAY => + if (counter = fwd & "00") or (abort = '1') then + ncounter <= (others => '1'); + nstate <= READ; + else + if la_inputReady = '1' then + ncounter <= counter + 1; + else + ncounter <= counter; + end if; + nstate <= state; + end if; + memoryWrite_i <= la_inputReady; + memoryRead_i <= '0'; + sendReg <= '0'; + rle_read_i <= '0'; + output_i <= memoryIn; + + -- read back 4 * bwd + 4 samples after DELAY + -- go into wait state after each sample to give transmitter time + when READ => + if counter = bwd & "11" then + if rle_busy = '1' then + ncounter <= counter; + nstate <= DATAWAIT; + rle_read_i <= '1'; + else + ncounter <= (others => '0'); + if rle_mode = '1' then + nstate <= RLE_POSTSCRIPT; + else + nstate <= SAMPLE; + end if; + rle_read_i <= '0'; + end if; + memoryRead_i <= '0'; + else + if rle_busy = '1' then + ncounter <= counter; + memoryRead_i <= '0'; + else + ncounter <= counter + 1; + memoryRead_i <= '1'; + end if; + nstate <= DATAWAIT; + rle_read_i <= '1'; + end if; + memoryWrite_i <= '0'; + sendReg <= '0'; + output_i <= memoryIn; + + when DATAWAIT => + if data_ready = '1' then + nstate <= READWAIT; + sendReg <= '1'; + else + nstate <= state; + sendReg <= '0'; + end if; + ncounter <= counter; + memoryWrite_i <= '0'; + memoryRead_i <= '0'; + rle_read_i <= '0'; + output_i <= memoryIn; + + -- wait for the transmitter to become ready again + when READWAIT => + if busy = '0' and send_i = '0' then + nstate <= READ; + else + nstate <= state; + end if; + ncounter <= counter; + memoryWrite_i <= '0'; + memoryRead_i <= '0'; + sendReg <= '0'; + rle_read_i <= '0'; + output_i <= memoryIn; + + -- send 0x00 0x00 0x00 0x00 0x55 as stop marker after the RLE data + when RLE_POSTSCRIPT => + if busy = '0' then + if counter = 5 then + sendReg <= '0'; + ncounter <= (others => '0'); + nstate <= SAMPLE; + output_i <= (others => '0'); + elsif counter = 4 and send_i = '0' then + sendReg <= '1'; + ncounter <= counter + 1; + nstate <= state; + output_i <= x"00000055"; + elsif send_i = '0' then + sendReg <= '1'; + ncounter <= counter + 1; + nstate <= state; + output_i <= (others => '0'); + else + sendReg <= '0'; + ncounter <= counter; + nstate <= state; + output_i <= (others => '0'); + end if; + else + sendReg <= '0'; + ncounter <= counter; + nstate <= state; + output_i <= (others => '0'); + end if; + memoryWrite_i <= '0'; + memoryRead_i <= '0'; + rle_read_i <= '0'; + + end case; + end process; + + -- set speed and size registers if indicated + process(clock) + begin + if rising_edge(clock) then + if wrSize = '1' then + fwd <= data(31 downto 16); + bwd <= data(15 downto 0); + end if; + end if; + end process; + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/decoder.vhd b/libraries/Wishbone_Sump_LA/decoder.vhd new file mode 100644 index 0000000..1439467 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/decoder.vhd @@ -0,0 +1,107 @@ +---------------------------------------------------------------------------------- +-- decoder.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Takes the opcode from the command received by the receiver and decodes it. +-- The decoded command will be executed for one cycle. +-- +-- The receiver keeps the cmd output active long enough so all the +-- data is still available on its cmd output when the command has +-- been decoded and sent out to other modules with the next +-- clock cycle. (Maybe this paragraph should go in receiver.vhd?) +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity decoder is + port( + opcode : in std_logic_vector (7 downto 0); + execute : in std_logic; + clock : in std_logic; + wrtrigmask : out std_logic_vector (3 downto 0); + wrtrigval : out std_logic_vector (3 downto 0); + wrtrigcfg : out std_logic_vector (3 downto 0); + wrspeed : out std_logic; + wrsize : out std_logic; + wrFlags : out std_logic; + arm : out std_logic; + reset : out std_logic; + abort : out std_logic; + ident : out std_logic; + meta : out std_logic + ); +end decoder; + +architecture behavioral of decoder is + + signal exe, exeReg: std_logic; + +begin + + exe <= execute; + + process(clock) + begin + if rising_edge(clock) then + reset <= '0'; arm <= '0'; + wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0'; + wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000"; + abort <= '0'; ident <= '0'; meta <= '0'; + + if (exe and not exeReg) = '1' then + case opcode is + -- short commands + when x"00" => reset <= '1'; + when x"01" => arm <= '1'; + when x"02" => ident <= '1'; + when x"04" => meta <= '1'; + when x"05" => abort <= '1'; + -- long commands + when x"80" => wrspeed <= '1'; + when x"81" => wrsize <= '1'; + when x"82" => wrFlags <= '1'; + when x"C0" => wrtrigmask(0) <= '1'; + when x"C1" => wrtrigval(0) <= '1'; + when x"C2" => wrtrigcfg(0) <= '1'; + when x"C4" => wrtrigmask(1) <= '1'; + when x"C5" => wrtrigval(1) <= '1'; + when x"C6" => wrtrigcfg(1) <= '1'; + when x"C8" => wrtrigmask(2) <= '1'; + when x"C9" => wrtrigval(2) <= '1'; + when x"CA" => wrtrigcfg(2) <= '1'; + when x"CC" => wrtrigmask(3) <= '1'; + when x"CD" => wrtrigval(3) <= '1'; + when x"CE" => wrtrigcfg(3) <= '1'; + when others => + end case; + end if; + + exeReg <= exe; + + end if; + end process; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/demux.vhd b/libraries/Wishbone_Sump_LA/demux.vhd new file mode 100644 index 0000000..cb28115 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/demux.vhd @@ -0,0 +1,57 @@ +---------------------------------------------------------------------------------- +-- demux.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Demultiplexes 16 la_input channels into 32 output channels, +-- thus doubling the sampling rate for those channels. +-- +-- This module barely does anything anymore, but is kept for historical reasons. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity demux is + port( + la_input : in std_logic_vector (15 downto 0); + la_input180 : in std_logic_vector (15 downto 0); + clock : in std_logic; + output : out std_logic_vector (31 downto 0) + ); +end demux; + +architecture behavioral of demux is + +begin + output(15 downto 0) <= la_input; + + process (clock) + begin + if rising_edge(clock) then + output(31 downto 16) <= la_input180; + end if; + end process; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/edit_library.ino b/libraries/Wishbone_Sump_LA/edit_library.ino new file mode 100644 index 0000000..a8e4252 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/edit_library.ino @@ -0,0 +1,25 @@ +/* + Gadget Factory + Use this to edit your libraries. + + To design your own DesignLab library do the following steps: + 1) Define your Chip: + sketchdir://Chip_Designer.xise + 2) Define your Circuit: + sketchdir://circuit/PSL_Papilio_Pro_LX9.xise + sketchdir://circuit/PSL_Papilio_DUO_LX9.xise + sketchdir://circuit/PSL_Papilio_One_500K.xise + sketchdir://circuit/PSL_Papilio_One_250k.xise + 3) Define your Arduino style library + Modify the .cpp and .h tabs of this sketch + 4) Make an example sketch for the library + Open the sketch under the examples folder - it should have automatically opened with this sketch. + 4) Share your library + http://forum.gadgetfactory.net/index.php?/page/articles.html + + created 2014 + by Jack Gassett + http://www.gadgetfactory.net + + There is no actual code that can be run from this sketch. + */ diff --git a/libraries/Wishbone_Sump_LA/eia232.vhd b/libraries/Wishbone_Sump_LA/eia232.vhd new file mode 100644 index 0000000..c8953ed --- /dev/null +++ b/libraries/Wishbone_Sump_LA/eia232.vhd @@ -0,0 +1,190 @@ +---------------------------------------------------------------------------------- +-- eia232.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- EIA232 aka RS232 interface. +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + + +entity eia232 is + generic ( + FREQ : integer; + SCALE : integer; + RATE : integer + ); + Port ( + clock : in STD_LOGIC; + reset : in std_logic; + speed : in std_logic_vector (1 downto 0); + rx : in STD_LOGIC; + tx : out STD_LOGIC; + cmd : out STD_LOGIC_VECTOR (39 downto 0); + execute : out STD_LOGIC; + data : in STD_LOGIC_VECTOR (31 downto 0); + send : in STD_LOGIC; + busy : out STD_LOGIC + ); +end eia232; + +architecture Behavioral of eia232 is + + COMPONENT sump_prescaler + generic ( + SCALE : integer + ); + PORT( + clock : IN std_logic; + reset : IN std_logic; + div : IN std_logic_vector(1 downto 0); + scaled : OUT std_logic + ); + END COMPONENT; + + COMPONENT receiver + generic ( + FREQ : integer; + RATE : integer + ); + PORT( + rx : IN std_logic; + clock : IN std_logic; + trxClock : IN std_logic; + reset : in STD_LOGIC; + op : out std_logic_vector(7 downto 0); + data : out std_logic_vector(31 downto 0); + execute : out STD_LOGIC + ); + END COMPONENT; + + COMPONENT transmitter + generic ( + FREQ : integer; + RATE : integer + ); + PORT( + data : IN std_logic_vector(31 downto 0); + disabledGroups : in std_logic_vector (3 downto 0); + write : IN std_logic; + id : in std_logic; + xon : in std_logic; + xoff : in std_logic; + clock : IN std_logic; + trxClock : IN std_logic; + reset : in std_logic; + tx : OUT std_logic; + busy : out std_logic + ); + END COMPONENT; + +constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter + +signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic; +signal disabledGroupsReg : std_logic_vector(3 downto 0); +signal opcode : std_logic_vector(7 downto 0); +signal opdata : std_logic_vector(31 downto 0); + +begin + cmd <= opdata & opcode; + execute <= executeReg; + + -- process special uart commands that do not belong in core decoder + process(clock) + begin + if rising_edge(clock) then + id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0'; + executePrev <= executeReg; + if executePrev = '0' and executeReg = '1' then + case opcode is + when x"02" => id <= '1'; + when x"11" => xon <= '1'; + when x"13" => xoff <= '1'; + when x"82" => wrFlags <= '1'; + when others => + end case; + end if; + end if; + end process; + + process(clock) + begin + if rising_edge(clock) then + if wrFlags = '1' then + disabledGroupsReg <= opdata(5 downto 2); + end if; + end if; + end process; + + + Inst_sump_prescaler: sump_prescaler + generic map ( + SCALE => SCALE + ) + PORT MAP( + clock => clock, + reset => reset, + div => speed, + scaled => trxClock + ); + + Inst_receiver: receiver + generic map ( + FREQ => TRXFREQ, + RATE => RATE + ) + PORT MAP( + rx => rx, + clock => clock, + trxClock => trxClock, + reset => reset, + op => opcode, + data => opdata, + execute => executeReg + ); + + Inst_transmitter: transmitter + generic map ( + FREQ => TRXFREQ, + RATE => RATE + ) + PORT MAP( + data => data, + disabledGroups => disabledGroupsReg, + write => send, + id => id, + xon => xon, + xoff => xoff, + clock => clock, + trxClock => trxClock, + reset => reset, + tx => tx, + busy => busy + ); + +end Behavioral; + diff --git a/libraries/Wishbone_Sump_LA/examples/OLS_Client/OLS_Client.ino b/libraries/Wishbone_Sump_LA/examples/OLS_Client/OLS_Client.ino new file mode 100644 index 0000000..ecf0fe7 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/examples/OLS_Client/OLS_Client.ino @@ -0,0 +1,271 @@ + +#define circuit Wishbone_Sump_LA + +using namespace ZPUino; + +class Capture: public BaseDevice +{ +private: + byte channel0; + byte channel1; + byte channel2; + byte channel3; + +public: + uint32_t *buffer; + uint32_t samples; + + Capture(): BaseDevice(-1) { + } + void begin() + { + if (deviceBegin(VENDOR_ZPUINO, 0x22)==0) { + } else { + printf("Cannot find device\n"); + } + //samples = 300000; + //samples = 65536; + //samples = 131072; + samples = 262144; + buffer = (uint32_t*)malloc(samples*sizeof(uint32_t)); + //memset(buffer, 0xff, samples*sizeof(uint32_t)); + armed=0; + channel0=0; + channel1=0; + channel2=0; + channel3=0; + } + unsigned getStatus() + { + return REG(0); + } + + unsigned getTriggerAddress() + { + return REG(1); + } + + unsigned getSamples() + { + return samples; + } + + void longCommand(uint8_t opcode, uint32_t data) + { + uint32_t tmpData; + switch (opcode) { + case 0x81: // Size + //samples = (data&0xffff)+((data>>16)&0xffff); + //samples = ((((data>>16)&0x00ff)*0x100 + ((data>>24)&0xff))); + tmpData = (data>>16); //Shift Read Count over + samples = ((tmpData & 0xFFU) << 8 | (tmpData & 0xFF00U) >> 8)*4 + 4; //Reverse bytes of Read Count + //samples = (((data>>16)&0x00ff)*0x100 + ((data>>24)&0xff)) + (((data&0xff)*0x100) + ((data>>8)&0xff)); + + //free(buffer); + //buffer = (uint32_t*)malloc(samples*sizeof(uint32_t)); + + //buffer = (uint32_t*) realloc(buffer,samples); + //memset(buffer, 0xff, samples*sizeof(uint32_t)); + //REG(100) = (unsigned)&buffer[0]; + //REG(101) = (unsigned)&buffer[samples]; + //Serial.write(samples); + break; + case 0x82: //Channel Groups + channel0 = data>>26&0x01; + channel1 = data>>27&0x01; + channel2 = data>>28&0x01; + channel3 = data>>29&0x01; +// Serial.print("Channel0: "); +// Serial.println(channel0); +// Serial.print("Channel1: "); +// Serial.println(channel1); +// Serial.print("Channel2: "); +// Serial.println(channel2); +// Serial.print("Channel3: "); +// Serial.println(channel3); + break; + } + + REG(opcode) = data; + } + + void start() + { + //REG(100) = (unsigned)&buffer[0]; + //REG(101) = (unsigned)&buffer[samples]; + + //Set base address for shared memory + REGISTER(IO_SLOT(14),0x100) = (unsigned)&buffer[0]; + //Set end of shared memory + //REGISTER(IO_SLOT(14),0x101) = (unsigned)&buffer[8192]; + REGISTER(IO_SLOT(14),0x101) = (unsigned)&buffer[samples]; + + } + void reset() + { + //REG(2) = 2; + REG(0) = 0; + armed = 0; + } + void arm() + { + REG(1) = 0; + armed=1; + } + void dump() + { + int i; + for (i=0;i<16; i++) { + printf("%08x\n", buffer[i]); + } + } + void sendIfReady() + { + int i; + unsigned trigAddress = 0; + if (armed) { + if ((getStatus())==0x43) { + // Transmit. + //Serial.println("In Transmit"); + trigAddress = getTriggerAddress(); + //Serial.print("Trigger address: "); + //Serial.println(trigAddress); + //for (i=samples+trigAddress;i>=trigAddress; i--) { + for (i=samples;i>=0; i--) { + //for (i=0;i<=samples; i++) { + if (channel0==0) Serial.write(buffer[i]&0xff); + if (channel1==0) Serial.write((buffer[i]>>8)&0xff); + if (channel2==0) Serial.write((buffer[i]>>16)&0xff); + if (channel3==0) Serial.write((buffer[i]>>24)&0xff); + } + reset(); + } + } + } + + uint8_t armed; +}; + +Capture mycap; + +void setup() +{ + //delay(3000); + Serial.begin(115200); + + mycap.begin(); + mycap.start(); + //mycap.arm(); +} + +typedef enum { + IDLE, + LONG1, + LONG2, + LONG3, + LONG4 +} state_t; + +state_t state = IDLE; +uint32_t longcommand; +uint8_t opcode; +unsigned int serialBuffer[8192]; +int serialIndex = 0; + + +void processLong(uint32_t v) +{ + + mycap.longCommand(opcode,longcommand); + +// Serial.println(); +// Serial.print("Opcode: "); +// Serial.println(opcode, HEX); +// Serial.print("LongCommand: "); +// Serial.println(longcommand, HEX); + +} + +void handleSerial(uint8_t v) +{ + //Serial.println(state, HEX); + switch(state) { + case IDLE: + //Serial.println("In Idle"); + switch (v) { + case 0x00: // Reset + mycap.reset(); + break; + case 0x01: // Arm + mycap.arm(); + break; + case 0x02: // id + Serial.write((const uint8_t*)"1ALS",4); + //Serial.print("1ALS"); + break; + case 0x61: // getStatus + Serial.println(mycap.getStatus()); + break; + case 0x62: // getStatus + for (int i = 0; i < serialIndex; i++ ){ + Serial.write(serialBuffer[i]); + } + break; + case 0x63: // getTrigger + + Serial.write(mycap.getTriggerAddress()); + break; + case 0x64: // getSamples + Serial.println(mycap.getSamples(), HEX); + break; + default: + if (v & 0x80) { + //longcommand = v; + opcode = v; + state = LONG1; + } + break; + } + break; + case LONG1: + //Serial.println("In LONG1"); +// longcommand<<=8; +// longcommand += v; + longcommand = v; + state = LONG2; + break; + case LONG2: + longcommand<<=8; + longcommand += v; + state = LONG3; + break; + case LONG3: + longcommand<<=8; + longcommand += v; + state = LONG4; + break; + case LONG4: + longcommand<<=8; + longcommand += v; + processLong(v); + state = IDLE; + break; + } +} + + +void loop() +{ + if (Serial.available()) + { + int i = Serial.read(); + //Serial.println(i, HEX); +// serialBuffer[serialIndex] = i; +// serialIndex++; + handleSerial(i&0xff); + //handleSerial(i); + } + mycap.sendIfReady(); + //mycap.arm(); + //mycap.dump(); +} diff --git a/libraries/Wishbone_Sump_LA/filter.vhd b/libraries/Wishbone_Sump_LA/filter.vhd new file mode 100644 index 0000000..b24ca91 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/filter.vhd @@ -0,0 +1,66 @@ +---------------------------------------------------------------------------------- +-- filter.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Fast 32 channel digital noise filter using a single LUT function for each +-- individual channel. It will filter out all pulses that only appear for half +-- a clock cycle. This way a pulse has to be at least 5-10ns long to be accepted +-- as valid. This is sufficient for sample rates up to 100MHz. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity filter is + port( + la_input : in std_logic_vector (31 downto 0); + la_input180 : in std_logic_vector (31 downto 0); + clock : in std_logic; + output : out std_logic_vector (31 downto 0) + ); +end filter; + +architecture behavioral of filter is + + signal la_input360, la_input180Delay, result : std_logic_vector (31 downto 0); + +begin + + process(clock) + begin + if rising_edge(clock) then + -- determine next result + for i in 31 downto 0 loop + result(i) <= (result(i) or la_input360(i) or la_input(i)) and la_input180Delay(i); + end loop; + + -- shift in la_input data + la_input360 <= la_input; + la_input180Delay <= la_input180; + end if; + end process; + output <= result; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/flags.vhd b/libraries/Wishbone_Sump_LA/flags.vhd new file mode 100644 index 0000000..0aa1548 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/flags.vhd @@ -0,0 +1,88 @@ +---------------------------------------------------------------------------------- +-- flags.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Flags register. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity flags is + port( + data : in std_logic_vector(10 downto 0); + clock : in std_logic; + write : in std_logic; + demux : out std_logic; + filter : out std_logic; + external : out std_logic; + inverted : out std_logic; + disabledGroups : out std_logic_vector (3 downto 0); + rle : out std_logic; + test_mode : out std_logic; + data_size : out std_logic_vector (1 downto 0); + num_scheme : out std_logic + ); +end flags; + +architecture behavioral of flags is + + signal ds : std_logic_vector (1 downto 0); + +begin + + -- write flags + process (clock) + begin + if rising_edge(clock) then + if write = '1' then + demux <= data(0); + filter <= data(1); + external <= data(6); + inverted <= data(7); + disabledGroups <= data(5 downto 2); + rle <= data(8); + num_scheme <= data(9); + test_mode <= data(10); + data_size <= ds; + end if; + end if; + end process; + + ds <= + "01" when data(5 downto 2) = "1110" else + "01" when data(5 downto 2) = "1101" else + "01" when data(5 downto 2) = "1011" else + "01" when data(5 downto 2) = "0111" else + "10" when data(5 downto 2) = "1100" else + "10" when data(5 downto 2) = "1010" else + "10" when data(5 downto 2) = "0110" else + "10" when data(5 downto 2) = "1001" else + "10" when data(5 downto 2) = "0101" else + "10" when data(5 downto 2) = "0011" else + "00"; + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/group_selector.vhd b/libraries/Wishbone_Sump_LA/group_selector.vhd new file mode 100644 index 0000000..9eb66ef --- /dev/null +++ b/libraries/Wishbone_Sump_LA/group_selector.vhd @@ -0,0 +1,85 @@ +---------------------------------------------------------------------------------- +-- group_selector.vhd +-- +-- Copyright (C) 2011 +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- multiplexes valid groups, output is registered +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity group_selector is + port( + clock : in std_logic; + la_input : in std_logic_vector(31 downto 0); + la_input_ready : in std_logic; + output : out std_logic_vector(31 downto 0); + output_ready : out std_logic; + disabledGroups : in std_logic_vector(3 downto 0) + ); +end group_selector; + +architecture behavioral of group_selector is + + signal ib0, ib1, ib2, ib3 : std_logic_vector(7 downto 0); + signal tmp : std_logic_vector(31 downto 0); + +begin + + ib0 <= la_input(7 downto 0); + ib1 <= la_input(15 downto 8); + ib2 <= la_input(23 downto 16); + ib3 <= la_input(31 downto 24); + + tmp <= -- select 8-bit enabled group + x"000000" & ib0 when disabledGroups = "1110" else + x"000000" & ib1 when disabledGroups = "1101" else + x"000000" & ib2 when disabledGroups = "1011" else + x"000000" & ib3 when disabledGroups = "0111" else + -- select 2 8-bit enabled groups + x"0000" & ib1 & ib0 when disabledGroups = "1100" else + x"0000" & ib2 & ib0 when disabledGroups = "1010" else + x"0000" & ib3 & ib0 when disabledGroups = "0110" else + x"0000" & ib2 & ib1 when disabledGroups = "1001" else + x"0000" & ib3 & ib1 when disabledGroups = "0101" else + x"0000" & ib3 & ib2 when disabledGroups = "0011" else + -- clear unused group + ib3 & ib2 & ib1 & x"00" when disabledGroups = "0001" else + ib3 & ib2 & x"00" & ib0 when disabledGroups = "0010" else + ib3 & x"00" & ib1 & ib0 when disabledGroups = "0100" else + x"00" & ib2 & ib1 & ib0 when disabledGroups = "1000" else + -- full + la_input when disabledGroups = "0000" else + (others => 'X'); + + process (clock) + begin + if rising_edge(clock) then + output <= tmp; + output_ready <= la_input_ready; + end if; + end process; + +end behavioral; \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/include_symbols.edif b/libraries/Wishbone_Sump_LA/include_symbols.edif new file mode 100644 index 0000000..e69de29 diff --git a/libraries/Wishbone_Sump_LA/muldex.vhd b/libraries/Wishbone_Sump_LA/muldex.vhd new file mode 100644 index 0000000..b063424 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/muldex.vhd @@ -0,0 +1,199 @@ +---------------------------------------------------------------------------------- +-- muldex.vhd +-- +-- Copyright (C) 2011 Kinsa +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, data_wr to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Performs dynamic sample depth. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity muldex is + port( + clock : in std_logic; + reset : in std_logic; + data_inp : in std_logic_vector (32 downto 0); + data_out : out std_logic_vector (32 downto 0); + data_rd : in std_logic; + data_wr : in std_logic; + mem_inp : in std_logic_vector (35 downto 0); + mem_out : out std_logic_vector (35 downto 0); + mem_rd : out std_logic; + mem_wr : out std_logic; + data_size : in std_logic_vector(1 downto 0); + rdstate : in std_logic; + data_ready : out std_logic + ); +end muldex; + +architecture behavioral of muldex is + + component muldex_16 + port( + clock : in std_logic; + reset : in std_logic; + data_inp : in std_logic_vector (15 downto 0); + data_out : out std_logic_vector (15 downto 0); + data_wr : in std_logic; + data_rd : in std_logic; + mem_inp : in std_logic_vector (33 downto 0); + mem_out : out std_logic_vector (33 downto 0); + mem_wr : out std_logic; + mem_rd : out std_logic; + rle_in : in std_logic; + rle_out : out std_logic + ); + end component; + + component muldex_8 + port( + clock : in std_logic; + reset : in std_logic; + data_inp : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0); + data_wr : in std_logic; + data_rd : in std_logic; + mem_inp : in std_logic_vector (35 downto 0); + mem_out : out std_logic_vector (35 downto 0); + mem_wr : out std_logic; + mem_rd : out std_logic; + rle_in : in std_logic; + rle_out : out std_logic + ); + end component; + + signal mem_wr_8, mem_rd_8, mem_wr_16, mem_rd_16, rle_in : std_logic; + signal data_out_8 : std_logic_vector (7 downto 0); + signal data_out_16 : std_logic_vector (15 downto 0); + signal mem_out_8 : std_logic_vector (35 downto 0); + signal mem_out_16 : std_logic_vector (33 downto 0); + signal rle_out_8, rle_out_16 : std_logic; + signal data_out_i : std_logic_vector (32 downto 0); + signal mem_wr_i, mem_rd_i : std_logic; + +begin + + -- generate data_ready after 3 clk cycles from data_rd + output_block: block + signal a : std_logic_vector (2 downto 0); + begin + process(clock) + begin + if rising_edge(clock) then + a <= a(1 downto 0) & data_rd; + data_ready <= a(2); + if a(2) = '1' then + data_out <= data_out_i; + end if; + end if; + end process; + end block; + + -- generate extra mem_rd pulse when there is a previous mem_wr pulse + sync_mem_block: block + signal a, b : std_logic; + begin + + mem_rd <= mem_rd_i or (not mem_wr_i and b) ; + mem_wr <= mem_wr_i; + + process(clock) + begin + if rising_edge(clock) then + a <= rdstate; + -- check for rdstate rising edge + if a = '0' and rdstate = '1' then + b <= '1'; + else + --extend only when dynamic sample depth is enabled + if b = '1' and (mem_wr_i = '1' or (mem_rd_i ='1' and data_size /= "00")) then + b <= '1'; + else + b <= '0'; + end if; + end if; + end if; + end process; + end block; + + mem_out <= + mem_out_8 when data_size = "01" else + "00" & mem_out_16 when data_size = "10" else + "000" & data_inp when data_size = "00" else + (others => 'X'); + + mem_rd_i <= + mem_rd_8 when data_size = "01" else + mem_rd_16 when data_size = "10" else + data_rd when data_size = "00" else + 'X'; + + mem_wr_i <= + mem_wr_8 when data_size = "01" else + mem_wr_16 when data_size = "10" else + data_wr when data_size = "00" else + 'X'; + + data_out_i <= + rle_out_8 & x"000000" & data_out_8 when data_size = "01" else + rle_out_16 & x"0000" & data_out_16 when data_size = "10" else + mem_inp(32 downto 0) when data_size = "00" else + (others => 'X'); + + rle_in <= data_inp(32); + + Inst_m16: muldex_16 + port map( + clock => clock, + reset => reset, + data_inp => data_inp(15 downto 0), + data_out => data_out_16, + data_wr => data_wr, + data_rd => data_rd, + mem_inp => mem_inp(33 downto 0), + mem_out => mem_out_16, + mem_wr => mem_wr_16, + mem_rd => mem_rd_16, + rle_in => rle_in, + rle_out => rle_out_16 + ); + + Inst_m8: muldex_8 + port map( + clock => clock, + reset => reset, + data_inp => data_inp(7 downto 0), + data_out => data_out_8, + data_wr => data_wr, + data_rd => data_rd, + mem_inp => mem_inp, + mem_out => mem_out_8, + mem_wr => mem_wr_8, + mem_rd => mem_rd_8, + rle_in => rle_in, + rle_out => rle_out_8 + ); + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/muldex_16.vhd b/libraries/Wishbone_Sump_LA/muldex_16.vhd new file mode 100644 index 0000000..f8686e9 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/muldex_16.vhd @@ -0,0 +1,153 @@ +---------------------------------------------------------------------------------- +-- muldex_8.vhd +-- +-- Copyright (C) 2011 Kinsa +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public Licenstate_wre as published by +-- the Free Software Foundation; either version 2 of the Licenstate_wre, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public Licenstate_wre for more details. +-- +-- You should have received a copy of the GNU General Public Licenstate_wre along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Multiplexes and demultiplexes the 16 bit data into a 32 bit memory bus. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity muldex_16 is + port( + clock : in std_logic; + reset : in std_logic; + data_inp : in std_logic_vector (15 downto 0); + data_out : out std_logic_vector (15 downto 0); + data_wr : in std_logic; + data_rd : in std_logic; + mem_inp : in std_logic_vector (33 downto 0); + mem_out : out std_logic_vector (33 downto 0); + mem_wr : out std_logic; + mem_rd : out std_logic; + rle_in : in std_logic; + rle_out : out std_logic + ); +end muldex_16; + +architecture behavioral of muldex_16 is + + type wr_state_type is (W0, W1); + type rd_state_type is (RI, R0, R1); + + signal state_wr, nstate_wr : wr_state_type; + signal state_rd, nstate_rd : rd_state_type; + signal wrtmp, wrtmp_r, rdtmp, rdtmp_r : std_logic_vector (33 downto 0); + signal mw, mr : std_logic; + +begin + + process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + state_wr <= W0; + state_rd <= RI; + else + state_wr <= nstate_wr; + state_rd <= nstate_rd; + end if; + wrtmp_r <= wrtmp; + rdtmp_r <= rdtmp; + + -- registered outputs + mem_out <= wrtmp; + mem_wr <= mw; + mem_rd <= mr; + end if; + end process; + + process(state_wr, data_wr, rle_in, wrtmp_r, data_inp) + begin + case state_wr is + when W0 => + if data_wr = '1' then + nstate_wr <= W1; + wrtmp <= wrtmp_r(33) & rle_in + & wrtmp_r(31 downto 16) & data_inp; + else + nstate_wr <= state_wr; + wrtmp <= wrtmp_r; + end if; + mw <= '0'; + when W1 => + if data_wr = '1' then + nstate_wr <= W0; + wrtmp <= rle_in & wrtmp_r(32) & data_inp + & wrtmp_r(15 downto 0); + mw <= '1'; + else + nstate_wr <= state_wr; + wrtmp <= wrtmp_r; + mw <= '0'; + end if; + end case; + end process; + + process(state_rd, data_rd, state_wr, wrtmp, rdtmp_r, mem_inp) + begin + case state_rd is + when RI => + if data_rd = '1' then + if state_wr = W0 then + nstate_rd <= R0; + mr <= '1'; + else + nstate_rd <= R1; + mr <= '0'; + end if; + else + nstate_rd <= state_rd; + mr <= '0'; + end if; + rdtmp <= wrtmp; + data_out <= (others => 'X'); + rle_out <= 'X'; + when R0 => + if data_rd = '1' then + nstate_rd <= R1; + else + nstate_rd <= state_rd; + end if; + rdtmp <= rdtmp_r; + mr <= '0'; + data_out <= rdtmp_r(31 downto 16); + rle_out <= rdtmp_r(33); + when R1 => + if data_rd = '1' then + nstate_rd <= R0; + rdtmp <= mem_inp; + mr <= '1'; + else + nstate_rd <= state_rd; + rdtmp <= rdtmp_r; + mr <= '0'; + end if; + data_out <= rdtmp_r(15 downto 0); + rle_out <= rdtmp_r(32); + end case; + end process; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/muldex_8.vhd b/libraries/Wishbone_Sump_LA/muldex_8.vhd new file mode 100644 index 0000000..5ce9be3 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/muldex_8.vhd @@ -0,0 +1,201 @@ +---------------------------------------------------------------------------------- +-- muldex_8.vhd +-- +-- Copyright (C) 2011 Kinsa +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Multiplexes and demultiplexes the 8 bit data into a 32 bit memory bus. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity muldex_8 is + port( + clock : in std_logic; + reset : in std_logic; + data_inp : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0); + data_wr : in std_logic; + data_rd : in std_logic; + mem_inp : in std_logic_vector (35 downto 0); + mem_out : out std_logic_vector (35 downto 0); + mem_wr : out std_logic; + mem_rd : out std_logic; + rle_in : in std_logic; + rle_out : out std_logic + ); +end muldex_8; + +architecture behavioral of muldex_8 is + + type wr_state_type is (W0, W1, W2, W3); + type rd_state_type is (RI, R0, R1, R2, R3); + + signal state_wr, nstate_wr : wr_state_type; + signal state_rd, nstate_rd : rd_state_type; + signal wrtmp, wrtmp_r, rdtmp, rdtmp_r : std_logic_vector (35 downto 0); + signal mw, mr : std_logic; + +begin + + process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + state_wr <= W0; + state_rd <= RI; + else + state_wr <= nstate_wr; + state_rd <= nstate_rd; + end if; + wrtmp_r <= wrtmp; + rdtmp_r <= rdtmp; + + -- registered outputs + mem_out <= wrtmp; + mem_wr <= mw; + mem_rd <= mr; + end if; + end process; + + process(state_wr, data_wr, rle_in, wrtmp_r, data_inp) + begin + case state_wr is + when W0 => + if data_wr = '1' then + nstate_wr <= W1; + wrtmp <= wrtmp_r(35 downto 33) & rle_in + & wrtmp_r(31 downto 8) & data_inp; + else + nstate_wr <= state_wr; + wrtmp <= wrtmp_r; + end if; + mw <= '0'; + when W1 => + if data_wr = '1' then + nstate_wr <= W2; + wrtmp <= wrtmp_r(35 downto 34) & rle_in + & wrtmp_r(32 downto 16) + & data_inp & wrtmp_r(7 downto 0); + else + nstate_wr <= state_wr; + wrtmp <= wrtmp_r; + end if; + mw <= '0'; + when W2 => + if data_wr = '1' then + nstate_wr <= W3; + wrtmp <= wrtmp_r(35 downto 35) & rle_in + & wrtmp_r(33 downto 24) & data_inp + & wrtmp_r(15 downto 0); + else + nstate_wr <= state_wr; + wrtmp <= wrtmp_r; + end if; + mw <= '0'; + when W3 => + if data_wr = '1' then + nstate_wr <= W0; + wrtmp <= rle_in & wrtmp_r(34 downto 32) + & data_inp & wrtmp_r(23 downto 0); + mw <= '1'; + else + nstate_wr <= state_wr; + wrtmp <= wrtmp_r; + mw <= '0'; + end if; + end case; + end process; + + process(state_rd, data_rd, state_wr, wrtmp, rdtmp_r, mem_inp) + begin + case state_rd is + when RI => + if data_rd = '1' then + if state_wr = W0 then + nstate_rd <= R0; + mr <= '1'; + elsif state_wr = W1 then + nstate_rd <= R1; + mr <= '0'; + elsif state_wr = W2 then + nstate_rd <= R2; + mr <= '0'; + else + nstate_rd <= R3; + mr <= '0'; + end if; + else + nstate_rd <= state_rd; + mr <= '0'; + end if; + rdtmp <= wrtmp; + data_out <= (others => 'X'); + rle_out <= 'X'; + when R0 => + if data_rd = '1' then + nstate_rd <= R3; + else + nstate_rd <= state_rd; + end if; + rdtmp <= rdtmp_r; + mr <= '0'; + data_out <= rdtmp_r(31 downto 24); + rle_out <= rdtmp_r(35); + when R1 => + if data_rd = '1' then + nstate_rd <= R0; + rdtmp <= mem_inp; + mr <= '1'; + else + nstate_rd <= state_rd; + rdtmp <= rdtmp_r; + mr <= '0'; + end if; + data_out <= rdtmp_r(7 downto 0); + rle_out <= rdtmp_r(32); + when R2 => + if data_rd = '1' then + nstate_rd <= R1; + else + nstate_rd <= state_rd; + end if; + rdtmp <= rdtmp_r; + mr <= '0'; + data_out <= rdtmp_r(15 downto 8); + rle_out <= rdtmp_r(33); + when R3 => + if data_rd = '1' then + nstate_rd <= R2; + else + nstate_rd <= state_rd; + end if; + rdtmp <= rdtmp_r; + mr <= '0'; + data_out <= rdtmp_r(23 downto 16); + rle_out <= rdtmp_r(34); + end case; + end process; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/prescaler.vhd b/libraries/Wishbone_Sump_LA/prescaler.vhd new file mode 100644 index 0000000..4b2df58 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/prescaler.vhd @@ -0,0 +1,70 @@ +---------------------------------------------------------------------------------- +-- prescaler.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Shared prescaler for transmitter and receiver timings. +-- Used to control the transfer speed. +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity sump_prescaler is + generic ( + SCALE : integer := 54 + ); + Port ( + clock : in STD_LOGIC; + reset : in std_logic; + div : in std_logic_vector(1 downto 0); + scaled : out std_logic + ); +end sump_prescaler; + +architecture Behavioral of sump_prescaler is + +signal counter : integer range 0 to (6 * SCALE) - 1; + +begin + process(clock, reset) + begin + if reset = '1' then + counter <= 0; + elsif rising_edge(clock) then + if + (counter = SCALE - 1 and div = "00") -- 115200 + or (counter = 2 * SCALE - 1 and div = "01") -- 57600 + or (counter = 3 * SCALE - 1 and div = "10") -- 38400 + or (counter = 6 * SCALE - 1 and div = "11") -- 19200 + then + counter <= 0; + scaled <= '1'; + else + counter <= counter + 1; + scaled <= '0'; + end if; + end if; + end process; +end Behavioral; diff --git a/libraries/Wishbone_Sump_LA/receiver.vhd b/libraries/Wishbone_Sump_LA/receiver.vhd new file mode 100644 index 0000000..7fe4e45 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/receiver.vhd @@ -0,0 +1,226 @@ +---------------------------------------------------------------------------------- +-- receiver.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Receives commands from the serial port. The first byte is the commands +-- opcode, the following (optional) four byte are the command data. +-- Commands that do not have the highest bit in their opcode set are +-- considered short commands without data (1 byte long). All other commands are +-- long commands which are 5 bytes long. +-- +-- After a full command has been received it will be kept available for 10 cycles +-- on the op and data outputs. A valid command can be detected by checking if the +-- execute output is set. After 10 cycles the registers will be cleared +-- automatically and the receiver waits for new data from the serial port. +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity receiver is + generic ( + FREQ : integer; + RATE : integer + ); + + Port ( rx : in STD_LOGIC; + clock : in STD_LOGIC; + trxClock : IN std_logic; + reset : in STD_LOGIC; + op : out STD_LOGIC_VECTOR (7 downto 0); + data : out STD_LOGIC_VECTOR (31 downto 0); + execute : out STD_LOGIC + ); +end receiver; + +architecture Behavioral of receiver is + + type UART_STATES is (INIT, WAITSTOP, WAITSTART, WAITBEGIN, READBYTE, ANALYZE, READY); + +-- constant BITLENGTH : integer := FREQ / RATE; + constant BITLENGTH : integer := 16; + + signal counter, ncounter : integer range 0 to BITLENGTH; -- clock prescaling counter + signal bitcount, nbitcount : integer range 0 to 8; -- count rxed bits of current byte + signal bytecount, nbytecount : integer range 0 to 5; -- count rxed bytes of current command + signal state, nstate : UART_STATES; -- receiver state + signal opcode, nopcode : std_logic_vector (7 downto 0); -- opcode byte + signal dataBuf, ndataBuf : std_logic_vector (31 downto 0); -- data dword + +begin + op <= opcode; + data <= dataBuf; + + process(clock, reset) + begin + if reset = '1' then + state <= INIT; + elsif rising_edge(clock) then + counter <= ncounter; + bitcount <= nbitcount; + bytecount <= nbytecount; + dataBuf <= ndataBuf; + opcode <= nopcode; + state <= nstate; + end if; + end process; + + process(trxClock, state, counter, bitcount, bytecount, dataBuf, opcode, rx) + begin + case state is + + -- reset uart + when INIT => + ncounter <= 0; + nbitcount <= 0; + nbytecount <= 0; + nopcode <= (others => '0'); + ndataBuf <= (others => '0'); + nstate <= WAITSTOP; + + -- wait for stop bit + when WAITSTOP => + ncounter <= 0; + nbitcount <= 0; + nbytecount <= bytecount; + nopcode <= opcode; + ndataBuf <= dataBuf; + if rx = '1' then + nstate <= WAITSTART; + else + nstate <= state; + end if; + + -- wait for start bit + when WAITSTART => + ncounter <= 0; + nbitcount <= 0; + nbytecount <= bytecount; + nopcode <= opcode; + ndataBuf <= dataBuf; + if rx = '0' then + nstate <= WAITBEGIN; + else + nstate <= state; + end if; + + -- wait for first half of start bit + when WAITBEGIN => + nbitcount <= 0; + nbytecount <= bytecount; + nopcode <= opcode; + ndataBuf <= dataBuf; + if counter = BITLENGTH / 2 then + ncounter <= 0; + nstate <= READBYTE; + else + if trxClock = '1' then + ncounter <= counter + 1; + else + ncounter <= counter; + end if; + nstate <= state; + end if; + + -- receive byte + when READBYTE => + if counter = BITLENGTH then + ncounter <= 0; + nbitcount <= bitcount + 1; + if bitcount = 8 then + nbytecount <= bytecount + 1; + nstate <= ANALYZE; + nopcode <= opcode; + ndataBuf <= dataBuf; + else + nbytecount <= bytecount; + if bytecount = 0 then + nopcode <= rx & opcode(7 downto 1); + ndataBuf <= dataBuf; + else + nopcode <= opcode; + ndataBuf <= rx & dataBuf(31 downto 1); + end if; + nstate <= state; + end if; + else + if trxClock = '1' then + ncounter <= counter + 1; + else + ncounter <= counter; + end if; + nbitcount <= bitcount; + nbytecount <= bytecount; + nopcode <= opcode; + ndataBuf <= dataBuf; + nstate <= state; + end if; + + -- check if long or short command has been fully received + when ANALYZE => + ncounter <= 0; + nbitcount <= 0; + nbytecount <= bytecount; + nopcode <= opcode; + ndataBuf <= dataBuf; + -- long command when 5 bytes have been received + if bytecount = 5 then + nstate <= READY; + -- short command when set flag not set + elsif opcode(7) = '0' then + nstate <= READY; + -- otherwise continue receiving + else + nstate <= WAITSTOP; + end if; + + -- done, give 10 cycles for processing + when READY => + ncounter <= counter + 1; + nbitcount <= 0; + nbytecount <= 0; + nopcode <= opcode; + ndataBuf <= dataBuf; + if counter = 10 then + nstate <= INIT; + else + nstate <= state; + end if; + + end case; + + end process; + + -- set execute flag properly + process(state) + begin + if state = READY then + execute <= '1'; + else + execute <= '0'; + end if; + end process; + +end Behavioral; diff --git a/libraries/Wishbone_Sump_LA/rle.vhd b/libraries/Wishbone_Sump_LA/rle.vhd new file mode 100644 index 0000000..ae00f72 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/rle.vhd @@ -0,0 +1,295 @@ +---------------------------------------------------------------------------------- +-- rle_enc.vhd +-- +-- Copyright (C) 2011 Kinsa +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity rle is + port( + clock : in std_logic; + reset : in std_logic; + enable : in std_logic; + raw_inp : in std_logic_vector (31 downto 0); + raw_inp_valid : in std_logic; + rle_out : out std_logic_vector (32 downto 0); + rle_out_valid : out std_logic; + rle_inp : in std_logic_vector (32 downto 0); + rle_inp_valid : in std_logic; + fmt_out : out std_logic_vector (31 downto 0); + busy : out std_logic; + rle_ready : out std_logic; + raw_ready : in std_logic; +-- start_count : in std_logic; +-- data_count : out std_logic_vector(15 downto 0); + data_size : in std_logic_vector(1 downto 0) + ); +end rle; + +architecture behavioral of rle is + + component rle_enc + generic( + data_width : integer + ); + port( + clock : in std_logic; + raw_inp : in std_logic_vector ((data_width-1) downto 0); + rle_out : out std_logic_vector ((data_width-1) downto 0); + raw_inp_valid : in std_logic; + rle_out_valid : out std_logic; + rle_bit : out std_logic + ); + end component; + + component rle_fmt + generic( + data_width : integer + ); + port( + clock : in std_logic; + reset : in std_logic; + rle_inp : in std_logic_vector (data_width downto 0); + fmt_out : out std_logic_vector ((data_width-1) downto 0); + rle_inp_valid : in std_logic; + busy : out std_logic; + raw_ready : in std_logic; + rle_ready : out std_logic + ); + end component; + + signal rle_tmp, valid_out : std_logic; + +begin + + rle_out_valid <= valid_out; + + format_block: block + signal fmt_out_8 : std_logic_vector (7 downto 0); + signal fmt_out_16 : std_logic_vector (15 downto 0); + signal fmt_out_i, fmt_out_32 : std_logic_vector (31 downto 0); + signal rle_inp_8 : std_logic_vector (8 downto 0); + signal rle_inp_16 : std_logic_vector (16 downto 0); + signal busy_i, busy_8, busy_16, busy_32 : std_logic; + signal delayed_ready : std_logic; + signal rle_ready_i, rle_ready_8, rle_ready_16, rle_ready_32 : std_logic; + begin + + rle_inp_8 <= rle_inp(32 downto 32) & rle_inp(7 downto 0); + rle_inp_16 <= rle_inp(32 downto 32) & rle_inp(15 downto 0); + + busy_i <= + '0' when enable = '0' else + busy_8 when data_size = "01" else + busy_16 when data_size = "10" else + busy_32 when data_size = "00" else + 'X'; + + rle_ready_i <= + delayed_ready when enable = '0' else + rle_ready_8 when data_size = "01" else + rle_ready_16 when data_size = "10" else + rle_ready_32 when data_size = "00" else + 'X'; + + fmt_out_i <= + rle_inp(31 downto 0) when enable = '0' else + x"000000" & fmt_out_8 when data_size = "01" else + x"0000" & fmt_out_16 when data_size = "10" else + fmt_out_32 when data_size = "00" else + (others => 'X'); + + -- register outputs + process(clock) + begin + if rising_edge(clock) then + fmt_out <= fmt_out_i; + busy <= busy_i; + rle_ready <= rle_ready_i; + delayed_ready <= raw_ready; + end if; + end process; + + Inst_rle_fmt_8: rle_fmt + generic map( + data_width => 8 + ) + port map ( + clock => clock, + reset => reset, + rle_inp => rle_inp_8, + fmt_out => fmt_out_8, + rle_inp_valid => rle_inp_valid, + busy => busy_8, + raw_ready => raw_ready, + rle_ready => rle_ready_8 + ); + + Inst_rle_fmt_16: rle_fmt + generic map( + data_width => 16 + ) + port map ( + clock => clock, + reset => reset, + rle_inp => rle_inp_16, + fmt_out => fmt_out_16, + rle_inp_valid => rle_inp_valid, + busy => busy_16, + raw_ready => raw_ready, + rle_ready => rle_ready_16 + ); + + Inst_rle_fmt_32: rle_fmt + generic map( + data_width => 32 + ) + port map ( + clock => clock, + reset => reset, + rle_inp => rle_inp, + fmt_out => fmt_out_32, + rle_inp_valid => rle_inp_valid, + busy => busy_32, + raw_ready => raw_ready, + rle_ready => rle_ready_32 + ); + + end block; + + encoder_block: block + signal out_8 : std_logic_vector (7 downto 0); + signal out_16 : std_logic_vector (15 downto 0); + signal out_32 : std_logic_vector (31 downto 0); + signal val_out_8, val_out_16, val_out_32, + rle_bit_8, rle_bit_16, rle_bit_32 : std_logic; + begin + rle_tmp <= + rle_bit_8 when data_size = "01" else + rle_bit_16 when data_size = "10" else + rle_bit_32 when data_size = "00" else + 'X'; + + valid_out <= + raw_inp_valid when enable = '0' else + val_out_8 when data_size = "01" else + val_out_16 when data_size = "10" else + val_out_32 when data_size = "00" else + 'X'; + + rle_out <= + '0' & raw_inp when enable = '0' else + rle_tmp & x"000000" & out_8 when data_size = "01" else + rle_tmp & x"0000" & out_16 when data_size = "10" else + rle_tmp & out_32 when data_size = "00" else + (others => 'X'); + + Inst_rle_enc_8: rle_enc + generic map( + data_width => 8 + ) + port map ( + clock => clock, + raw_inp => raw_inp(7 downto 0), + raw_inp_valid => raw_inp_valid, + rle_out => out_8, + rle_out_valid => val_out_8, + rle_bit => rle_bit_8 + ); + + Inst_rle_enc_16: rle_enc + generic map( + data_width => 16 + ) + port map ( + clock => clock, + raw_inp => raw_inp(15 downto 0), + raw_inp_valid => raw_inp_valid, + rle_out => out_16, + rle_out_valid => val_out_16, + rle_bit => rle_bit_16 + ); + + Inst_rle_enc_32: rle_enc + generic map( + data_width => 32 + ) + port map ( + clock => clock, + raw_inp => raw_inp(31 downto 0), + raw_inp_valid => raw_inp_valid, + rle_out => out_32, + rle_out_valid => val_out_32, + rle_bit => rle_bit_32 + ); + end block; + + -- data counter +-- counter_block: block +-- type state_type is (S0, S1); +-- signal cs, ns : state_type; +-- signal dcnt, dcntreg : std_logic_vector (15 downto 0); +-- begin +-- -- synchronous +-- process(clock, reset) +-- begin +-- if rising_edge(clock) then +-- if reset = '1' then +-- cs <= S0; +-- else +-- cs <= ns; +-- end if; +-- dcntreg <= dcnt; +-- end if; +-- end process; +-- +-- -- combinatorial +-- process(cs, dcntreg, rle_tmp, valid_out, start_count) +-- begin +-- case cs is +-- when S0 => +-- if start_count = '1' then +-- ns <= S1; +-- else +-- ns <= cs; +-- end if; +-- dcnt <= (others => '0'); +-- when S1 => +-- -- counts the current data transitions +-- if valid_out = '1' and rle_tmp = '0' then +-- dcnt <= dcntreg + 1; +-- else +-- dcnt <= dcntreg; +-- end if; +-- ns <= cs; +-- end case; +-- end process; +-- +-- data_count <= dcnt; +-- +-- end block; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/rle_enc.vhd b/libraries/Wishbone_Sump_LA/rle_enc.vhd new file mode 100644 index 0000000..d9f362b --- /dev/null +++ b/libraries/Wishbone_Sump_LA/rle_enc.vhd @@ -0,0 +1,113 @@ +---------------------------------------------------------------------------------- +-- rle_enc.vhd +-- +-- Copyright (C) 2011 Kinsa +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity rle_enc is + generic( + data_width : integer := 32 + ); + port( + clock : in std_logic; + raw_inp : in std_logic_vector ((data_width-1) downto 0); + rle_out : out std_logic_vector ((data_width-1) downto 0); + raw_inp_valid : in std_logic; + rle_out_valid : out std_logic; + rle_bit : out std_logic + ); +end rle_enc; + +architecture behavioral of rle_enc is + + signal count, data, rle_out_i : std_logic_vector ((data_width-1) downto 0); + signal c0, c1, c2, c3, valid, rle : std_logic; + signal state : std_logic_vector(3 downto 0); + +begin + + -- count repeating data + process(clock) + begin + if rising_edge(clock) then + if raw_inp_valid = '1' then + if data = raw_inp then + count <= count + 1; + else + data <= raw_inp; + count <= (others => '0'); + end if; + end if; + end if; + end process; + + + -- previous and current data is not the same; send old data + c0 <= '1' when data /= raw_inp and count = 0 else '0'; + -- start of repeating data; send current data + c1 <= '1' when data = raw_inp and count = 0 else '0'; + -- end of repeating data; send count + c2 <= '1' when data /= raw_inp and count /= 0 else '0'; + -- count overflow; send count + c3 <= '1' when data = raw_inp and 0 = not count else '0'; + + state <= c3 & c2 & c1 & c0; + + rle_out_i <= + data when state = "0001" else + data when state = "0010" else + count when state = "0100" else + count when state = "1000" else + (others => 'X'); + + valid <= + '1' when state = "0001" else + '1' when state = "0010" else + '1' when state = "0100" else + '1' when state = "1000" else + '0'; + + rle <= + '1' when state = "0100" else + '1' when state = "1000" else + '0'; + + process(clock) + begin + if rising_edge(clock) then + if raw_inp_valid = '1' then + rle_out <= rle_out_i; + rle_out_valid <= valid; + rle_bit <= rle; + else + rle_out_valid <= '0'; + rle_bit <= '0'; + end if; + end if; + end process; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/rle_fmt.vhd b/libraries/Wishbone_Sump_LA/rle_fmt.vhd new file mode 100644 index 0000000..c57d88b --- /dev/null +++ b/libraries/Wishbone_Sump_LA/rle_fmt.vhd @@ -0,0 +1,136 @@ +--------------------------------------------------------------------------------- +-- rle_fmt.vhd +-- +-- Copyright (C) 2011 Kinsa +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- inserts a zero count when the rle bit is not set. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity rle_fmt is + generic( + data_width : integer := 32 + ); + port( + clock : in std_logic; + reset : in std_logic; + rle_inp : in std_logic_vector (data_width downto 0); + fmt_out : out std_logic_vector ((data_width-1) downto 0); + rle_inp_valid : in std_logic; + busy : out std_logic; + raw_ready : in std_logic; + rle_ready : out std_logic + ); +end rle_fmt; + +architecture behavioral of rle_fmt is + + type state_type is (S0, S1, S2, S3, S4); + + signal state, nstate : state_type; + signal tmp, tmp_r, fmt_out_i, fmt_out_r : std_logic_vector ((data_width-1) downto 0); + signal busy_i, rle_ready_i : std_logic; + +begin + + fmt_out <= fmt_out_i; + + process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + state <= S0; + else + state <= nstate; + tmp_r <= tmp; + busy <= busy_i; + fmt_out_r <= fmt_out_i; + rle_ready <= rle_ready_i; + end if; + end if; + end process; + + busy_i <= '1' when state = S4 else '0'; + + process(state, rle_inp_valid, raw_ready, rle_inp, tmp, tmp_r, fmt_out_r) + begin + case state is + when S0 => + if rle_inp_valid = '1' then + nstate <= S1; + else + nstate <= state; + end if; + fmt_out_i <= fmt_out_r; + tmp <= tmp_r; + rle_ready_i <= '0'; + when S1 => + if raw_ready = '1' then + if rle_inp(data_width) = '1' then + nstate <= S2; + fmt_out_i <= rle_inp((data_width - 1) downto 0); + else + nstate <= S4; + fmt_out_i <= (others => '0'); + end if; + else + nstate <= state; + fmt_out_i <= fmt_out_r; + end if; + tmp <= rle_inp((data_width - 1) downto 0); + rle_ready_i <= raw_ready; + when S2 => -- send RLE data + if rle_inp_valid = '1' then + nstate <= S3; + else + nstate <= state; + end if; + fmt_out_i <= rle_inp((data_width - 1) downto 0); + tmp <= tmp_r; + rle_ready_i <= '0'; + when S3 => + if raw_ready = '1' then + nstate <= S0; + else + nstate <= state; + end if; + fmt_out_i <= rle_inp((data_width - 1) downto 0); + tmp <= tmp_r; + rle_ready_i <= raw_ready; + when S4 => -- send RLE data, counts = 0 + if rle_inp_valid = '1' then + nstate <= S0; + fmt_out_i <= tmp; + else + nstate <= state; + fmt_out_i <= fmt_out_r; + end if; + tmp <= tmp_r; + rle_ready_i <= rle_inp_valid; + end case; + end process; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/sampler.vhd b/libraries/Wishbone_Sump_LA/sampler.vhd new file mode 100644 index 0000000..671f502 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/sampler.vhd @@ -0,0 +1,116 @@ +---------------------------------------------------------------------------------- +-- sampler.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Produces samples from la_input applying a programmable divider to the clock. +-- Sampling rate can be calculated by: +-- +-- r = f / (d + 1) +-- +-- Where r is the sampling rate, f is the clock frequency and d is the value +-- programmed into the divider register. +-- +-- As of version 0.6 sampling on an external clock is also supported. If external +-- is set '1', the external clock will be used to sample data. (Divider is +-- ignored for this.) +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity sampler is + port( + la_input : in std_logic_vector(31 downto 0); -- 32 la_input channels + clock : in std_logic; -- internal clock + exClock : in std_logic; -- external clock + external : in std_logic; -- clock selection + data : in std_logic_vector(23 downto 0); -- configuration data + wrDivider : in std_logic; -- write divider register + sample : out std_logic_vector(31 downto 0); -- sampled data + ready : out std_logic; -- new sample ready + trig_delay : out std_logic_vector(1 downto 0); + num_scheme : in std_logic + ); +end sampler; + +architecture behavioral of sampler is + + signal divider, counter : std_logic_vector (23 downto 0); + signal lastExClock, syncExClock : std_logic; + signal la_input_i : std_logic_vector(31 downto 0); + +begin + + trig_delay <= + "01" when divider = 0 else + "10" when divider = 1 else + "00"; + + process(la_input, num_scheme) + begin + if num_scheme = '1' then + for i in 31 downto 0 loop + la_input_i(i) <= la_input(31 - i); + end loop; + else + la_input_i <= la_input; + end if; + end process; + + -- sample data + process(clock) + begin + if rising_edge(clock) then + syncExClock <= exClock; + + if wrDivider = '1' then + divider <= data(23 downto 0); + counter <= (others => '0'); + ready <= '0'; + + elsif external = '1' then + if syncExClock = '0' and lastExClock = '1' then + ready <= '1'; + else + sample <= la_input_i; + ready <= '0'; + end if; + lastExClock <= syncExClock; + + elsif counter = divider then + sample <= la_input_i; + counter <= (others => '0'); + ready <= '1'; + + else + counter <= counter + 1; + ready <= '0'; + + end if; + end if; + end process; + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/sim.vhd b/libraries/Wishbone_Sump_LA/sim.vhd new file mode 100644 index 0000000..3aee5cf --- /dev/null +++ b/libraries/Wishbone_Sump_LA/sim.vhd @@ -0,0 +1,112 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +package sim is + + procedure hexread(L : inout line; value:out bit_vector); + procedure hexread(L : inout line; value:out std_logic_vector); + function ishex(c : character) return boolean; + +end package; + +package body sim is + + procedure char2hex(C: character; result: out bit_vector(3 downto 0); + good: out boolean; report_error: in boolean) is + begin + good := true; + case C is + when '0' => result := x"0"; + when '1' => result := x"1"; + when '2' => result := X"2"; + when '3' => result := X"3"; + when '4' => result := X"4"; + when '5' => result := X"5"; + when '6' => result := X"6"; + when '7' => result := X"7"; + when '8' => result := X"8"; + when '9' => result := X"9"; + when 'A' => result := X"A"; + when 'B' => result := X"B"; + when 'C' => result := X"C"; + when 'D' => result := X"D"; + when 'E' => result := X"E"; + when 'F' => result := X"F"; + + when 'a' => result := X"A"; + when 'b' => result := X"B"; + when 'c' => result := X"C"; + when 'd' => result := X"D"; + when 'e' => result := X"E"; + when 'f' => result := X"F"; + when others => + if report_error then + assert false report + "hexread error: read a '" & C & "', expected a hex character (0-F)."; + end if; + good := false; + end case; + end; + + procedure hexread(L:inout line; value:out bit_vector) is + variable OK: boolean; + variable C: character; + constant NE: integer := value'length/4; --' + variable BV: bit_vector(0 to value'length-1); --' + variable S: string(1 to NE-1); + begin + if value'length mod 4 /= 0 then --' + assert false report + "hexread Error: Trying to read vector " & + "with an odd (non multiple of 4) length"; + return; + end if; + + loop -- skip white space + read(L,C); + exit when ((C /= ' ') and (C /= CR) and (C /= HT)); + end loop; + char2hex(C, BV(0 to 3), OK, false); + if not OK then + return; + end if; + + read(L, S, OK); +-- if not OK then +-- assert false report "hexread Error: Failed to read the STRING"; +-- return; +-- end if; + + for I in 1 to NE-1 loop + char2hex(S(I), BV(4*I to 4*I+3), OK, false); + if not OK then + return; + end if; + end loop; + value := BV; + end hexread; + + procedure hexread(L:inout line; value:out std_ulogic_vector) is + variable tmp: bit_vector(value'length-1 downto 0); --' + begin + hexread(L, tmp); + value := TO_X01(tmp); + end hexread; + + procedure hexread(L:inout line; value:out std_logic_vector) is + variable tmp: std_ulogic_vector(value'length-1 downto 0); --' + begin + hexread(L, tmp); + value := std_logic_vector(tmp); + end hexread; + + function ishex(c:character) return boolean is + variable tmp : bit_vector(3 downto 0); + variable OK : boolean; + begin + char2hex(C, tmp, OK, false); + return OK; + end ishex; + +end ; \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/sincos_lut.vhd b/libraries/Wishbone_Sump_LA/sincos_lut.vhd new file mode 100644 index 0000000..7bb92ae --- /dev/null +++ b/libraries/Wishbone_Sump_LA/sincos_lut.vhd @@ -0,0 +1,1091 @@ +---------------------------------------------------------------------- +-- -- +-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE -- +-- -- +---------------------------------------------------------------------- +-- -- +-- Filename : sincos_lut.vhd -- +-- -- +-- Author : Simon Doherty -- +-- Senior Design Consultant -- +-- www.zipcores.com -- +-- -- +-- Date last modified : 26.05.2008 -- +-- -- +-- Description : 4096 x 12-bit SIN/COS Look-up table -- +-- -- +---------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +entity sincos_lut is + +port ( + + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + sin_out : out std_logic_vector(11 downto 0); + cos_out : out std_logic_vector(11 downto 0) + + ); + +end entity; + + +architecture rtl of sincos_lut is + + +type rom_type is array (0 to 4095) of std_logic_vector (11 downto 0); + +constant SIN_ROM : rom_type := + +( +X"000", X"003", X"006", X"009", X"00d", X"010", X"013", X"016", +X"019", X"01c", X"01f", X"023", X"026", X"029", X"02c", X"02f", +X"032", X"035", X"039", X"03c", X"03f", X"042", X"045", X"048", +X"04b", X"04e", X"052", X"055", X"058", X"05b", X"05e", X"061", +X"064", X"068", X"06b", X"06e", X"071", X"074", X"077", X"07a", +X"07e", X"081", X"084", X"087", X"08a", X"08d", X"090", X"093", +X"097", X"09a", X"09d", X"0a0", X"0a3", X"0a6", X"0a9", X"0ac", +X"0b0", X"0b3", X"0b6", X"0b9", X"0bc", X"0bf", X"0c2", X"0c6", +X"0c9", X"0cc", X"0cf", X"0d2", X"0d5", X"0d8", X"0db", X"0df", +X"0e2", X"0e5", X"0e8", X"0eb", X"0ee", X"0f1", X"0f4", X"0f7", +X"0fb", X"0fe", X"101", X"104", X"107", X"10a", X"10d", X"110", +X"113", X"117", X"11a", X"11d", X"120", X"123", X"126", X"129", +X"12c", X"12f", X"133", X"136", X"139", X"13c", X"13f", X"142", +X"145", X"148", X"14b", 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X"8a0", X"89f", X"89e", +X"89d", X"89c", X"89a", X"899", X"898", X"897", X"896", X"895", +X"893", X"892", X"891", X"890", X"88f", X"88e", X"88c", X"88b", +X"88a", X"889", X"888", X"887", X"886", X"885", X"883", X"882", +X"881", X"880", X"87f", X"87e", X"87d", X"87c", X"87b", X"87a", +X"879", X"878", X"877", X"876", X"874", X"873", X"872", X"871", +X"870", X"86f", X"86e", X"86d", X"86c", X"86b", X"86a", X"869", +X"868", X"867", X"866", X"865", X"864", X"863", X"862", X"862", +X"861", X"860", X"85f", X"85e", X"85d", X"85c", X"85b", X"85a", +X"859", X"858", X"857", X"856", X"856", X"855", X"854", X"853", +X"852", X"851", X"850", X"84f", X"84f", X"84e", X"84d", X"84c", +X"84b", X"84a", X"849", X"849", X"848", X"847", X"846", X"845", +X"845", X"844", X"843", X"842", X"841", X"841", X"840", X"83f", +X"83e", X"83e", X"83d", X"83c", X"83b", X"83b", X"83a", X"839", +X"838", X"838", X"837", X"836", X"836", X"835", X"834", X"833", +X"833", X"832", X"831", X"831", X"830", X"82f", X"82f", X"82e", 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X"801", X"801", X"801", X"801", X"801", +X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"801", +X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"801", +X"801", X"801", X"801", X"801", X"801", X"801", X"801", X"802", +X"802", X"802", X"802", X"802", X"802", X"802", X"802", X"802", +X"802", X"803", X"803", X"803", X"803", X"803", X"803", X"803", +X"803", X"804", X"804", X"804", X"804", X"804", X"804", X"805", +X"805", X"805", X"805", X"805", X"806", X"806", X"806", X"806", +X"807", X"807", X"807", X"807", X"808", X"808", X"808", X"808", +X"809", X"809", X"809", X"809", X"80a", X"80a", X"80a", X"80b", +X"80b", X"80b", X"80b", X"80c", X"80c", X"80c", X"80d", X"80d", +X"80d", X"80e", X"80e", X"80f", X"80f", X"80f", X"810", X"810", +X"810", X"811", X"811", X"812", X"812", X"812", X"813", X"813", +X"814", X"814", X"814", X"815", X"815", X"816", X"816", X"817", +X"817", X"818", X"818", X"819", X"819", X"81a", X"81a", X"81a", +X"81b", X"81b", X"81c", X"81d", X"81d", X"81e", X"81e", X"81f", +X"81f", X"820", X"820", X"821", X"821", X"822", X"822", X"823", +X"824", X"824", X"825", X"825", X"826", X"827", X"827", X"828", +X"828", X"829", X"82a", X"82a", X"82b", X"82b", X"82c", X"82d", +X"82d", X"82e", X"82f", X"82f", X"830", X"831", X"831", X"832", +X"833", X"833", X"834", X"835", X"836", X"836", X"837", X"838", +X"838", X"839", X"83a", X"83b", X"83b", X"83c", X"83d", X"83e", +X"83e", X"83f", X"840", X"841", X"841", X"842", X"843", X"844", +X"845", X"845", X"846", X"847", X"848", X"849", X"849", X"84a", +X"84b", X"84c", X"84d", X"84e", X"84f", X"84f", X"850", X"851", +X"852", X"853", X"854", X"855", X"856", X"856", X"857", X"858", +X"859", X"85a", X"85b", X"85c", X"85d", X"85e", X"85f", X"860", +X"861", X"862", X"862", X"863", X"864", X"865", X"866", X"867", +X"868", X"869", X"86a", X"86b", X"86c", X"86d", X"86e", X"86f", +X"870", X"871", X"872", X"873", X"874", X"876", X"877", X"878", +X"879", X"87a", X"87b", X"87c", X"87d", X"87e", X"87f", X"880", +X"881", X"882", X"883", X"885", X"886", X"887", X"888", X"889", +X"88a", X"88b", X"88c", X"88e", X"88f", X"890", X"891", X"892", +X"893", X"895", X"896", X"897", X"898", X"899", X"89a", X"89c", +X"89d", X"89e", X"89f", X"8a0", X"8a2", X"8a3", X"8a4", X"8a5", +X"8a7", X"8a8", X"8a9", X"8aa", X"8ac", X"8ad", X"8ae", X"8af", +X"8b1", X"8b2", X"8b3", X"8b4", X"8b6", X"8b7", X"8b8", X"8ba", +X"8bb", X"8bc", X"8be", X"8bf", X"8c0", X"8c2", X"8c3", X"8c4", +X"8c6", X"8c7", X"8c8", X"8ca", X"8cb", X"8cc", X"8ce", X"8cf", +X"8d0", X"8d2", X"8d3", X"8d5", X"8d6", X"8d7", X"8d9", X"8da", +X"8dc", X"8dd", X"8de", X"8e0", X"8e1", X"8e3", X"8e4", X"8e6", +X"8e7", X"8e8", X"8ea", X"8eb", X"8ed", X"8ee", X"8f0", X"8f1", +X"8f3", X"8f4", X"8f6", X"8f7", X"8f9", X"8fa", X"8fc", X"8fd", +X"8ff", X"900", X"902", X"903", X"905", X"906", X"908", X"909", +X"90b", X"90c", X"90e", X"910", X"911", X"913", X"914", X"916", +X"917", X"919", X"91b", X"91c", X"91e", X"91f", X"921", X"923", +X"924", X"926", X"927", X"929", X"92b", X"92c", X"92e", X"930", +X"931", X"933", X"935", X"936", X"938", X"93a", X"93b", X"93d", +X"93f", X"940", X"942", X"944", X"945", X"947", X"949", X"94a", +X"94c", X"94e", X"950", X"951", X"953", X"955", X"957", X"958", +X"95a", X"95c", X"95d", X"95f", X"961", X"963", X"965", X"966", +X"968", X"96a", X"96c", X"96d", X"96f", X"971", X"973", X"975", +X"976", X"978", X"97a", X"97c", X"97e", X"97f", X"981", X"983", +X"985", X"987", X"989", X"98b", X"98c", X"98e", X"990", X"992", +X"994", X"996", X"998", X"999", X"99b", X"99d", X"99f", X"9a1", +X"9a3", X"9a5", X"9a7", X"9a9", X"9ab", X"9ac", X"9ae", X"9b0", +X"9b2", X"9b4", X"9b6", X"9b8", X"9ba", X"9bc", X"9be", X"9c0", +X"9c2", X"9c4", X"9c6", X"9c8", X"9ca", X"9cc", X"9ce", X"9d0", +X"9d2", X"9d4", X"9d6", X"9d8", X"9da", X"9dc", X"9de", X"9e0", +X"9e2", X"9e4", X"9e6", X"9e8", X"9ea", X"9ec", X"9ee", X"9f0", +X"9f2", X"9f4", X"9f6", X"9f8", X"9fa", X"9fc", X"9fe", X"a00", +X"a03", X"a05", X"a07", X"a09", X"a0b", X"a0d", X"a0f", X"a11", +X"a13", X"a15", X"a17", X"a1a", X"a1c", X"a1e", X"a20", X"a22", +X"a24", X"a26", X"a29", X"a2b", X"a2d", X"a2f", X"a31", X"a33", +X"a35", X"a38", X"a3a", X"a3c", X"a3e", X"a40", X"a43", X"a45", +X"a47", X"a49", X"a4b", X"a4d", X"a50", X"a52", X"a54", X"a56", +X"a59", X"a5b", X"a5d", X"a5f", X"a61", X"a64", X"a66", X"a68", +X"a6a", X"a6d", X"a6f", X"a71", X"a73", X"a76", X"a78", X"a7a", +X"a7d", X"a7f", X"a81", X"a83", X"a86", X"a88", X"a8a", X"a8d", +X"a8f", X"a91", X"a93", X"a96", X"a98", X"a9a", X"a9d", X"a9f", +X"aa1", X"aa4", X"aa6", X"aa8", X"aab", X"aad", X"aaf", X"ab2", +X"ab4", X"ab6", X"ab9", X"abb", X"abd", X"ac0", X"ac2", X"ac5", +X"ac7", X"ac9", X"acc", X"ace", X"ad0", X"ad3", X"ad5", X"ad8", +X"ada", X"adc", X"adf", X"ae1", X"ae4", X"ae6", X"ae9", X"aeb", +X"aed", X"af0", X"af2", X"af5", X"af7", X"afa", X"afc", X"afe", +X"b01", X"b03", X"b06", X"b08", X"b0b", X"b0d", X"b10", X"b12", +X"b15", X"b17", X"b1a", X"b1c", X"b1f", X"b21", X"b24", X"b26", +X"b29", X"b2b", X"b2e", X"b30", X"b33", X"b35", X"b38", X"b3a", +X"b3d", X"b3f", X"b42", X"b44", X"b47", X"b49", X"b4c", X"b4e", +X"b51", X"b53", X"b56", X"b59", X"b5b", X"b5e", X"b60", X"b63", +X"b65", X"b68", X"b6a", X"b6d", X"b70", X"b72", X"b75", X"b77", +X"b7a", X"b7d", X"b7f", X"b82", X"b84", X"b87", X"b8a", X"b8c", +X"b8f", X"b91", X"b94", X"b97", X"b99", X"b9c", X"b9e", X"ba1", +X"ba4", X"ba6", X"ba9", X"bac", X"bae", X"bb1", X"bb4", X"bb6", +X"bb9", X"bbc", X"bbe", X"bc1", X"bc3", X"bc6", X"bc9", X"bcb", +X"bce", X"bd1", X"bd4", X"bd6", X"bd9", X"bdc", X"bde", X"be1", +X"be4", X"be6", X"be9", X"bec", X"bee", X"bf1", X"bf4", X"bf7", +X"bf9", X"bfc", X"bff", X"c01", X"c04", X"c07", X"c0a", X"c0c", +X"c0f", X"c12", X"c15", X"c17", X"c1a", X"c1d", X"c1f", X"c22", +X"c25", X"c28", X"c2a", X"c2d", X"c30", X"c33", X"c36", X"c38", +X"c3b", X"c3e", X"c41", X"c43", X"c46", X"c49", X"c4c", X"c4e", +X"c51", X"c54", X"c57", X"c5a", X"c5c", X"c5f", X"c62", X"c65", +X"c68", X"c6a", X"c6d", X"c70", X"c73", X"c76", X"c79", X"c7b", +X"c7e", X"c81", X"c84", X"c87", X"c89", X"c8c", X"c8f", X"c92", +X"c95", X"c98", X"c9a", X"c9d", X"ca0", X"ca3", X"ca6", X"ca9", +X"cac", X"cae", X"cb1", X"cb4", X"cb7", X"cba", X"cbd", X"cc0", +X"cc2", X"cc5", X"cc8", X"ccb", X"cce", X"cd1", X"cd4", X"cd7", +X"cd9", X"cdc", X"cdf", X"ce2", X"ce5", X"ce8", X"ceb", X"cee", +X"cf1", X"cf4", X"cf6", X"cf9", X"cfc", X"cff", X"d02", X"d05", +X"d08", X"d0b", X"d0e", X"d11", X"d14", X"d17", X"d19", X"d1c", +X"d1f", X"d22", X"d25", X"d28", X"d2b", X"d2e", X"d31", X"d34", +X"d37", X"d3a", X"d3d", X"d40", X"d43", X"d46", X"d48", X"d4b", +X"d4e", X"d51", X"d54", X"d57", X"d5a", X"d5d", X"d60", X"d63", +X"d66", X"d69", X"d6c", X"d6f", X"d72", X"d75", X"d78", X"d7b", +X"d7e", X"d81", X"d84", X"d87", X"d8a", X"d8d", X"d90", X"d93", +X"d96", X"d99", X"d9c", X"d9f", X"da2", X"da5", X"da8", X"dab", +X"dae", X"db1", X"db4", X"db7", X"dba", X"dbd", X"dc0", X"dc3", +X"dc6", X"dc9", X"dcc", X"dcf", X"dd2", X"dd5", X"dd8", X"ddb", +X"dde", X"de1", X"de4", X"de7", X"dea", X"ded", X"df0", X"df3", +X"df6", X"df9", X"dfc", X"dff", X"e02", X"e05", X"e09", X"e0c", +X"e0f", X"e12", X"e15", X"e18", X"e1b", X"e1e", X"e21", X"e24", +X"e27", X"e2a", X"e2d", X"e30", X"e33", X"e36", X"e39", X"e3c", +X"e3f", X"e43", X"e46", X"e49", X"e4c", X"e4f", X"e52", X"e55", +X"e58", X"e5b", X"e5e", X"e61", X"e64", X"e67", X"e6a", X"e6e", +X"e71", X"e74", X"e77", X"e7a", X"e7d", X"e80", X"e83", X"e86", +X"e89", X"e8c", X"e8f", X"e93", X"e96", X"e99", X"e9c", X"e9f", +X"ea2", X"ea5", X"ea8", X"eab", X"eae", X"eb2", X"eb5", X"eb8", +X"ebb", X"ebe", X"ec1", X"ec4", X"ec7", X"eca", X"ecd", X"ed1", +X"ed4", X"ed7", X"eda", X"edd", X"ee0", X"ee3", X"ee6", X"ee9", +X"eed", X"ef0", X"ef3", X"ef6", X"ef9", X"efc", X"eff", X"f02", +X"f05", X"f09", X"f0c", X"f0f", X"f12", X"f15", X"f18", X"f1b", +X"f1e", X"f21", X"f25", X"f28", X"f2b", X"f2e", X"f31", X"f34", +X"f37", X"f3a", X"f3e", X"f41", X"f44", X"f47", X"f4a", X"f4d", +X"f50", X"f54", X"f57", X"f5a", X"f5d", X"f60", X"f63", X"f66", +X"f69", X"f6d", X"f70", X"f73", X"f76", X"f79", X"f7c", X"f7f", +X"f82", X"f86", X"f89", X"f8c", X"f8f", X"f92", X"f95", X"f98", +X"f9c", X"f9f", X"fa2", X"fa5", X"fa8", X"fab", X"fae", X"fb2", +X"fb5", X"fb8", X"fbb", X"fbe", X"fc1", X"fc4", X"fc7", X"fcb", +X"fce", X"fd1", X"fd4", X"fd7", X"fda", X"fdd", X"fe1", X"fe4", +X"fe7", X"fea", X"fed", X"ff0", X"ff3", X"ff7", X"ffa", X"ffd" +); + +constant COS_ROM : rom_type := + +( +X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", +X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7fe", +X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", +X"7fe", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", +X"7fd", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fb", +X"7fb", X"7fb", X"7fb", X"7fb", X"7fa", X"7fa", X"7fa", X"7fa", +X"7f9", X"7f9", X"7f9", X"7f9", X"7f8", X"7f8", X"7f8", X"7f8", +X"7f7", X"7f7", X"7f7", X"7f7", X"7f6", X"7f6", X"7f6", X"7f5", +X"7f5", X"7f5", X"7f5", X"7f4", X"7f4", X"7f4", X"7f3", X"7f3", +X"7f3", X"7f2", X"7f2", X"7f1", X"7f1", X"7f1", X"7f0", X"7f0", +X"7f0", X"7ef", X"7ef", X"7ee", X"7ee", X"7ee", X"7ed", X"7ed", +X"7ec", X"7ec", X"7ec", X"7eb", X"7eb", X"7ea", X"7ea", X"7e9", +X"7e9", X"7e8", X"7e8", X"7e7", X"7e7", X"7e6", X"7e6", X"7e6", +X"7e5", X"7e5", X"7e4", X"7e3", X"7e3", X"7e2", X"7e2", X"7e1", +X"7e1", X"7e0", X"7e0", X"7df", X"7df", X"7de", X"7de", X"7dd", +X"7dc", X"7dc", X"7db", X"7db", X"7da", X"7d9", X"7d9", X"7d8", +X"7d8", X"7d7", X"7d6", X"7d6", X"7d5", X"7d5", X"7d4", X"7d3", +X"7d3", X"7d2", X"7d1", X"7d1", X"7d0", X"7cf", X"7cf", X"7ce", +X"7cd", X"7cd", X"7cc", X"7cb", X"7ca", X"7ca", X"7c9", X"7c8", +X"7c8", X"7c7", X"7c6", X"7c5", X"7c5", X"7c4", X"7c3", X"7c2", +X"7c2", X"7c1", X"7c0", X"7bf", X"7bf", X"7be", X"7bd", X"7bc", +X"7bb", X"7bb", X"7ba", X"7b9", X"7b8", X"7b7", X"7b7", X"7b6", +X"7b5", X"7b4", X"7b3", X"7b2", X"7b1", X"7b1", X"7b0", X"7af", +X"7ae", X"7ad", X"7ac", X"7ab", X"7aa", X"7aa", X"7a9", X"7a8", +X"7a7", X"7a6", X"7a5", X"7a4", X"7a3", X"7a2", X"7a1", X"7a0", +X"79f", X"79e", X"79e", X"79d", X"79c", X"79b", X"79a", X"799", +X"798", X"797", X"796", X"795", X"794", X"793", X"792", X"791", +X"790", X"78f", X"78e", X"78d", X"78c", X"78a", X"789", X"788", +X"787", X"786", X"785", X"784", X"783", X"782", X"781", X"780", +X"77f", X"77e", X"77d", X"77b", X"77a", X"779", X"778", X"777", +X"776", X"775", X"774", X"772", X"771", X"770", X"76f", X"76e", +X"76d", X"76b", X"76a", X"769", X"768", X"767", X"766", X"764", +X"763", X"762", X"761", X"760", X"75e", X"75d", X"75c", X"75b", +X"759", X"758", X"757", X"756", X"754", X"753", X"752", X"751", +X"74f", X"74e", X"74d", X"74c", X"74a", X"749", X"748", X"746", +X"745", X"744", X"742", X"741", X"740", X"73e", X"73d", X"73c", +X"73a", X"739", X"738", X"736", X"735", X"734", X"732", X"731", +X"730", X"72e", X"72d", X"72b", X"72a", X"729", X"727", X"726", +X"724", X"723", X"722", X"720", X"71f", X"71d", X"71c", X"71a", +X"719", X"718", X"716", X"715", X"713", X"712", X"710", X"70f", +X"70d", X"70c", X"70a", X"709", X"707", X"706", X"704", X"703", +X"701", X"700", X"6fe", X"6fd", X"6fb", X"6fa", X"6f8", X"6f7", +X"6f5", X"6f4", X"6f2", X"6f0", X"6ef", X"6ed", X"6ec", X"6ea", +X"6e9", X"6e7", X"6e5", X"6e4", X"6e2", X"6e1", X"6df", X"6dd", +X"6dc", X"6da", X"6d9", X"6d7", X"6d5", X"6d4", X"6d2", X"6d0", +X"6cf", X"6cd", X"6cb", X"6ca", X"6c8", X"6c6", X"6c5", X"6c3", +X"6c1", X"6c0", X"6be", X"6bc", X"6bb", X"6b9", X"6b7", X"6b6", +X"6b4", X"6b2", X"6b0", X"6af", X"6ad", X"6ab", X"6a9", X"6a8", +X"6a6", X"6a4", X"6a3", X"6a1", X"69f", X"69d", X"69b", X"69a", +X"698", X"696", X"694", X"693", X"691", X"68f", X"68d", X"68b", +X"68a", X"688", X"686", X"684", X"682", X"681", X"67f", X"67d", +X"67b", X"679", X"677", X"675", X"674", X"672", X"670", X"66e", +X"66c", X"66a", X"668", X"667", X"665", X"663", X"661", X"65f", +X"65d", X"65b", X"659", X"657", X"655", X"654", X"652", X"650", +X"64e", X"64c", X"64a", X"648", X"646", X"644", X"642", X"640", +X"63e", X"63c", X"63a", X"638", X"636", X"634", X"632", X"630", +X"62e", X"62c", X"62a", X"628", X"626", X"624", X"622", X"620", +X"61e", X"61c", X"61a", X"618", X"616", X"614", X"612", X"610", +X"60e", X"60c", X"60a", X"608", X"606", X"604", X"602", X"600", +X"5fd", X"5fb", X"5f9", X"5f7", X"5f5", X"5f3", X"5f1", X"5ef", +X"5ed", X"5eb", X"5e9", X"5e6", X"5e4", X"5e2", X"5e0", X"5de", +X"5dc", X"5da", X"5d7", X"5d5", X"5d3", X"5d1", X"5cf", X"5cd", +X"5cb", X"5c8", X"5c6", X"5c4", X"5c2", X"5c0", X"5bd", X"5bb", +X"5b9", X"5b7", X"5b5", X"5b3", X"5b0", X"5ae", X"5ac", X"5aa", +X"5a7", X"5a5", X"5a3", X"5a1", X"59f", X"59c", X"59a", X"598", +X"596", X"593", X"591", X"58f", X"58d", X"58a", X"588", X"586", +X"583", X"581", X"57f", X"57d", X"57a", X"578", X"576", X"573", +X"571", X"56f", X"56d", X"56a", X"568", X"566", X"563", X"561", +X"55f", X"55c", X"55a", X"558", X"555", X"553", X"551", X"54e", +X"54c", X"54a", X"547", X"545", X"543", X"540", X"53e", X"53b", +X"539", X"537", X"534", X"532", X"530", X"52d", X"52b", X"528", +X"526", X"524", X"521", X"51f", X"51c", X"51a", X"517", X"515", +X"513", X"510", X"50e", X"50b", X"509", X"506", X"504", X"502", +X"4ff", X"4fd", X"4fa", X"4f8", X"4f5", X"4f3", X"4f0", X"4ee", +X"4eb", X"4e9", X"4e6", X"4e4", X"4e1", X"4df", X"4dc", X"4da", +X"4d7", X"4d5", X"4d2", X"4d0", X"4cd", X"4cb", X"4c8", X"4c6", +X"4c3", X"4c1", X"4be", X"4bc", X"4b9", X"4b7", X"4b4", X"4b2", +X"4af", X"4ad", X"4aa", X"4a7", X"4a5", X"4a2", X"4a0", X"49d", +X"49b", X"498", X"496", X"493", X"490", X"48e", X"48b", X"489", +X"486", X"483", X"481", X"47e", X"47c", X"479", X"476", X"474", +X"471", X"46f", X"46c", X"469", X"467", X"464", X"462", X"45f", +X"45c", X"45a", X"457", X"454", X"452", X"44f", X"44c", X"44a", +X"447", X"444", X"442", X"43f", X"43d", X"43a", X"437", X"435", +X"432", X"42f", X"42c", X"42a", X"427", X"424", X"422", X"41f", +X"41c", X"41a", X"417", X"414", X"412", X"40f", X"40c", X"409", +X"407", X"404", X"401", X"3ff", X"3fc", X"3f9", X"3f6", X"3f4", +X"3f1", X"3ee", X"3eb", X"3e9", X"3e6", X"3e3", X"3e1", X"3de", +X"3db", X"3d8", X"3d6", X"3d3", X"3d0", X"3cd", X"3ca", X"3c8", +X"3c5", X"3c2", X"3bf", X"3bd", X"3ba", X"3b7", X"3b4", X"3b2", +X"3af", X"3ac", X"3a9", X"3a6", X"3a4", X"3a1", X"39e", X"39b", +X"398", X"396", X"393", X"390", X"38d", X"38a", X"387", X"385", +X"382", X"37f", X"37c", X"379", X"377", X"374", X"371", X"36e", +X"36b", X"368", X"366", X"363", X"360", X"35d", X"35a", X"357", +X"354", X"352", X"34f", X"34c", X"349", X"346", X"343", X"340", +X"33e", X"33b", X"338", X"335", X"332", X"32f", X"32c", X"329", +X"327", X"324", X"321", X"31e", X"31b", X"318", X"315", X"312", +X"30f", X"30c", X"30a", X"307", X"304", X"301", X"2fe", X"2fb", +X"2f8", X"2f5", X"2f2", X"2ef", X"2ec", X"2e9", X"2e7", X"2e4", +X"2e1", X"2de", X"2db", X"2d8", X"2d5", X"2d2", X"2cf", X"2cc", +X"2c9", X"2c6", X"2c3", X"2c0", X"2bd", X"2ba", X"2b8", X"2b5", +X"2b2", X"2af", X"2ac", X"2a9", X"2a6", X"2a3", X"2a0", X"29d", +X"29a", X"297", X"294", X"291", X"28e", X"28b", X"288", X"285", +X"282", X"27f", X"27c", X"279", X"276", X"273", X"270", X"26d", +X"26a", X"267", X"264", X"261", X"25e", X"25b", X"258", X"255", +X"252", X"24f", X"24c", X"249", X"246", X"243", X"240", X"23d", +X"23a", X"237", X"234", X"231", X"22e", X"22b", X"228", X"225", +X"222", X"21f", X"21c", X"219", X"216", X"213", X"210", X"20d", +X"20a", X"207", X"204", X"201", X"1fe", X"1fb", X"1f7", X"1f4", +X"1f1", X"1ee", X"1eb", X"1e8", X"1e5", X"1e2", X"1df", X"1dc", +X"1d9", X"1d6", X"1d3", X"1d0", X"1cd", X"1ca", X"1c7", X"1c4", +X"1c1", X"1bd", X"1ba", X"1b7", X"1b4", X"1b1", X"1ae", X"1ab", +X"1a8", X"1a5", X"1a2", X"19f", X"19c", X"199", X"196", X"192", +X"18f", X"18c", X"189", X"186", X"183", X"180", X"17d", X"17a", +X"177", X"174", X"171", X"16d", X"16a", X"167", X"164", X"161", +X"15e", X"15b", X"158", X"155", X"152", X"14e", X"14b", X"148", +X"145", X"142", X"13f", X"13c", X"139", X"136", X"133", X"12f", +X"12c", X"129", X"126", X"123", X"120", X"11d", X"11a", X"117", +X"113", X"110", X"10d", X"10a", X"107", X"104", X"101", X"0fe", +X"0fb", X"0f7", X"0f4", X"0f1", X"0ee", X"0eb", X"0e8", X"0e5", +X"0e2", X"0df", X"0db", X"0d8", X"0d5", X"0d2", X"0cf", X"0cc", +X"0c9", X"0c6", X"0c2", X"0bf", X"0bc", X"0b9", X"0b6", X"0b3", +X"0b0", X"0ac", X"0a9", X"0a6", X"0a3", X"0a0", X"09d", X"09a", +X"097", X"093", X"090", X"08d", X"08a", X"087", X"084", X"081", +X"07e", X"07a", X"077", X"074", X"071", X"06e", X"06b", X"068", +X"064", X"061", X"05e", X"05b", X"058", X"055", X"052", X"04e", +X"04b", X"048", X"045", X"042", X"03f", X"03c", X"039", X"035", +X"032", X"02f", X"02c", X"029", X"026", X"023", X"01f", X"01c", +X"019", X"016", X"013", X"010", X"00d", X"009", X"006", X"003", +X"000", X"ffd", X"ffa", X"ff7", X"ff3", X"ff0", X"fed", X"fea", +X"fe7", X"fe4", X"fe1", X"fdd", X"fda", X"fd7", X"fd4", X"fd1", +X"fce", X"fcb", X"fc7", X"fc4", X"fc1", X"fbe", X"fbb", X"fb8", +X"fb5", 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X"78e", X"78f", +X"790", X"791", X"792", X"793", X"794", X"795", X"796", X"797", +X"798", X"799", X"79a", X"79b", X"79c", X"79d", X"79e", X"79e", +X"79f", X"7a0", X"7a1", X"7a2", X"7a3", X"7a4", X"7a5", X"7a6", +X"7a7", X"7a8", X"7a9", X"7aa", X"7aa", X"7ab", X"7ac", X"7ad", +X"7ae", X"7af", X"7b0", X"7b1", X"7b1", X"7b2", X"7b3", X"7b4", +X"7b5", X"7b6", X"7b7", X"7b7", X"7b8", X"7b9", X"7ba", X"7bb", +X"7bb", X"7bc", X"7bd", X"7be", X"7bf", X"7bf", X"7c0", X"7c1", +X"7c2", X"7c2", X"7c3", X"7c4", X"7c5", X"7c5", X"7c6", X"7c7", +X"7c8", X"7c8", X"7c9", X"7ca", X"7ca", X"7cb", X"7cc", X"7cd", +X"7cd", X"7ce", X"7cf", X"7cf", X"7d0", X"7d1", X"7d1", X"7d2", +X"7d3", X"7d3", X"7d4", X"7d5", X"7d5", X"7d6", X"7d6", X"7d7", +X"7d8", X"7d8", X"7d9", X"7d9", X"7da", X"7db", X"7db", X"7dc", +X"7dc", X"7dd", X"7de", X"7de", X"7df", X"7df", X"7e0", X"7e0", +X"7e1", X"7e1", X"7e2", X"7e2", X"7e3", X"7e3", X"7e4", X"7e5", +X"7e5", X"7e6", X"7e6", X"7e6", X"7e7", X"7e7", X"7e8", X"7e8", +X"7e9", X"7e9", X"7ea", X"7ea", X"7eb", X"7eb", X"7ec", X"7ec", +X"7ec", X"7ed", X"7ed", X"7ee", X"7ee", X"7ee", X"7ef", X"7ef", +X"7f0", X"7f0", X"7f0", X"7f1", X"7f1", X"7f1", X"7f2", X"7f2", +X"7f3", X"7f3", X"7f3", X"7f4", X"7f4", X"7f4", X"7f5", X"7f5", +X"7f5", X"7f5", X"7f6", X"7f6", X"7f6", X"7f7", X"7f7", X"7f7", +X"7f7", X"7f8", X"7f8", X"7f8", X"7f8", X"7f9", X"7f9", X"7f9", +X"7f9", X"7fa", X"7fa", X"7fa", X"7fa", X"7fb", X"7fb", X"7fb", +X"7fb", X"7fb", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", X"7fc", +X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", X"7fd", +X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", X"7fe", +X"7fe", X"7fe", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", +X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff", X"7ff" +); + + +begin + + +rom_select: process (clk) +begin + if clk'event and clk = '1' then + sin_out <= SIN_ROM(conv_integer(addr)) + 2048; + cos_out <= COS_ROM(conv_integer(addr)) + 2048; + end if; +end process rom_select; + + +end rtl; \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/spi_receiver.vhd b/libraries/Wishbone_Sump_LA/spi_receiver.vhd new file mode 100644 index 0000000..38a7246 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/spi_receiver.vhd @@ -0,0 +1,136 @@ +---------------------------------------------------------------------------------- +-- spi_receiver.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Receives commands from the SPI port. The first byte is the command +-- opcode, the following (optional) four byte are the command data. +-- Commands that do not have the highest bit in their opcode set are +-- considered short commands without data (1 byte long). All other commands are +-- long commands which are 5 bytes long. +-- +-- After a full command has been received the data it will be latched until the +-- next command is issued. A valid command can be detected by checking if the +-- execute output is set. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity spi_receiver is + port( + rx : in std_logic; + clock : in std_logic; + sclk : in std_logic; + cmd : out std_logic_vector (39 downto 0); + execute : out std_logic; + reset : in std_logic; + cs : in std_logic + ); +end spi_receiver; + +architecture behavioral of spi_receiver is + + type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA); + + signal state: states; + signal rx_buf : std_logic_vector(7 downto 0); + signal data_buf : std_logic_vector(31 downto 0); + signal bits : integer range 0 to 8; + signal bytes : integer range 0 to 4; + signal code : std_logic_vector (7 downto 0); + signal data : std_logic_vector (31 downto 0); + signal exec : std_logic := '0'; + signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0); + +begin + + cmd <= data & code; + + process(clock) + begin + if rising_edge(clock) then + + execute <= exec; + rsync_sclk <= rsync_sclk(0) & sclk; + rsync_cs <= rsync_cs(0) & cs; + + case state is + when IDLE => + -- cs falling edge starts rx + if rsync_cs = "10" then + state <= READ_OPCODE; + end if; + rx_buf <= (others => '0'); + data_buf <= (others => '0'); + bits <= 0; + bytes <= 0; + exec <= '0'; + when READ_OPCODE => + -- read bit at sclk rising edge + if reset = '1' then + state <= IDLE; + elsif rsync_sclk = "01" then + rx_buf <= rx_buf(6 downto 0) & rx; + bits <= bits + 1; + elsif bits = 8 then + -- if hi bit is set then wait for cmd data + if rx_buf(7) = '1' then + state <= WAIT_CS; + else + state <= IDLE; + exec <= '1'; + end if; + code <= rx_buf; + end if; + when WAIT_CS => + -- wait for cs falling edge before reading next data + if reset = '1' then + state <= IDLE; + elsif rsync_cs = "10" then + state <= READ_DATA; + bytes <= bytes + 1; + elsif bytes = 4 then + state <= IDLE; + data <= data_buf; + exec <= '1'; + end if; + rx_buf <= (others => '0'); + bits <= 0; + when READ_DATA => + -- read bit at sclk rising edge + if reset = '1' then + state <= IDLE; + elsif rsync_sclk = "01" then + rx_buf <= rx_buf(6 downto 0) & rx; + bits <= bits + 1; + elsif bits = 8 then + state <= WAIT_CS; + data_buf <= rx_buf & data_buf(31 downto 8); + end if; + end case; + end if; + end process; + +end behavioral; \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/spi_slave.vhd b/libraries/Wishbone_Sump_LA/spi_slave.vhd new file mode 100644 index 0000000..ee83b21 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/spi_slave.vhd @@ -0,0 +1,108 @@ +---------------------------------------------------------------------------------- +-- spi_slave.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- spi_slave +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity spi_slave is + port( + clock : in std_logic; + data : in std_logic_vector(31 downto 0); + send : in std_logic; + mosi : in std_logic; + sclk : in std_logic; + cs : in std_logic; + miso : out std_logic; + cmd : out std_logic_vector(39 downto 0); + execute : out std_logic; + busy : out std_logic; + dataReady : out std_logic; + reset : in std_logic; + tx_bytes : in integer range 0 to 4 + ); +end spi_slave; + +architecture behavioral of spi_slave is + + component spi_receiver + port( + rx : in std_logic; + clock : in std_logic; + sclk : in std_logic; + cmd : out std_logic_vector(39 downto 0); + execute : out std_logic; + reset : in std_logic; + cs : in std_logic + ); + end component; + + component spi_transmitter + port( + data : in std_logic_vector(31 downto 0); + tx_bytes : in integer range 0 to 4; + send : in std_logic; + clock : in std_logic; + sclk : in std_logic; + tx : out std_logic; + cs : in std_logic; + busy : out std_logic; + reset : in std_logic; + dataReady : out std_logic + ); + end component; + +begin + + Inst_spi_receiver: spi_receiver + port map( + rx => mosi, + clock => clock, + sclk => sclk, + cmd => cmd, + execute => execute, + reset => reset, + cs => cs + ); + + Inst_spi_transmitter: spi_transmitter + port map( + data => data, + tx_bytes => tx_bytes, + send => send, + clock => clock, + sclk => sclk, + tx => miso, + cs => cs, + busy => busy, + reset => reset, + dataReady => dataReady + ); + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/spi_transmitter.vhd b/libraries/Wishbone_Sump_LA/spi_transmitter.vhd new file mode 100644 index 0000000..85a6242 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/spi_transmitter.vhd @@ -0,0 +1,141 @@ +---------------------------------------------------------------------------------- +-- spi_transmitter.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Takes 32bit (one sample) and sends it out on the SPI port. +-- End of transmission is signalled by taking back the busy flag. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity spi_transmitter is + port( + data : in std_logic_vector (31 downto 0); + tx_bytes : in integer range 0 to 4; + send : in std_logic; + clock : in std_logic; + sclk : in std_logic; + tx : out std_logic := '0'; + cs : in std_logic; + busy: out std_logic := '0'; + reset : in std_logic; + dataReady : out std_logic := '0' + ); +end spi_transmitter; + +architecture behavioral of spi_transmitter is + + type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI); + + signal tx_buf : std_logic_vector (39 downto 0) := (others => '0'); + signal bits : integer range 0 to 7; + signal bytes, end_byte : integer range 0 to 4; + signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0'); + signal state: states; + signal send_i: std_logic := '1'; + signal timeout : std_logic_vector(31 downto 0) := (others => '0'); + +begin + + process(clock) + begin + if rising_edge(clock) then + + rsync_sclk <= rsync_sclk(0) & sclk; + rsync_cs <= rsync_cs(0) & cs; + + case state is + when IDLE => + if send = '1' then + state <= START; + busy <= '1'; + dataReady <= '1'; + end if; + tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8) + & data(23 downto 16) & data(31 downto 24); + end_byte <= tx_bytes; + bytes <= 0; + bits <= 0; + when START => + -- tx starts at cs falling edge + --if rsync_cs = "10" then +-- timeout <= timeout +1; +-- if timeout = x"ffffffffff" then +-- timeout <= (others => '0'); +-- state <= WAIT_CS_HI; +-- elsif rsync_cs = "10" or cs = '0' then + if reset = '1' then + state <= IDLE; + elsif rsync_cs = "10" or cs = '0' then + state <= WAIT_CS_LO; + tx <= tx_buf(39); +-- timeout <= (others => '0'); + end if; + when WAIT_CS_LO => + -- wait for cs before sending the next byte + if cs = '0' and rsync_sclk = "01" then + state <= SEND_BITS; + tx_buf <= tx_buf(38 downto 0) & '0'; + bytes <= bytes + 1; + elsif bytes = end_byte+1 then + state <= WAIT_CS_HI; + dataReady <= '0'; + end if; + tx <= tx_buf(39); + when SEND_BITS => + -- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns. +-- timeout <= timeout +1; +-- if timeout = x"0b" then +-- timeout <= (others => '0'); +-- state <= START; +-- bits <= 0; +-- bytes <= bytes - 1; +-- -- transfer bits at rising edge of sclk +-- elsif rsync_sclk = "01" then + if reset = '1' then + state <= IDLE; + elsif rsync_sclk = "01" then + tx_buf <= tx_buf(38 downto 0) & '0'; + bits <= bits + 1; +-- timeout <= (others => '0'); + elsif bits = 7 then + state <= WAIT_CS_LO; + bits <= 0; +-- timeout <= (others => '0'); + end if; + tx <= tx_buf(39); + when WAIT_CS_HI => + -- tx stops until cs rising edge +-- if rsync_cs = "01" or cs = '0' then + state <= IDLE; + busy <= '0'; +-- end if; + end case; + + end if; + end process; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/sram_bram.vhd b/libraries/Wishbone_Sump_LA/sram_bram.vhd new file mode 100644 index 0000000..811077f --- /dev/null +++ b/libraries/Wishbone_Sump_LA/sram_bram.vhd @@ -0,0 +1,113 @@ +---------------------------------------------------------------------------------- +-- sram_bram.vhd +-- +-- Copyright (C) 2007 Jonas Diemer +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Simple BlockRAM interface. +-- +-- This module should be used instead of sram.vhd if no external SRAM is present. +-- Instead, it will use internal BlockRAM (16 Blocks). +-- +-- Modified to use BRAM4k32bit to fit on Butterfly Platform +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity sram_bram is + generic ( + brams: integer := 12 + ); + port( + clock : in std_logic; + output : out std_logic_vector(35 downto 0); + la_input : in std_logic_vector(35 downto 0); + read : in std_logic; + write : in std_logic + ); +end sram_bram; + +architecture behavioral of sram_bram is + + component Mem_Gen_36bit -- SampleRAM + generic ( + brams: integer := 12 + ); + port ( + clk: IN std_logic; + we: IN std_logic; + addr: IN std_logic_VECTOR(13 downto 0); + din: IN std_logic_VECTOR(35 downto 0); + dout: OUT std_logic_VECTOR(35 downto 0) + ); + end component; + + signal addra : std_logic_vector (13 downto 0) := (others => '0'); + signal writeSignal : std_logic; + signal bramIn, bramOut : std_logic_vector (35 downto 0); + +begin + + -- assign signals + output <= bramOut; + + -- memory io interface state controller + bramIn <= la_input; + + writeSignal <= write; + + -- memory address controller + process(clock) + begin + if rising_edge(clock) then + if write = '1' then + if addra >= (brams*512) - 1 then + addra <= (others => '0'); + else + addra <= addra + 1; + end if; + elsif read = '1' then + if addra = "0" then + addra <= std_logic_vector(to_unsigned((brams*512) - 1, addra'length)); + else + addra <= addra - 1; + end if; + end if; + end if; + end process; + + Inst_SampleRAM : Mem_Gen_36bit + generic map ( + brams => brams + ) + port map ( + clk => clock, + we => writeSignal, + addr => addra, + din => bramIn, + dout => bramOut + ); + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/sump_wishbone.vhd b/libraries/Wishbone_Sump_LA/sump_wishbone.vhd new file mode 100644 index 0000000..66dbbee --- /dev/null +++ b/libraries/Wishbone_Sump_LA/sump_wishbone.vhd @@ -0,0 +1,347 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library DesignLab; +use DesignLab.all; + +library work; +use work.all; + +entity sump_wishbone is + port ( + clk: in std_logic; + rst: in std_logic; + -- Main wishbone signals + wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) + wb_adr_i: in std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) + wb_we_i: in std_logic; -- Wishbone write enable signal + wb_cyc_i: in std_logic; -- Wishbone cycle signal + wb_stb_i: in std_logic; -- Wishbone strobe signal + + wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) + wb_ack_o: out std_logic; -- Wishbone acknowledge out signal + + + + -- Signals to/from core + --clock: in std_logic; + reset: in std_logic; + write: in std_logic; + memoryOut: in std_logic_vector(31 downto 0); + run: in std_logic; + armed: in std_logic_vector(3 downto 0); + send: in std_logic; + cmd: out std_logic_vector(39 downto 0); + execute: out std_logic; + -- DMA + mi_wb_dat_i: in std_logic_vector(31 downto 0); + mi_wb_dat_o: out std_logic_vector(31 downto 0); + mi_wb_adr_o: out std_logic_vector(27 downto 0); + mi_wb_sel_o: out std_logic_vector(3 downto 0); + mi_wb_cti_o: out std_logic_vector(2 downto 0); + mi_wb_we_o: out std_logic; + mi_wb_cyc_o: out std_logic; + mi_wb_stb_o: out std_logic; + mi_wb_ack_i: in std_logic; + mi_wb_stall_i: in std_logic + + ); +end entity sump_wishbone; + +architecture behave of sump_wishbone is + + + signal fifo_read : std_logic := '0'; + signal sob,eob,wnext,rnext: std_logic; + signal fifo_almost_full, fifo_empty: std_logic; + type fillstate_t is ( IDLE, FILL ); + type oregs_type is record + state: fillstate_t; + sob: std_logic; + flush: std_logic; + sent: std_logic; + filled: std_logic; + addr: unsigned(27 downto 0); -- Current address + taddr: unsigned(27 downto 0); -- Triggered address + eaddr: unsigned(27 downto 0); -- End address + tset: std_logic; + end record; + signal oregs: oregs_type; + signal abort: std_logic := '0'; + signal fifo_data: std_logic_vector(32 downto 0); + + type rregs_type is record + ack: std_logic; + triggered: std_logic; + enabled: std_logic; + dat_o: std_logic_vector(31 downto 0); + baddr: unsigned(27 downto 0); -- Base address + asize: unsigned(27 downto 0); -- Address size + end record; + signal rregs: rregs_type; + + signal memidle: std_logic; + signal breq: std_logic; + signal write_int: std_logic; + signal fifo_write_data: std_logic_vector(32 downto 0); +begin + + mi_wb_sel_o <= "1111"; + write_int <= write and rregs.enabled; + + fifo_write_data <= rregs.triggered & memoryOut(31 downto 0); + + fifo_inst: entity async_fifo + generic map ( + address_bits => 10, + data_bits => 33, + threshold => 900 + ) + port map ( + clk_r => clk, + clk_w => clk, + arst => reset, + wr => write_int, + rd => fifo_read, + write => fifo_write_data, + read => fifo_data, + almost_full => fifo_almost_full, + empty => fifo_empty + ); + + inst_burstctrl: entity wb_burstctrl + generic map ( + WIDTH_BITS => 16 + ) + port map ( + clk => clk, + rst => rst, + sob => sob, + + rnext => rnext, + wnext => wnext, + + stb => mi_wb_stb_o, + cyc => mi_wb_cyc_o, + cti => mi_wb_cti_o, + stall => mi_wb_stall_i, + ack => mi_wb_ack_i, + + req => breq, + eob => eob + ); + + mi_wb_adr_o <= std_logic_vector(oregs.addr); + mi_wb_dat_o <= fifo_data(31 downto 0); + mi_wb_we_o <= '1'; + + sob <= oregs.sob; + + memidle<='1' when oregs.state=IDLE else '0'; + + -- Outputter + process(clk,oregs, fifo_empty, send, abort, wnext, eob, rregs, fifo_almost_full) + variable w: oregs_type; + variable addrinc: unsigned(27 downto 0); + begin + w:=oregs; + + addrinc := oregs.addr + 4; + + case oregs.state is + when IDLE => + w.sob:='0'; + if send='1' then + w.flush := '1'; + w.sent := '1'; + end if; + + if fifo_almost_full='1' or oregs.flush='1' then + fifo_read <= not fifo_empty; + w.state := FILL; + w.sob :='1'; + else + fifo_read <= '0'; + end if; + + when FILL => + if fifo_empty='1' then + fifo_read<='0'; + else + fifo_read <= wnext; + end if; + if wnext='1' then + if (addrinc > rregs.asize) then + w.addr := rregs.baddr; -- Wrap + else + w.addr := addrinc; + end if; + end if; + + w.sob := '0'; + + if send='1' then + w.flush := '1'; + w.sent := '1'; + end if; + + if abort='1' then -- + end if; + + if eob='1' then + if oregs.flush='0' then + w.state := IDLE; + w.filled:='1'; + else + -- Need to flush + fifo_read <= not fifo_empty; + + if fifo_empty='1' then + w.state := IDLE; + w.filled:='1'; + else + w.sob :='1'; + end if; + + w.flush := not fifo_empty; + + end if; + end if; + + when others => + end case; + + if oregs.sent='1' and oregs.filled='1' then + w.eaddr := oregs.addr; + end if; + + if wnext='1' and fifo_data(32)='1' then + if oregs.tset='0' then + w.taddr := oregs.addr; + end if; + w.tset := '1'; + end if; + + if reset='1' then + w.addr := rregs.baddr; + w.tset:='0'; + w.sent:='0'; + w.filled:='0'; + end if; + + if rst='1' then + w.state := IDLE; + w.sob :='0'; + w.flush :='0'; + end if; + + if rising_edge(clk) then + oregs<=w; + end if; + end process; + + + -- Register access + + --cmd <= wb_dat_i & wb_adr_i(9 downto 2); + -- Reverse the byte order of the data portion of cmd + --cmd <= wb_dat_i(0) & wb_dat_i(1) & wb_dat_i(2) & wb_dat_i(3) & wb_dat_i(4) & wb_dat_i(5) & wb_dat_i(6) & wb_dat_i(7) & wb_dat_i(8) & wb_dat_i(9) & wb_dat_i(10) & wb_dat_i(11) & wb_dat_i(12) & wb_dat_i(13) & wb_dat_i(14) & wb_dat_i(15) & wb_dat_i(16) & wb_dat_i(17) & wb_dat_i(18) & wb_dat_i(19) & wb_dat_i(20) & wb_dat_i(21) & wb_dat_i(22) & wb_dat_i(23) & wb_dat_i(24) & wb_dat_i(25) & wb_dat_i(26) & wb_dat_i(27) & wb_dat_i(28) & wb_dat_i(29) & wb_dat_i(30) & wb_dat_i(31) & wb_adr_i(9 downto 2); + cmd <= wb_dat_i(7) & wb_dat_i(6) & wb_dat_i(5) & wb_dat_i(4) & wb_dat_i(3) & wb_dat_i(2) & wb_dat_i(1) & wb_dat_i(0) & wb_dat_i(15) & wb_dat_i(14) & wb_dat_i(13) & wb_dat_i(12) & wb_dat_i(11) & wb_dat_i(10) & wb_dat_i(9) & wb_dat_i(8) & wb_dat_i(23) & wb_dat_i(22) & wb_dat_i(21) & wb_dat_i(20) & wb_dat_i(19) & wb_dat_i(18) & wb_dat_i(17) & wb_dat_i(16) & wb_dat_i(31) & wb_dat_i(30) & wb_dat_i(29) & wb_dat_i(28) & wb_dat_i(27) & wb_dat_i(26) & wb_dat_i(25) & wb_dat_i(24) & wb_adr_i(9 downto 2); + wb_dat_o <= rregs.dat_o; + + process(clk,rst,reset,wb_dat_i, wb_adr_i, wb_we_i, wb_cyc_i, wb_stb_i, rregs, wb_dat_i, run, + memidle, armed,fifo_empty, fifo_almost_full,send,oregs.flush,abort,breq,write,write_int + ) + variable w: rregs_type; + begin + w:=rregs; + w.ack:='0'; + execute<='0'; + if run='1' then + w.triggered := '1'; + end if; + + if wb_cyc_i='1' and wb_stb_i='1' and rregs.ack='0' then + if wb_we_i='1' then + -- Writes + if wb_adr_i(10)='0' then + -- Direct SUMP writes + execute<='1'; + else + case wb_adr_i(3 downto 2) is + when "00" => + w.baddr := unsigned( wb_dat_i(w.baddr'RANGE)); + when "01" => + w.asize := unsigned( wb_dat_i(w.asize'RANGE)); + when "10" => + if wb_dat_i(0)='1' then + w.triggered:='0'; + end if; + w.enabled := wb_dat_i(1); + when others => + end case; + + end if; + end if; + case wb_adr_i(2) is + when '0' => + w.dat_o := (others => '0'); + w.dat_o(0) := memidle; + w.dat_o(1) := rregs.triggered; + w.dat_o(2) := fifo_empty; + w.dat_o(3) := oregs.sent; + w.dat_o(4) := oregs.filled; + w.dat_o(5) := oregs.flush; +-- w.dat_o(6) := armed(0); +-- w.dat_o(7) := armed(1); +-- w.dat_o(8) := armed(2); +-- w.dat_o(9) := armed(3); + +-- w.dat_o(7) := fifo_almost_full; +-- w.dat_o(8) := send; +-- w.dat_o(10) := abort; +-- w.dat_o(11) := breq; +-- w.dat_o(12) := write; +-- w.dat_o(13) := write_int; + + +-- w.dat_o(0) := memidle; +-- w.dat_o(1) := rregs.triggered; +-- w.dat_o(2) := armed(0); +-- w.dat_o(3) := armed(1); +-- w.dat_o(4) := armed(2); +-- w.dat_o(5) := armed(3); +-- w.dat_o(6) := fifo_empty; +-- w.dat_o(7) := fifo_almost_full; +-- w.dat_o(8) := send; +-- w.dat_o(9) := oregs.flush; +-- w.dat_o(10) := abort; +-- w.dat_o(11) := breq; +-- w.dat_o(12) := write; +-- w.dat_o(13) := write_int; + when '1' => + w.dat_o := (others => '0'); + --w.dat_o(oregs.taddr'range) := std_logic_vector(oregs.taddr); + w.dat_o(oregs.eaddr'range) := std_logic_vector(oregs.eaddr); + when others => + end case; + + w.ack:='1'; + end if; + + if rst='1' or reset='1' then + w.ack:='0'; + w.triggered:='0'; + w.enabled := '1'; + end if; + + if rising_edge(clk) then + rregs<=w; + end if; + end process; + + wb_ack_o <= rregs.ack; + +end behave; diff --git a/libraries/Wishbone_Sump_LA/sync.vhd b/libraries/Wishbone_Sump_LA/sync.vhd new file mode 100644 index 0000000..70896aa --- /dev/null +++ b/libraries/Wishbone_Sump_LA/sync.vhd @@ -0,0 +1,118 @@ +---------------------------------------------------------------------------------- +-- sync.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Synchronizes la_input with clock on rising or falling edge and does some +-- optional preprocessing. (Noise filter and demux.) +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity sync is + port( + la_input : in std_logic_vector (31 downto 0); + clock : in std_logic; + enableFilter : in std_logic; + enableDemux : in std_logic; + falling : in std_logic; + output : out std_logic_vector (31 downto 0) + ); +end sync; + +architecture behavioral of sync is + + component demux + port( + la_input : in std_logic_vector(15 downto 0); + la_input180 : in std_logic_vector(15 downto 0); + clock : in std_logic; + output : out std_logic_vector(31 downto 0) + ); + end component; + + component filter + port( + la_input : in std_logic_vector(31 downto 0); + la_input180 : in std_logic_vector(31 downto 0); + clock : in std_logic; + output : out std_logic_vector(31 downto 0) + ); + end component; + + attribute equivalent_register_removal : string; + signal filteredla_input, demuxedla_input, synchronizedla_input, synchronizedla_input180: std_logic_vector (31 downto 0); + attribute equivalent_register_removal of demuxedla_input : signal is "no"; + +begin + Inst_demux: demux + port map( + la_input => synchronizedla_input(15 downto 0), + la_input180 => synchronizedla_input180(15 downto 0), + clock => clock, + output => demuxedla_input + ); + + Inst_filter: filter + port map( + la_input => synchronizedla_input, + la_input180 => synchronizedla_input180, + clock => clock, + output => filteredla_input + ); + + -- synch la_input guarantees use of iob ff on spartan 3 (as filter and demux do) + process (clock) + begin + if rising_edge(clock) then + synchronizedla_input <= la_input; + end if; + if falling_edge(clock) then + synchronizedla_input180 <= la_input; + end if; + end process; + + -- add another pipeline step for la_input selector to not decrease maximum clock rate + process (clock) + begin + if rising_edge(clock) then + if enableDemux = '1' then + output <= demuxedla_input; + else + if enableFilter = '1' then + output <= filteredla_input; + else + if falling = '1' then + output <= synchronizedla_input180; + else + output <= synchronizedla_input; + end if; + end if; + end if; + end if; + end process; + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/tb.vhd b/libraries/Wishbone_Sump_LA/tb.vhd new file mode 100644 index 0000000..c010236 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/tb.vhd @@ -0,0 +1,190 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity la_tb is +end entity; + +architecture sim of la_tb is + + signal cmd : std_logic_vector (39 downto 0) := (others => '0'); + signal memoryIn, memoryOut : std_logic_vector (35 downto 0); + signal output : std_logic_vector (31 downto 0); + signal la_input : std_logic_vector (31 downto 0) := x"00000001"; + + signal clock : std_logic := '0'; + signal read, write, execute, send, busy, reset, run : std_logic; + signal tx_bytes : integer range 0 to 4; + signal extClockIn, extTriggerIn : std_logic; + signal sysrst : std_logic; + + signal stb, cyc, stall, ack: std_logic; + signal cti: std_logic_vector(2 downto 0); + +begin + + clock <= not clock after 5 ns; + sysrst <= '0', '1' after 10 ns, '0' after 30 ns; + + + Inst_core: entity work.core + port map( + clock => clock, + reset => reset, + cmd => cmd, + run => run, + execute => execute, + la_input => la_input, + la_inputClock => extClockIn, + output => output, + outputSend => send, + outputBusy => busy, + memoryIn => memoryIn, + memoryOut => memoryOut, + memoryRead => read, + memoryWrite => write, + extTriggerIn => extTriggerIn, + extTriggerOut => open, + extClockOut => open, + armLED => open, + triggerLED => open, + tx_bytes => tx_bytes + ); + + -- Waveform + process + begin + wait until rising_edge(clock); + la_input <= la_input(30 downto 0) & la_input(31); + wait until rising_edge(clock); + end process; + + stim: process + + procedure command(cmdin: in std_logic_vector(7 downto 0); data: std_logic_vector(31 downto 0) ) is + begin + wait until rising_edge(clock); + cmd <= data & cmdin; + execute<='1'; + wait until rising_edge(clock); + execute<='0'; + end procedure; + + begin + execute<='0'; + wait for 1 us; + command(x"00",x"00000000"); -- Reset + command(x"C0",x"FFFFFFFE"); -- Mask + command(x"C1",x"00000001"); -- Value + command(x"C2",x"08000000"); -- Conf + command(x"80",x"00000001"); -- Speed + command(x"81",x"01000010"); -- Size + command(x"82",x"00000000"); -- Flags + wait until rising_edge(clock); + wait until rising_edge(clock); + wait until rising_edge(clock); + wait until rising_edge(clock); + wait until rising_edge(clock); + wait until rising_edge(clock); + command(x"01",x"00000000"); -- Arm + wait for 60 us; + end process; + + + sumpwb_inst: entity work.sump_wishbone + port map ( + clk => clock, + rst => sysrst, + + clock => clock, + reset => reset, + write => write, + memoryout => memoryout(31 downto 0), + run => run, + send => send, + -- DMA + mi_wb_dat_i => x"00000000", + mi_wb_dat_o => open, + mi_wb_adr_o => open, + mi_wb_sel_o => open, + mi_wb_cti_o => open, + mi_wb_we_o => open, + mi_wb_cyc_o => cyc, + mi_wb_stb_o => stb, + mi_wb_ack_i => ack, + mi_wb_stall_i => stall + + ); + + -- Memorysim - write only + memsim: block + type memstate_t is (IDLE, ACC, BURST); + + type memregs_t is record + state: memstate_t; + oddeven: std_logic; + cnt: integer; + ack: std_logic; + queued: std_logic; + end record; + + signal mr: memregs_t; + + begin + process(clock, mr, cyc, stb) + variable w: memregs_t; + begin + w := mr; + + case mr.state is + when IDLE => + stall <= '0'; + ack <= '0'; + if cyc='1' and stb='1' then + w.state := ACC; + w.queued:='1'; + w.cnt := 6; + end if; + when ACC => + stall <= '1'; + if mr.cnt=0 then + w.state := BURST; + w.oddeven := '0'; + else + w.cnt := mr.cnt - 1; + end if; + when BURST => + stall <= mr.oddeven; + if mr.oddeven='0' and cyc='1' then + w.oddeven := not mr.oddeven; + w.queued:='1'; + else + w.oddeven:= not cyc; + end if; + + if mr.queued='1' then + w.queued:= '0'; + end if; + w.ack := w.queued; + if cyc='0' then + w.state := IDLE; + end if; + when others => + end case; + ack <= mr.ack; + + if sysrst='1' then + w.state := IDLE; + w.ack := '0'; + end if; + + if rising_edge(clock) then + mr <= w; + end if; + end process; + end block; + + + +end sim; diff --git a/libraries/Wishbone_Sump_LA/tb_top.vhd b/libraries/Wishbone_Sump_LA/tb_top.vhd new file mode 100644 index 0000000..caae88e --- /dev/null +++ b/libraries/Wishbone_Sump_LA/tb_top.vhd @@ -0,0 +1,242 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity tb_top is +end entity; + +architecture sim of tb_top is + + + signal wishbone_in: std_logic_vector(100 downto 0); + signal wishbone_out: std_logic_vector(100 downto 0); + signal wishbone_slot_video_in : std_logic_vector(100 downto 0); + signal wishbone_slot_video_out : std_logic_vector(100 downto 0); + signal la :std_logic_vector(31 downto 0) := x"00000001"; + + -- Aliasing + alias wb_clk_i: std_logic is wishbone_in(61); + alias wb_rst_i: std_logic is wishbone_in(60); + alias wb_dat_i: std_logic_vector(31 downto 0) is wishbone_in(59 downto 28); + alias wb_adr_i: std_logic_vector(26 downto 2) is wishbone_in(27 downto 3); + alias wb_we_i: std_logic is wishbone_in(2); + alias wb_cyc_i: std_logic is wishbone_in(1); + alias wb_stb_i: std_logic is wishbone_in(0); + + alias id: std_logic_vector(15 downto 0) is wishbone_out(49 downto 34); + alias wb_dat_o: std_logic_vector(31 downto 0) is wishbone_out(33 downto 2); + alias wb_ack_o: std_logic is wishbone_out(1); + alias wb_inta_o: std_logic is wishbone_out(0); +-- End unpacking Wishbone array + +--Unpack DMA array + alias mi_wb_dat_o: std_logic_vector(31 downto 0) is wishbone_slot_video_in(31 downto 0); + alias mi_wb_adr_o: std_logic_vector(27 downto 0) is wishbone_slot_video_in(77 downto 50); + alias mi_wb_we_o: std_logic is wishbone_slot_video_in(100); + alias mi_wb_cyc_o: std_logic is wishbone_slot_video_in(99); + alias mi_wb_stb_o: std_logic is wishbone_slot_video_in(98); + + alias mi_wb_dat_i: std_logic_vector(31 downto 0) is wishbone_slot_video_out(31 downto 0); + alias mi_wb_ack_i: std_logic is wishbone_slot_video_out(100); + alias mi_wb_stall_i:std_logic is wishbone_slot_video_out(99); + + -- SDRAM signals + signal DRAM_ADDR : STD_LOGIC_VECTOR (12 downto 0); + signal DRAM_BA : STD_LOGIC_VECTOR (1 downto 0); + signal DRAM_CAS_N : STD_LOGIC; + signal DRAM_CKE : STD_LOGIC; + signal DRAM_CLK : STD_LOGIC; + signal DRAM_CS_N : STD_LOGIC; + signal DRAM_DQ : STD_LOGIC_VECTOR(15 downto 0); + signal DRAM_DQM : STD_LOGIC_VECTOR(1 downto 0); + signal DRAM_RAS_N : STD_LOGIC; + signal DRAM_WE_N : STD_LOGIC; + signal sram_addr: std_logic_vector(18 downto 0); + signal sram_data: std_logic_vector(15 downto 0); + signal sram_ce: std_logic; + signal sram_we: std_logic; + signal sram_oe: std_logic; + signal sram_be: std_logic; + signal sram_addr_i: std_logic_vector(18 downto 0); + signal sram_ce_i: std_logic; + signal sram_we_i: std_logic; + signal sram_oe_i: std_logic; + signal sram_be_i: std_logic; + + + signal clk: std_logic := '0'; + constant PERIOD: time := 31.25 ns; + + signal rb: std_logic_vector(31 downto 0); + +begin + + clk <= not clk after 10.416667 ns; + wb_clk_i<=clk; + + uut: entity work.BENCHY_wb_SumpBlaze_LogicAnalyzer32 + port map ( + wishbone_in => wishbone_in, + wishbone_out => wishbone_out, + wishbone_slot_video_in => wishbone_slot_video_in, + wishbone_slot_video_out => wishbone_slot_video_out, + la => la + ); + + wb_rst_i<='0', '1' after 20 ns, '0' after 80 ns; + + + -- Waveform + process + begin + wait until rising_edge(clk); + la <= la(30 downto 0) & la(31); + wait until rising_edge(clk); + end process; + + + stim: process + + procedure wbwrite(addr: in std_logic_vector(31 downto 0); data: std_logic_vector(31 downto 0) ) is + begin + wait until rising_edge(clk); + wait for 5 ns; + wb_adr_i <= addr(26 downto 2); + wb_dat_i <= data; + wb_cyc_i<='1'; + wb_stb_i<='1'; + wb_we_i<='1'; + + dly: loop + wait until rising_edge(clk); + if wb_ack_o='1' then + + wb_cyc_i<='0'; + wb_stb_i<='0'; + wb_we_i<='0'; + exit dly; + end if; + end loop; + end procedure; + + procedure wbread(addr: in std_logic_vector(31 downto 0); signal data: out std_logic_vector(31 downto 0) ) is + begin + wait until rising_edge(clk); + wait for 5 ns; + wb_adr_i <= addr(26 downto 2); + wb_dat_i <= (others =>'X'); + wb_cyc_i<='1'; + wb_stb_i<='1'; + wb_we_i<='0'; + + dly: loop + wait until rising_edge(clk); + if wb_ack_o='1' then + data <= wb_dat_o; + wb_cyc_i<='0'; + wb_stb_i<='0'; + wb_we_i<='0'; + exit dly; + end if; + end loop; + end procedure; + + procedure command(cmdin: in std_logic_vector(7 downto 0); data: std_logic_vector(31 downto 0) ) is + begin + wbwrite( x"0000" & "000000" & cmdin & "00", data ); + end procedure; + begin + wb_cyc_i<='0'; + wait for 1 us; + wbwrite(x"00000400", x"00100000"); -- Base Address + wbwrite(x"00000404", x"00200000"); -- End of memory + + command(x"00",x"00000000"); -- Reset + command(x"C0",x"FFFFFFFE"); -- Mask + command(x"C1",x"00000001"); -- Value + command(x"C2",x"08000000"); -- Conf + command(x"80",x"00000001"); -- Speed + command(x"81",x"01000010"); -- Size + command(x"82",x"00000000"); -- Flags + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + command(x"01",x"00000000"); -- Arm + --wait for 200 us; + --wbwrite(x"00000408", x"00000001"); -- Clear trigger indicator + rbl: loop + wbread(x"00000408", rb); + end loop; + end process; + + + memorystuff: block + signal sysclk_sram_we: std_logic; + begin + + sdram: entity work.mt48lc16m16a2 + GENERIC MAP ( + addr_bits => 12, + data_bits => 16, + col_bits => 8, + index => 0, + fname => "sdram.srec" + ) + PORT MAP ( + Dq => DRAM_DQ, + Addr => DRAM_ADDR(11 downto 0), + Ba => DRAM_BA, + Clk => DRAM_CLK, + Cke => DRAM_CKE, + Cs_n => DRAM_CS_N, + Ras_n => DRAM_RAS_N, + Cas_n => DRAM_CAS_N, + We_n => DRAM_WE_N, + Dqm => DRAM_DQM + ); + + + + sram_addr <= transport sram_addr_i after 1.7 ns; + sram_we <= transport sram_we_i after 1.9 ns; + sram_oe <= transport sram_oe_i after 1.7 ns; + sram_ce <= transport sram_ce_i after 1.7 ns; + + sysclk_sram_we <= transport wb_clk_i after 3 ns; + + sram_inst: entity work.sdram_ctrl + port map ( + wb_clk_i => wb_clk_i, + wb_rst_i => wb_rst_i, + wb_dat_o => mi_wb_dat_i, + wb_dat_i => mi_wb_dat_o, + wb_adr_i => mi_wb_adr_o(26 downto 2), + wb_we_i => mi_wb_we_o, + wb_cyc_i => mi_wb_cyc_o, + wb_stb_i => mi_wb_stb_o, + wb_sel_i => "1111",--mi_wb_sel_o, + wb_ack_o => mi_wb_ack_i, + wb_stall_o => mi_wb_stall_i, + + clk_off_3ns => sysclk_sram_we, + DRAM_ADDR => DRAM_ADDR(11 downto 0), + DRAM_BA => DRAM_BA, + DRAM_CAS_N => DRAM_CAS_N, + DRAM_CKE => DRAM_CKE, + DRAM_CLK => DRAM_CLK, + DRAM_CS_N => DRAM_CS_N, + DRAM_DQ => DRAM_DQ, + DRAM_DQM => DRAM_DQM, + DRAM_RAS_N => DRAM_RAS_N, + DRAM_WE_N => DRAM_WE_N + ); + + DRAM_ADDR(12) <= '0'; + + end block; + +end sim; diff --git a/libraries/Wishbone_Sump_LA/testmode.vhd b/libraries/Wishbone_Sump_LA/testmode.vhd new file mode 100644 index 0000000..4c2c2b7 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/testmode.vhd @@ -0,0 +1,78 @@ +---------------------------------------------------------------------------------- +-- muldex.vhd +-- +-- Copyright (C) 2011 Kinsa +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- generates test data +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity testmode is + port( + clock : in std_logic; + enable : in std_logic; + la_input : in std_logic_vector (31 downto 0); + output : out std_logic_vector (31 downto 0) + ); +end testmode; + +architecture behavioral of testmode is + + signal counter : std_logic_vector (27 downto 0); + signal a,b,c : std_logic_vector (7 downto 0); + signal d : std_logic; + +begin + + process(clock) + begin + if rising_edge(clock) then + counter <= counter + 1; + if counter(9 downto 0) = "1111111111" then + d <= not d; + end if; + end if; + end process; + + a <= counter(9 downto 2); + b <= not a; + + c <= a when d = '0' else b; + + process(clock) + begin + if rising_edge(clock) then + if enable = '0' then + output <= la_input; + else + output <= counter(27 downto 12) & counter(7 downto 0) & c; + end if; + end if; + end process; + +end behavioral; + + \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/transmitter.vhd b/libraries/Wishbone_Sump_LA/transmitter.vhd new file mode 100644 index 0000000..53ef128 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/transmitter.vhd @@ -0,0 +1,179 @@ +---------------------------------------------------------------------------------- +-- transmitter.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Takes 32bit (one sample) and sends it out on the serial port. +-- End of transmission is signalled by taking back the busy flag. +-- Supports xon/xoff flow control. +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity transmitter is + generic ( + FREQ : integer; + RATE : integer + ); + Port ( + data : in STD_LOGIC_VECTOR (31 downto 0); + disabledGroups : in std_logic_vector (3 downto 0); + write : in std_logic; + id : in std_logic; + xon : in std_logic; + xoff : in std_logic; + clock : in STD_LOGIC; + trxClock : IN std_logic; + reset : in std_logic; + tx : out STD_LOGIC; + busy: out std_logic +-- pause: out std_logic + ); +end transmitter; + +architecture Behavioral of transmitter is + + type TX_STATES is (IDLE, SEND, POLL); + +-- constant BITLENGTH : integer := FREQ / RATE; --FREQ = 100000000/28=3571428 : RATE = 115200 : FREQ/RATE = 3571428/115200 = 31 + constant BITLENGTH : integer := 16; + + signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0); + signal disabledBuffer : std_logic_vector (3 downto 0); + signal txBuffer : std_logic_vector (9 downto 0) := "1000000000"; + signal byte : std_logic_vector (7 downto 0); + signal counter : integer range 0 to BITLENGTH; + signal bits : integer range 0 to 10; + signal bytes : integer range 0 to 4; + signal state : TX_STATES; + signal paused, writeByte, byteDone, disabled : std_logic; + +begin +-- pause <= paused; + tx <= txBuffer(0); + + -- sends one byte + process(clock) + begin + if rising_edge(clock) then + if writeByte = '1' then + counter <= 0; + bits <= 0; + byteDone <= disabled; + txBuffer <= '1' & byte & "0"; + elsif counter = BITLENGTH then + counter <= 0; + txBuffer <= '1' & txBuffer(9 downto 1); + if bits = 10 then + byteDone <= '1'; + else + bits <= bits + 1; + end if; + elsif trxClock = '1' then + counter <= counter + 1; + end if; + end if; + end process; + + -- control mechanism for sending a 32 bit word + process(clock, reset) + begin + + if reset = '1' then + writeByte <= '0'; + state <= IDLE; + dataBuffer <= (others => '0'); + disabledBuffer <= (others => '0'); + + elsif rising_edge(clock) then + if (state /= IDLE) or (write = '1') or (paused = '1') then + busy <= '1'; + else + busy <= '0'; + end if; + + case state is + + -- when write is '1', data will be available with next cycle + when IDLE => + if write = '1' then + dataBuffer <= data; + disabledBuffer <= disabledGroups; + state <= SEND; + bytes <= 0; + elsif id = '1' then + dataBuffer <= x"534c4131"; + disabledBuffer <= "0000"; + state <= SEND; + bytes <= 0; + end if; + + when SEND => + if bytes = 4 then + state <= IDLE; + else + bytes <= bytes + 1; + case bytes is + when 0 => + byte <= dataBuffer(7 downto 0); + disabled <= disabledBuffer(0); + when 1 => + byte <= dataBuffer(15 downto 8); + disabled <= disabledBuffer(1); + when 2 => + byte <= dataBuffer(23 downto 16); + disabled <= disabledBuffer(2); + when others => + byte <= dataBuffer(31 downto 24); + disabled <= disabledBuffer(3); + end case; + writeByte <= '1'; + state <= POLL; + end if; + + when POLL => + writeByte <= '0'; + if byteDone = '1' and writeByte = '0' and paused = '0' then + state <= SEND; + end if; + + end case; + end if; + end process; + + -- set paused mode according to xon/xoff commands + process(clock, reset) + begin + if reset = '1' then + paused <= '0'; + elsif rising_edge(clock) then + if xon = '1' then + paused <= '0'; + elsif xoff = '1' then + paused <= '1'; + end if; + end if; + end process; + +end Behavioral; diff --git a/libraries/Wishbone_Sump_LA/waveform_gen.vhd b/libraries/Wishbone_Sump_LA/waveform_gen.vhd new file mode 100644 index 0000000..cec5794 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/waveform_gen.vhd @@ -0,0 +1,132 @@ +---------------------------------------------------------------------- +-- -- +-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE -- +-- -- +---------------------------------------------------------------------- +-- -- +-- Filename : waveform_gen.vhd -- +-- -- +-- Author : Simon Doherty -- +-- Senior Design Consultant -- +-- www.zipcores.com -- +-- -- +-- Date last modified : 23.10.2008 -- +-- -- +-- Description : NCO / Periodic Waveform Generator -- +-- -- +---------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + + +entity waveform_gen is + +port ( + + -- system signals + clk : in std_logic; + reset : in std_logic; + + -- NCO frequency control + phase_inc : in std_logic_vector(31 downto 0); + + -- Output waveforms + sin_out : out std_logic_vector(11 downto 0); + cos_out : out std_logic_vector(11 downto 0); + squ_out : out std_logic_vector(11 downto 0); + saw_out : out std_logic_vector(11 downto 0) ); + +end entity; + + +architecture rtl of waveform_gen is + + +component sincos_lut + +port ( + + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + sin_out : out std_logic_vector(11 downto 0); + cos_out : out std_logic_vector(11 downto 0)); + +end component; + + +signal phase_acc : std_logic_vector(31 downto 0); +signal lut_addr : std_logic_vector(11 downto 0); +signal lut_addr_reg : std_logic_vector(11 downto 0); +signal sin_out_reg : std_logic_vector(11 downto 0); + + +begin + + +-------------------------------------------------------------------------- +-- Phase accumulator increments by 'phase_inc' every clock cycle -- +-- Output frequency determined by formula: Phase_inc = (Fout/Fclk)*2^32 -- +-- E.g. Fout = 36MHz, Fclk = 100MHz, Phase_inc = 36*2^32/100 -- +-- Frequency resolution is 100MHz/2^32 = 0.00233Hz -- +-------------------------------------------------------------------------- + +phase_acc_reg: process(clk, reset) +begin + if reset = '0' then + phase_acc <= (others => '0'); + elsif clk'event and clk = '1' then + phase_acc <= unsigned(phase_acc) + unsigned(phase_inc); +-- sin_out <= signed(sin_out_reg) + 2047; --Modified to make it unsigned - jpg 10/6/2011 + end if; +end process phase_acc_reg; + +--------------------------------------------------------------------- +-- use top 12-bits of phase accumulator to address the SIN/COS LUT -- +--------------------------------------------------------------------- + +lut_addr <= phase_acc(31 downto 20); + +---------------------------------------------------------------------- +-- SIN/COS LUT is 4096 by 12-bit ROM -- +-- 12-bit output allows sin/cos amplitudes between 2047 and -2047 -- +-- (-2048 not used to keep the output signal perfectly symmetrical) -- +-- Phase resolution is 2Pi/4096 = 0.088 degrees -- +---------------------------------------------------------------------- + +lut: sincos_lut + + port map ( + + clk => clk, + addr => lut_addr, + sin_out => sin_out, + cos_out => cos_out ); + +--------------------------------- +-- Hide the latency of the LUT -- +--------------------------------- + +delay_regs: process(clk) +begin + if clk'event and clk = '1' then + lut_addr_reg <= lut_addr; + end if; +end process delay_regs; + +--------------------------------------------- +-- Square output is msb of the accumulator -- +--------------------------------------------- + +squ_out <= "011111111111" when lut_addr_reg(11) = '1' else "100000000000"; + +------------------------------------------------------- +-- Sawtooth output is top 12-bits of the accumulator -- +------------------------------------------------------- + +saw_out <= lut_addr_reg; + + +end rtl; \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/wb_burstctrl.vhd b/libraries/Wishbone_Sump_LA/wb_burstctrl.vhd new file mode 100644 index 0000000..b131cc1 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/wb_burstctrl.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library work; +use work.wishbonepkg.all; + +entity wb_burstctrl is + generic ( + WIDTH_BITS: natural := 16 + ); + port ( + clk: in std_logic; + rst: in std_logic; + + sob: in std_logic; + + rnext: out std_logic; + wnext: out std_logic; + + stb: out std_logic; + cyc: out std_logic; + cti: out std_logic_vector(2 downto 0); + stall:in std_logic; + ack: in std_logic; + + req: out std_logic; + eob: out std_logic + ); + +end entity wb_burstctrl; + +architecture behave of wb_burstctrl is + + type state_type is ( IDLE, BURST ); + type regs_type is record + state: state_type; + req: std_logic; + end record; + signal r: regs_type; + signal shr_shift: std_logic; + signal shr_msb: std_logic; + signal shw_shift: std_logic; + signal shw_msb: std_logic; + signal shw_last: std_logic; + signal sh_clr: std_logic; +begin + + + cti <= CTI_CYCLE_INCRADDR when shw_last='0' else CTI_CYCLE_ENDOFBURST; + + process(clk,rst,r,sob,stall,ack,shw_msb,shr_msb) + variable w: regs_type; + variable rstcnt: std_logic; + variable shiftr, shiftw: std_logic; + begin + w := r; + rstcnt := '0'; + shiftr := '0'; + shiftw := '0'; + + case r.state is + + when IDLE => + --cyc <= '0'; + stb <= 'X'; + + if sob='1' then + w.state := BURST; + w.req := '1'; + shiftw := '1'; + shiftr := '1'; + end if; + + wnext <= '0'; + rnext <= '0'; + when BURST => + + stb <= shw_msb; + + if shw_msb='1' then + -- Still writing + if stall='0' then + shiftw := '1'; + wnext <= '1'; + else + wnext <= '0'; + end if; + else + wnext <= '0'; + end if; + + if ack='1' then + rnext <= '1'; + shiftr := '1'; + if shr_msb='0' then + w.state := IDLE; + w.req := '0'; + rstcnt := '1'; + end if; + else + rnext <= '0'; + end if; + when others => + end case; + + if rst='1' then + w.state := IDLE; + w.req := '0'; + end if; + + shr_shift <= shiftr; + shw_shift <= shiftw; + sh_clr <= rstcnt; + + if rising_edge(clk) then + r <= w; + end if; + + end process; + + req <= r.req; + cyc <= r.req; + eob <= (not shr_msb) and ack; + + shr: entity work.wb_burstctrl_shreg + generic map ( + WIDTH_BITS => WIDTH_BITS-1 + ) + port map ( + clk => clk, + rst => rst, + clr => sh_clr, + shift => shr_shift, + msb => shr_msb, + last => open + ); + + shw: entity work.wb_burstctrl_shreg + generic map ( + WIDTH_BITS => WIDTH_BITS + ) + port map ( + clk => clk, + rst => rst, + clr => sh_clr, + shift => shw_shift, + msb => shw_msb, + last => shw_last + ); + +end behave; \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/wb_burstctrl_shreg.vhd b/libraries/Wishbone_Sump_LA/wb_burstctrl_shreg.vhd new file mode 100644 index 0000000..4e408ee --- /dev/null +++ b/libraries/Wishbone_Sump_LA/wb_burstctrl_shreg.vhd @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +entity wb_burstctrl_shreg is + generic ( + WIDTH_BITS: natural := 16 + ); + port ( + clk: in std_logic; + rst: in std_logic; + clr: in std_logic; + msb: out std_logic; + last: out std_logic; + shift: in std_logic + ); +end entity wb_burstctrl_shreg; + +architecture behave of wb_burstctrl_shreg is + signal shreg: std_logic_vector(WIDTH_BITS downto 0); +begin + +process(clk) +begin + if rising_edge(clk) then + if rst='1' or clr='1' then + shreg(WIDTH_BITS-1 downto 0) <= (others => '1'); + shreg(WIDTH_BITS) <= '0'; + else + if shift='1' then + shreg <= shreg(WIDTH_BITS-1 downto 0) & '0'; + end if; + end if; + end if; +end process; + +msb <= shreg(WIDTH_BITS); +last <= shreg(WIDTH_BITS) and not shreg(WIDTH_BITS-1); + +end behave; \ No newline at end of file diff --git a/libraries/Wishbone_Sump_LA/wb_core.vhd b/libraries/Wishbone_Sump_LA/wb_core.vhd new file mode 100644 index 0000000..ccca9dd --- /dev/null +++ b/libraries/Wishbone_Sump_LA/wb_core.vhd @@ -0,0 +1,532 @@ +---------------------------------------------------------------------------------- +-- core.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- The core contains all "platform independent" modules and provides a +-- simple interface to those components. The core makes the analyzer +-- memory type and computer interface independent. +-- +-- This module also provides a better target for test benches as commands can +-- be sent to the core easily. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity wb_core is + port( + clock : in std_logic; + cmd : in std_logic_vector (39 downto 0); + execute : in std_logic; + la_input : in std_logic_vector (31 downto 0); + la_inputClock : in std_logic; + output : out std_logic_vector (31 downto 0); + outputSend : out std_logic; + outputBusy : in std_logic; + memoryIn : in std_logic_vector (35 downto 0); + memoryOut : out std_logic_vector (35 downto 0); + memoryRead : out std_logic; + memoryWrite : out std_logic; + extTriggerIn : in std_logic; + extTriggerOut : out std_logic; + extClockOut : out std_logic; + armLED : out std_logic; + triggerLED : out std_logic; + reset : out std_logic; + run: out std_logic; + armed: out std_logic_vector(3 downto 0); + tx_bytes : out integer range 0 to 4 + ); +end wb_core; + +architecture behavioral of wb_core is + + component decoder + port( + opcode : in std_logic_vector (7 downto 0); + execute : in std_logic; + clock : in std_logic; + wrtrigmask : out std_logic_vector(3 downto 0); + wrtrigval : out std_logic_vector(3 downto 0); + wrtrigcfg : out std_logic_vector(3 downto 0); + wrspeed : out std_logic; + wrsize : out std_logic; + wrFlags : out std_logic; + arm : out std_logic; + reset : out std_logic; + abort : out std_logic; + ident : out std_logic; + meta : out std_logic + ); + end component; + + component flags + port( + data : in std_logic_vector(10 downto 0); + clock : in std_logic; + write : in std_logic; + demux : out std_logic; + filter : out std_logic; + external : out std_logic; + inverted : out std_logic; + disabledGroups : out std_logic_vector (3 downto 0); + rle : out std_logic; + test_mode : out std_logic; + data_size : out std_logic_vector (1 downto 0); + num_scheme : out std_logic + ); + end component; + + component sync is + port( + la_input : in std_logic_vector (31 downto 0); + clock : in std_logic; + enableFilter : in std_logic; + enableDemux : in std_logic; + falling : in std_logic; + output : out std_logic_vector (31 downto 0) + ); + end component; + + component testmode is + port( + clock : in std_logic; + enable : in std_logic; + la_input : in std_logic_vector (31 downto 0); + output : out std_logic_vector (31 downto 0) + ); + end component; + + component sampler + port( + la_input : in std_logic_vector(31 downto 0); + clock : in std_logic; + exClock : in std_logic; + external : in std_logic; + data : in std_logic_vector(23 downto 0); + wrDivider : in std_logic; + sample : out std_logic_vector(31 downto 0); + ready : out std_logic; + trig_delay : out std_logic_vector(1 downto 0); + num_scheme : in std_logic + ); + end component; + + component wb_trigger + port( + la_input : in std_logic_vector(31 downto 0); + la_inputReady : in std_logic; + data : in std_logic_vector(31 downto 0); + clock : in std_logic; + reset : in std_logic; + wrMask : in std_logic_vector(3 downto 0); + wrValue : in std_logic_vector(3 downto 0); + wrConfig : in std_logic_vector(3 downto 0); + arm : in std_logic; + demuxed : in std_logic; + run : out std_logic; + armed : out std_logic_vector(3 downto 0); + ExtTriggerIn : in std_logic + ); + end component; + + component group_selector + port( + clock : in std_logic; + la_input : in std_logic_vector(31 downto 0); + la_input_ready : in std_logic; + output : out std_logic_vector(31 downto 0); + output_ready : out std_logic; + disabledGroups : in std_logic_vector(3 downto 0) + ); + end component; + + component rle + port( + clock : in std_logic; + reset : in std_logic; + enable : in std_logic; + raw_inp : in std_logic_vector (31 downto 0); + raw_inp_valid : in std_logic; + rle_out : out std_logic_vector (32 downto 0); + rle_out_valid : out std_logic; + rle_inp : in std_logic_vector (32 downto 0); + rle_inp_valid : in std_logic; + fmt_out : out std_logic_vector (31 downto 0); + busy : out std_logic; + rle_ready : out std_logic; + raw_ready : in std_logic; + -- start_count : in std_logic; + -- data_count : out std_logic_vector(15 downto 0); + data_size : in std_logic_vector(1 downto 0) + ); + end component; + + component controller + port( + clock : in std_logic; + reset : in std_logic; + la_input : in std_logic_vector (32 downto 0); + la_inputReady : in std_logic; + run : in std_logic; + wrSize : in std_logic; + data : in std_logic_vector (31 downto 0); + busy : in std_logic; + send : out std_logic; + output : out std_logic_vector (31 downto 0); + memoryIn : in std_logic_vector (31 downto 0); + memoryOut : out std_logic_vector (32 downto 0); + memoryRead : out std_logic; + memoryWrite : out std_logic; + rle_busy : in std_logic; + rle_read : out std_logic; + rle_mode : in std_logic; + rdstate : out std_logic; + data_ready : in std_logic; + trig_delay : in std_logic_vector(1 downto 0); + abort : in std_logic + ); + end component; + + component muldex + port( + clock : in std_logic; + reset : in std_logic; + data_inp : in std_logic_vector (32 downto 0); + data_out : out std_logic_vector (32 downto 0); + data_rd : in std_logic; + data_wr : in std_logic; + mem_inp : in std_logic_vector (35 downto 0); + mem_out : out std_logic_vector (35 downto 0); + mem_rd : out std_logic; + mem_wr : out std_logic; + data_size : in std_logic_vector(1 downto 0); + rdstate : in std_logic; + data_ready : out std_logic + ); + end component; + + signal opcode : std_logic_vector (7 downto 0); + signal data : std_logic_vector (31 downto 0); + signal sample, syncedla_input : std_logic_vector (31 downto 0); + signal sampleClock, run_i : std_logic; + signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0); + signal wrDivider, wrsize, arm, resetCmd: std_logic; + signal flagDemux, flagFilter, flagExternal, flagInverted : std_logic; + signal wrFlags, sampleReady, flagRLE, flagTest : std_logic; + signal armLEDreg : std_logic := '0'; + signal triggerLEDreg : std_logic := '0'; + + signal data_rd, data_wr, controller_la_inputReady : std_logic; + signal rle_busy, rle_inp_valid, raw_inp_ready : std_logic; + + signal data_size : std_logic_vector(1 downto 0); + signal disabledGroups : std_logic_vector (3 downto 0); + signal la_input_sampler : std_logic_vector(31 downto 0); + signal controller_memoryIn, raw_inp : std_logic_vector (31 downto 0); + signal data_inp, controller_la_input, rle_inp : std_logic_vector (32 downto 0); + signal data_ready, raw_ready, rdstate : std_logic := '0'; + signal trig_delay : std_logic_vector(1 downto 0); + signal num_scheme, abort, ident, meta : std_logic; + signal output_i : std_logic_vector (31 downto 0); + signal outputSend_i : std_logic; + signal tx_bytes_i : integer range 0 to 4; + +begin + + data <= cmd(39 downto 8); + opcode <= cmd(7 downto 0); + reset <= resetCmd; + --armLED <= not armLEDreg; --Logic Sniffers LEDs are connected to 3.3V so a logic 0 turns the LED on. + --triggerLED <= not triggerLEDreg; + --extClockOut <= sampleClock; + --extTriggerOut <= run; + + tx_bytes_i <= + 1 when data_size = "01" else + 2 when data_size = "10" else + 3 when disabledGroups = "1000" and flagRLE = '0' else + 3 when disabledGroups = "0100" and flagRLE = '0' else + 3 when disabledGroups = "0010" and flagRLE = '0' else + 3 when disabledGroups = "0001" and flagRLE = '0' else + 4; + + -- process commands + process_cmd_block : block + + constant rom_size : natural := 18; + type states is (IDLE, IDENTIFY, METADATA, BUSYWAIT); + type rom_type is array (rom_size-1 downto 0) of + std_logic_vector (31 downto 0); + + constant rom : rom_type := ( + 0 => x"00000020", 1 => x"00002120", -- 0x20 0x00000020 + 2 => x"00220018", 3 => x"23001800", -- 0x21 0x00001800 + 4 => x"00e1f505", 5 => x"00000024", -- 0x22 0x00001800 + 6 => x"41204002", 7 => x"704f0102", -- 0x23 0x05f5e100 + 8 => x"65626e65", 9 => x"2068636e", -- 0x24 0x00000002 + 10 => x"69676f4c", 11 => x"6e532063", -- 0x40 0x20 + 12 => x"65666669", 13 => x"31762072", -- 0x41 0x02 + 14 => x"0031302e", 15 => x"302e3302", + 16 => x"48560300", others => x"00004c44" + ); + + -- 0x01 "Openbench Logic Sniffer v1.01" + -- 0x02 "3.0" + -- 0x03 "VHDL" + + signal state : states; + signal send_cmd : std_logic; + signal cmd_output : std_logic_vector (31 downto 0); + signal addr : integer range 0 to rom_size + 1; + + begin + + tx_bytes <= 4 when send_cmd = '1' else tx_bytes_i; + output <= cmd_output when send_cmd = '1' else output_i; + outputSend <= '1' when send_cmd = '1' else outputSend_i; + + process(clock) + begin + if rising_edge(clock) then + case state is + when IDLE => + if outputBusy = '0' then + if ident = '1' then + state <= IDENTIFY; + end if; + --Disabled, this was wreaking havoc with SPI slave +-- if meta = '1' then +-- state <= METADATA; +-- end if; + end if; + send_cmd <= '0'; + addr <= 0; + when IDENTIFY => + send_cmd <= '1'; + cmd_output <= x"534c4131"; -- "SLA1" + state <= IDLE; + when METADATA => + send_cmd <= '1'; + cmd_output <= rom(addr); + addr <= addr + 1; + state <= BUSYWAIT; + when BUSYWAIT => + send_cmd <= '0'; + if outputBusy = '0' and send_cmd = '0' then + if addr = rom_size then + state <= IDLE; + else + state <= METADATA; + end if; + end if; + end case; + end if; + end process; + end block; + + --Generates observable trigger and arm LED signals +-- process (clock) +-- begin +-- if rising_edge(clock) then +-- if arm = '1' then +-- armLEDreg <= '1'; +-- triggerLEDreg <= '0'; +-- elsif run = '1' then +-- armLEDreg <= '0'; +-- triggerLEDreg <= '1'; +-- end if; +-- end if; +-- end process; + + -- select between internal and external sampling clock +-- BUFGMUX_intex: BUFGMUX +-- port map ( +-- O => sampleClock, -- Clock MUX output +-- I0 => clock, -- Clock0 la_input +-- I1 => la_inputClock, -- Clock1 la_input +-- S => flagExternal -- Clock select la_input +-- ); + + sampleClock <= clock; + + Inst_decoder: decoder + port map( + opcode => opcode, + execute => execute, + clock => clock, + wrtrigmask => wrtrigmask, + wrtrigval => wrtrigval, + wrtrigcfg => wrtrigcfg, + wrspeed => wrDivider, + wrsize => wrsize, + wrFlags => wrFlags, + arm => arm, + reset => resetCmd, + abort => abort, + ident => ident, + meta => meta + ); + + Inst_flags: flags + port map( + data => data(10 downto 0), + clock => clock, + write => wrFlags, + demux => flagDemux, + filter => flagFilter, + external => flagExternal, + inverted => flagInverted, + disabledGroups => disabledGroups, + rle => flagRLE, + test_mode => flagTest, + data_size => data_size, + num_scheme => num_scheme + ); + + Inst_sync: sync + port map( + la_input => la_input, + clock => sampleClock, + enableFilter => flagFilter, + enableDemux => flagDemux, + falling => flagInverted, + output => syncedla_input + ); + + Inst_testmode: testmode + port map( + clock => clock, + enable => flagTest, + la_input => syncedla_input, + output => la_input_sampler + ); + + Inst_sampler: sampler + port map( + la_input => la_input_sampler, + clock => clock, + exClock => la_inputClock, + external => flagExternal, + data => data(23 downto 0), + wrDivider => wrDivider, + sample => sample, + ready => sampleReady, + trig_delay => trig_delay, + num_scheme => num_scheme + ); + + Inst_trigger: wb_trigger + port map( + la_input => sample, + la_inputReady => sampleReady, + data => data, + clock => clock, + reset => resetCmd, + wrMask => wrtrigmask, + wrValue => wrtrigval, + wrConfig => wrtrigcfg, + arm => arm, + armed => armed, + demuxed => flagDemux, + run => run_i, + extTriggerIn => extTriggerIn + ); + + Inst_group_selector: group_selector + port map( + clock => clock, + la_input => sample, + la_input_ready => sampleReady, + output => raw_inp, + output_ready => raw_inp_ready, + disabledGroups => disabledGroups + ); + + Inst_rle: rle + port map( + clock => clock, + reset => resetCmd, + raw_inp => raw_inp, + fmt_out => controller_memoryIn, + enable => flagRLE, + raw_inp_valid => raw_inp_ready, + rle_inp_valid => rle_inp_valid, +-- start_count => run, + data_size => data_size, + rle_out => controller_la_input, + rle_inp => rle_inp, + rle_out_valid => controller_la_inputReady, + busy => rle_busy, + rle_ready => data_ready, + raw_ready => raw_ready + ); + + Inst_controller: controller + port map( + clock => clock, + reset => resetCmd, + la_input => controller_la_input, + la_inputReady => controller_la_inputReady, + run => run_i, + wrSize => wrSize, + data => data, + busy => outputBusy, + send => outputSend_i, + output => output_i, + memoryIn => controller_memoryIn, + memoryOut => data_inp, + memoryRead => data_rd, + memoryWrite => data_wr, + rle_busy => rle_busy, + rle_read => rle_inp_valid, + rle_mode => flagRLE, + rdstate => rdstate, + data_ready => data_ready, + trig_delay => trig_delay, + abort => abort + ); + + Inst_muldex : muldex + port map( + clock => clock, + reset => resetCmd, + data_inp => data_inp, + data_out => rle_inp, + data_rd => data_rd, + data_wr => data_wr, + mem_inp => memoryIn, + mem_out => memoryOut, + mem_rd => memoryRead, + mem_wr => memoryWrite, + data_size => data_size, + rdstate => rdstate, + data_ready => raw_ready + ); + + run <= run_i; + reset <= resetCmd; + +end behavioral; diff --git a/libraries/Wishbone_Sump_LA/wb_stage.vhd b/libraries/Wishbone_Sump_LA/wb_stage.vhd new file mode 100644 index 0000000..67d0d6e --- /dev/null +++ b/libraries/Wishbone_Sump_LA/wb_stage.vhd @@ -0,0 +1,203 @@ +---------------------------------------------------------------------------------- +-- stage.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Programmable 32 channel trigger stage. It can operate in serial +-- and parallel mode. In serial mode any of the la_input channels +-- can be used as la_input for the 32bit shift register. Comparison +-- is done using the value and mask registers on the la_input in +-- parallel mode and on the shift register in serial mode. +-- If armed and 'level' has reached the configured minimum value, +-- the stage will start to check for a match. +-- The match and run output signal delay can be configured. +-- The stage will disarm itself after a match occured or when reset is set. +-- +-- The stage supports "high speed demux" operation in serial and parallel +-- mode. (Lower and upper 16 channels contain a 16bit sample each.) +-- +-- Matching is done using a pipeline. This should not increase the minimum +-- time needed between two dependend trigger stage matches, because the +-- dependence is evaluated in the last pipeline step. +-- It does however increase the delay for the capturing process, but this +-- can easily be compensated by software. +-- (By adjusting the before/after ratio.) +-- +-- Changes: Synchronous reset. +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity wb_stage is + port( + la_input : in std_logic_vector (31 downto 0); + la_inputReady : in std_logic; + data : in std_logic_vector (31 downto 0); + clock : in std_logic; + reset : in std_logic; + wrMask : in std_logic; + wrValue : in std_logic; + wrConfig : in std_logic; + arm : in std_logic; + level : in std_logic_vector (1 downto 0); + demuxed : in std_logic; + run : out std_logic; + is_armed: out std_logic; + match : out std_logic + ); +end wb_stage; + +architecture behavioral of wb_stage is + + type STATES is (OFF, ARMED, MATCHED); + + signal maskRegister, valueRegister : std_logic_vector (31 downto 0); + signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0); + signal testValue: std_logic_vector (31 downto 0); + signal cfgStart, cfgSerial : std_logic; + signal cfgChannel : std_logic_vector(4 downto 0); + signal cfgLevel : std_logic_vector(1 downto 0); + signal counter, cfgDelay : std_logic_vector(15 downto 0); + signal matchL16, matchH16, match32Register : std_logic; + signal state : STATES; + signal serialChannelL16, serialChannelH16 : std_logic; + +begin + + is_armed<='1' when state=ARMED else '0'; + + -- use shift register or la_input depending on configuration + testValue <= shiftRegister when cfgSerial = '1' else la_input; + + -- apply mask and value and create a additional pipeline step + process(clock) + begin + if rising_edge(clock) then + intermediateRegister <= (testValue xor valueRegister) and maskRegister; + end if; + end process; + + -- match upper and lower word separately + matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0'; + matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0'; + + -- in demux mode only one half must match, in normal mode both words must match + process(clock) + begin + if rising_edge(clock) then + if demuxed = '1' then + match32Register <= matchL16 or matchH16; + else + match32Register <= matchL16 and matchH16; + end if; + end if; + end process; + + -- select serial channel based on cfgChannel + process(la_input, cfgChannel) + begin + for i in 0 to 15 loop + if conv_integer(cfgChannel(3 downto 0)) = i then + serialChannelL16 <= la_input(i); + serialChannelH16 <= la_input(i + 16); + end if; + end loop; + end process; + + -- shift in bit from selected channel whenever la_input is ready + process(clock) + begin + if rising_edge(clock) then + if la_inputReady = '1' then + if demuxed = '1' then -- in demux mode two bits come in per sample + shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16; + elsif cfgChannel(4) = '1' then + shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16; + else + shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16; + end if; + end if; + end if; + end process; + + -- trigger state machine + process(clock, reset) + begin + if rising_edge(clock) then + if reset = '1' then + state <= OFF; + else + run <= '0'; + match <= '0'; + case state is + + when OFF => + if arm = '1' then + state <= ARMED; + end if; + + when ARMED => + if match32Register = '1' and level >= cfgLevel then + counter <= cfgDelay; + state <= MATCHED; + end if; + + when MATCHED => + if la_inputReady = '1' then + if counter = "0000000000000000" then + run <= cfgStart; + match <= not cfgStart; + state <= OFF; + else + counter <= counter - 1; + end if; + end if; + + end case; + end if; + end if; + end process; + + -- handle mask, value & config register write requests + process(clock) + begin + if rising_edge(clock) then + if wrMask = '1' then + maskRegister <= data; + end if; + if wrValue = '1' then + valueRegister <= data; + end if; + if wrConfig = '1' then + cfgStart <= data(27); + cfgSerial <= data(26); + cfgChannel <= data(24 downto 20); + cfgLevel <= data(17 downto 16); + cfgDelay <= data(15 downto 0); + end if; + end if; + end process; + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/wb_trigger.vhd b/libraries/Wishbone_Sump_LA/wb_trigger.vhd new file mode 100644 index 0000000..be86cb5 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/wb_trigger.vhd @@ -0,0 +1,138 @@ +---------------------------------------------------------------------------------- +-- trigger.vhd +-- +-- Copyright (C) 2006 Michael Poppitz +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA +-- +---------------------------------------------------------------------------------- +-- +-- Details: http://www.sump.org/projects/analyzer/ +-- +-- Complex 4 stage 32 channel trigger. +-- +-- All commands are passed on to the stages. This file only maintains +-- the global trigger level and it outputs the run condition if it is set +-- by any of the stages. +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity wb_trigger is + port( + la_input : in std_logic_vector (31 downto 0); + la_inputReady : in std_logic; + data : in std_logic_vector (31 downto 0); + clock : in std_logic; + reset : in std_logic; + wrMask : in std_logic_vector (3 downto 0); + wrValue : in std_logic_vector (3 downto 0); + wrConfig : in std_logic_vector (3 downto 0); + arm : in std_logic; + demuxed : in std_logic; + run : out std_logic; + armed: out std_logic_vector(3 downto 0); + ExtTriggerIn : in std_logic + ); +end wb_trigger; + +architecture behavioral of wb_trigger is + + component wb_stage + port( + la_input : in std_logic_vector(31 downto 0); + la_inputReady : in std_logic; + data : in std_logic_vector(31 downto 0); + clock : in std_logic; + reset : in std_logic; + wrMask : in std_logic; + wrValue : in std_logic; + wrConfig : in std_logic; + arm : in std_logic; + level : in std_logic_vector(1 downto 0); + demuxed : in std_logic; + run : out std_logic; + is_armed : out std_logic; + match : out std_logic + ); + end component; + + signal stageMatch : std_logic_vector(3 downto 0); + signal stageRun : std_logic_vector(4 downto 0); + signal levelReg : std_logic_vector(1 downto 0); +begin + + --Connect ExtTriggerIn to the last stageRun + --stageRun(4) <= ExtTriggerIn; --Disable external trigger + + -- BUG BUG - alvie. At least set stageRun(4).... + stageRun(4)<='0'; + + -- create stages + stages: for i in 0 to 3 generate + Inst_stage: wb_stage + port map( + la_input => la_input, + la_inputReady => la_inputReady, + data => data, + clock => clock, + reset => reset, + wrMask => wrMask(i), + wrValue => wrValue(i), + wrConfig => wrConfig(i), + arm => arm, + level => levelReg, + demuxed => demuxed, + run => stageRun(i), + is_armed => armed(i), + match => stageMatch(i) + ); + end generate; + + -- increase level on match + process(clock, arm) + variable tmp : std_logic; + begin + if arm = '1' then + levelReg <= "00"; + elsif rising_edge(clock) then + tmp := stageMatch(0); + for i in 1 to 3 loop + tmp := tmp or stageMatch(i); + end loop; + if tmp = '1' then + levelReg <= levelReg + 1; + end if; + end if; + + end process; + + -- if any of the stages set run, capturing starts + process(stageRun) + variable tmp : std_logic; + begin + tmp := stageRun(0); + for i in 1 to 4 loop + tmp := tmp or stageRun(i); + end loop; + run <= tmp; + end process; + +end behavioral; + diff --git a/libraries/Wishbone_Sump_LA/wishbonepkg.vhd b/libraries/Wishbone_Sump_LA/wishbonepkg.vhd new file mode 100644 index 0000000..b8f3613 --- /dev/null +++ b/libraries/Wishbone_Sump_LA/wishbonepkg.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package wishbonepkg is + +constant CTI_CYCLE_CLASSIC: std_logic_vector(2 downto 0) := "000"; +constant CTI_CYCLE_CONSTADDR: std_logic_vector(2 downto 0) := "001"; +constant CTI_CYCLE_INCRADDR: std_logic_vector(2 downto 0) := "010"; +constant CTI_CYCLE_ENDOFBURST: std_logic_vector(2 downto 0) := "111"; + +constant BTE_BURST_LINEAR: std_logic_vector(1 downto 0) := "00"; +constant BTE_BURST_4BEATWRAP: std_logic_vector(1 downto 0) := "01"; +constant BTE_BURST_8BEATWRAP: std_logic_vector(1 downto 0) := "10"; +constant BTE_BURST_16BEATWRAP: std_logic_vector(1 downto 0) := "11"; + +type wb_p_miso_type is record + ack: std_logic; + dat: std_logic_vector(31 downto 0); + tag: std_logic_vector(31 downto 0); + int: std_logic; + err: std_logic; + rty: std_logic; + stall: std_logic; +end record; + +type wb_miso_type is record + ack: std_logic; + dat: std_logic_vector(31 downto 0); + tag: std_logic_vector(31 downto 0); + int: std_logic; + err: std_logic; + rty: std_logic; +end record; + +type wb_mosi_type is record + dat: std_logic_vector(31 downto 0); + adr: std_logic_vector(31 downto 0); + tag: std_logic_vector(31 downto 0); + cyc: std_logic; + stb: std_logic; + sel: std_logic_vector(3 downto 0); + cti: std_logic_vector(2 downto 0); + bte: std_logic_vector(1 downto 0); + we: std_logic; +end record; + +type wb_syscon_type is record + clk: std_logic; + rst: std_logic; +end record; + + +end wishbonepkg;